JP5067670B2 - Machine controller system - Google Patents

Description

The present invention relates to a machine controller device that performs distributed control by a combination of a plurality of controllers.

In machine devices that use machine controllers with PLC functions, the advancement and complexity of sequence control and motion control has progressed, and one device has been divided into sections for each function. Applications that perform coordinated operations are increasing.
The sectioning of such a mechanical device also has an object of adding or replacing each section and easily changing the machine configuration according to the application.
As described above, when the mechanical device is configured by sectioning, that is, distributed control, in order for the device to exhibit sufficient performance, it is required that the synchronism between individual sections is guaranteed.
Conventionally, such a device has been realized by a decentralized controller exchanging data and signals through communication means such as a network.
Alternatively, the same input signal is input to all distributed controllers, and synchronization is realized by performing an operation using the signal as a trigger.
For example, Patent Document 1 (FIGS. 1, 4, and 7) discloses a distributed system in which one controller and another controller are connected by a data link.

FIG. 11 shows a configuration in which a plurality of machine controllers are connected by communication means to perform distributed control. In FIG. 11, reference numeral 1 denotes a program input device that creates and outputs an application program S1. Reference numeral 2 denotes a master controller, which includes a CPU module 3 and a communication module 4. The CPU module 3 exchanges input / output data S2 with the communication module 4 through the bus according to the processing procedure of the application program S1. The timing for transmitting / receiving the input / output data S2 and the timing for executing the application program, that is, the scan cycle are generally created based on a clock generated by a crystal oscillator mounted on the CPU module 3.
The communication module 4 transmits / receives communication data S3 to / from the slave controllers 51 to 5N at a fixed communication cycle.
Similarly to the master controller 2, the slave controllers 51 to 5N also store application programs created by the program input device 1. The broken line indicating the program input device 1 connected to the slave controllers 51 to 5N means that the program input device 1 is connected as necessary.

In FIG. 11, the command data from the master controller 2 is transmitted to the slave controllers 51 to 5N. The slave controllers 51 to 5N execute processing on the received command data in accordance with the processing procedure of the application program, and return the execution result to the master controller 2 as response data.
The master controller 2 manages the progress of the application program based on the response data of the slave controllers 51 to 5N.
FIG. 12 shows a block diagram of the slave controllers 51 to 5N. Slave scan cycle generation for generating a slave scan cycle signal S15s based on an original slave reference cycle generation circuit 16s and its output slave reference cycle signal S14s. A circuit 17s is provided. The slave controllers 51 to 5N execute a scan operation based on the slave scan cycle signal S15s generated by the slave scan cycle generation circuit 17s.

In the control system having such a configuration, the master scan cycle (scan cycle of the master controller 2) and each slave scan cycle (scan cycles of the slave controllers 51 to 5N) are not synchronized as in the case of Patent Document 1.
Further, since the crystal oscillators included in the master controller 2 and each slave controller have individual differences, even if the same scan period is set, a slight deviation occurs in the scan period. When the scan cycle shift accumulates, the operation timing of each controller shifts.
For this reason, there is a problem in applications where synchronization performance between sections is required such that the timing at which command data from the master controller 2 is transmitted to the slave controllers 51 to 5N is shifted or the operation start timing is shifted by an application.
There is also a request to change the scan cycle depending on the device connected to each slave controller. For example, when controlling a servo device requiring high speed, the scan cycle is shortened, and input / output with a general-purpose I / O device is lengthened.

Even when the I / O input signal is used for synchronization, there is a shift in the timing for capturing the input signal due to the accumulation of minute shifts in the scan period of each controller. There was a problem.
JP 2000-4243 (FIGS. 1, 4, and 7)

  In order to address such problems and requirements, the present invention can synchronize the scan cycle of the slave controller with the scan cycle of the master controller. Furthermore, the scan cycle of the slave controller is an integer of the scan cycle of the master controller. An object of the present invention is to provide a machine controller system that can be set to a multiple or 1 / integer multiple.

According to the first aspect of the present invention, one master controller and one or a plurality of slave controllers are connected via a communication network, and the master controller broadcasts a synchronization frame to the slave controller every communication cycle. In the machine controller system that sends
The slave controller is
CPU,
And slave reference period generation circuit for generating a slave reference period signal,
And slave scan cycle generating circuit for generating a slave scan cycle signal by counting the slave reference periodic signal,
A synchronization permission unit for synchronizing the slave scan cycle master scan cycle of the master controller,
With
The synchronization permission unit
After synchronization permission signal is written to the synchronous authorization unit by the CPU, when outputting the first flag and an edge signal upon receiving a synchronization frame signal for the first time, receiving the synchronization frame signal of second and subsequent Outputs only the edge signal,
The slave scan cycle generation circuit
It is reset only when both the initial flag and the edge signal are input, and when the initial flag is input, the slave scan cycle signal is not output.

According to a second aspect of the present invention, in the first aspect of the invention, the slave reference period generation circuit is reset by the input of the edge signal, and the slave reference period signal is output when the initial flag is input. It is characterized by not outputting .

According to a third aspect of the present invention, in the first or second aspect of the present invention, the slave controller is configured such that the slave scan period is an integer multiple or an integer of the master scan period in order to determine whether synchronization is possible. It is determined that synchronization is possible only when it is 1 / minute, and the slave scan period is synchronized with the master scan period.

The invention according to claim 4 is the invention according to claim 3 , wherein the master controller transmits transmission data storing data of the master scan period to the slave controller,
The slave controller returns a result of the synchronization determination to the master controller,
When the master controller returns that the slave controller can be synchronized, a synchronization start request and a scan counter value obtained by counting the master scan period in the communication period are transmitted to the slave controller,
When the slave controller receives the synchronization start request and the scan counter value, the slave controller performs a synchronization process, and when the synchronization process is completed, transmits response data in which a status indicating completion of synchronization is set to the master controller It is characterized by doing.

  According to a fifth aspect of the present invention, in the invention according to the fourth aspect, in the synchronization process, the CPU monitors the scan counter value transmitted from the master controller to detect a master scan start timing. When the master scan start timing is detected, the synchronization permission signal is written in the synchronization permission unit.

According to a sixth aspect of the invention, in the fifth aspect of the invention, the detection of the master scan start timing is performed by determining whether or not the scan counter value is equal to a preset value. It is characterized by being.

According to the present invention, if the scan cycle of the slave controller is an integral multiple of the master controller's scan cycle or an integral multiple of an integer, the scan cycle of the slave controller can be synchronized with the scan cycle of the master controller.
In addition, since a different scan cycle can be set for each slave controller, each slave controller can use a CPU that matches the actually required control performance. Therefore, it is economical without using a CPU having a higher performance than necessary.

Hereinafter, specific examples of the method of the present invention will be described with reference to the drawings.
In the embodiment shown in FIG. 1, a master controller 2 and a plurality of slave controllers are connected by high-speed serial communication to synchronize scan cycles. Although FIG. 1 is described assuming a star connection, the topology of high-speed serial communication is not limited to the star connection.
FIG. 1 shows an embodiment of the control system of the present invention, and the outline is the same as that of the conventional FIG. 11, but the configuration of each of the slave controllers 51 to 5N (FIG. 3) is the same as that of the conventional slave controller (FIG. 12). This is different and will be described later.

FIG. 2 is a block diagram showing the configuration of the master controller 2 to which the method of the present invention is applied. The same components as those of the slave controller are denoted by the same reference numerals and attached with 'm' meaning the master controller. .
In FIG. 2, reference numeral 3 denotes a CPU module, which has a function as a programmable controller. The CPU module 3 includes an input unit 10m for capturing an external signal, an output unit 11m for outputting a signal to the outside, a data memory unit 12m, a program memory unit 14m storing a user program, and the program memory unit It comprises CPU13m which calculates according to the control program stored in. The CPU 13m operates based on a clock signal generated by the crystal oscillator 15m.

  Reference numeral 16m denotes a master reference period generation circuit which outputs a master reference period signal S14m based on an output clock of a crystal oscillator input to the CPU 13m, and the period is set in advance. Reference numeral 17m denotes a master scan cycle generation circuit which counts the master reference cycle signal S14m and outputs a master scan cycle signal S15m having an arbitrary integer multiple and a fixed cycle. The cycle is preset. Based on the cycle of the master scan cycle signal S15m, the CPU 13m executes input, output and calculation of the programmable controller. The master reference periodic signal S14m and the master scan periodic signal S15m are also output to the communication module 4 through the bus.

  Reference numeral 4 denotes a communication module, which includes a memory 25 for storing data set by the CPU module 3 in the own module, a CPU 21 that operates based on the clock of the shared memory 20 and the crystal oscillator 24, and slave controllers 51 to 5N. A master data transmission / reception circuit 22m that transmits / receives communication data S3 and a communication cycle generation circuit 23 that counts the master reference cycle signal S14m and generates a communication cycle signal S13 having a fixed cycle which is an arbitrary integer multiple thereof. The cycle of the communication cycle signal S13 is set in advance.

In this configuration, the master data transmission / reception circuit 22m operates based on the communication cycle signal S13 obtained by dividing the master reference cycle signal S14m. Therefore, the master data transmission / reception circuit 22m is synchronized with the master reference cycle signal S14m and has a communication cycle that is an integral multiple of the cycle. Data can be sent and received. This communication cycle signal S13 is also input to the CPU 21.
In addition, when the master scan cycle signal S15m is input to the communication cycle generation circuit 23, the frequency division circuit count value of the communication cycle generation circuit is reset for each scan cycle, so that the scan cycle and the communication cycle are synchronized. become. Since the master scan cycle signal S15m is generated by counting the master reference cycle signal S14m, the output of the communication cycle signal S13 in the communication cycle generation circuit 23 and the reset of the communication cycle generation circuit 23 are almost the same. It will be performed at the same timing. In order to avoid this, the reset of the communication cycle generation circuit 23 is performed after the input timing of the master scan cycle signal S15m is set so that the communication cycle generation circuit 23 outputs the communication cycle signal S13 to the master data transmission / reception circuit 22m. similar to adjust.

3 is a block diagram showing the configuration of the slave controllers 51 to 5N to which the method of the present invention is applied. The same parts as those in FIG. 2 are given the same names and the same numbers, and the numbers are distinguished from the numbers in FIG. In order to do this, 's' meaning slave is added.
The slave controllers 51 to 5N operate based on a clock signal generated by the crystal oscillator 15s. A slave reference period signal S14s is generated by the slave reference period generation circuit 16s based on the clock, and the period is set in advance. Note that the slave reference period is equal to the master reference period.
The slave reference period signal S14s is counted by the slave scan period generation circuit 17s to generate the slave scan period signal S15s, and the period is set in advance. This is the same as in the case of the master controller 2.

When the slave data transmission / reception circuit 22s receives a synchronization frame from the master controller 2 every communication cycle, it outputs a synchronization frame signal S16. The synchronization frame signal S16 is the same as the conventional one in that it is input to the CPU 13s to notify the start of the communication cycle.
What is different from the prior art is that the signal is input to the slave reference cycle generation circuit 16 s and the slave scan cycle generation circuit 17 s through the synchronization permission unit 18.
The initial flag S20 generated by the synchronization permission unit 18 and indicating the first synchronization frame signal after the synchronization permission is input to the slave reference period generation circuit 16s and the slave scan period generation circuit 17s. .

Details of the synchronization permission unit 18, the slave reference cycle generation circuit 16s, and the slave scan cycle generation circuit 17s will be described with reference to FIG.
The synchronization permission unit 18 includes a register, an AND gate, an edge detection unit, and an initial flag generation unit. When the slave controller 5 is operating asynchronously with the synchronization frame signal S16 (asynchronously with the master controller 2), the CPU 13s writes “0” as a synchronization permission signal in the register, and the synchronization frame signal S16 is cut off. .
Since the slave controller 5 operates in synchronization with the synchronization frame signal S16 (synchronization with the master controller 2), when the CPU 13s writes “1” as a synchronization permission signal to the register, the synchronization frame signal S16 becomes the edge detection unit. The edge signal S19 is generated.
The edge signal S19 is input to the initial flag generation unit, and an initial flag S20 indicating that the synchronization frame signal S16 is input first after the synchronization permission signal “1” is written to the register is generated.

Next, a mechanism in which the slave reference period signal S14s and the slave scan period signal S15s are synchronized with the synchronization frame signal S16 using the edge signal S19 and the initial flag S20 will be described.
The slave reference period generation circuit 16s counts the clock output from the crystal oscillator 15s by the up counter A, and outputs a slave reference period signal S14s every time the count value reaches a preset value.
Here, when the edge signal S19 is input, the up-counter A is reset, and the slave reference period signal S14s is output at the timing, and the synchronization frame signal S16 and the slave reference period signal S14s are synchronized. .
However, at the timing when the initial flag is set, the slave reference period signal S14s is cut off. This is to prevent the period of the slave scan period signal 15s generated by counting the slave reference period signal S14s from becoming shorter than a preset period and making it impossible to perform a scan process with a constant period.

The slave scan cycle generation circuit 17s counts the slave reference cycle signal S14s with the up counter B, and generates a slave scan cycle signal S15s for each preset count value. The up counter B is reset only at the timing when the initial flag is set. At that timing, the slave scan cycle signal S15s is cut off. This is to avoid the case where the cycle of the slave scan cycle signal S15s becomes shorter than a preset cycle and the scan processing with a fixed cycle cannot be executed.

  FIG. 4 is an outline of the frame flow between the master controller and the slave controller in the process of synchronizing the master scan period and the slave scan period, but only one slave controller is shown for simplicity.

First, the master controller 2 stores and transmits the master scan cycle of its own station in the transmission data to the slave controllers 51 to 5N.
The slave controllers 51 to 5N compare the master scan cycle in the received data with the slave scan cycle of the local station and the communication cycle, and determine whether or not all of the following conditions are satisfied.
1) Is the master scan cycle and communication cycle an integer multiple or a fraction of an integer?
2) Is the slave scan cycle and communication cycle an integer multiple or a fraction of an integer?
3) Is the master scan period and slave scan period an integer multiple or a fraction of an integer?
When all the above conditions are satisfied, a status indicating that synchronization is possible (hereinafter referred to as “SYNCRDY”) is stored in the response data to the master controller 2.

When SYNCRDY is set in the received data from the slave controllers 51 to 5N, the master controller 2 sets a synchronization start request in the transmission data to the slave controllers 51 to 5N, and sets the master scan cycle to the communication cycle. Stores the counted scan counter value.
Here, the scan counter is processed by software (not shown) executed by the CPU 21, and counts the communication period within the scan period.

FIG. 5 shows an example of counting the communication cycle by the scan counter.
In this example, the master scan period is 8 times the reference period, and the communication period is twice the reference period. Therefore, the master scan period is 4 times the communication period.
In FIG. 5, the shaded portion of the master scan cycle and the communication cycle indicates software processing. The communication cycle processing is set to be processed with priority over the master scan cycle processing.
The initial value of the scan counter is a positive integer value including 0 indicating how many communication cycles the master scan cycle is composed of, and is calculated by the following equation.

Scan counter initial value = master scan cycle / communication cycle-1
(However, if the calculation result is a negative value, the initial value of the scan counter is 0.)

When the software processing of the master scan cycle is executed by the interruption by the master scan cycle signal S15m from the master scan cycle generation circuit 17m, the initial value is reset in the scan counter. (In FIG. 5, the initial value = 3.)
And it is decremented every time the software processing of the communication cycle is executed by the interruption by the communication cycle signal S13. (In FIG. 5, it changes from 3 → 2 → 1 → 0.) The decrement timing is after the data transmission to the slave controller is completed. When the scan counter value is 0, the decrement is performed. Absent.
Here, the initial value setting to the scan counter by the software processing in the master scan cycle is scheduled to be performed immediately after the start of the software processing so as not to be affected by the software processing timing of the communication cycle.

When software (not shown) executed by the CPU 13s of the slave controllers 51 to 5N receives the synchronization start request, it monitors the scan counter value of the master controller stored in the received data, and scan start timing of the master controller Wait for.
FIG. 6 is an example of scan counter reception in the slave controller 5. The setting of the master scan cycle and the communication cycle is the same as in FIG.
In FIG. 6, the scan counter value transmitted from the master controller 2 is received by the slave controller 5 with a delay of one communication cycle due to a transmission delay. Therefore, when the scan counter value received by the slave controller 5 is 1, it can be determined that it coincides with the scan start timing of the master controller 2.
As described above, the slave controller 5 determines the scan start timing of the master controller 2 based on the received scan counter value. This determination is performed as follows.

(1) When master scan cycle ÷ communication cycle ≥ 2
When scan counter value = 1, it matches the scan start timing

(2) When master scan cycle ÷ communication cycle <2
Always consistent with scan start timing

When detecting the scan start timing of the master controller 2, the CPU 13 s of the slave controller 5 writes “1” as the synchronization permission signal S 17 to the synchronization permission unit 18. Thereafter, synchronization between the synchronization frame signal S16, the slave reference period signal S14s, and the slave scan period signal S15s is established by the procedure described in paragraphs 0026 to 0028.
When the synchronization between the synchronization frame signal S16 and the slave scan cycle signal S15s can be established in this way, the slave controllers 51 to 5N set a status indicating synchronization completion (hereinafter, SYNC) in response data to the master controller 2. .
When SYNC is set in the received data from the slave controllers 51 to 5N, the master controller 2 clears the synchronization start request and ends the synchronization process. In this way, synchronization between the master scan period and the slave scan period is established.

Next, a specific example of synchronization between the master scan period and the slave scan period will be described.
FIG. 7 is a timing chart when the master scan period and the slave scan period are synchronized according to the present invention, but for simplicity, only one slave controller is shown.
In this example, the master scan period is four times the reference period, and the communication period is twice the reference period. Therefore, the master scan period is twice the communication period.
In the asynchronous state, the scan cycles of the master controller 2 and the slave controllers 51 to 5N are not synchronized, and the timings of both are gradually shifted due to individual differences between the crystal oscillator 15m and the crystal oscillator 15s.
When the slave controllers 51 to 5N determine that synchronization with the master controller 2 is possible, the slave controllers 51 to 5N set SYNCRDY and wait for a synchronization start request from the master controller 2.

The master controller 2 transmits a scan counter value to the slave controllers 51 to 5N every communication cycle synchronized with the scan cycle.
In FIG. 7, the scan counter changes from 0 → 1 → 0 because it is reset by the master scan cycle signal S15m from the master scan cycle generation circuit 17m and is set to the initial value 1, and from the communication cycle generation circuit 23. This is decremented every time the communication cycle signal S13 is input, and immediately after it becomes 0, the master scan cycle signal S15m is input and reset to indicate that the initial value 1 is reset.

  The slave controllers 51 to 5N monitor the scan counter value transmitted from the master controller 2 after receiving the synchronization start request, and the scan counter value is 1, that is, the current communication cycle is the start timing of the master scan cycle. When it is determined that there is, “1” is output to the synchronization permission unit 18 as the synchronization permission signal S17. The subsequent synchronization procedure of the synchronization frame signal S16 with the slave reference period signal S14s and the slave scan period signal S15s is as described in paragraphs 0026 to 0028.

In this synchronization, the timing at which the edge signal S19 is first input to the slave reference cycle generation circuit 16s is the head of the reference cycle, so the reference cycle at this timing is the reference cycle + α. Α is a fluctuation amount within one reference period.
Furthermore, the synchronization of the scan cycle signal is also performed at the same time, and the scan cycle at this timing is the scan cycle + β as in the case of the reference cycle. Note that β is a fluctuation amount within one slave scan cycle.
Thereafter, the reset of the reference period by the synchronization frame signal S16 is continuously performed every communication period, and the synchronization state of both is maintained. The synchronization frame signal S16 is synchronized with the master scan period that is the scan period of the master controller 2, and the slave scan periods of the slave controllers 51 to 5N are synchronized with the master scan period.

  FIG. 7 shows an example in which the master scan period and the slave scan period have the same length, but it is also easy to configure the master scan period to be an integral multiple or a fraction of an integral number of the slave scan period. It is. This is because the slave scan cycle generation circuit 17s may be set in advance so as to generate the slave scan cycle signal S15s having a cycle that is an integral multiple of the master scan cycle or a fraction of an integer.

FIG. 8 shows an example in which the master scan period is 1/4 times the communication period. The slave scan cycle is set to one time of the communication cycle, and the master scan cycle is one quarter of the slave scan cycle.
In this case, the scan counter initial value = 0, and the scan counter value is always 0. Therefore, the slave controller side can determine that the timing coincides with the master scan period at any timing.

FIG. 9 shows an example in which the master scan cycle is twice the communication cycle and the slave scan cycle is a quarter of the communication cycle. The master scan cycle is 8 times the slave scan cycle.
In this case, the scan counter initial value = 1, and the scan counter value changes from 0 → 1 → 0 as in the case of FIG. The determination of the timing coincident with the master scan cycle and the synchronization processing are also the same as in FIG.

FIG. 10 shows an example in which the master scan cycle is 16 times the communication cycle and the slave scan cycle is 8 times the communication cycle. The master scan period is twice the slave scan period.
In this case, the scan counter initial value = 15, and the scan counter value changes from 0 → 15 → 14 →... → 1 → 0. Even with such a setting, the determination of the timing coincident with the master scan period and the synchronization processing can be performed in the same manner as in FIG.

  FIG. 7 shows an example in which the reset of the slave scan cycle generation circuit 17s is performed by the next synchronization frame signal S16 after the synchronization permission signal S17 is set to “1”. The slave scan period generation circuit 17s is reset by inputting the desired number of slave reference period signals S14s after the next synchronization frame signal S16 is input after the synchronization permission signal S17 is set to '1'. It is also possible to configure the scan cycle generation circuit 17s as sometimes done.

  As described above, according to the present invention, the scan periods of the master controller 2 and the slave controllers 51 to 5N connected via the network can be synchronized. Then, set the slave scan cycle to an integral multiple of the master scan cycle or 1 / integer, and delay the phase of the slave scan cycle from the phase of the master scan cycle by an integral multiple of the communication cycle or an integral multiple of the reference cycle. Is possible.

Machine controller system to which the method of the present invention is applied Block diagram of a master controller to which the method of the present invention is applied Block diagram of a slave controller to which the method of the present invention is applied Frame flow diagram showing synchronization processing of the present invention Diagram showing how the scan counter changes Diagram showing how the scan counter is transmitted to the slave controller The figure which shows the timing at the time of the synchronous processing of this invention (1) The figure which shows the timing at the time of the synchronous processing of this invention (2) The figure which shows the timing at the time of the synchronous processing of this invention (3) The figure which shows the timing at the time of the synchronous processing of this invention (4) Conventional distributed machine controller system Block diagram of a conventional slave controller Details of the synchronization permission unit, reference cycle generation circuit, and scan cycle generation circuit of the slave controller of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Program input device 2 Master controller 3 CPU module 4 Communication module 5 Slave controller 10m, 10s Input part 11m, 11s Output part 12m, 12s Data memory part 13m, 13s, 21 CPU
14m, 14s Program memory units 15m, 15s, 24 Crystal oscillator 16m Master reference period generation circuit 16s Slave reference period generation circuit 17m Master scan period generation circuit 17s Slave scan period generation circuit 20 Shared memory 22m Master data transmission / reception circuit 22s Slave data transmission / reception Circuit 23 Communication cycle generation circuit 25 Memory S1 Application program S2 Input / output data S3 Communication data S13 Communication cycle signal S14m Master reference cycle signal S14s Slave reference cycle signal S15m Master scan cycle signal S15s Slave scan cycle signal S16 Synchronization frame signal S17 Synchronization enable signal S19 Edge signal S20 Initial flag

Claims (6)

In a machine controller system in which one master controller and one or more slave controllers are connected via a communication network, and the master controller broadcasts a synchronization frame to the slave controller every communication cycle.
The slave controller is
CPU,
And slave reference period generation circuit for generating a slave reference period signal,
And slave scan cycle generating circuit for generating a slave scan cycle signal by counting the slave reference periodic signal,
A synchronization permission unit for synchronizing the slave scan cycle master scan cycle of the master controller,
With
The synchronization permission unit
After synchronization permission signal is written to the synchronous authorization unit by the CPU, when outputting the first flag and an edge signal upon receiving a synchronization frame signal for the first time, receiving the synchronization frame signal of second and subsequent Outputs only the edge signal,
The slave scan cycle generation circuit
The machine controller system is reset only when both the initial flag and the edge signal are input, and does not output the slave scan cycle signal when the initial flag is input.   2. The machine controller system according to claim 1, wherein the slave reference period generation circuit is reset by the input of the edge signal and does not output a slave reference period signal when the initial flag is input.   The slave controller determines that synchronization is possible only when the slave scan period is an integral multiple of the master scan period or a fraction of an integer, and synchronizes the slave scan period with the master scan period. The machine controller system according to any one of claims 1 and 2. The master controller transmits transmission data storing the data of the master scan cycle to the slave controller,
The slave controller returns a result of the synchronization determination to the master controller,
When the master controller returns that the slave controller can be synchronized, a synchronization start request and a scan counter value obtained by counting the master scan period in the communication period are transmitted to the slave controller,
When the slave controller receives the synchronization start request and the scan counter value, the slave controller performs a synchronization process, and when the synchronization process is completed, transmits response data in which a status indicating completion of synchronization is set to the master controller The machine controller system according to claim 3.   In the synchronization process, the CPU monitors the scan counter value transmitted from the master controller to detect the master scan start timing. When the CPU detects the master scan start timing, the CPU transmits the synchronization permission signal to the synchronization The machine controller system according to claim 4, wherein the permission is performed by writing in the permission unit. 6. The machine controller system according to claim 5, wherein the detection of the master scan start timing is performed by determining whether or not the scan counter value is equal to a preset value.

Images