JP5064692B2 - Manufacturing method of SOI substrate - Google Patents
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- JP5064692B2 JP5064692B2 JP2006031913A JP2006031913A JP5064692B2 JP 5064692 B2 JP5064692 B2 JP 5064692B2 JP 2006031913 A JP2006031913 A JP 2006031913A JP 2006031913 A JP2006031913 A JP 2006031913A JP 5064692 B2 JP5064692 B2 JP 5064692B2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
Description
本発明は、透明絶縁性基板上に単結晶シリコン薄膜を有するSOI基板の製造方法に関する。 The present invention relates to a method for manufacturing an SOI substrate having a single crystal silicon thin film on a transparent insulating substrate.
従来の貼り合わせによるSOI基板の製造方法としては、SmartCut法やSiGen法などが知られている。 As a conventional method for manufacturing an SOI substrate by bonding, a SmartCut method, a SiGen method, or the like is known.
SmartCut法は、貼り合せ面側に水素イオンを注入したシリコン基板とシリコン基板や他の材料の基板とを貼り合わせ、400℃以上(例えば500℃)の熱処理を施して、注入水素イオンの濃度が最も高い領域からシリコン薄膜を熱剥離させてSOI基板を得る方法である(例えば、特許文献1や非特許文献1)。 In the SmartCut method, a silicon substrate into which hydrogen ions are implanted on the bonding surface side is bonded to a silicon substrate or another material substrate, and a heat treatment of 400 ° C. or higher (for example, 500 ° C.) is performed. In this method, the silicon thin film is thermally peeled from the highest region to obtain an SOI substrate (for example, Patent Document 1 and Non-Patent Document 1).
また、SiGen法は、貼り合せ面側に水素イオンを注入したシリコン基板とシリコン基板あるいは他の材料の基板とを貼り合わせる前に、これらの基板の貼り合せ面の双方もしくは一方の表面をプラズマ処理し、表面が活性化された状態で両基板を貼り合わせ、低温(例えば、100〜300℃)で熱処理を施して接合強度を高めた後に、常温で機械的に剥離してSOI基板を得る方法である(例えば、特許文献2〜4)。
これら2つの方法の相違点は、主としてシリコン薄膜の剥離プロセスにあり、SmartCut法はシリコン薄膜の剥離のために高温での処理を必要とするが、SiGen法は常温での剥離が可能である。 The difference between these two methods is mainly in the silicon thin film peeling process. The SmartCut method requires high-temperature treatment for peeling the silicon thin film, but the SiGen method can be peeled off at room temperature.
一般に、貼り合せSOI基板の製造には、シリコン基板とシリコン以外の他種材料基板との張り合わせが行われるが、このような異種材料同士は熱膨張率や固有耐熱温度などにおいて相違するのが通常であるから、製造工程中で張り合わせ基板に施される熱処理の温度が高くなると、両基板間の熱的諸特性の相違に起因して、割れや局所的なクラックなどが生じ易くなる。このような観点からは、シリコン薄膜の剥離に高温を要するSmartCut法は、異種材料基板の貼り合わせによるSOI基板の製造方法として好ましいものとはいえない。 In general, in manufacturing a bonded SOI substrate, a silicon substrate and a different type material substrate other than silicon are bonded to each other, but such dissimilar materials usually differ in thermal expansion coefficient, intrinsic heat resistance temperature, and the like. Therefore, if the temperature of the heat treatment applied to the bonded substrate during the manufacturing process increases, cracks and local cracks are likely to occur due to differences in thermal characteristics between the two substrates. From this point of view, the SmartCut method that requires high temperature for peeling the silicon thin film is not preferable as a method for manufacturing an SOI substrate by bonding different types of material substrates.
一方、低温剥離が可能なSiGen法は、上述したような熱的諸特性の相違に起因した割れや局所的クラックは生じ難いものの、機械的にシリコン薄膜の剥離を実行するこの手法では、剥離工程中に基板の接着面が剥がれたり剥離痕が生じたり或いはシリコン薄膜に機械的なダメージが導入され易いという問題がある。 On the other hand, the SiGen method, which can be peeled off at a low temperature, is unlikely to cause cracks or local cracks due to differences in thermal characteristics as described above, but in this method of mechanically peeling the silicon thin film, There is a problem that the adhesive surface of the substrate is peeled off, peeling marks are generated, or mechanical damage is easily introduced into the silicon thin film.
本発明は、このような問題に鑑みてなされたものであり、その目的とするところは、単結晶シリコン基板と透明絶縁性基板とを張り合わせてSOI基板を製造する工程において、基板間の熱的諸特性の相違に起因する割れや局所的クラック等および機械的ダメージのSOI層への導入を回避し、もって膜厚均一性、結晶性、電気的諸特性(キャリア移動度など)に優れたSOI層を有するSOI基板を提供することにある。 The present invention has been made in view of such problems, and an object of the present invention is to provide thermal processing between substrates in a process of manufacturing an SOI substrate by bonding a single crystal silicon substrate and a transparent insulating substrate. SOI with excellent film thickness uniformity, crystallinity, and various electrical characteristics (carrier mobility, etc.) by avoiding the introduction of cracks, local cracks, etc. due to differences in various characteristics and mechanical damage to the SOI layer. It is to provide an SOI substrate having a layer.
本発明は、このような課題を解決するために、請求項1に記載の発明は、SOI基板の製造方法であって、単結晶シリコン基板である第1の基板の表面側に水素イオン注入層を形成する第1のステップと、透明絶縁性基板である第2の基板の表面及び前記第1の基板の表面の少なくとも一方に表面活性化処理を施す第2のステップと、前記第1の基板の表面と前記第2の基板の表面とを貼り合わせる第3のステップと、前記張り合わせた基板の前記第1の基板の裏面を200℃以上350℃以下の温度に保持された加熱板に密着させて前記第1の基板を加熱し、該第1の基板からシリコン層を剥離して前記第2の基板の表面上にSOI層を形成する第4のステップと、を備えていることを特徴とする。 In order to solve such problems, the present invention provides a method for manufacturing an SOI substrate, wherein a hydrogen ion implanted layer is formed on a surface side of a first substrate which is a single crystal silicon substrate. A second step of performing a surface activation process on at least one of the surface of the second substrate which is a transparent insulating substrate and the surface of the first substrate, and the first substrate. A third step of bonding the surface of the first substrate and the surface of the second substrate, and the back surface of the first substrate of the bonded substrate is brought into close contact with a heating plate maintained at a temperature of 200 ° C. or higher and 350 ° C. or lower. And a fourth step of heating the first substrate and peeling the silicon layer from the first substrate to form an SOI layer on the surface of the second substrate. To do.
請求項2に記載の発明は、請求項1に記載のSOI基板の製造方法において、前記第2の基板は、石英基板、サファイア(アルミナ)基板、ホウ珪酸ガラス基板、又は結晶化ガラス基板の何れかであることを特徴とする。 According to a second aspect of the present invention, in the method for manufacturing an SOI substrate according to the first aspect, the second substrate is any one of a quartz substrate, a sapphire (alumina) substrate, a borosilicate glass substrate, and a crystallized glass substrate. It is characterized by.
請求項3に記載の発明は、請求項1または2に記載のSOI基板の製造方法において、前記第1のステップの水素イオンの注入量(ドーズ量)は、1×1016〜5×1017atoms/cm2であることを特徴とする。 According to a third aspect of the present invention, in the method for manufacturing an SOI substrate according to the first or second aspect, a hydrogen ion implantation amount (dose amount) in the first step is 1 × 10 16 to 5 × 10 17. It is characterized by atoms / cm 2 .
請求項4に記載の発明は、請求項1乃至3の何れか1項に記載のSOI基板の製造方法において、前記第2のステップの表面活性化処理は、プラズマ処理又はオゾン処理の少なくとも一方で実行されることを特徴とする。 According to a fourth aspect of the present invention, in the method for manufacturing an SOI substrate according to any one of the first to third aspects, the surface activation treatment of the second step is at least one of plasma treatment or ozone treatment. It is executed.
請求項5に記載の発明は、請求項1乃至4の何れか1項に記載のSOI基板の製造方法において、前記第3のステップは、前記貼り合わせ後に、前記第1の基板と前記第2の基板を貼り合わせた状態で100〜350℃で熱処理するサブステップを備えていることを特徴とする。 According to a fifth aspect of the present invention, in the method for manufacturing an SOI substrate according to any one of the first to fourth aspects, the third step includes the first substrate and the second substrate after the bonding. And a sub-step of heat treatment at 100 to 350 ° C. in a state where the substrates are bonded together.
請求項6に記載の発明は、請求項1乃至5の何れか1項に記載のSOI基板の製造方法において、前記第4のステップで用いられる加熱板は、平滑面を有する半導体基板もしくはセラミック基板であることを特徴とする。 According to a sixth aspect of the present invention, in the method for manufacturing an SOI substrate according to any one of the first to fifth aspects, the heating plate used in the fourth step is a semiconductor substrate or a ceramic substrate having a smooth surface. It is characterized by being.
請求項7に記載の発明は、請求項1乃至6の何れか1項に記載のSOI基板の製造方法において、前記第4のステップは、前記第1の基板の加熱の前もしくは後に、前記水素イオン注入層の端部から剥離促進のための外部衝撃を付与するサブステップを備えていることを特徴とする。 The invention described in claim 7 is the method for manufacturing an SOI substrate according to any one of claims 1 to 6, wherein the fourth step is performed before or after the heating of the first substrate. A sub-step of applying an external impact for promoting peeling from an end of the ion implantation layer is provided.
本発明によれば、200℃以上350℃以下の温度に保持された加熱板に絶縁性基板と張り合わされた単結晶Si基板の裏面を密着させて、透明絶縁性基板との間に温度差を生じさせ、これにより両基板間で大きな応力を発生させてシリコン薄膜を剥離することとしたので、基板間の熱的諸特性の相違に起因する割れや局所的クラック等および機械的ダメージのシリコン基板の表面領域から剥離されるシリコン薄膜への導入が回避される。その結果、膜厚均一性、結晶性、電気的諸特性(キャリア移動度など)に優れたSOI層を有するSOI基板を提供することが可能となる。 According to the present invention, the back surface of the single crystal Si substrate bonded to the insulating substrate is brought into close contact with a heating plate maintained at a temperature of 200 ° C. or higher and 350 ° C. or lower, and a temperature difference is established between the transparent insulating substrate and the transparent insulating substrate. Since this caused a large stress between the two substrates to peel off the silicon thin film, the silicon substrate suffered from cracks, local cracks, etc. due to differences in thermal characteristics between the substrates and mechanical damage. Introduction into the silicon thin film that is peeled off from the surface region is avoided. As a result, it is possible to provide an SOI substrate having an SOI layer that is excellent in film thickness uniformity, crystallinity, and various electrical characteristics (such as carrier mobility).
以下に、図面を参照して本発明を実施するための最良の形態について説明する。 The best mode for carrying out the present invention will be described below with reference to the drawings.
図1は、本発明のSOI基板の製造方法のプロセス例を説明するための図で、図1(A)に図示された第1の基板10は単結晶Si基板、第2の基板20は石英基板、サファイア(アルミナ)基板、ホウ珪酸ガラス基板、結晶化ガラス基板などの透明絶縁性基板である。
FIG. 1 is a diagram for explaining a process example of a method for manufacturing an SOI substrate according to the present invention. The
ここで、単結晶Si基板10は、例えば、CZ法(チョクラルスキ法)により育成された一般に市販されているSi基板であり、その導電型や比抵抗率などの電気特性値や結晶方位や結晶径は、本発明の方法で製造されるSOI基板が供されるデバイスの設計値やプロセスあるいは製造されるデバイスの表示面積などに依存して適宜選択される。
Here, the single
なお、これらの基板の直径は同一であり、後のデバイス形成プロセスの便宜のため、透明絶縁性基板20にも単結晶Si基板10に設けられているオリエンテーション・フラット(OF)と同様のOFを設けておき、これらのOF同士を一致させて貼り合わせるようにすると好都合である。
Note that these substrates have the same diameter, and for the convenience of the subsequent device formation process, the transparent
先ず、第1の基板(単結晶Si基)10の表面に水素イオンを注入し、水素イオン注入層を形成する(図1(B))。このイオン注入面が後の「接合面(貼り合せ面)」となる。この水素イオン注入により、単結晶Si基板10の表面近傍の所定の深さ(平均イオン注入深さL)に均一なイオン注入層11が形成され、単結晶Si基板10の表面領域での平均イオン注入深さLに対応する領域には、当該領域に局在する「微小気泡層」が形成される(図1(C))。
First, hydrogen ions are implanted into the surface of the first substrate (single crystal Si group) 10 to form a hydrogen ion implanted layer (FIG. 1B). This ion-implanted surface becomes a later “bonding surface (bonding surface)”. By this hydrogen ion implantation, a uniform ion implantation layer 11 is formed at a predetermined depth (average ion implantation depth L) in the vicinity of the surface of the single
イオン注入層11の単結晶Si基板10表面からの深さ(平均イオン注入深さL)はイオン注入時の加速電圧により制御され、どの程度の厚さのSOI層を剥離させるかに依存して決定される。例えば、平均イオン注入深さLを0.5μm以下とし、イオン注入条件を、ドーズ量1×1016〜5×1017atoms/cm2、加速電圧50〜100keVなどとする。 The depth of the ion implantation layer 11 from the surface of the single crystal Si substrate 10 (average ion implantation depth L) is controlled by the acceleration voltage at the time of ion implantation, and depends on how thick the SOI layer is peeled off. It is determined. For example, the average ion implantation depth L is 0.5 μm or less, and the ion implantation conditions are a dose of 1 × 10 16 to 5 × 10 17 atoms / cm 2 and an acceleration voltage of 50 to 100 keV.
なお、Si結晶中へのイオン注入プロセスにおいて注入イオンのチャネリング抑制のために通常行われているように、単結晶Si基板10のイオン注入面に予め酸化膜等の絶縁膜を形成させておき、この絶縁膜を通してイオン注入を施すようにしてもよい。
In addition, an insulating film such as an oxide film is formed in advance on the ion implantation surface of the single-
このようにしてイオン注入層11を形成した単結晶Si基板10と透明絶縁性基板20のそれぞれの接合面に、表面清浄化や表面活性化などを目的としたプラズマ処理やオゾン処理を施す(図1(D))。なお、このような表面処理は、接合面となる表面の有機物除去や表面上のOH基を増大させて表面活性化を図るなどの目的で行われるものであり、単結晶Si基板10と透明絶縁性基板20の双方の接合面に処理を施す必要は必ずしもなく、何れか一方の接合面にのみ施すこととしてもよい。
Plasma treatment and ozone treatment for the purpose of surface cleaning, surface activation, and the like are performed on the bonding surfaces of the single
この表面処理をプラズマ処理により実行する場合には、予めRCA洗浄等を施した表面清浄な単結晶Si基板および/または透明絶縁性基板を真空チャンバ内の試料ステージに載置し、当該真空チャンバ内にプラズマ用ガスを所定の真空度となるように導入する。なお、ここで用いられるプラズマ用ガス種としては、単結晶Si基板の表面処理用として、酸素ガス、水素ガス、アルゴンガス、またはこれらの混合ガス、あるいは水素ガスとヘリウムガスの混合ガスなどがあり、単結晶Si基板の表面状態や目的などにより適宜変更され得る。 When performing this surface treatment by plasma treatment, a surface-clean single crystal Si substrate and / or a transparent insulating substrate that has been subjected to RCA cleaning or the like is placed on a sample stage in a vacuum chamber, and the inside of the vacuum chamber is The plasma gas is introduced to a predetermined degree of vacuum. Examples of the plasma gas used here include oxygen gas, hydrogen gas, argon gas, or a mixed gas thereof, or a mixed gas of hydrogen gas and helium gas, for surface treatment of a single crystal Si substrate. The surface condition and purpose of the single crystal Si substrate can be changed as appropriate.
また、当該表面処理が単結晶Si表面を酸化させることをも目的とするような場合には、少なくとも酸素ガスを含有するものをプラズマ用ガスとして用いる。なお、透明絶縁性基板として、石英基板などのようにその表面が酸化状態にあるものを用いる場合には、このようなプラズマ用ガス種の選定に特別な制限はない。プラズマ用ガスの導入後、100W程度の電力の高周波プラズマを発生させ、プラズマ処理される単結晶Si基板および/または透明絶縁性基板の表面に5〜10秒程度の処理を施して終了する。 When the surface treatment is intended to oxidize the single crystal Si surface, a gas containing at least oxygen gas is used as the plasma gas. Note that when a transparent insulating substrate such as a quartz substrate whose surface is in an oxidized state is used, there is no particular restriction on the selection of such a plasma gas species. After the introduction of the plasma gas, high-frequency plasma with a power of about 100 W is generated, the surface of the single crystal Si substrate and / or the transparent insulating substrate to be plasma-treated is subjected to treatment for about 5 to 10 seconds, and the process is terminated.
表面処理をオゾン処理で実行する場合には、予めRCA洗浄等を施した表面清浄な単結晶Si基板および/または透明絶縁性基板を酸素含有の雰囲気とされたチャンバ内の試料ステージに載置し、当該チャンバ内に窒素ガスやアルゴンガスなどのプラズマ用ガスを導入した後に所定の電力の高周波プラズマを発生させ、当該プラズマにより雰囲気中の酸素をオゾンに変換させ、処理される単結晶Si基板および/または透明絶縁性基板の表面に所定の時間の処理が施される。 When the surface treatment is performed by ozone treatment, a surface-cleaned single crystal Si substrate and / or a transparent insulating substrate that has been subjected to RCA cleaning or the like is placed on a sample stage in an oxygen-containing chamber. A high-frequency plasma having a predetermined power after introducing a plasma gas such as nitrogen gas or argon gas into the chamber, oxygen in the atmosphere is converted into ozone by the plasma, and a single crystal Si substrate to be processed; The surface of the transparent insulating substrate is treated for a predetermined time.
このような表面処理が施された単結晶Si基板10と透明絶縁性基板20の表面を接合面として密着させて張り合わせる(図1(E))。上述したように、単結晶Si基板10と透明絶縁性基板20の少なくとも一方の表面(接合面)は、プラズマ処理やオゾン処理などにより表面処理が施されて活性化しているために、室温で密着(貼り合せ)した状態でも後工程での機械的剥離や機械研磨に十分耐え得るレベルの接合強度を得ることができるが、より高い貼り合せ強度をもたせる場合には、図1(E)の「貼り合せ」に続いて、比較的低温で加熱して「接合処理」を施すサブステップを設けてもよい。
The single
このときの接合処理温度は、貼り合せに用いられる基板の種類に応じて適宜選択されるが、単結晶Si基板と張り合わされる基板が、石英基板、サファイア(アルミナ)基板、ホウ珪酸ガラス基板、又は結晶化ガラス基板などの透明絶縁性基板である場合には、350℃以下の温度、例えば100〜350℃の温度範囲とする。 The bonding processing temperature at this time is appropriately selected according to the type of the substrate used for bonding, but the substrate bonded to the single crystal Si substrate is a quartz substrate, a sapphire (alumina) substrate, a borosilicate glass substrate, Alternatively, in the case of a transparent insulating substrate such as a crystallized glass substrate, the temperature is set to 350 ° C. or lower, for example, a temperature range of 100 to 350 ° C.
単結晶Si基板と張り合わされる基板が透明絶縁性基板(特に石英基板)である場合に350℃以下の温度選択とするのは、単結晶Siと石英との熱膨張係数差と当該熱膨張係数差に起因する歪量、およびこの歪量と単結晶Si基板10ならびに透明絶縁性基板20の厚みを考慮したものである。単結晶Si基板10と透明絶縁性基板20の厚みが概ね同程度である場合、単結晶Siの熱膨張係数(2.33×10-6)と石英の熱膨張係数(0.6×10-6)の間に大きな差異があるために、350℃を超える温度で熱処理を施した場合には、両基板間の剛性差に起因して、熱歪によるクラックや接合面における剥離などが生じたり、極端な場合には単結晶Si基板や石英基板が割れてしまうということが生じ得る。このため、熱処理温度の上限を350℃と選択し、好ましくは100〜300℃の温度範囲で熱処理を施す。
When the substrate to be bonded to the single crystal Si substrate is a transparent insulating substrate (particularly a quartz substrate), the temperature selection of 350 ° C. or lower is selected because of the difference in thermal expansion coefficient between the single crystal Si and quartz and the thermal expansion coefficient. The amount of strain due to the difference and the thickness of the single
このような貼り合せ処理に続いて、張り合わされた基板の単結晶シリコン基板10の裏面をホットプレートなどの加熱板に密着させて加熱する(図1(F))。
Following such a bonding process, the back surface of the single
上述したように、水素のイオン注入により、平均イオン注入深さLに対応する領域に局在する「微小気泡層」が形成されるが、この「微小気泡層」には不対結合手をもつSi原子や高密度の「Si−H結合」が発生しており、「微小気泡層」内および当該領域近傍の元素の結合状態は局所的に脆弱化されている。従って、当該「微小気泡層」が形成された状態のイオン注入層11は、僅かな熱エネルギで「ヘキ開」が生じ易い状態となっている。 As described above, hydrogen ion implantation forms a “microbubble layer” localized in a region corresponding to the average ion implantation depth L, and this “microbubble layer” has a dangling bond. Si atoms and high-density “Si—H bonds” are generated, and the bonding state of elements in the “microbubble layer” and in the vicinity of the region is locally weakened. Therefore, the ion-implanted layer 11 in the state where the “microbubble layer” is formed is in a state where “opening” is likely to occur with a little heat energy.
これに加えて、シリコン結晶は透明性絶縁基板材料よりも熱膨張係数が大きいため、短時間の比較的低温での加熱によっても両基板間で大きな応力が発生して「ヘキ開」が生じ易い環境が得られる。 In addition, since silicon crystals have a larger coefficient of thermal expansion than transparent insulating substrate materials, even when heated at a relatively low temperature for a short time, a large stress is generated between the two substrates, and “open cleavage” tends to occur. The environment is obtained.
本発明においては、水素イオン注入された単結晶Si基板10のイオン注入層11内での局所的な化学結合の脆弱化、およびSi基板と透明絶縁性基板20の熱膨張係数の差異を利用して、比較的低温での短時間加熱により「ヘキ開」に必要な熱エネルギを付与してシリコン薄膜を剥離する。
In the present invention, the local chemical bond weakening in the ion implantation layer 11 of the single
図2は、シリコン薄膜剥離のための基板加熱の様子を説明するための概念図である。この図において、符号30が加熱部であり、この図では、ホットプレート31の上に平滑面を有する加熱板32を載せ、この加熱板32の平滑面を、透明絶縁性基板20と張り合わされた単結晶Si基板10の裏面に密着させるようにしている。加熱板32にはダミーのシリコン基板を用いているが、平滑面が得られやすいもの(半導体基板やセラミック基板)であれば特に材料的な制限はない。シリコーンゴムなども加熱板材料として用いることも可能ではあるが、耐熱温度は250℃程度と考えられるのでそれ以上の温度での使用には適さない。また、ホットプレート31の面が十分に平滑であれば特別に加熱板32を用いることなく、ホットプレート31そのものを「加熱板」としてもよい。
FIG. 2 is a conceptual diagram for explaining how the substrate is heated for peeling the silicon thin film. In this figure,
加熱板32の温度は200℃以上350℃以下の温度に保持され、この加熱板32に絶縁性基板20と張り合わされた単結晶Si基板10の裏面を密着させると熱伝導により単結晶Si基板10が加熱され、透明絶縁性基板20との間に温度差が生じる。上述したように、シリコン結晶の熱膨張係数は透明性絶縁基板に用いる材料の熱膨張係数よりも大きいため、張り合わされた状態の単結晶Si基板10が裏面から加熱されると、単結晶Si基板10側の急激な膨張によって両基板間で大きな応力が発生する。
The temperature of the
通常の拡散炉などを用いた加熱の場合には、張り合わされた状態の単結晶Si基板10と透明絶縁性基板20は同時加熱されるため、両基板間の熱膨張係数の差異に起因する応力が生じても、この応力によってシリコン薄膜の剥離が生じる前に応力緩和が生じてしまうが、上述したような加熱方法によれば、貼り合わせた基板が応力緩和する前に、急激な単結晶Si基板10の膨張によって水素イオン注入界面で剥離が生じることとなる。
In the case of heating using a normal diffusion furnace or the like, the single
ここで、加熱板32の温度を200℃以上350℃以下とするのは、200℃未満の温度ではシリコン薄膜の剥離に必要となる応力を得ることが困難となるためであり、350℃を越える温度とすると貼り合わせ基板の接合界面で割れが生じ易いためである。
Here, the reason for setting the temperature of the
なお、このような加熱板32によるシリコン薄膜の剥離プロセスの前あるいは後に、イオン注入層11の端部から剥離促進のための外部衝撃を付与するサブステップを設けるようにしてもよい。
In addition, before or after the peeling process of the silicon thin film by the
図3は、シリコン薄膜の剥離工程において外部衝撃を与える手法の例示のための概念図である。衝撃付与手法としては種々のものが考えられるが、例えば、ガスや液体などの流体をノズル40の先端部41からジェット状に噴出させて単結晶Siウエーハ10の側面から吹き付けることで衝撃を与えたり(図3(A))、あるいはブレード50の先端部51をイオン注入層の近傍領域に押し当てるなどして衝撃を付与する(図3(B))などの手法によることができる。
FIG. 3 is a conceptual diagram for illustrating a technique for applying an external impact in the silicon thin film peeling step. Various methods for applying the impact are conceivable. For example, a fluid such as a gas or a liquid is jetted from the
このように、上述のような熱処理を施すと、イオン注入層11中での不対結合手をもつSi原子の化学結合やSi−H結合の切断が生じ、結果として、単結晶Si基板10の表面近傍の所定の深さ(平均イオン注入深さL)に相当する位置の結晶面に沿って単結晶シリコンのバルク部13からのシリコン薄膜12の剥離が生じ(図1(G))、第2の基板20上にSOI層12が得られる(図1(H))。
As described above, when the heat treatment as described above is performed, a chemical bond of Si atoms having an unpaired bond in the ion-implanted layer 11 or a break of the Si—H bond occurs, and as a result, the single
本発明者らの実験によれば、300℃で3秒程度の基板加熱でシリコン薄膜の剥離を生じさせることができた。このようにして得られた剥離後のSOI層の表面は、局所的なシリコン薄膜の剥がれや剥離痕あるいは未転写領域といった欠陥もなく、極めて平坦な状態を呈している。剥離後のSOI層表面の10μm×10μmの領域を原子間力顕微鏡(AFM)で測定したところ、RMSの平均値は6nm以下と良好であった。 According to the experiments by the present inventors, the silicon thin film can be peeled off by heating the substrate at 300 ° C. for about 3 seconds. The surface of the SOI layer after peeling obtained in this way is in an extremely flat state without defects such as local peeling of the silicon thin film, peeling marks or untransferred areas. When an area of 10 μm × 10 μm on the surface of the SOI layer after peeling was measured with an atomic force microscope (AFM), the average value of RMS was as good as 6 nm or less.
このように、本発明においては、単結晶Si基板10と透明絶縁性基板20との接合工程およびSOI層の剥離工程の何れの工程においても、従来法のような高温処理や機械的剥離処理を必要とせず、しかも、一貫して低温(350℃以下)での処理が可能である。従来から知られているSOI基板の製造方法の多くは高温処理工程を備えているために、熱歪に起因して生じるクラックや剥離を回避するための特別の工夫が必要であったが、本発明の剥離プロセスは、高温処理および機械的剥離処理の何れをも必要としないため、膜厚均一性、結晶性、電気的諸特性(キャリア移動度など)に優れたSOI層を有するSOI基板を提供することが可能となることに加え、SOI基板の製造工程の安定化と簡易化の観点から極めて有利である。
As described above, in the present invention, the high temperature treatment and the mechanical peeling treatment as in the conventional method are performed in any of the bonding step between the single
本発明によれば、単結晶シリコン基板と透明絶縁性基板とを張り合わせてSOI基板を製造する工程において、基板間の熱的諸特性の相違に起因する割れや局所的クラック等および機械的ダメージのSOI層への導入を回避することが可能となる。その結果、膜厚均一性、結晶性、電気的諸特性(キャリア移動度など)に優れたSOI層を有するSOI基板を提供することが可能となる。 According to the present invention, in the process of manufacturing an SOI substrate by laminating a single crystal silicon substrate and a transparent insulating substrate, cracks, local cracks, and the like due to differences in thermal characteristics between the substrates and mechanical damage are prevented. It is possible to avoid introduction into the SOI layer. As a result, it is possible to provide an SOI substrate having an SOI layer that is excellent in film thickness uniformity, crystallinity, and various electrical characteristics (such as carrier mobility).
10 単結晶Si基板
11 イオン注入層
12 SOI層
13 バルク部
20 透明絶縁性基板
30 加熱部
31 ホットプレート
32 加熱板
40 ノズル
41 ノズル先端部
50 ブレード
51 ブレード先端部
DESCRIPTION OF
Claims (5)
単結晶シリコン基板である第1の基板の表面側に水素イオン注入層を形成する第1のステップと、
透明絶縁性基板である第2の基板の表面及び前記第1の基板の表面の少なくとも一方に表面活性化処理を施す第2のステップと、
前記第1の基板の表面と前記第2の基板の表面とを密着させた状態で100〜300℃の温度で熱処理して前記第1の基板と前記第2の基板とを貼り合わせる第3のステップ
前記張り合わせた基板の前記第1の基板の裏面を200℃以上350℃以下の温度に保持された加熱板に密着させて前記第1の基板を加熱し、該第1の基板からシリコン層を剥離して前記第2の基板の表面上にSOI層を形成する第4のステップと、を備え、
前記第2の基板は、石英基板、サファイア(アルミナ)基板、ホウ珪酸ガラス基板、又は結晶化ガラス基板の何れかである、
ことを特徴とするSOI基板の製造方法。 A method for manufacturing an SOI substrate by consistently performing only a low temperature treatment of 350 ° C. or lower ,
A first step of forming a hydrogen ion implanted layer on the surface side of the first substrate which is a single crystal silicon substrate;
A second step of performing a surface activation treatment on at least one of the surface of the second substrate which is a transparent insulating substrate and the surface of the first substrate;
A third heat treatment is performed at a temperature of 100 to 300 ° C. in a state where the surface of the first substrate and the surface of the second substrate are in close contact with each other to bond the first substrate and the second substrate together. Step The back surface of the first substrate of the bonded substrates is brought into close contact with a heating plate maintained at a temperature of 200 ° C. or higher and 350 ° C. or lower to heat the first substrate, and a silicon layer is formed from the first substrate. And a fourth step of peeling and forming an SOI layer on the surface of the second substrate ,
The second substrate is either a quartz substrate, a sapphire (alumina) substrate, a borosilicate glass substrate, or a crystallized glass substrate.
A method for manufacturing an SOI substrate, comprising:
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006031913A JP5064692B2 (en) | 2006-02-09 | 2006-02-09 | Manufacturing method of SOI substrate |
US12/161,819 US7977209B2 (en) | 2006-02-09 | 2007-02-08 | Method for manufacturing SOI substrate |
EP07713948.3A EP1983553B8 (en) | 2006-02-09 | 2007-02-08 | Method for manufacturing soi substrate |
KR1020087012517A KR20080100160A (en) | 2006-02-09 | 2007-02-08 | Method for manufacturing soi substrate |
PCT/JP2007/052232 WO2007091639A1 (en) | 2006-02-09 | 2007-02-08 | Method for manufacturing soi substrate |
US13/010,103 US20110111575A1 (en) | 2006-02-09 | 2011-01-20 | Method for manufacturing soi substrate |
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JP2006031913A JP5064692B2 (en) | 2006-02-09 | 2006-02-09 | Manufacturing method of SOI substrate |
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JP2007214304A JP2007214304A (en) | 2007-08-23 |
JP5064692B2 true JP5064692B2 (en) | 2012-10-31 |
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JP2006031913A Active JP5064692B2 (en) | 2006-02-09 | 2006-02-09 | Manufacturing method of SOI substrate |
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US (2) | US7977209B2 (en) |
EP (1) | EP1983553B8 (en) |
JP (1) | JP5064692B2 (en) |
KR (1) | KR20080100160A (en) |
WO (1) | WO2007091639A1 (en) |
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US9362439B2 (en) * | 2008-05-07 | 2016-06-07 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled shear region |
US20100044827A1 (en) * | 2008-08-22 | 2010-02-25 | Kinik Company | Method for making a substrate structure comprising a film and substrate structure made by same method |
US8133800B2 (en) * | 2008-08-29 | 2012-03-13 | Silicon Genesis Corporation | Free-standing thickness of single crystal material and method having carrier lifetimes |
US8551862B2 (en) * | 2009-01-15 | 2013-10-08 | Shin-Etsu Chemical Co., Ltd. | Method of manufacturing laminated wafer by high temperature laminating method |
FR2942910B1 (en) * | 2009-03-06 | 2011-09-30 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A HETEROSTRUCTURE TO REDUCE THE STRAIN STRENGTH OF THE DONOR SUBSTRATE |
JP2010278338A (en) * | 2009-05-29 | 2010-12-09 | Shin-Etsu Chemical Co Ltd | Sos substrate low in defect density in proximity of interface |
JP2010278341A (en) * | 2009-05-29 | 2010-12-09 | Shin-Etsu Chemical Co Ltd | Stuck sos substrate |
JP2010278337A (en) * | 2009-05-29 | 2010-12-09 | Shin-Etsu Chemical Co Ltd | Sos substrate reduced in surface defect density |
WO2011087789A2 (en) | 2009-12-22 | 2011-07-21 | Becton, Dickinson And Company | Methods for the detection of microorganisms |
JP5643509B2 (en) * | 2009-12-28 | 2014-12-17 | 信越化学工業株式会社 | SOS substrate manufacturing method with reduced stress |
FR2969664B1 (en) * | 2010-12-22 | 2013-06-14 | Soitec Silicon On Insulator | METHOD FOR CLEAVING A SUBSTRATE |
KR101273363B1 (en) * | 2012-02-24 | 2013-06-17 | 크루셜텍 (주) | Substrate for fabricating led module, and led module using the same, and method for fabricating the led module |
JP6137196B2 (en) * | 2012-12-07 | 2017-05-31 | 信越化学工業株式会社 | Interposer substrate and manufacturing method thereof |
FR3000092B1 (en) * | 2012-12-26 | 2015-01-16 | Commissariat Energie Atomique | CHLORINATED PLASMA SURFACE TREATMENT IN A BONDING PROCESS |
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-
2006
- 2006-02-09 JP JP2006031913A patent/JP5064692B2/en active Active
-
2007
- 2007-02-08 WO PCT/JP2007/052232 patent/WO2007091639A1/en active Application Filing
- 2007-02-08 EP EP07713948.3A patent/EP1983553B8/en active Active
- 2007-02-08 US US12/161,819 patent/US7977209B2/en active Active
- 2007-02-08 KR KR1020087012517A patent/KR20080100160A/en not_active Application Discontinuation
-
2011
- 2011-01-20 US US13/010,103 patent/US20110111575A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
EP1983553B1 (en) | 2013-11-06 |
US20110111575A1 (en) | 2011-05-12 |
EP1983553B8 (en) | 2014-02-19 |
EP1983553A1 (en) | 2008-10-22 |
KR20080100160A (en) | 2008-11-14 |
JP2007214304A (en) | 2007-08-23 |
EP1983553A4 (en) | 2010-12-22 |
US20100227452A1 (en) | 2010-09-09 |
US7977209B2 (en) | 2011-07-12 |
WO2007091639A1 (en) | 2007-08-16 |
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