JP5045334B2 - Cash system - Google Patents

Description

  The present invention relates to a cache system.

  In general, in a computer system, a small-capacity and high-speed cache memory is provided separately from the main memory. By copying a part of the information stored in the main memory to the cache, when accessing this information, it is possible to read the information at a high speed by reading from the cache instead of the main memory.

  The cache includes a plurality of cache lines, and information is copied from the main memory to the cache in units of cache lines. The memory space of the main memory is divided in units of cache lines, and the divided memory areas are sequentially assigned to the cache lines. Since the capacity of the cache is smaller than the capacity of the main memory, the memory area of the main memory is repeatedly assigned to the same cache line.

  When the first access is executed to an address in the memory space, the information (data or program) at that address is copied to the corresponding cache line in the cache. When executing the next access to the same address, information is read directly from the cache. Generally, out of all bits of the address, a predetermined number of lower bits serve as a cache index, and the remaining bits positioned higher than that serve as a cache tag.

  When accessing the data, the tag of the corresponding index in the cache is read using the index portion in the address indicating the access destination. It is determined whether or not the read tag matches the bit pattern of the tag portion in the address. If they do not match, a cache miss occurs. If they match, a cache hit occurs, and the cache data corresponding to the index (data of a predetermined number of bits for one cache line) is accessed.

  A cache configuration in which only one tag is provided for each cache line is called a direct mapping method. A cache configuration in which N tags are provided for each cache line is called an N-way set associative. The direct mapping method can be regarded as a one-way set associative.

  In order to reduce the penalty for accessing the main memory when a cache miss occurs, a system in which the cache memory is hierarchized is used. For example, by providing a secondary cache that can be accessed faster than the main memory between the primary cache and the main memory, the frequency at which access to the main memory is required when a cache miss occurs in the primary cache. Can be reduced to reduce the cache miss penalty.

  Conventionally, in a processor, the processing speed has been improved by improving the operating frequency and improving the architecture. However, in recent years, a technical limit has begun to appear when the frequency is further increased, and there is a strong movement toward improving the processing speed by a multiprocessor configuration using a plurality of processors.

  A system having a plurality of processors can be realized by providing a plurality of existing single processor cores each having a cache and simply connecting them. Such a configuration can keep the design cost low, but there are problems with cache usage efficiency and cache consistency.

  The following patent document 1 is a method for managing replacement of data stored in a plurality of cache buffers, each of which exists on a certain node in a set of one or more nodes. Each node in the set of one or more nodes includes one or more caches of the plurality of caches, the plurality of caches includes a first cache, and the method is based on one or more factors. Selecting a first buffer for replacement from the first cache based on the first buffer, wherein the first buffer is currently being used to store a first data item and the one or more The factors include either the state of at least one other cache among the plurality of caches, or the configuration of the at least one other cache among the plurality of caches. Further comprising the step of replacing the first of the stored in the buffer the first data item and the second data item, the method has been described.

  Further, in Patent Document 2 below, in a buffer storage device that copies and stores a part of data in a main storage device in units of blocks, and determines a block to be replaced when a new block is stored by the LRU method, A block of the storage device is divided into a plurality of groups, and a means for determining a replacement block by the LRU method is provided for each group, and a flag bit that indicates which group is to be replaced is provided. An LRU control method for a buffer storage device is described in which flag bits are provided in triplicate and a majority vote is taken at the time of reading.

  In Patent Document 3 below, a plurality of processor modules including a CPU having a CPU cache and a CPU-SC interface control unit having a CPU cache duplication tag memory, and a main memory are connected to a system connection (SC). And a CPU cache replication tag memory of the CPU-SC interface control unit is set by setting the CPU cache of the CPU as a set associative with the number of sets k and the number of ways w. A cache configuration method is described in which a set associative of a number k and a number of ways w + α is used.

Japanese translation of PCT publication No. 2004-511840 JP 59-003773 A JP 2002-55880 A

  An object of the present invention is to provide a cache system capable of efficiently transferring data between a plurality of caches when a plurality of caches are connected to a plurality of processing devices on a one-to-one basis.

  A cache system according to the present invention includes a plurality of processing devices, a plurality of caches connected to the plurality of processing devices on a one-to-one basis, and a controller connected to the plurality of caches and controlling data transfer between the plurality of caches. And an information memory for storing first information indicating an entry in its own cache and the order of use of other caches for each of the processing devices.

  By using the first information, data can be efficiently transferred between a plurality of caches, and an increase in traffic can be prevented.

  FIG. 14 is a diagram illustrating a configuration example of a shared distributed cache system. This shared distributed cache system is connected to a plurality of cores (processors: processing devices) 101 to 103, a plurality of caches (cache memories) 111 to 113 corresponding to the plurality of cores 101 to 103, and caches 111 to 113. And an inter-cache connection controller (ICC) 120 and a main memory 130. Each of the cores 101 to 103 can access caches (self core cache) 111 to 113 directly connected to the cores 101 to 113 as primary caches. This shared distributed cache system is further configured so that a cache of another core (another core cache) can be accessed as a secondary cache. That is, for example, when viewed from the core 101, the cache 111 can be accessed as a primary cache, and the caches 112 and 113 can be accessed as secondary caches. A path for accessing such a secondary cache is provided via the inter-cache connection controller 120. The inter-cache connection controller 120 has LRU information 1400. LRU means “Least Recent Used”, and LRU information is information that identifies the longest unused one. Specifically, the LRU information for a plurality of entries is information indicating the order of use of the plurality of entries (the order of least used).

  For example, the core 101 makes a load request to the own core cache 111 and reads data from the own core cache 111 when a cache hit occurs. If a cache miss occurs, the secondary cache 112 or 113 is accessed. For example, if a cache hit occurs in the secondary cache 112, a cache line data exchange process is performed between the primary cache 111 and the secondary cache 112 as in process 1411. When a cache miss occurs in the secondary caches 112 and 113, the data in the main memory 130 is copied to the primary cache 111 for the cache line by the processing 1412 and the data is output to the core 101. At that time, the cache line evicted from the primary cache 111 by the process 1413 is moved to the secondary cache 112.

  When the other core cache 112 or 113 is hit, if the LRU information 1400 of the hit entry is not the latest, the exchange process 1411 is always performed. However, in this case, the exchange process 1411 occurs even when the entry is not used much, and traffic increases. As a result, the operation of the system is lowered, and it is necessary to reduce the traffic.

  Further, when the number of cores 101 to 103 is increased, the number of bits of the LRU information 1400 is increased because more other core caches are used as lower layer caches. Therefore, a countermeasure for preventing an increase in the number of bits of the LRU information 1400 is desired.

  FIG. 15 is a diagram illustrating a configuration example of another shared distributed cache system. Hereinafter, the points of FIG. 15 different from FIG. 14 will be described. The LRU information 1500 corresponds to the LRU information 1400 in FIG. The first LRU information 1501 indicates the oldest order of the entries a, b, and c in the cache 111, “0” being the oldest and “2” indicating the latest. The first LRU information 1502 indicates the oldest order of entries a, b, and c in the cache 112. First LRU information 1503 indicates the oldest order of entries a, b, and c in the cache 113. When the first LRU information 1501 to 1503 is encoded by the binary relation method, each becomes 3 bits. The second LRU information 1509 indicates the oldest order of entries in the three caches 111 to 113 as a whole. When the second LRU information 1509 is encoded by the order relation method, it becomes 18 bits. Therefore, the LRU information 1500 is 3 + 3 + 3 + 18 = 27 bits. Thereby, the cache lines of the caches 111 to 113 of all the cores can be regarded as one large cache and the complete oldest relationship can be maintained.

  FIG. 16 is a flowchart showing cache entry eviction processing in the shared distributed cache system of FIG. Any one of the plurality of cores 101 to 103 issues an access request to a cache (self-core cache) directly connected to itself, first makes a cache miss in the self-core, and further caches in a lower level cache. When the data needs to be read from the main memory 130 and allocated to the own core, the operation of the flowchart of FIG. 16 is executed. Here, the data read source read by the operation of the flowchart of FIG. 16 is not necessarily the main memory 130. The inter-cache connection controller 120 tiers the cache by accessing the caches 111 to 113 according to the priority order, but is managed as a management unit separate from the cache under the hierarchical cache. The memory becomes the reading source. If the main memory 130 is located immediately below the hierarchical cache, the data read destination is the main memory 130. Hereinafter, the case of the main memory 130 will be described as an example.

  In step S <b> 11, one of the cores 101 to 103 transmits an access destination address (for example, a read destination address) to the inter-cache connection controller 120 in order to access the main memory 130. In step S12, the second LRU information 1509 is referenced to search for the oldest entry in the caches 111 to 113 as a whole among the entries of the index corresponding to the access destination.

  In step S13, it is determined whether the oldest entry as a whole is in its own core cache (cache corresponding to the core that issued the access request). If the oldest entry in total exists in the own core cache, the first LRU information 1501 to 1503 and the second LRU information 1509 are updated in step S14. That is, the first LRU information 1501-1503 is updated so that the oldest entry becomes the latest entry in the own core cache, and the second LRU information so that the oldest entry becomes the latest entry as a whole. 1509 is updated. Thereafter, in step S17, the data read from the main memory 130 is overwritten on the oldest entry (the entry updated to the latest entry by the LRU update) in the own core cache.

  If it is determined in step S13 that the oldest entry does not exist in the own core cache as a whole, the first LRU information 1501-1503 and the second LRU information 1509 are updated in step S15. In other words, the first LRU information of the own core cache is updated so that the oldest entry in the own core cache becomes the latest entry, and the entry evicted from the own core cache (evicted entry) in the destination cache The first LRU information in the destination cache is updated so that the oldest entry (the oldest entry as a whole) matches the oldest entry in the eviction entry. Also, the second LRU information 1509 is updated so that the oldest entry as a whole becomes an entry in the order matching the oldest entry of the eviction entry, and the oldest entry becomes the latest entry in the own core cache.

  Thereafter, in step S16, the oldest entry in the own core cache is transferred (moved) to the oldest entry as a whole. Finally, in step S17, the data read from the main memory 130 is overwritten on the oldest entry (entry updated to the latest entry by LRU update) in the own core cache.

  However, the system replacement operation determination method of FIG. 14 has a problem that the traffic becomes large and the operation of the system may be reduced. In addition, the LRU encoding method of the system of FIG. 15 is general, but does not fully utilize the characteristics unique to the shared distributed cache. Also, in order to use more other core caches as lower layer caches when the number of cores has increased, a method for suppressing an increase in the number of bits of LRU information with respect to the increase in other core caches is required. Hereinafter, in the embodiment of the present invention, means for solving the above problems will be described.

  FIG. 1 is a diagram showing a configuration example of a shared distributed cache system according to an embodiment of the present invention. This shared distributed cache system has three cores (processors: processing devices) 101 to 103, three three-way primary caches 111 to 113 corresponding to the three cores 101 to 103, and caches 111 to 113. And an inter-cache connection controller (ICC) 120 connected to the main memory (or secondary cache) 130. Each of the cores 101 to 103 can access a cache (own core cache) directly connected to itself as an upper layer cache. This shared distributed cache system is further configured so that a cache of another core (another core cache) can be accessed as a lower hierarchy cache. That is, for example, when viewed from the core 101, the cache 111 can be accessed as an upper hierarchy cache, and the other core caches 112 and 113 can be accessed as lower hierarchy caches. A path for accessing such a lower hierarchy cache is provided via the inter-cache connection controller 120.

  The inter-cache connection controller 120 includes an information memory that stores the first LRU information 121 to 123 and the second LRU information 129. The information memory may be outside the inter-cache connection controller 120. The first LRU information 121 indicates the oldest order of the entries a, b, and c of the cache 111 and the group x of the other core caches 112 and 113, with “0” indicating the oldest and “2” indicating the latest. That is, the first LRU information 121 is LRU information obtained by adding n (= 1) other core cache groups x to the three entries a, b, and c of the own cache 111.

  FIG. 2 is a diagram showing details of the first LRU information 121 to 123 and the second LRU information 129 of FIG. Similar to the first LRU information 121, the first LRU information 122 indicates the oldest order of the entries a, b, and c of the cache 112 and the group x of the other core caches 111 and 113. Similarly to the first LRU information 121, the first LRU information 123 also indicates the oldest order of the entries a, b, and c of the cache 113 and the group x of the other core caches 111 and 112. When the first LRU information 121 to 123 is encoded by the binary relation method, each becomes 6 bits.

  The core 101 is the core A, and the cache 111 is the cache A. The core 102 is the core B, and the cache 112 is the cache B. The core 103 is the core C, and the cache 113 is the cache C.

  The second LRU information 129 indicates the usage order of the caches 111 to 113 among the three cores 101 to 103, A is the LRU information of the cache A (111), and B is the cache B (112). LRU information, and C is the LRU information of the cache C (113). When the second LRU information 129 is encoded by the binary relation method, it becomes 3 bits. Therefore, the sum of the LRU information 121 to 123 and 129 is 6 + 6 + 6 + 3 = 21 bits, which is smaller than the number of bits of the system of FIG. The information memory of the first LRU information 121 to 123 holds the first LRU information 121 to 123 for each cache on the assumption that the other core cache group is increased by one way in the local LRU information of each of the caches 111 to 113. To do.

  FIG. 3 is a diagram showing another configuration example of the shared distributed cache system according to the embodiment of the present invention. Hereinafter, the points of FIG. 3 different from FIG. 1 will be described. The shared distributed cache system includes six cores 101 to 106, six primary caches 111 to 116 corresponding to the six cores 101 to 106, and an inter-cache connection controller connected to the caches 111 to 116. (ICC) 120 and main memory (or secondary cache) 130 are included. The caches 111 to 114 and 116 are 3 ways, and the cache 115 is 2 ways. Each of the cores 101 to 106 can access the own core caches 111 to 116 as an upper hierarchy cache. This shared distributed cache system is further configured so that the other core cache can be accessed as a lower hierarchy cache. That is, for example, when viewed from the core 101, the cache 111 can be accessed as a higher-level cache, and the group x of the other core caches 112 and 113, the group y of the other core caches 114 and 115, and the other core cache 116 The group z is configured to be accessible as a lower hierarchy cache.

  The inter-cache connection controller 120 includes an information memory that stores the first LRU information 121 to 126 and the second LRU information 129. The first LRU information 121 indicates the earliest order of the entries a, b, and c of the cache 111, the group x of the other core caches 112 and 113, the group y of the other core caches 114 and 115, and the other core cache 116 group z. , “0” indicates the oldest and “5” indicates the latest. That is, the first LRU information 121 is LRU information obtained by adding n (= 3) other core cache groups x, y, and z to the three entries a, b, and c of the own cache 111. .

  FIG. 4 is a diagram showing details of the first LRU information 121 to 126 and the second LRU information 129 of FIG. Similarly to the first LRU information 121, the first LRU information 122 includes the entries a, b, c, n (= 3) of the other core caches 111 and 113 of the cache 112, the group x of the other core caches 114, and the other core cache 114. , 115 of group y, and the oldest order of group z of other core cache 116. The first LRU information 123 includes entries a, b, c and n (= 3) of the cache 113, the group x of the other core caches 111 and 112, the group y of the other core caches 114 and 115, and the other core cache 116. Indicates the oldest order of group z. The first LRU information 124 includes the entries a, b, c and n (= 2) of the cache 114, the group x of the other core caches 111 and 112, and the oldest group y of the other core caches 113, 115 and 116. Indicates the order. The first LRU information 125 includes two entries a and b in the cache 115, group x of n (= 3) other core caches 111 and 112, group y of other core caches 113 and 114, and other core caches. 116 shows the oldest order of 116 groups z. The first LRU information 126 includes entries a, b, c and n (= 3) of the cache 116, the group x of the other core caches 111 and 112, the group y of the other core caches 113 and 114, and the other core cache 115. Indicates the oldest order of group z. The combination of groups can be determined arbitrarily.

  When the first LRU information 121 to 123, 126 is encoded by the binary relation method, each becomes 15 bits. Since the first LRU information 124 includes information on two other core cache groups x and y, the first LRU information 124 becomes 10 bits when encoded by the binary relational method. Since the first LRU information 125 includes information on two entries a and b in the cache 115, the first LRU information 125 becomes 10 bits when encoded by the binary relation method.

  The core 101 is the core A, and the cache 111 is the cache A. The core 102 is the core B, and the cache 112 is the cache B. The core 103 is the core C, and the cache 113 is the cache C. The core 104 is the core D, and the cache 114 is the cache D. The core 105 is the core E, and the cache 115 is the cache E. The core 106 is the core F, and the cache 116 is the cache F.

  The second LRU information 129 indicates the used order of the caches 111 to 116 among the six cores 101 to 106, A is the LRU information of the cache A (111), and B is the cache B (112). LRU information of the cache C (113), D is LRU information of the cache D (114), E is LRU information of the cache E (115), and F is LRU information of the cache F (116). When the second LRU information 129 is encoded by the binary relation method, it becomes 15 bits. Therefore, the sum of the LRU information 121 to 126, 129 is 15 + 15 + 15 + 10 + 10 + 15 + 15 = 95 bits, and when the number of cores is large, the effect of reducing the number of bits is great.

  FIG. 5 is a flowchart showing a data load access operation in the shared distributed cache system according to the present embodiment. Hereinafter, the system of FIG. 1 will be described as an example. In step S1, first, any one of the plurality of cores 101 to 103 issues a load request to a cache (own core cache) directly connected to itself.

  In step S2, the cache that has received the load request determines whether or not the requested data exists in the cache, that is, whether or not it is a cache hit. If it is a cache hit, in step S3, the requested data is read from the own core cache, and the data is returned to the core that issued the load request.

  If there is a cache miss in step S2, the process proceeds to step S4. In step S4, it is determined whether or not a lower hierarchy cache exists under the cache in which a cache miss is detected. For example, when a cache miss is detected in step S2 and the process proceeds to step S4, the cache in which the cache miss is detected is any one of the caches 111 to 113. In this case, the other two caches are in the lower level. It exists as a hierarchical cache. If a lower hierarchy cache exists, the process proceeds to step S5.

  In step S5, the cache hierarchy accesses the other core cache one level below. In step S6, the cache that has received the access request determines whether or not the requested data exists in the cache, that is, whether or not it is a cache hit. If it is a cache miss, the process returns to step S4 and the above processing is repeated.

  If it is a cache hit in step S6, the process proceeds to step S7. In step S7, cache data exchange processing is performed. That is, the cache line to be accessed (data to be accessed) is moved from the cache hit to the own core cache, and the data is returned to the core. At this time, as the cache line moves to the own core cache, the cache line evicted from the own core cache is moved to another core. Details of step S7 will be described later with reference to FIG.

  If it is determined in step S4 that there is no lower hierarchy cache, the process proceeds to step S8. For example, when a cache miss is detected in step S6 and the process proceeds to step S4, if the cache in which this cache miss is detected is already the lowermost cache, only the main memory 130 exists in the lower layer. In such a case, in step S8, the requested data is read from the main memory 130, allocated to the own core cache (the requested data for one cache line is copied to the own core cache), and a load request is issued. Return data to the issued core. Further, the cache line evicted from the own core cache as a result of this operation is moved to, for example, a lower hierarchy cache. Details of step S8 will be described later with reference to FIG.

  In the above operation flow, step S7 is an operation related to data transfer between the cache and the cache, and step S8 is an operation related to data transfer between the main memory 130 and the cache.

  FIG. 6 is a flowchart showing the exchange process in step S7 of FIG. First, in step A1, it is determined that another core cache that can be used as a lower hierarchy cache has been hit by the determination in step S6 of FIG.

  Next, in step A2, the inter-cache connection controller 120 performs a determination process. That is, whether the condition that the first LRU information of the local core local of the group to which the hit other core cache belongs is the latest and the entry of the first LRU information of the hit other core cache is not the latest is satisfied Determine whether or not. If the condition is satisfied, the process proceeds to step A4. If the condition is not satisfied, the process proceeds to step A7.

  In step A4, the inter-cache connection controller 120 performs exchange processing between the own core cache and the other core cache. That is, the oldest entry in the own core cache and the hit entry in the other core cache are exchanged.

  Next, in step A5, the inter-cache connection controller 120 performs LRU update processing. That is, for the first LRU information of the own core, the exchanged entry of the own core cache is updated to the latest, and for the first LRU information of the other core, the exchanged entry of the other core cache is updated the oldest. The second LRU information is updated so that the own core cache becomes the latest. Then, it progresses to step A6 and complete | finishes a process.

  In step A7, the self-core performs a reference process via the inter-cache connection controller 120. That is, it directly refers to (reads out) the entry hit in the other core cache.

  Next, in step A3, the inter-cache connection controller 120 performs LRU update processing. That is, for the first LRU information of the own core, the group to which the hit other core cache belongs is updated to the latest, and for the first LRU information of the other core, 2 if the entry of the hit other core cache is the latest. The second LRU information is updated so that the hit other core cache becomes the latest. Then, it progresses to step A6 and complete | finishes a process.

  7 to 9 are diagrams illustrating an example of the exchange process of FIG. 6 in the system of FIGS. 1 and 2. FIG. 7 shows an initial state. The first LRU information 121 to 123 and the second LRU information 129 indicate that 0 is the oldest and newer as the value increases.

  First, the case where the entry c of the cache B (112) of the other core B (102) is hit from the own core A (101) in step A1 will be described.

  Next, in step A2, the first LRU information 121 of the own core local of the group x to which the hit other core cache B (112) belongs is 1 and is not the latest, so the process proceeds to step A7. In step A7, the entry c hit in the other core cache B (112) is directly referenced.

  Next, in step A3, as shown in FIG. 8, for the first LRU information 121 of the own core A (101), the group x to which the hit other core cache B (112) belongs is updated (value “3”). ), The entry c of the other core cache B (112) that has been hit is the latest (value “3” in FIG. 7) for the first LRU information 122 of the other core B (102). The new entry x is updated to be exchanged, and the second LRU information 129 is updated so that the hit other core cache B (112) becomes the latest. Then, it progresses to step A6 and complete | finishes a process.

  Next, the case where the entry c of the cache B (112) of the other core B (102) is hit again from the own core A (101) in step A1 will be described.

  Next, in Step A2, the first LRU information 121 of the own core local of the group x to which the hit other core cache B (112) belongs is the latest (value “3”), and the hit other core cache Since the entry c of the first LRU information 122 of B (112) is not the latest (value “2”), the process proceeds to step A4. In step A4, the oldest entry b in the own core cache A (111) and the hit entry c in the other core cache B (112) are exchanged.

  Next, in step A5, as shown in FIG. 9, for the first LRU information 121 of the own core A (101), the exchanged entry b of the own core cache A (111) is updated to the latest, and the other cores For the first LRU information 122 of B (102), the exchanged entry c of the other core cache B (112) is updated to the oldest, and for the second LRU information 129, the own core cache A (111) is the latest Update to be Then, it progresses to step A6 and complete | finishes a process.

  As described above, when the entry c of the other core cache B is hit at the first time, the replacement process is not performed, and when the entry c of the other core cache B is hit at the second time, the replacement process is performed. , Useless exchange processing can be eliminated and traffic can be reduced. In other words, efficient exchange processing can be performed by exchanging only the entry c that is continuously accessed by the own core A and that is currently not frequently used in the hit other core cache B.

  Next, the exchange process will be described by taking the system of FIGS. 3 and 4 as an example. Similarly to the above, an example of operation when the first time is not exchanged and the second time is exchanged is shown.

The initial first and second LRU information is shown below. The first and second LRU information indicate entries in the order of old → new.
Core A first LRU information 121: bxaczy
Core B first LRU information 122: abxzyc
Core C first LRU information 123: bxczya
Core D first LRU information 124: abcxy
Core E first LRU information 125: abxyz
Core F first LRU information 126: abcxyz
Second LRU information 129: CBFADE

First, in step A1, an entry c in the cache B of the core B is hit from the core A.
In step A2, since the entry x of the cache A is not the latest, it is not exchanged.
In step A7, direct reference is made.
In step A3, the entry x of the cache A is updated to the latest, the entry c of the cache B is updated second to the first LRU information corresponding to each of the cores A and B, and the cache B is updated. The second LRU information 129 is updated so that
The process ends at step A6.

Below, the 1st and 2nd LRU information after an update is shown. The first and second LRU information indicate entries in the order of old → new.
Core A first LRU information 121: baczyx
Core B first LRU information 122: abxzcy
Core C first LRU information 123: bxczya
Core D first LRU information 124: abcxy
Core E first LRU information 125: abxyz
Core F first LRU information 126: abcxyz
Second LRU information 129: CFADEB

Next, in step A1, the entry c of the cache B of the core B is hit again from the core A.
In step A2, since the entry x of the cache A is the latest and the entry c of the cache B is not the latest, they are exchanged.
In step A4, the entry b in the cache A and the entry c in the cache B are exchanged.
In step A5, the first LRU information corresponding to each of core A and core B is updated with the latest entry b of cache A and the oldest entry c of cache B by the LRU update process, and cache A is the latest. The second LRU information 129 is updated so that
The process ends at step A6.

Below, the 1st and 2nd LRU information after an update is shown. The first and second LRU information indicate entries in the order of old → new.
Core A first LRU information 121: aczyxb
Core B first LRU information 122: cabxzy
Core C first LRU information 123: bxczya
Core D first LRU information 124: abcxy
Core E first LRU information 125: abxyz
Core F first LRU information 126: abcxyz
Second LRU information 129: CFDEBA

  As described above, when the other core cache is hit, the replacement operation determination is that the hit entry is frequently used by the own core, and the other core having the entry is frequently used at the same time in time. When the condition that no access is made is satisfied, it is determined that the exchange process is performed.

  FIG. 10 is a flowchart showing the eviction process in step S8 of FIG. First, in step B1, it is determined that all other core caches that can be used as the lower hierarchy cache have missed by the determination in step S4 of FIG.

  Next, in step B2, the inter-cache connection controller 120 performs a determination process. That is, referring to the second LRU information, it is determined whether or not the self-core satisfies the condition that it is not the most recently used core of the index. If the condition is satisfied, the process proceeds to step B4. If the condition is not satisfied, the process proceeds to step B7.

  In step B4, the inter-cache connection controller 120 performs an eviction process from the own core cache to another core cache. That is, the oldest entry of the own core cache (the oldest entry among those not including the other core group entry) is moved to the oldest entry of the other core cache that has not been used most recently.

  Next, in step B5, the inter-cache connection controller 120 performs LRU update processing. That is, the oldest entry of the own core cache is updated to the latest for the first LRU information of the own core, and the oldest entry of the other core cache to be evicted is updated to the latest for the first LRU information of the other core. The second LRU information is updated so that its own core cache is the latest and the other core cache of the eviction destination is the second most recent. Then, it progresses to step B6.

  In step B7, the inter-cache connection controller 120 performs a discard process. That is, the oldest entry in the own core cache is discarded. Specifically, nothing is processed in this step, and the oldest entry in the own core cache is discarded by the overwrite process in the subsequent step B6.

  Next, in step B3, the inter-cache connection controller 120 performs LRU update processing. That is, for the first LRU information of the own core, the oldest entry in the own core cache is updated to the latest, and the second LRU information is updated to be the latest. Then, it progresses to step B6.

  In step B6, the inter-cache connection controller 120 overwrites the data read from the main memory 130 on the oldest entry (the latest entry after the LRU information update) of the own core cache, and the own core acquires the data. Thus, the process ends.

  11 to 13 are diagrams illustrating an example of the eviction process of FIG. 10 in the system of FIGS. 1 and 2. FIG. 11 shows an initial state. The first LRU information 121 to 123 and the second LRU information 129 indicate that 0 is the oldest and newer as the value increases.

  First, in step B1, the case where the access of the own core A (101) misses in all other core caches will be described.

  Next, in step B2, when referring to the second LRU information 129, since the own core cache A (111) has not been used most recently, the process proceeds to step B3 via step B7.

  In step B3, as shown in FIG. 12, for the first LRU information 121 of the own core A (101), the oldest entry b of the own core cache A (111) is updated to the latest, and the second LRU information 129 is updated. Is updated so that its own core cache A becomes the latest.

  Next, in step B6, the data read from the main memory 130 is overwritten on the oldest entry (latest entry after updating the LRU information) b of the own core cache A (111). The process ends here.

  Next, the case where the access of the own core A (101) misses in all other core caches again in step B1 will be described.

  Next, in step B2, referring to the second LRU information 129, the other core cache C (113) has not been used most recently, so the process proceeds to step B4.

  In step B4, the oldest entry b of the own core cache A (111) is included in the oldest entry b of the other core cache C (113) that has not been used most recently (the oldest entry among those not including the other core group entry). Move a.

  Next, in step B5, as shown in FIG. 13, for the first LRU information 121 of the own core A (101), the oldest entry a of the own core cache A (111) is updated to the latest, and the other core C For the first LRU information 123 of (103), the oldest entry b of the other core cache C (113) to be evicted is updated to the latest, and for the second LRU information 129, the own core cache A (111) is the latest Then, the other core cache C (113) of the eviction destination is updated so as to be the second newest.

  Next, in step B6, the data read from the main memory 130 is overwritten on the oldest entry (latest entry after updating the LRU information) a of the own core cache A (111). The process ends here.

  As described above, if all other core caches miss in the first time, the eviction process is not performed, and if the other core cache misses in the second time, the eviction process is performed, so that unnecessary eviction is performed. Processing can be eliminated and traffic can be reduced. In other words, efficient eviction processing can be performed by performing eviction processing only when the own core A continuously misses the cache and the other core cache is the oldest.

  Next, the eviction process will be described using the system of FIGS. 3 and 4 as an example. In the same manner as described above, an operation example in the case where the first time is not driven and the second time is driven is shown.

The initial first and second LRU information is shown below. The first and second LRU information indicate entries in the order of old → new.
Core A first LRU information 121: bxaczy
Core B first LRU information 122: abxzyc
Core C first LRU information 123: bxczya
Core D first LRU information 124: abcxy
Core E first LRU information 125: abxyz
Core F first LRU information 126: abcxyz
Second LRU information 129: ACBFDE

First, in step B1, the access of core A misses in all other core caches.
In step B2, since the own core A has not been accessed most recently from the second LRU information 129, it is not evicted.
In step B3, the entry B of the cache A is updated to the latest, the first LRU information corresponding to the core A is updated by the LRU update process, and the second LRU information 129 is updated so that the cache A is the latest.
In step B6, the entry b in the cache A is overwritten.

Below, the 1st and 2nd LRU information after an update is shown. The first and second LRU information indicate entries in the order of old → new.
Core A first LRU information 121: xaczyb
Core B first LRU information 122: abxzyc
Core C first LRU information 123: bxczya
Core D first LRU information 124: abcxy
Core E first LRU information 125: abxyz
Core F first LRU information 126: abcxyz
Second LRU information 129: CBFDEA

Next, in step B1, the access of core A misses again in all other core caches.
In step B2, eviction occurs from the second LRU information 129 because the other core has not been accessed most recently.
In step B4, the entry b of the cache A and the entry b of the cache C are exchanged.
In step B5, the LRU update process updates the entry b of the cache A to the latest, updates the entry b of the cache C to the latest, and updates the first LRU information corresponding to each of the cores A and C. The second LRU information 129 is updated so that the cache C is the second most recent.
In step B6, the entry b in the cache A is overwritten.

Below, the 1st and 2nd LRU information after an update is shown. The first and second LRU information indicate entries in the order of old → new.
Core A first LRU information 121: xaczyb
Core B first LRU information 122: cabxzy
Core C first LRU information 123: xczyab
Core D first LRU information 124: abcxy
Core E first LRU information 125: abxyz
Core F first LRU information 126: abcxyz
Second LRU information 129: BFDECA

  As described above, in the eviction operation determination, the second LRU information 129 is evacuated to the oldest core. In the present embodiment, the second LRU information 129 holds only the latest access, but it may hold the complete oldest order. The reason for retaining only the latest access is to reduce the number of bits. In addition, when the second LRU information 129 is updated, the eviction destination core is updated to the second most recent one, and the eviction destination is carried around, so that it is possible to suppress the performance degradation compared to the case where the complete oldest order is maintained. .

  The occurrence probability of the cache line exchange traffic in the system of FIG. 14 is (the number of ways of all caches−1) / (the number of ways of all caches). For example, in the case of a 3-way 4-core, it is 11/12. Even if an entry that the core does not access frequently is exchanged unless it is the latest, the exchange traffic is large.

  In contrast, the probability of occurrence of cache line exchange traffic in the system of the present embodiment is (1 / (the number of ways of all caches + n)) × ((the number of ways of caches) / (the number of ways of caches + n)). . For example, in the case of 3 ways, 4 cores and n = 1, (1/4) × (3/4) = 3/16. Since only the entries that are continuously accessed by the own core and that are not currently used in the hit other core cache are exchanged, the exchange traffic is reduced.

Further, the LRU information in the system of FIG. 15 has the following number of bits according to (first LRU information) + (second LRU information).
3-way 4-core: 3 × 4 + 2 × 12 = 36 bits 4-way 4-core: 6 × 4 + 2 × 16 = 56 bits 3-way 8-core: 3 × 8 + 2 × 24 = 106 bits 4-way 8-core: 6 × 8 + 3 × 32 = 144 bits

On the other hand, the LRU information of the present embodiment has the following number of bits according to (first LRU information) + (second LRU information).
3-way 4-core: 6 × 4 + 6 = 30 bits 4-way 4-core: 10 × 4 + 6 = 46 bits 3-way 8-core: 6 × 8 + 28 = 76 bits 4-way 8-core: 10 × 8 + 28 = 108 bits

  In the present embodiment, the number of bits of LRU information can be reduced. In particular, when the number of cores or the number of ways increases, the effect of reducing the number of bits is large.

  As described above, the cache system according to the present embodiment includes, for example, a plurality of processing devices (cores) 101 to 103 and a plurality of processing devices 101 to 103 connected one-on-one to each other, as shown in FIG. Caches 111 to 113, a controller 120 that is connected to the plurality of caches 111 to 113 and controls data transfer between the plurality of caches 111 to 113, and an entry in the own cache for each processing device and other caches And an information memory for storing first information 121 to 123 indicating the order of use age.

  For example, as shown in FIG. 6 to FIG. 9, when the data requested by the processing apparatus 101 misses in its own cache 111 and hits in another cache 112, the controller 120 sends the first information 121. Based on this, the entry of the own cache 111 and the entry of the other hit cache 112 are exchanged.

  As shown in FIG. 2, the first information 121 to 123 includes one entry x in which entries a, b and c in its own cache and a plurality of other caches are grouped for each of the processing devices 101 to 103. This is information indicating the order of use. Further, as shown in FIG. 4, the first information 121 to 126 includes a plurality of entries in which entries a, b, and c in the own cache and a plurality of other caches are grouped for each of the processing devices 101 to 106. This is information indicating the order of use of entries x, y, and z.

  For example, as shown in FIGS. 6 to 9, when the data requested by the processing device 101 misses in its own cache 111 and hits in another cache 112, the controller 120 determines that the other caches When the grouped entry x is up-to-date, the entry of its own cache 111 and the entry of the other cache 112 that has been hit are exchanged.

  More specifically, when the data requested by the processing device 101 misses in its own cache 111 and hits in another cache 112, the controller 120 is an entry in which the plurality of other caches are grouped. When x is the latest and the entry c of the other hit cache 112 is not the latest, the entry b of the own cache 111 and the entry c of the other hit cache 112 are exchanged.

  The first information 121 to 123 is an entry x in which the plurality of other caches are grouped when the data requested by the processing device 101 misses in its own cache 111 and hits in another cache 112. Is not the latest, or the entry c of the other hit cache 112 is the latest, the entry c of the other hit cache 112 is the latest in the processing device 102 corresponding to the other hit cache 112. In some cases, the entry c is updated in the second most recent order, and the second new entry x is updated in the most recent order.

  As shown in FIG. 2, the information memory stores second information 129 indicating the order of use with respect to its own cache among the plurality of processing apparatuses 101 to 103.

  For example, as shown in FIGS. 10 to 13, when the data requested by the processing device 101 misses in all of the plurality of caches 111 to 113, the controller 120 determines that the controller 120 is based on the second information 129. The entry a of the cache 111 is moved to the entry b of the other cache 123, and the data read from the main memory (main memory) or the cache (secondary cache) 130 at a lower hierarchy than the plurality of caches is moved. The entry a of the cache 111 is overwritten.

  More specifically, when the data requested by the processing device 101 misses in all of the plurality of caches 111 to 113, the controller 120 uses the cache 111 most recently. When the processing device is not a non-processing device, the entry a of the own cache 111 is moved to the entry b of the other cache 113, and the data read from the main storage device or the cache 130 at a lower hierarchy than the plurality of caches is moved. Overwrite entry a in its own cache 111.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

  The embodiment of the present invention can be applied in various ways as follows, for example.

(Appendix 1)
A plurality of processing devices;
A plurality of caches connected one-to-one to the plurality of processing devices;
A controller connected to the plurality of caches for controlling data transfer between the plurality of caches;
A cache system comprising: an information memory for storing an entry in its own cache and first information indicating the order of use of other caches for each processing device.
(Appendix 2)
The controller, when the data requested by the processing device misses in its own cache and hits in another cache, based on the first information, the entry in the own cache and the other cache hit The cache system according to appendix 1, wherein the entries are exchanged.
(Appendix 3)
The first information is information indicating an order of use of one or a plurality of entries in which an entry in its own cache and a plurality of other caches are grouped for each processing device. 1. The cache system according to 1.
(Appendix 4)
When the data requested by the processing unit misses in its own cache and hits in another cache, when the entry into which the plurality of other caches are grouped is the latest, the controller 4. The cache system according to appendix 3, wherein a cache entry and the hit other cache entry are exchanged.
(Appendix 5)
When the data requested by the processing device misses in its own cache and hits in another cache, the controller has the latest entry in which the other caches are grouped, and the other hit 4. The cache system according to claim 3, wherein when the cache entry is not up-to-date, the entry of the own cache and the entry of the other hit cache are exchanged.
(Appendix 6)
In the first information, when the data requested by the processing device misses in its own cache and hits in another cache, an entry in which the plurality of other caches are grouped is not the latest, or When the entry of the other hit cache is the latest, when the entry of the other hit cache is the latest in the processing device corresponding to the other hit cache, the entry is updated in the second newest order. The cache system according to appendix 5, wherein the second newest entry is updated in the latest order.
(Appendix 7)
2. The cache system according to claim 1, wherein the information memory stores second information indicating an order of use with respect to the own cache among the plurality of processing devices.
(Appendix 8)
When the data requested by the processing device misses in all of the plurality of caches, the controller moves the cache entry to another cache entry based on the second information, and the main storage device Alternatively, the cache system according to appendix 7, wherein data read from a cache lower than the plurality of caches is overwritten on the entry of the moved own cache.
(Appendix 9)
The controller, when the data requested by the processing device misses in all of the plurality of caches, when the requested processing device is not the processing device that has not used the cache most recently, The cache according to appendix 8, wherein the entry is moved to an entry in another cache, and the data read from the main storage device or a cache in a lower hierarchy than the plurality of caches is overwritten on the moved cache entry. system.

It is a figure which shows the structural example of the shared distributed cache system by embodiment of this invention. It is a figure which shows the detail of the 1st LRU information and 2nd LRU information of FIG. It is a figure which shows the other structural example of the shared distributed cache system by embodiment of this invention. It is a figure which shows the detail of the 1st LRU information and 2nd LRU information of FIG. It is a flowchart which shows the data load access operation | movement in the shared distributed cache system by this embodiment. It is a flowchart which shows the exchange process of FIG.5 S7. It is a figure which shows the example of the exchange process of FIG. 6 in the system of FIG.1 and FIG.2. It is a figure which shows the example of the exchange process of FIG. 6 in the system of FIG.1 and FIG.2. It is a figure which shows the example of the exchange process of FIG. 6 in the system of FIG.1 and FIG.2. It is a flowchart which shows the eviction process of step S8 of FIG. It is a figure which shows the example of the eviction process of FIG. 10 in the system of FIG.1 and FIG.2. It is a figure which shows the example of the eviction process of FIG. 10 in the system of FIG.1 and FIG.2. It is a figure which shows the example of the eviction process of FIG. 10 in the system of FIG.1 and FIG.2. It is a figure which shows the structural example of a shared distributed cache system. It is a figure which shows the structural example of another shared distributed cache system. It is a flowchart which shows the cache entry eviction process in the shared distributed cache system of FIG.

Explanation of symbols

101-103 core (processing equipment)
111 to 113 cache 120 inter-cache connection controllers 121 to 123 first LRU information 129 second LRU information 130 main memory

Claims (5)

A plurality of processing devices;
A plurality of caches connected one-to-one to the plurality of processing devices;
A controller connected to the plurality of caches for controlling data transfer between the plurality of caches;
A cache system comprising: an information memory for storing an entry in its own cache and first information indicating the order of use of other caches for each processing device.   The controller, when the data requested by the processing device misses in its own cache and hits in another cache, based on the first information, the entry in the own cache and the other cache hit 2. The cache system according to claim 1, wherein the entries are exchanged.   The first information is information indicating an order of use of one or a plurality of entries in which an entry in its own cache and a plurality of other caches are grouped for each processing device. Item 3. The cache system according to item 1 or 2.   4. The cache system according to claim 1, wherein the information memory stores second information indicating an order of use with respect to a cache of the cache among the plurality of processing devices. 5. .   When the data requested by the processing device misses in all of the plurality of caches, the controller moves the cache entry to another cache entry based on the second information, and the main storage device 5. The cache system according to claim 4, wherein data read from a cache lower than the plurality of caches is overwritten on the entry of the moved own cache.

Images