JP5039058B2 - 半導体素子の実装構造体 - Google Patents
半導体素子の実装構造体 Download PDFInfo
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- JP5039058B2 JP5039058B2 JP2008551119A JP2008551119A JP5039058B2 JP 5039058 B2 JP5039058 B2 JP 5039058B2 JP 2008551119 A JP2008551119 A JP 2008551119A JP 2008551119 A JP2008551119 A JP 2008551119A JP 5039058 B2 JP5039058 B2 JP 5039058B2
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- substrate
- semiconductor chip
- mounting structure
- semiconductor element
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
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Description
複数の基板電極を有する基板と、
上記それぞれの素子電極と基板電極とを接続する複数の突起電極と、
上記それぞれの素子電極、基板電極、及び突起電極を封止するとともに、上記半導体素子と上記基板とを接着させるように、上記半導体素子と上記基板との間に配置された封止接着用樹脂と、
上記基板の電極形成面において、上記半導体素子の外周端部に対向する位置に形成され、その内側の一部に上記封止接着用樹脂が配置された凹部とを備える、半導体素子の実装構造体を提供する。
上記半導体素子を上記基板に上記封止接着用樹脂を介して押圧して、上記半導体素子のそれぞれの素子電極と上記基板のそれぞれの基板電極とを、それぞれの突起電極を介して接続するとともに、上記実装領域外へ拡がる上記封止接着用樹脂の一部を上記凹部内へ導いて、上記樹脂の拡がり領域を規制しながら、上記それぞれの素子電極、基板電極、及び突起電極を上記樹脂により封止し、
その後、上記封止接着用樹脂を加熱して硬化させて、上記半導体素子を上記基板に実装することを特徴とする半導体素子の実装方法を提供する。
本発明の第1の実施形態にかかる半導体素子の実装構造体の一例である半導体チップの実装構造体1の模式断面図を図1に示す。
なお、本発明は上記実施形態に限定されるものではなく、その他種々の態様で実施できる。例えば、本発明の第2の実施形態にかかる半導体素子の実装構造体の一例である半導体チップの実装構造体31の模式断面図を図6に示す。なお、図6の半導体チップの実装構造体31において、上記第1実施形態の実装構造体1と同じ構成の部材には同じ参照番号を付してその説明を省略する。
次に、本発明の第3の実施形態にかかる半導体チップの実装構造体71の模式断面図を図10に示す。図10に示すように、本第3実施形態の半導体チップの実装構造体71は、図6に示す上記第2実施形態の実装構造体31と同じ凹部38の配置構成を有するものの、基板4における実装領域の略中央付近に他の表面よりも隆起された隆起部79が形成されている点において、図6の構成とは相違している。
次に、本発明の第4の実施形態にかかる半導体チップの実装構造体として、凹部の平面的な配置構成の様々な形態について説明する。本第4実施形態にかかる半導体チップの実装構造体101、111、121、及び131の模式平面図を、図11〜図14に示す。なお、以下の説明においては、凹部の平面的な配置構成について行うものとし、凹部の断面的な形状については、上記第1実施形態から第3実施形態までの構成が適用される。
次に、本発明の第5の実施形態にかかる半導体チップの実装構造体201の模式平面図を図20に示す。また、図20の半導体チップの実装構造体201のB−B線断面図を図21に示し、C−C線断面図を図22に示す。
Claims (5)
- 複数の素子電極を有する半導体素子と、
複数の基板電極を有する基板と、
上記それぞれの素子電極と基板電極とを接続する複数の突起電極と、
上記それぞれの素子電極、基板電極、及び突起電極を封止するとともに、上記半導体素子と上記基板とを接着させるように、上記半導体素子と上記基板との間に配置された封止接着用樹脂と、
上記基板の電極形成面において、上記半導体素子の外周端部に対向する位置に形成され、その内側の一部に上記封止接着用樹脂が配置された凹部と、
上記凹部の内底部の下部に配置された加工用の停止層とを備え、
上記凹部は、上記基板における上記半導体素子との対向領域の周囲に向けて深くなるように傾斜された内底部を有し、
略方形状の形状を有する上記半導体素子の角部に対向する位置に形成される上記凹部は、その他の位置に形成される上記凹部の上記内底部の傾斜角度よりも大きな傾斜角度を有する上記内底部を有するように形成されている、半導体素子の実装構造体。 - 上記凹部は、上記基板における上記半導体素子との対向領域の外周端部よりも内側の領域を含んで形成されている、請求項1に記載の半導体素子の実装構造体。
- 上記基板における上記半導体素子との対向領域の中心に上記凹部の開口端部よりも隆起された隆起部が形成され、上記隆起部より上記凹部の内底部にかけて降り勾配が設けられている、請求項1または2に記載の半導体素子の実装構造体。
- 略方形状の形状を有する上記半導体素子の角部に対向する位置に形成される上記凹部は、その他の位置に形成される上記凹部よりもその内側の容積が小さくなるように形成されている、請求項1から3のいずれか1つに記載の半導体素子の実装構造体。
- 略方形状の形状を有する上記半導体素子の角部に対向する位置に形成される上記凹部は、その他の位置に形成される上記凹部よりも深い内底部を有するように形成されている、請求項1から3のいずれか1つに記載の半導体素子の実装構造体。
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JP5210839B2 (ja) * | 2008-12-10 | 2013-06-12 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP5017399B2 (ja) * | 2010-03-09 | 2012-09-05 | 株式会社東芝 | 半導体発光装置および半導体発光装置の製造方法 |
US9484279B2 (en) * | 2010-06-02 | 2016-11-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die |
US8536718B2 (en) | 2010-06-24 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit packaging system with trenches and method of manufacture thereof |
JP5246215B2 (ja) * | 2010-07-21 | 2013-07-24 | 株式会社村田製作所 | セラミック電子部品及び配線基板 |
US8617926B2 (en) * | 2010-09-09 | 2013-12-31 | Advanced Micro Devices, Inc. | Semiconductor chip device with polymeric filler trench |
US8546957B2 (en) | 2010-12-09 | 2013-10-01 | Stats Chippac Ltd. | Integrated circuit packaging system with dielectric support and method of manufacture thereof |
CN102563557B (zh) * | 2010-12-30 | 2016-08-17 | 欧司朗股份有限公司 | 用于灯条的封装方法 |
TW201246501A (en) * | 2011-01-27 | 2012-11-16 | Panasonic Corp | Substrate with though electrode and method for producing same |
US9355924B2 (en) * | 2012-10-30 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit underfill scheme |
US9368422B2 (en) * | 2012-12-20 | 2016-06-14 | Nvidia Corporation | Absorbing excess under-fill flow with a solder trench |
US9437520B2 (en) * | 2013-03-13 | 2016-09-06 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device including a semiconductor element and a fixed member to which the semiconductor element is fixed |
CN104112739A (zh) * | 2013-04-16 | 2014-10-22 | 展晶科技(深圳)有限公司 | 发光二极管 |
CN104112806A (zh) * | 2013-04-17 | 2014-10-22 | 展晶科技(深圳)有限公司 | 发光二极管及其封装结构 |
CN103325702A (zh) * | 2013-07-04 | 2013-09-25 | 北京京东方光电科技有限公司 | 芯片的绑定方法及芯片绑定结构 |
JP6662002B2 (ja) * | 2015-11-27 | 2020-03-11 | 富士電機株式会社 | 半導体装置 |
JP2017120800A (ja) * | 2015-12-28 | 2017-07-06 | 富士通株式会社 | 半導体素子、半導体素子の製造方法及び電子機器 |
JP2017152484A (ja) * | 2016-02-23 | 2017-08-31 | 京セラ株式会社 | 配線基板 |
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US11676929B2 (en) | 2016-10-21 | 2023-06-13 | Sony Semiconductor Solutions Corporation | Electronic substrate and electronic apparatus |
US10910289B2 (en) | 2016-10-21 | 2021-02-02 | Sony Semiconductor Solutions Corporation | Electronic substrate and electronic apparatus |
JP6726821B2 (ja) * | 2017-01-10 | 2020-07-22 | 株式会社デンソー | 半導体装置の製造方法 |
DE112018005713T5 (de) * | 2017-10-30 | 2020-07-16 | Mitsubishi Electric Corporation | Leistungshalbleitereinheit und herstellungsverfahren für eine leistungshalbleitereinheit |
CN110349847B (zh) * | 2018-04-08 | 2022-11-04 | 上海新微技术研发中心有限公司 | 一种通过键合材料进行键合的方法和键合结构 |
JP6905958B2 (ja) * | 2018-06-27 | 2021-07-21 | 京セラ株式会社 | 接着構造、撮像装置、および移動体 |
JP7321009B2 (ja) * | 2019-07-01 | 2023-08-04 | 新光電気工業株式会社 | 配線基板、接合型配線基板及び配線基板の製造方法 |
US11778293B2 (en) * | 2019-09-02 | 2023-10-03 | Canon Kabushiki Kaisha | Mounting substrate to which image sensor is mounted, sensor package and manufacturing method thereof |
KR20210058165A (ko) * | 2019-11-13 | 2021-05-24 | 삼성전자주식회사 | 반도체 패키지 |
JP2022125682A (ja) * | 2021-02-17 | 2022-08-29 | レノボ・シンガポール・プライベート・リミテッド | 電子基板および電子機器 |
CN113038698B (zh) * | 2021-03-08 | 2022-09-09 | 京东方科技集团股份有限公司 | 柔性电路板、显示面板、制备方法和显示装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0451144U (ja) * | 1990-09-03 | 1992-04-30 | ||
JP2000165047A (ja) * | 1998-11-26 | 2000-06-16 | Nippon Carbide Ind Co Inc | プリント配線板の製造方法 |
JP2003051579A (ja) * | 2001-08-03 | 2003-02-21 | Hitachi Ltd | 電子機器の製造方法および加工システム |
JP2004214344A (ja) * | 2002-12-27 | 2004-07-29 | Nec Kansai Ltd | 固体撮像装置 |
JP2004266016A (ja) * | 2003-02-28 | 2004-09-24 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、及び半導体基板 |
JP2004289083A (ja) * | 2003-03-25 | 2004-10-14 | Matsushita Electric Ind Co Ltd | 電子部品実装用の基板および電子部品実装方法 |
JP2005109037A (ja) * | 2003-09-29 | 2005-04-21 | Sanyo Electric Co Ltd | 半導体装置 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0451144A (ja) | 1990-06-19 | 1992-02-19 | Toray Ind Inc | インドメチレン色素系記録材料 |
JP3233535B2 (ja) * | 1994-08-15 | 2001-11-26 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2858569B2 (ja) * | 1996-11-25 | 1999-02-17 | 日本電気株式会社 | チップ型デバイスの実装方法及びその実装方法により製造するデバイス |
JPH10270496A (ja) * | 1997-03-27 | 1998-10-09 | Hitachi Ltd | 電子装置、情報処理装置、半導体装置並びに半導体チップの実装方法 |
US6288451B1 (en) * | 1998-06-24 | 2001-09-11 | Vanguard International Semiconductor Corporation | Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength |
JP2000188362A (ja) | 1998-12-21 | 2000-07-04 | Kyocera Corp | 半導体素子の実装構造 |
JP2001035886A (ja) | 1999-07-23 | 2001-02-09 | Nec Corp | 半導体装置及びその製造方法 |
US6391683B1 (en) * | 2000-06-21 | 2002-05-21 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package structure and process for fabricating the same |
JP2002134558A (ja) | 2000-10-25 | 2002-05-10 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4963148B2 (ja) * | 2001-09-18 | 2012-06-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2003347460A (ja) | 2002-05-28 | 2003-12-05 | Kyocera Corp | 電子装置 |
TWI315094B (en) * | 2003-04-25 | 2009-09-21 | Advanced Semiconductor Eng | Flip chip package |
JP2004349399A (ja) | 2003-05-21 | 2004-12-09 | Nec Corp | 部品実装基板 |
US6939751B2 (en) * | 2003-10-22 | 2005-09-06 | International Business Machines Corporation | Method and manufacture of thin silicon on insulator (SOI) with recessed channel |
US7235431B2 (en) * | 2004-09-02 | 2007-06-26 | Micron Technology, Inc. | Methods for packaging a plurality of semiconductor dice using a flowable dielectric material |
US7148560B2 (en) * | 2005-01-25 | 2006-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | IC chip package structure and underfill process |
JP4551255B2 (ja) * | 2005-03-31 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4760361B2 (ja) | 2005-12-20 | 2011-08-31 | ソニー株式会社 | 半導体装置 |
JP2007189005A (ja) | 2006-01-12 | 2007-07-26 | Sharp Corp | 半導体装置の実装構造 |
-
2007
- 2007-12-25 WO PCT/JP2007/074844 patent/WO2008078746A1/ja active Application Filing
- 2007-12-25 JP JP2008551119A patent/JP5039058B2/ja not_active Expired - Fee Related
- 2007-12-25 CN CN2007800485532A patent/CN101578695B/zh not_active Expired - Fee Related
- 2007-12-25 US US12/521,020 patent/US8110933B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0451144U (ja) * | 1990-09-03 | 1992-04-30 | ||
JP2000165047A (ja) * | 1998-11-26 | 2000-06-16 | Nippon Carbide Ind Co Inc | プリント配線板の製造方法 |
JP2003051579A (ja) * | 2001-08-03 | 2003-02-21 | Hitachi Ltd | 電子機器の製造方法および加工システム |
JP2004214344A (ja) * | 2002-12-27 | 2004-07-29 | Nec Kansai Ltd | 固体撮像装置 |
JP2004266016A (ja) * | 2003-02-28 | 2004-09-24 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、及び半導体基板 |
JP2004289083A (ja) * | 2003-03-25 | 2004-10-14 | Matsushita Electric Ind Co Ltd | 電子部品実装用の基板および電子部品実装方法 |
JP2005109037A (ja) * | 2003-09-29 | 2005-04-21 | Sanyo Electric Co Ltd | 半導体装置 |
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CN101578695B (zh) | 2012-06-13 |
US20100025847A1 (en) | 2010-02-04 |
CN101578695A (zh) | 2009-11-11 |
WO2008078746A1 (ja) | 2008-07-03 |
US8110933B2 (en) | 2012-02-07 |
JPWO2008078746A1 (ja) | 2010-04-30 |
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