JP5037876B2 - Encryption processing apparatus and decryption processing apparatus - Google Patents

Description

  The present invention relates to a circuit for processing an encryption algorithm, and relates to a circuit configuration and a processing method for providing an encryption processing device and a decryption processing device that realize high-speed processing with a small circuit area.

Generally, in electronic commerce, network communication, etc., encrypted communication is performed to ensure safety.
For example, in a mobile phone system, authentication processing and encrypted communication are performed between a mobile terminal and a base station.
Also, in a system such as a VPN (Virtual Private Network) for ensuring safety between networks, encryption processing is performed in a device such as a router constituting the system.
In the apparatus mentioned as an example above, the processing performance and cost problems are solved by incorporating an arithmetic circuit exclusively for cryptographic processing into the apparatus.
For example, as a processing circuit for AES (Advanced Encryption Standard) encryption (FIPS-197), Japanese Patent Application Laid-Open No. 2004-233427 discloses an architecture that performs an operation with one S-box table (substitution table).
In Japanese Patent Application Laid-Open No. 2003-288209 and Japanese Patent Application Laid-Open No. 5-249891, high-speed processing is performed by inserting a latch for each stage function of the DES (Data Encryption Standard) cipher (FIPS46-3) and performing a pipeline operation. An architecture is disclosed.
JP 2004-233427 A JP 2003-288209 A JP-A-5-249891

Hereinafter, problems in the prior art will be described.
For example, in Japanese Patent Laid-Open No. 2004-233427, substitution processing that can be processed in one cycle is compared with a general architecture that implements a stage function in a cryptographic algorithm disclosed in Japanese Patent Laid-Open No. 2004-184567. Fewer bytes are possible, increasing the number of cycles required to process the entire cryptographic algorithm.
In addition, the architectures of Japanese Patent Application Laid-Open Nos. 2004-233427 and 2004-184567 require at least a circuit delay for substitution processing. For this reason, it can be said that the operating frequency is small in either architecture, and that Japanese Patent Laid-Open No. 2004-184567 with a small number of required cycles operates at a higher speed.
On the other hand, Japanese Patent Application Laid-Open No. 2004-184567 that implements all the stage functions requires a larger circuit area than Japanese Patent Application Laid-Open No. 2004-233427.
In addition, an architecture that inserts a latch for each stage function such as Japanese Patent Application Laid-Open No. 2003-28809 and Japanese Patent Application Laid-Open No. 5-249891 can operate at high speed, but it has a very large circuit area. I need.
Furthermore, it is assumed that multiple blocks of input data are processed in parallel as a condition for high-speed operation. In a system where multiple blocks of data are not input continuously, parallel processing cannot be performed and the speed-up effect is obtained. I can't.

  The present invention has been made in view of the technical problems as described above. The main object of the present invention is to achieve high-speed operation even in a system in which a plurality of blocks of data are not continuously input with a small circuit configuration. An object is to provide a possible encryption processing circuit and decryption processing circuit.

The cryptographic processing apparatus according to the present invention includes:
A cipher including a substitution processing unit for performing substitution processing by performing a plurality of internal processes on block data composed of a plurality of sub-block data, and a transposition processing unit for performing transposition processing by performing a plurality of internal processes A processing device comprising:
At least one of the substitution processing unit and the transposition processing unit performs pipeline processing in units of sub-block data to perform a plurality of internal processes, and a plurality of sub-block data included in the same block data And performing parallel processing.

The decryption processing device according to the present invention comprises:
Decoding includes a substitution processing unit that performs substitution processing by performing a plurality of internal processes on block data composed of a plurality of sub-block data, and a transposition processing unit that performs transposition processing by performing a plurality of internal processes A processing device comprising:
At least one of the substitution processing unit and the transposition processing unit performs pipeline processing in units of sub-block data to perform a plurality of internal processes, and a plurality of sub-block data included in the same block data And performing parallel processing.

  According to the present invention, pipeline processing in units of sub-block data can be performed in at least one of substitution processing and transposition processing, and parallel processing can be performed on a plurality of sub-block data included in the same block data. Therefore, high-speed operation is possible even in a system in which a plurality of block data are not continuously input with a small circuit configuration.

Embodiment 1 FIG.
Hereinafter, the present embodiment will be described with reference to the drawings.
FIG. 1 is a basic configuration diagram of an encryption processing circuit (encryption processing apparatus) taking AES encryption processing as an example.
Although FIG. 1 shows an encryption processing circuit, a decryption processing circuit can be realized with the same configuration. 2 and 3 have been described as the internal configuration of the encryption processing circuit, but can also be applied as the internal configuration of the decryption processing circuit.
In FIG. 1, the cryptographic processing circuit (100) has a port for input data and key data as external inputs, and a port for output data as external outputs.

The cryptographic processing circuit (100) includes a randomizing unit processing circuit (101) and an extended key generation unit processing circuit (102).
The extended key generation unit processing circuit (102) inputs the substitution processing input and the expansion key to the randomization unit processing circuit (101), and receives the substitution processing result that is the output of the randomization unit processing circuit (101).
The randomization unit processing circuit (101) is an example of a randomization processing unit, and the extended key generation unit processing circuit (102) is an example of an extended key generation processing unit.

FIG. 2 shows an internal configuration of the randomizing unit processing circuit (101).
The selector 1 (201) selects the input data and the output of the key addition circuit (212).
The data register (202) stores word data for every 32 bits, which is an output from the selector 1 (201), and outputs 128-bit block data.
The selector 2 (203) selects the output of the data register (202) for each word data.
The selector 3 (204) selects the word data that is the output of the selector 2 (203) for each byte data.
The selector 4 (205) selects the substitution processing input input from the output of the selector 3 (204) and the extended key generation unit processing circuit (102).
The substitution processing circuit (206) performs AES encryption SubByte processing. The substitution processing circuit (206) is an example of a substitution processing unit. The substitution processing circuit (206) includes a pipeline register (207) for time-sharing internal processes. In the example of FIG. 2, a four-stage pipeline register is included.
The intermediate register (208) stores byte data, which is an output of the substitution processing circuit (206), for each word data.
The transposition processing circuit (209) performs MixColumns and InvMixColumns processing in the substitution processing circuit (206) and the AES cipher. The transposition processing circuit (209) is an example of a transposition processing unit. The transposition processing circuit (209) includes a pipeline register (207) for time-sharing internal processes. In the example of FIG. 2, a two-stage pipeline register (207) is included.
The selector 5 (210) selects the output of the intermediate register (208) and the output of the selector 2 (203).
The selector 6 (211) selects the outputs of the transposition processing circuit (209) and the selector 5 (210).
The key addition circuit (212) performs AddRoundKey processing in AES encryption on the output of the selector 6 (211) and the expanded key.

FIG. 3 shows an internal configuration of the extended key generation unit processing circuit (102).
The selector 1 (301) selects the key data and the output of the selector 2 (305).
The key register (302) stores word data for every 32 bits, which is an output from the selector 1 (301), and outputs 128-bit key data.
The extended key generation circuit (303) performs a predetermined extended key generation process based on the output of the key register (302), the substitution processing output from the randomizing unit processing circuit (101), and the output of the extended key register (304).
The extended key register (304) stores 128-bit extended key block data generated by the extended key generation circuit (303).
The selector 2 (305) selects necessary word data from the output of the extended key register (304).
The transposition processing circuit (306) performs InvMixColumns processing in AES encryption. The transposition processing circuit (306) is an example of a transposition processing unit. The transposition processing circuit (306) includes a pipeline register (207) for time-sharing internal processes. In the example of FIG. 3, a two-stage pipeline register (207) is included.
The selector 3 (307) selects the output of the transposition processing circuit and the output of the selector 2.

In this embodiment, the cryptographic processing circuit (100) that processes the AES encryption is taken as an example.
FIG. 7 shows an outline of the AES encryption algorithm.
In the AES encryption algorithm, the randomizing unit processing circuit (101) performs encryption processing on 128-bit block data using the expanded key generated by the expanded key generation unit processing circuit (102).
First, plaintext block data is input while being divided into subblock data units, and an initialization process is performed by an EXOR operation of the subblock data and the expanded key. The sub-block data is word data or byte data. Depending on the target processing, it may be divided into word data or byte data.
Thereafter, in the randomizing unit processing circuit (101), the block data after the initialization processing is divided into sub-block data units, and the sub-byte data is subjected to SubByte processing (substitution processing), ShiftRows processing, MixColumns processing (transposition processing), and AddRoundKey processing using the extended key from the extended key generation unit processing circuit (102) is performed, and this is set as one round of encryption processing. This is repeated n rounds, and finally 128-bit ciphertext is created and output. The
Of these processes, the amount of calculation in the SubByte process (substitution process) and the MixColumns process (transposition process) is larger than that of the other processes, and the SubByte process (substitution process) and the MixColumns process (transposition process). Circuit delay becomes a problem.
In this embodiment, in the randomizing unit processing circuit (101) that performs processing including substitution processing and transposition processing, the circuit that performs substitution processing and transposition processing includes a pipeline register, and substitution processing is performed by pipeline processing in units of sub-block data. A plurality of internal processes in the processing and the transposition processing are performed, and parallel processing is performed on a plurality of sub-block data included in the same block data, thereby increasing the speed.
Further, in the extended key generation unit processing circuit (102) that performs processing including transposition processing on 128-bit extended key block data composed of a plurality of byte data, the circuit that performs the transposition processing includes a pipeline register, A plurality of internal processes in the transposition process are performed by pipeline processing in units of sub-block data, and parallel processing is performed on a plurality of sub-block data included in the same block data to increase the speed.

Next, the operation will be described.
4 and 5 are diagrams showing a processing flow of the cryptographic processing apparatus (100).
4 and 5, an example in which a 4-stage pipeline register (207) is mounted on the substitution processing circuit (206) and a 2-stage pipeline register (207) is mounted on the transposition processing circuit (209) will be described.
4 illustrates the 0th cycle to the 32nd cycle in the cryptographic processing circuit (100), and FIG. 5 illustrates the 184th cycle to the 212th cycle in the cryptographic processing circuit (100).

First, in the 0th cycle to the 3rd cycle, the input data (plain text data) from the input port of the cryptographic processing circuit (100) is sent to the data register via the selector 1 (201) of the randomizing unit processing circuit (101) for each word data. (202).
Next, as initialization processing in the AES cipher, in the 4th to 7th cycles, the 128-bit plaintext block data stored in the data register (202) is divided into word data, and the selector 2 (203), the selector AddRoundKey processing is performed for each word data in the key addition circuit (212) via 5 (210) and selector 6 (211). Further, the data subjected to AddRoundKey processing is stored as ciphertext block data in the data register (202) via the selector 1 (201).
At the same time, in the 4th to 7th cycles, the substitution processing input from the expanded key generation unit processing circuit (102) is sent to the substitution processing circuit (206) via the selector 4 (205) (for expanded key generation). (4) Perform substitution processing for 4 bytes.

Subsequently, the 128-bit ciphertext block data stored in the data register (202) from the 8th cycle to the 23rd cycle passes through the selector 2 (203), the selector 3 (204), and the selector 4 (205). In the substitution processing circuit (206), substitution processing (SubByte processing) is performed in units of byte data. As described above, in the substitution processing circuit (206), pipeline processing is performed using the pipeline register (207).
In the eighth to eleventh cycles, the processing result for the substitution processing performed in the fourth to seventh cycles is output from the substitution processing circuit (206) to the extended key generation unit processing circuit (102). In the extended key generation circuit (303) of the extended key generation unit processing circuit (102), KeyExpansion processing is performed for each byte data.
Subsequently, in the 12th to 14th cycles, the key expansion process for the remaining 3 words is performed by the extended key generation circuit (303) of the extended key generation unit processing circuit (102). The reason why the KeyExpansion process for the first word to the third word is completed in one cycle is that it is only necessary to perform an EXOR operation on the output of the KeyExpansion process for the 0th word.
Although not shown in FIGS. 4 and 5, after the key expansion process in the extended key generation circuit (303), the 128-bit extended key block data passes through the extended key register (304) and the selector 2 (305). Then, in the transposition processing circuit (306), the MixColumns processing (transposition processing) is performed for each word data, and the 32-bit extended key is passed through the selector 3 (307) to the key of the randomizing unit processing circuit (101). It is supplied to the addition circuit (212). In the transposition processing circuit (306), pipeline processing is performed using the pipeline register (207).

Further, in the 16th cycle, the 20th cycle, the 24th cycle, and the 28th cycle, the MixColumn processing is performed by the transposition processing circuit (209) on the data of the intermediate register (208) storing the output of the substitution processing circuit (206). .
As described above, in the transposition processing circuit (209), pipeline processing is performed using the pipeline register (207).
Then, an AddRoundKey process is performed in the key addition circuit (212) for each result after two cycles of the MixColumns process.
Thereafter, in the 24th and subsequent cycles, the processing in the second and subsequent rounds is performed in the same manner as in the first round.

Next, a method for updating the data register in the description related to the above operation will be described.
Input data d0_0, d0_1, d0_2,..., D0_f (1 byte each, total 128 bits (16 bytes)), every 4 bytes from the 0th cycle to the 3rd cycle ({d0_0, d0_1, d0_2, d0_3) }, {D0_4, d0_5, d0_6, d0_7}, {d0_8, d0_9, d0_a, d0_b}, {d0_c, d0_d, d0_e, d0_f}) are subjected to data storage processing.
Hereinafter, the processing result after N rounds in the AES algorithm is
dN_0, dN_1, dN_2, ..., dN_f
Is written.
At this time, the output data is
d11_0, d11_1, d11_2,..., d11_f (each 1 byte, total 128 bits (16 bytes))
It becomes.

From the 4th cycle to the 7th cycle, the selector 2 (203) fetches a total of 4 bytes {d0_0, d0_1, d0_2, d0_3} from the data register (202), and passes through the selector 5 (210) and selector 6 (211). The key addition circuit (212) performs exclusive OR processing with the extended key to calculate {d1_0, d1_1, d1_2, d1_3}.
Similarly, processing is also performed for {d0_4, d0_5, d0_6, d0_7},... (Total 4 cycles).
In the SubByte processing of the first round, d1_0 is input from the data register (202) to the substitution processing circuit (206) via the selector 2 (203) and the selector 3 (204). Subsequently, d1_5, d1_a, and d1_f are input to the substitution processing circuit (206) every cycle continuously in the next cycle.
Further subsequently, d1_4, d1_9, d1_e, d1_3
d1_8, d1_d, d1_2, d1_7
d1_c, d1_1, d1_6, d1_b
Are input to the substitution processing circuit.
In this way, the ShiftRows process is performed by changing the input order for the SubByte process.
Here, assuming that the pipeline register of the substitution processing circuit has four stages, the substitution processing circuit outputs a SubByte processing result after four cycles.
Hereinafter, the processing result is described as S (d1_0).
For the first round of MixColumns, S (d1_0) is stored in the most significant byte of the intermediate register. Thereafter, S (d1_5), S (d1_a), and S (d1_f) are sequentially stored in the lower byte. That is, the value of the intermediate register after three cycles from the storage of S (d1_0) is 4 bytes in total, S (d1_0) | S (d1_5) | S (d1_a) | S (d1_f).
The transposition processing circuit (209) performs MixColumns processing on the 4-byte value, and then, after two cycles, the key rounding circuit (212) performs AddRoundKey processing (key addition processing).
The results are d2_0, d2_1, d2_2, and d2_3, and d2_0, d2_1, d2_2, and d2_3 are re-stored in the register positions where d1_0, d1_5, d1_a, and d1_f are stored.
Thereafter, S (d1_4), S (d1_9), S (d1_e), S (d1_3)
S (d1_8), S (d1_d), S (d1_2), S (d1_7)
S (d1_c), S (d1_1), S (d1_6), S (d1_b)
The same processing is performed for.

SubByte processing and MixColumns processing after the second to ninth rounds are also performed in the same manner as the first round.
The 10th round SubByte processing is also performed in the same manner as the 1st round.
The intermediate register S (d10_0) | S (d10_5) | S (d10_a) | S (d10_f) in the tenth round passes the MixColumns process via the selector 5 (210) and the selector 6 (211), and the AddRoundKey process (key addition) Process) and re-store in the data register (202).
Finally, from the 209th cycle to the 212th cycle, the ciphertext block data stored in the data register (202) is output for each word data via the selector 2 (203).

In the present embodiment, unlike the prior art, the stage function circuit path defined by the algorithm is divided by a plurality of pipeline registers. For this reason, the circuit delay between the registers is smaller than that in the prior art, so that processing can be performed at a higher operating frequency.
In the case of FIG. 2, the circuit between the data register (202) and the intermediate register (208), which is expected to have the largest circuit delay, is divided into five by the pipeline register (207). The operating frequency can be improved by about 5 times compared to the conventional technology described.
Note that the above five divisions are (1) the first-stage pipeline register from the data register (202), (2) the second-stage pipeline register from the first-stage pipeline register, and (3) two-stage pipeline register. The pipeline register of the third stage from the pipeline register of the fourth stage, (4) the pipeline register of the fourth stage from the pipeline register of the third stage, and (5) the intermediate register (208) from the pipeline register of the fourth stage. It means 5 divisions.

Further, compared to the case where the pipeline register (207) is not used in the substitution processing circuit (206) or the transposition processing circuit (209), the number of cycles to be increased is only four cycles corresponding to the latency of the substitution processing circuit (206). Yes, considering the ratio of the total number of cycles, it is about 2%. From the above, the processing performance of the entire cryptographic processing is improved.
The circuit scale is about the increase of the pipeline register as compared with the prior art Japanese Patent Application Laid-Open No. 2004-233427, and Japanese Patent Application Laid-Open No. 2003-28809 and Japanese Patent Application Laid-Open No. 5-249891 that implement all the stage functions. It can be implemented on a small scale as compared with the implementation disclosed in.

In addition, all the processes in the present embodiment are time-sharing processes in one block data, and do not perform parallel processes on a plurality of block data inputs. Therefore, even in a system in which data is not continuously input, processing performance is improved.
That is, in the techniques of Japanese Patent Application Laid-Open Nos. 2003-288209 and 5-249891, pipeline processing is performed on a plurality of block data, and therefore, a plurality of block data must be input continuously. The parallel processing by the pipeline is not effective. In the present embodiment, in substitution processing and transposition processing, parallel processing is performed by pipeline for a plurality of sub-block data units for one block data, so even when a plurality of block data are not continuously input. , Processing performance is improved.

Finally, FIG. 6 shows a configuration example of the security chip 500 as a device using the above-described cryptographic processing circuit (100).
The security chip is assumed to be incorporated in communication devices such as small terminals such as mobile phones, IC cards, IC card readers / writers, and network routers.
A CPU (Central Processing Unit) (501) in FIG. 6 is a processor that executes a program for controlling input / output with respect to the cryptographic processing circuit (100) and control with a memory and an external interface.
A memory (502) includes a RAM (Random Access Memory) used as a work area of the CPU, and various programs include a ROM (Read Only Memory) that stores setting parameters and the like.
The external interface (503) is various interfaces such as serial communication and LAN (Local Area Network), and inputs / outputs data processed by the cryptographic processing circuit (100) to / from the security chip.

  In this embodiment, in a circuit that processes an encryption method including substitution processing and transposition processing on a plaintext block or ciphertext block composed of a plurality of byte data, a pipeline is connected to a circuit that performs substitution processing and transposition processing. An encryption processing circuit including a register and processing the plaintext and ciphertext in the same block in parallel in a time-sharing manner has been described.

  In the encryption processing circuit, the substitution processing circuit and the transposition processing circuit including the pipeline register perform time division processing on a plurality of byte data of the same block.

  In the cryptographic processing circuit, the substitution processing circuit including the pipeline register performs time-sharing processing on key information used in processing of the same block or information created based on the key information.

In this embodiment, the encryption processing circuit has been described. However, the configuration illustrated in FIGS. 1 to 3 and the operation illustrated in FIGS. 4 and 5 can be applied to a decryption processing circuit (decryption processing device).
That is, a substitution processing unit that performs substitution processing by performing a plurality of internal processes on block data composed of a plurality of sub-block data, and a transposition processing unit that performs transposition processing by performing a plurality of internal processes are included. And at least one of the substitution processing unit and the transposition processing unit performs pipeline processing in units of sub-block data and performs a plurality of internal processes, and is included in the same block data It is possible to realize a decoding processing device that performs parallel processing on a plurality of sub-block data.
The decryption processing apparatus includes a substitution processing unit that performs a plurality of internal processes on the ciphertext block data to perform a substitution process, and a transposition processing unit that performs a plurality of internal processes and performs a transposition process. A randomization processing unit, and in the randomization processing unit, at least one of the substitution processing unit and the transposition processing unit performs pipeline processing in units of sub-block data, and performs a plurality of internal processes. It is possible to perform parallel processing on a plurality of sub-block data included in the ciphertext block data.
In addition, the decryption processing device includes an extended key generation processing unit including a transposition processing unit that performs a transposition process by performing a plurality of internal processes on the key block data, and in the extended key generation processing unit, The transposition processing unit can perform a plurality of internal processes by performing pipeline processing in units of sub-block data, and can perform parallel processing on a plurality of sub-block data included in the same key block data.

Further, a decryption processing circuit can be mounted on the security chip 500 of FIG. 6 instead of the encryption processing circuit (100).
In addition, both the encryption processing circuit and the decryption processing circuit can be mounted on the security chip 500 in FIG.

  In the above description, both the substitution processing circuit (206) and the transposition processing circuit (209) of the randomizing unit processing circuit (101) include the pipeline register (207), but the substitution processing circuit (206). Only one of the transposition processing circuit (209) may include the pipeline register (207).

  In the above description, the pipeline processing by the pipeline register (207) is performed in both the randomization unit processing circuit (101) and the extended key generation unit processing circuit (102). However, the randomization unit processing circuit (101) ) And the extended key generation unit processing circuit (102) may include the pipeline register (207).

  In the above description, the AES cipher has been described as an example. However, the present invention is not limited to this, and any encryption algorithm that can process block data composed of a plurality of sub-block data and can perform parallel processing in units of sub-block data. For example, the encryption processing circuit and the decryption processing circuit according to the present embodiment are applicable.

  In the present embodiment, the encryption process or the decryption process is realized by hardware such as a randomization unit processing circuit and an extended key generation unit processing circuit, but may be realized by software processing.

FIG. 3 illustrates a configuration example of a cryptographic processing circuit according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of a randomization unit processing circuit according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of an extended key generation unit processing circuit according to the first embodiment. FIG. 6 is a diagram illustrating an operation example in each cycle of cryptographic processing according to the first embodiment. FIG. 6 is a diagram illustrating an operation example in each cycle of cryptographic processing according to the first embodiment. FIG. 3 is a diagram showing an example of a security chip using the cryptographic processing circuit according to the first embodiment. The figure which shows the outline | summary of an AES encryption algorithm.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 Encryption processing circuit, 101 Randomization part processing circuit, 102 Extended key generation part processing circuit, 201 Selector 1, 202 Data register, 203 Selector 2, 204 Selector 3, 205 Selector 4, 206 Substitution processing circuit, 207 Pipeline register, 208 Intermediate register, 209 transposition processing circuit, 210 selector 5, 211 selector 6, 212 key addition circuit, 301 selector 1, 302 key register, 303 expanded key generation circuit, 304 expanded key register, 305 selector 2, 306 transposition processing circuit, 307 Selector 3, 500 Security chip, 501 CPU, 502 memory, 503 External interface.

Claims (10)

Includes a substitution processing unit that performs substitution processing by performing a plurality of stages of internal processes on block data composed of a plurality of sub-block data, and a transposition processing section that performs substitution processing by performing a plurality of stages of internal processes. A cryptographic processing device,
The substitution processing unit and at least one of the transposition processing section performs pipeline processing of the sub-block data units included in the same block data conduct internal processes of a plurality of stages, contained in the same block data A cryptographic processing apparatus that performs parallel processing of a plurality of internal processes on a plurality of sub-block data. The cryptographic processing device includes:
An encryption processing device that repeats a predetermined round of encryption processing including the substitution processing and the transposition processing on the same block data;
In each round of encryption processing, at least one of the substitution processing unit and the transposition processing unit performs pipeline processing in units of sub-block data included in the same block data and performs a plurality of internal processes. The cryptographic processing apparatus according to claim 1, wherein parallel processing of a plurality of internal processes is performed on a plurality of sub-block data included in the same block data. The cryptographic processing device includes:
Randomizing process includes a permutation unit for performing permutation to carry out internal process of the substitution processing unit and a plurality performing a substitution process to carry out internal processes of a plurality of stages with respect to the plaintext block data or ciphertext block data Part
In the randomization processing unit, at least one of the substitution processing unit and the transposition processing unit performs pipeline processing in units of sub-block data included in the same plaintext block data or ciphertext block data, and performs a plurality of stages . 2. The cryptographic process according to claim 1, wherein an internal process is performed , and parallel processing of a plurality of internal processes is performed on a plurality of sub-block data included in the same plaintext block data or ciphertext block data. apparatus. The substitution processing unit
Against 128-bit plaintext block data or ciphertext block data, conduct internal processes of a plurality of stages by performing pipeline processing of 8-bit sub-block data units,
The transposition processing unit is
Against 128-bit plaintext block data or ciphertext block data, the cryptographic processing according to claim 3, characterized in that to carry out the internal processes of the plurality of stages by performing pipeline processing of the 32-bit sub-block data units apparatus. The cryptographic processing device includes:
Has expanded key generation processing unit included permutation unit for performing permutation to carry out internal process of plural steps to the key block data,
Within the expanded key generation processing unit, wherein the permutation unit performs pipeline processing of the sub-block data units included in the same key block data conduct internal processes of a plurality of stages, it is included in the same key block data The cryptographic processing apparatus according to claim 1, wherein parallel processing of a plurality of internal processes is performed on a plurality of sub-block data. The transposition processing unit is
Against 128-bit key block data, the cryptographic processing apparatus according to claim 5, characterized in that to carry out the internal processes of the plurality of stages by performing pipeline processing of the 32-bit sub-block data units. Includes a substitution processing unit that performs substitution processing by performing a plurality of stages of internal processes on block data composed of a plurality of sub-block data, and a transposition processing section that performs substitution processing by performing a plurality of stages of internal processes. A decryption processing device comprising:
The substitution processing unit and at least one of the transposition processing section performs pipeline processing of the sub-block data units included in the same block data conduct internal processes of a plurality of stages, contained in the same block data A decoding processing device that performs parallel processing of a plurality of stages of internal processes on a plurality of sub-block data. The decryption processing device comprises:
A decoding processing device that repeats a predetermined round of decoding processing including the substitution processing and the transposition processing on the same block data;
In each round of decoding processing, at least one of the substitution processing unit and the transposition processing unit performs pipeline processing in units of sub-block data included in the same block data and performs a plurality of internal processes. The decoding processing apparatus according to claim 7, wherein parallel processing of a plurality of internal processes is performed on a plurality of sub-block data included in the same block data. The decryption processing device comprises:
A randomization processing unit that includes a substitution processing unit that performs a plurality of stages of internal processes on ciphertext block data and performs a substitution process, and a transposition processing unit that performs a plurality of stages of internal processes and performs transposition processing. ,
Within the randomizing processing unit, the substitution processing unit and at least one of the transposition processing section performs internal processes of a plurality of stages by performing pipeline processing of block data units included in the same ciphertext block data The decryption processing apparatus according to claim 7 , wherein parallel processing of a plurality of stages of internal processes is performed on a plurality of sub-block data included in the same ciphertext block data. The decryption processing device comprises:
Has expanded key generation processing unit included permutation unit for performing permutation to carry out internal process of plural steps to the key block data,
Within the expanded key generation processing unit, wherein the permutation unit performs pipeline processing of the sub-block data units included in the same key block data conduct internal processes of a plurality of stages, it is included in the same key block data The decoding processing apparatus according to claim 7 , wherein parallel processing of a plurality of stages of internal processes is performed on a plurality of sub-block data.

Images