JP5019324B2 - Information processing system, information processing terminal, cartridge, and program execution method - Google Patents

Description

  The present invention relates to the execution of a program recorded on a cartridge, and more particularly to an information processing system, an information processing terminal, a cartridge, and a program execution method for suppressing unauthorized copying of a program recorded on a cartridge.

  In recent years, with the development of various information terminal devices, storage devices such as memory cartridges for game machines, video storage memories, music storages, memory cards, and IC (Integrated Circuit) cards have been distributed in large quantities in the market. Such storage devices often contain data that is not desirable for unauthorized reading or duplication by a third party, such as information that should be protected by copyright or information relating to personal privacy. For this reason, conventionally, various techniques for incorporating a security circuit or a circuit for generating dummy data into peripheral devices that control the storage device have been proposed in order to restrict reading and copying of information from the storage device.

  For example, Japanese Patent Laid-Open No. 59-152599 (Patent Document 1) discloses an apparatus including a circuit as shown in FIG.

Referring to FIG. 11, the apparatus includes an interface circuit 1001, a security circuit 1002, and a comparison circuit 1004, and data stored in the storage device 1003 passes through the security circuit 1002 and the interface circuit 1001. And read. In the device, when a password is input from the outside, the password is input to the comparison circuit 1004. On the other hand, in the interface circuit 1001, a preset password is fixedly stored, and the password is input to the comparison circuit 1004. The comparison circuit 1004 compares the password input from the outside with the password input from the interface circuit 1001. If the two match, the comparison circuit 1004 inputs a security release signal to the security circuit 1002.
JP 59-152599 A

  In the conventional technique as described above, for example, in the technique disclosed in Patent Document 1, a copy of program data can be managed by a password.

  However, in the above-described conventional technique, when an illegal copy of program data is attempted, such a copy operation is prohibited and thus cannot be completed. For this reason, the person who attempted the unauthorized copy immediately recognizes that the execution of the copy operation has been unsuccessful. Therefore, the above-described conventional technique gives the person the motivation to take the next measure such as the decoding of the data structure in the system.

  The present invention has been conceived in view of such circumstances, and an object of the present invention is to provide an information processing system, an information processing terminal, a cartridge, and a program execution method that reliably suppress an unauthorized copy operation. is there.

An information processing system according to the present invention is an information processing system including a cartridge and an information processing terminal to which the cartridge is detachably attached, and the cartridge includes a recording unit that records a first program, A decoder for decoding the first program; and the information processing terminal includes execution means for executing a second program, the first program being a program decoded by the decoder, at regular intervals. , Further comprising invalidation processing means for executing the processing for invalidating the decoder after a specific time longer than the predetermined time , and the second program causes the execution processing means to execute the processing by the invalidation processing means at every predetermined time. A third program for avoiding invalidation of the decoder is included.

  In the information processing system of the present invention, it is preferable that the decoder and the invalidation processing unit are provided in the information processing terminal.

  In the information processing system of the present invention, it is preferable that the decoder and the invalidation processing unit are provided in the cartridge.

  In the information processing system of the present invention, the information processing terminal further includes a memory and a compiler, the compiler expands the second program in the memory, and the cartridge is attached to the information processing terminal. Detecting means for detecting whether or not the second program developed in the memory is detected when the detecting means detects that the cartridge has been removed from the attached state. And erasing means for erasing at least the third program therein.

An information processing terminal according to the present invention is an information processing terminal to which a cartridge is detachably attached, and the cartridge includes recording means for recording a first program, and the first program is decoded by a decoder. Execution means for executing a second program that is a program, and invalidation processing means for executing processing for invalidating the decoder after a specific time longer than the certain time for each fixed time, Is characterized in that, by executing the second program, processing for avoiding invalidation of the decoder by the invalidation processing means is performed at the predetermined time intervals.

The information processing terminal of the present invention preferably further includes the decoder.
The cartridge according to the present invention is a cartridge that is detachably attached to the information processing terminal, and includes recording means for recording the first program, and the second program obtained by decoding the first program is constant. for each time, including a command to execute processing for avoiding invalid of the decoder to the information processing terminal, for each of the predetermined time, executes a process of the decoder to disabled after the predetermined time longer than a specified time And an invalidation processing unit .

The cartridge of the present invention preferably further comprises the decoders.

A program execution method according to the present invention is a program execution method in an information processing system including a cartridge including a recording unit that records a first program, and an information processing terminal to which the cartridge is detachably attached. The information processing terminal includes a memory, a compiler, and an execution unit that executes the program. The compiler expands the decoded code of the first program in the memory as a second program, and the program The execution means includes a step of executing the second program, and the program execution means executes a process for invalidating the decoder after a specific time longer than the predetermined time for every predetermined time. The step of executing the second program includes the predetermined time Characterized in that it comprises a step of executing processing for avoiding invalid of the decoder and.

  According to the present invention, the program recorded in the cartridge is decoded and executed in the information processing terminal, and the processing for invalidating the decoder that decodes the program is executed at regular intervals. Note that, by decoding and executing the program, processing for avoiding invalidation of the decoder is performed at regular intervals.

  That is, according to the present invention, when a program recorded in a cartridge is simply copied in the information processing terminal, an abnormality occurs in a part of the copied data. This is because if the program recorded in the cartridge is not executed, the decoder is merely invalidated at regular intervals, and processing for avoiding the invalidation is not executed. On the other hand, when the program recorded on the cartridge is executed in the information processing terminal, the program is executed without any problem. This is because a process for invalidating the decoder is executed for each fixed period for the decoder, but a process for avoiding the invalidation is executed for each fixed period by executing the program. .

  As described above, according to the present invention, the program recorded on the cartridge can be prevented from being illegally copied in the information processing terminal.

  According to the present invention, when the information processing terminal attempts to copy the program recorded on the cartridge, the copy operation is apparently executed. For this reason, a person who has attempted unauthorized copying cannot immediately recognize that the copying has failed. Therefore, it is possible to delay the timing for giving a motivation to take the next measure to those who have attempted illegal copying. Therefore, according to the present invention, unauthorized copying can also be suppressed from such a viewpoint.

  Hereinafter, an information processing system according to an embodiment of the present invention will be described with reference to the drawings.

[1. First Embodiment]
[1-1. System configuration]
FIG. 1 is a diagram schematically showing a hardware configuration of a game processing system according to the first embodiment of the information processing system of the present invention. The game processing system mainly includes a game apparatus 1 and game cartridges 40 and 50 that are detachably attached to the game apparatus 1.

  The game apparatus 1 includes a CPU (Central Processing Unit) 10 that controls the overall operation of the game apparatus 1. In addition, the game apparatus 1 includes an input unit 33 that is operated by the user to input information to the game apparatus 1, a display unit 31 that displays information, and an audio output unit 32 that outputs sound. . The input unit 33 includes a single key or a plurality of keys. The display unit 31 includes a display device such as an LCD (Liquid Crystal Display). The audio output unit 32 includes a speaker.

  The game apparatus 1 further includes a connector 22 for connecting to the game cartridge 40 and a connector 21 for connecting to the game cartridge 50.

  The game apparatus 1 includes a decoder 11, a timer 12, a comparator 13, an interrupt signal generation circuit 14, a key data storage unit 15, a key generation circuit 16, a buffer memory 17, and a flash memory 18.

  In the game apparatus 1, when a game program stored in the memory 41 of the game cartridge 40 is executed, the program is read into the decoder 11 via the connector 22, decoded, and sent to the CPU 10. The CPU 10 functions as a compiler by executing a predetermined program stored in the flash memory 18 (compiler 10A), and compiles the decoded program (source code) into a native code and expands it in the buffer memory 17. The CPU 10 executes the game program by executing the native code expanded in the buffer memory 17.

  In game device 1, interrupt signal generation circuit 14 determines the remaining time for supplying the clock signal to decoder 11 for a specific time (above-mentioned) for timer 12 at regular time intervals (for example, 0.1 sec). An interrupt signal is output that is shorter than “a certain time”. The decoder 11 performs a decoding operation on condition that the clock signal output from the timer 12 is input. The timer 12 receives the interrupt signal output from the interrupt signal generation circuit 14, whereby the remaining time of the output of the clock signal to the decoder 11 is set as the “specific time”.

  In the game apparatus 1, as will be described later, when the game program is executed, the CPU 10 outputs a signal for generating a specific key to the key generation circuit 16. As a result, a signal for extending the remaining time for supplying the clock signal to the decoder 11 in the timer 12 from the comparator 13 is output to the timer 12 as described above.

  That is, in the game device 1 of the present embodiment, even if an interrupt signal is sent from the interrupt signal generation circuit 14 to the timer 12, if the game program is executed, the CPU 10 specifies a specific key generation circuit 16. By outputting a signal for generating a key, the supply of the clock signal from the timer 12 to the decoder 11 is continued. Therefore, the decoding operation of the decoder 11 is continued.

[1-2. About illegal program copy operations]
Here, the operation of the game apparatus 1 when the game program stored in the memory 41 of the game cartridge 40 in the game apparatus 1 is illegally copied to the flash memory 51 of the game cartridge 50 will be described.

  In the game apparatus 1, the CPU 10 causes the decoder 11 to decode the game program so as to suck the game program from the memory 41 of the game cartridge 40 as the execution of the illegal copy program, and the decoded data The program written in the buffer memory 17 and the program written in the buffer memory 17 are recorded in the flash memory 51 of the game cartridge 50 via the connector 21.

[1-3. Regarding processing executed in game device]
[1-3-1. Run game program]
Next, how the CPU 10 executes the game program recorded in the memory 41 of the game cartridge 40 will be described with reference to FIG. 2, which is a flowchart of processing executed by the CPU 10 when the program is executed. .

  Referring to FIG. 2, in the game program execution process, CPU 10 first determines whether or not game cartridge 40 is connected to connector 22 in step S10. If it is determined that game cartridge 40 is connected, the process proceeds to step S20.

  In step S20, the CPU 10 enters a state in which an instruction to execute the game program is received on the input unit 33, and the process proceeds to step S30. Here, the state of accepting an instruction to execute the game program includes, for example, displaying a message prompting the user to input the instruction on the display unit 31.

  In step S30, the CPU 10 determines whether or not an instruction to execute the game program has been input. If it is determined that the instruction has been input, the process proceeds to step S40, and if it is not input, the process proceeds to step S31. Proceed.

  In step S31, the CPU 10 determines whether or not information for executing another process has been input to the input unit 33. If it is determined that such information has been input, the process instructed in step S30. Is executed in step S32, and the process returns to step S10. On the other hand, when determining that such information is not input, the CPU 10 returns the process to step S30.

  In step S40, the CPU 10 executes the game program and proceeds to step S50. In step S50, a timer refresh process described later is executed, and the process proceeds to step S60.

  In step S60, the CPU 10 determines whether or not the connection between the game cartridge 40 and the connector 22 has been released and the game cartridge 40 has been removed from the game apparatus 1. If it is determined that the game cartridge 40 has not been removed, the process proceeds to step S40. If it is determined that it has been removed and removed, the process returns to step S10.

[1-3-2. Execution of interrupt signal output processing]
Next, the content of the interrupt signal output process, which is a process for causing the interrupt signal generation circuit 14 to output an interrupt signal to the timer 12 at regular intervals as described above, is a flowchart of the process. This will be described with reference to FIG. This process is executed in the game apparatus 1 independently of the above-described game program execution process.

  Referring to FIG. 3, in interrupt signal output processing, CPU 10 first determines in step SA10 whether or not the above-mentioned count for a certain time has timed out, and if it determines that time-out has occurred, proceeds to step SA20.

  Note that the counting of the predetermined time here is performed by a timer built in the CPU 10, for example.

  In step SA20, the CPU 10 causes the interrupt signal generation circuit 14 to output an interrupt signal to the timer 12, and returns the process to step SA10.

  When an interrupt signal is output from the interrupt signal generation circuit 14 to the timer 12 in step SA20, the timer 12 counters until a signal for invalidating the decoding operation of the decoder 11 (hereinafter referred to as “ The counting of “invalid signal transmission counter” is started. It should be noted that the time (count time) from the start of counting until the timer 12 transmits the signal to the decoder 11 is longer than the above-described fixed time (specific time).

[1-3-3. Execution of subroutine for game program]
Returning to FIG. 2, the timer refresh process in step S50 is a process for clearing the count value of the counter that the timer 12 has started to count in the interrupt signal output process described with reference to FIG. Here, the timer refresh process will be described with reference to FIG. 4 which is a subroutine of the process.

  Referring to FIG. 4, in the timer refresh process, first, in step S501, CPU 10 determines whether or not a timeout period has elapsed since the previous timer refresh process was executed. If it is determined that it has not yet elapsed, the process is returned as it is.

  In step S502, the CPU 10 clears the count of the invalid signal transmission counter of the timer 12 and returns the process.

  In the present embodiment, the interrupt signal output processing program executed by the CPU 10 is recorded in, for example, the flash memory 18.

[1-4. Characteristic operation in the first embodiment]
As described above, in the present embodiment, in the game device 1, the program decoded by the decoder 11 is compiled by the compiler 10A and expanded in the buffer memory 17, and the CPU 10 expands the expanded program (native code). Execute. As described with reference to FIG. 3, the interrupt signal output process causes the game apparatus 1 to start counting a counter for transmitting a signal for invalidating the decoding operation of the decoder 11 at regular intervals. Is done. Note that the processing executed based on the game program recorded in the memory 41 of the game cartridge 40 includes timer refresh processing as described with reference to FIGS. In the timer refresh process, the count of the invalid signal transmission counter is cleared at regular intervals. In other words, in the present embodiment, the timer refresh process is executed at regular intervals, the invalid signal transmission counter times out, and the timer 12 transmits a signal for invalidating the decoding operation to the decoder 11. Can be avoided. Therefore, in the game apparatus 1, if the game program is being executed, the decoder 11 continues to perform the decoding operation.

  As described in the section “1-2.”, When the game program recorded in the memory 41 of the game cartridge 40 is simply subjected to the copy operation in the game apparatus 1, the timer refresh process is performed. (See FIG. 2 and FIG. 4) is not executed. Therefore, during the copying operation, the decoding operation of the decoder 11 is invalidated, and the game program is written into the flash memory 51 of the game cartridge 50 in a state where the game program is not partially decoded normally.

  According to the present embodiment described above, the information processing system of the present invention can be realized by making a design change such that the decoder 11 and the timer 12 are added in the game apparatus 1. Note that it is considered that the game device 1 and the game cartridge 40 are overwhelmingly produced in the game cartridge 40. Therefore, according to the present embodiment, the present invention can be realized at low cost.

  In the present embodiment, the information processing system is realized by the game device 1 and the game cartridge 40 that records the program executed in the game device 1, but the program executed in the present invention is for games. However, the application program may be other types of application programs such as spreadsheet software or word processing software.

[2. Second Embodiment]
FIG. 5 is a diagram schematically showing the configuration of the information processing system according to the second embodiment of the present invention.

  In the present embodiment, a game processing system that is an example of an information processing system mainly includes a game apparatus 1A and game cartridges 40A and 50A that are detachably attached to the game apparatus 1A.

  In the present embodiment, the decoder and timer provided in the game apparatus 1 in the first embodiment are provided on the game cartridge 40A side.

  The CPU 10 provided in the game apparatus 1A of the present embodiment executes each process described with reference to FIGS. 2 to 4 in the first embodiment, but the contents thereof are the same. It can be. That is, for example, in the first embodiment, in the interrupt signal output process, the interrupt signal generation circuit 14 starts counting the invalid signal transmission counter of the timer 12. Also in the interrupt signal output processing executed in the present embodiment, the interrupt signal generation circuit 14 counts the invalid signal transmission counter with respect to the timer 43 provided in the game cartridge 40A via the connector 22. To start.

  In the present embodiment, the game cartridge 40A includes a memory 41, a decoder 42, and a timer 43. The operations of the decoder 42 and the timer 43 are controlled by the CPU 10 of the game apparatus 1 </ b> A via the connector 22. When the game program recorded in the memory 41 is executed, the program is decoded by the decoder 42, and the decoded program is sent to the CPU 10 via the connector 22, and the CPU 10 executes a predetermined program. Compiled by the compiler 10A realized by execution, and is expanded in the buffer memory 17 as native code. The CPU 10 executes the expanded native code.

  In the present embodiment described above, the decoder and timer, which are characteristic components of the present invention, are provided on the game cartridge 40A side. Therefore, the information processing system according to the present invention can be realized without particularly adding components to the game apparatus 1A that is already sold or the like on the game apparatus 1A side and is at hand of the user. The interrupt signal generation circuit 14 can be realized by adding and storing a program for starting counting of the invalid signal transmission counter in the flash memory 18.

[3. Third Embodiment]
FIG. 6 is a diagram schematically showing a configuration of a game processing system according to the third embodiment of the information processing system of the present invention.

  The game processing system of the present embodiment mainly includes a game device 1B and a game cartridge 40. Game device 1B of the present embodiment is different from game device 1 of the first embodiment in that there is one connector. A game cartridge 40 can be connected to the connector 22 of the game apparatus 1B as shown in FIG. 6, and a game cartridge 50 which is a different type of game cartridge from the game cartridge 40 as shown in FIG. Can also be connected.

  Also in game device 1B of the present embodiment, each process described with reference to FIGS. 2 to 4 is executed in the same manner as described in the first embodiment.

[4. Fourth Embodiment]
FIG. 8 is a diagram schematically showing a configuration of a game processing system according to the fourth embodiment of the information processing system of the present invention. In the present embodiment, for game device 1, game cartridge 40 comprises a USB (Universal Serial Bus) memory. A USB port is connected to the connector 22 of the game apparatus 1. The game cartridge 40 is connected to the game apparatus 1 via the USB port 60 by being connected to the USB port 60 by USB.

  Also in game device 1 of the present embodiment, each process described with reference to FIGS. 2 to 4 is executed.

[5. Fifth embodiment]
FIG. 9 is a diagram schematically showing a configuration of a game processing system according to the fifth embodiment of the information processing system of the present invention.

  In the game processing system of the present embodiment, a wireless communication device 61 such as a LAN (Local Area Network) card is connected to the connector 22 of the game device 1.

  Further, the game program recorded in the memory 41 of the game cartridge 40 in the first embodiment is stored in the storage device 73 of the information terminal 70. The information terminal 70 includes a control device 71 that controls the operation of the information terminal as a whole and a wireless communication device such as a LAN card.

  The game device 1 is connected to the information terminal 70 via the wireless communication device 61.

  The CPU 10 of the game apparatus 1 according to the present embodiment reads the game program recorded in the storage device 73 by communicating with the information terminal 70 via the wireless communication device 61.

  Also in game device 1 of the present embodiment, each process described with reference to FIGS. 2 to 4 is executed.

[6. Sixth Embodiment]
FIG. 10 is a flowchart of a game program execution process executed by the CPU 10 of the game apparatus 1 which is an example of an information processing terminal in the information processing system according to the sixth embodiment of the information processing system of the present invention.

  In the flowchart shown in FIG. 10, the process of step S70 is added to the flowchart shown in FIG. 2 after the process of step S60. In step S <b> 70, the CPU 10 erases the native code of the process written in the buffer memory 17. That is, when game device 1 of the present embodiment determines that game cartridge 40 has been removed in step S60, native code for executing timer refresh processing (see FIG. 4) is stored in buffer memory 17 in step S70. After erasing, the process returns to step S10.

  According to the present embodiment, after the game cartridge 40 is removed from the game apparatus 1, the native code corresponding to the timer refresh process is quickly deleted. Therefore, after the game cartridge 40 is removed from the game apparatus 1, the native code corresponding to the timer refresh process that has been left as written in the buffer memory 17 is connected to the connector 22. Thus, the situation where the contents of the timer refresh process are analyzed can be avoided more reliably.

  Each embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims. In addition, it is intended that the techniques described in the embodiments are combined as much as possible.

It is a figure which shows typically the structure of the game processing system which is 1st Embodiment of the information processing system of this invention. It is a flowchart of the game program execution process which CPU of FIG. 1 performs. It is a flowchart of the interrupt signal output process which CPU of FIG. 1 performs. 3 is a flowchart of a timer refresh process subroutine of FIG. 2. It is a figure which shows typically the structure of the game processing system which is 2nd Embodiment of the information processing system of this invention. It is a figure which shows typically the structure of the game processing system which is 3rd Embodiment of the information processing system of this invention. It is a figure which shows typically the structure of the game processing system which is 3rd Embodiment of the information processing system of this invention. It is a figure which shows typically the structure of the game processing system which is 4th Embodiment of the information processing system of this invention. It is a figure which shows typically the structure of the game processing system which is 5th Embodiment of the information processing system of this invention. It is a flowchart of the game program execution process performed in the game device of the game processing system which is the 6th Embodiment of the information processing system of this invention. It is a figure which shows typically the structure of the conventional apparatus by which reading of the program data from program ROM is controlled.

Explanation of symbols

  1, 1A, 1B game device, 10 CPU, 11, 42 decoder, 12, 43 timer, 13 comparator, 14 interrupt signal generation circuit, 15 key data storage unit, 16 key generation circuit, 17 buffer memory, 18, 51 Flash memory, 21, 22 connector, 31 display unit, 32 audio output unit, 33 input unit, 40, 50 game cartridge, 41 memory, 60 USB port, 61, 72 wireless communication device, 71 control device, 73 storage device, 70 Information terminal.

Claims (9)

An information processing system comprising a cartridge and an information processing terminal to which the cartridge is detachably attached,
The cartridge includes recording means for recording a first program,
A decoder for decoding the first program;
The information processing terminal includes execution means for executing a second program, the first program being a program decoded by the decoder,
It further comprises invalidation processing means for executing processing for invalidating the decoder after a specific time longer than the certain time for each certain time,
The information processing system, wherein the second program includes a third program that causes the execution unit to avoid invalidation of the decoder by the invalidation processing unit at regular intervals.   The information processing system according to claim 1, wherein the decoder and the invalidation processing unit are provided in the information processing terminal.   The information processing system according to claim 1, wherein the decoder and the invalidation processing unit are provided in the cartridge. The information processing terminal further includes a memory and a compiler,
The compiler expands the second program in the memory;
The information processing terminal
Detecting means for detecting whether or not the cartridge is attached;
When the detection unit detects that the cartridge is removed from the attached state, at least the third program in the second program expanded in the memory is deleted. The information processing system according to claim 1, further comprising an erasing unit. An information processing terminal to which a cartridge can be detachably attached,
The cartridge includes recording means for recording the first program,
Execution means for executing a second program, wherein the first program is a program decoded by a decoder;
Invalidity processing means for executing processing for invalidating the decoder after a specific time longer than the certain time for each fixed time;
The information processing terminal, wherein the execution unit executes the second program to execute processing for avoiding invalidation of the decoder by the invalidation processing unit at every predetermined time.   The information processing terminal according to claim 5, further comprising the decoder. A cartridge detachably attached to an information processing terminal,
Recording means for recording the first program;
The second program obtained by decoding the first program by a decoder includes an instruction for causing the information processing terminal to execute processing for avoiding invalidation of the decoder at regular intervals,
The regular time intervals, further comprising a disabling processing means for executing a process of the decoder to disabled after the predetermined time longer than a specified time, the cartridge. Further comprising the decoders A cartridge according to claim 7. A program execution method in an information processing system comprising a cartridge including recording means for recording a first program, and an information processing terminal to which the cartridge is detachably attached,
The information processing terminal includes a memory, a compiler, and execution means for executing a program,
The compiler expanding the decoded code of the first program into the memory as a second program;
The program executing means executing the second program;
The program execution means includes a step of performing processing for invalidating the decoder after a specific time longer than the predetermined time, at fixed time intervals,
The step of executing the second program includes a step of executing a process for avoiding invalidation of the decoder every predetermined time.

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