JP5008266B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, in which a semiconductor element formed over an insulating surface is peeled off.

  A flexible substrate such as a plastic substrate is superior in mechanical strength against vibration and impact compared to a glass substrate, and can easily be reduced in thickness. The flexible substrate has a higher degree of freedom in shape than a glass substrate. Therefore, various applications are expected for a semiconductor device using the flexible substrate. However, a flexible substrate such as a plastic substrate is often not excellent in heat resistance to withstand heat treatment in a manufacturing process of a semiconductor element. Therefore, a manufacturing method in which a semiconductor element is formed over a heat-resistant substrate, and then peeled off and bonded to a separately prepared flexible substrate has been conventionally used.

JP-A-8-262475

  In Patent Document 1, a peeling layer using silicon is formed over a substrate, an integrated circuit using a thin film transistor is formed over the peeling layer, and the peeling layer is removed by etching. A technique for bonding the integrated circuit to another substrate after peeling is disclosed.

  However, the above-described manufacturing process of the semiconductor element has a problem that when the heat treatment is applied to the release layer in the process of manufacturing the semiconductor element, the release layer is easily peeled from the substrate. After the semiconductor element is completed, the release layer is finally peeled off from the substrate. However, if the release layer is peeled off from the substrate before the semiconductor element is completed, it is difficult to continue manufacturing the semiconductor element. become. Therefore, it is necessary to suppress the peeling layer from peeling from the substrate at least before the semiconductor element is completed.

  In the production of a semiconductor device formed by peeling a semiconductor element as described above, the time spent for the peeling step depends on the etching rate (etching rate) of the peeling layer. Therefore, the higher the etching rate, the faster the semiconductor element can be peeled off, which is preferable because TAT (Turn Around Time) can be shortened.

  Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device, in which the peeling layer is prevented from peeling from the substrate before the semiconductor element is completed, and the semiconductor element can be peeled more quickly. To do.

  The present inventors found that the release layer is easily peeled off from the substrate by heat treatment because stress is applied to the release layer due to the difference in thermal expansion coefficient between the substrate and the release layer, or the release layer is crystallized by heat treatment. As a result, the volume was reduced, and it was considered that stress was applied to the release layer. Therefore, in the present invention, before forming the release layer on the substrate, an insulating film (buffer film) for relaxing the stress of the release layer is formed between the substrate and the release layer so that the substrate and the release layer are in close contact with each other. It is characterized by enhancing sex.

  In addition, an insulating film (base film) for protecting the semiconductor element is formed on the peeling layer in the step of peeling the semiconductor element (peeling process), and a semiconductor film used for the semiconductor element is formed on the base film. Form. In the present invention, a continuous wave laser is used for crystallization of the semiconductor film.

  In the case of a continuous wave laser, unlike a pulsed laser, a semiconductor film is irradiated with laser light while scanning in one direction, and a crystal is continuously grown in the scanning direction. It is possible to form a collection of long crystal grains. By using a collection of crystal grains extending along the scanning direction in an active layer of a thin film transistor (TFT), a TFT having high characteristics in which there is almost no crystal grain boundary in a direction crossing the direction of carrier movement is obtained. Can be formed.

  In place of the continuous wave laser, the laser crystallization is performed using a frequency band that is significantly higher than the frequency band of several tens to several hundreds Hz that is normally used, with the oscillation frequency of the pulsed laser light being 10 MHz or higher. You can do it. It is said that the time from irradiating a semiconductor film with laser light by pulse oscillation until the semiconductor film is completely solidified is several tens to several hundreds nsec. Therefore, by using the above frequency band, it is possible to irradiate the next pulse of laser light from when the semiconductor film is melted by the laser light to solidification. Accordingly, since the solid-liquid interface can be continuously moved in the semiconductor film, a semiconductor film having crystal grains continuously grown in the scanning direction is formed. By forming single crystal grains extending long along the scanning direction, it is possible to form a semiconductor film having almost no crystal grain boundaries in at least the channel direction of the TFT.

  Further, in the present invention, the release layer may be crystallized at the time of laser crystallization of the semiconductor film. By crystallizing the release layer, the etching rate of the release layer can be improved and the semiconductor element can be released more quickly. Note that when heat is applied to the release layer by laser crystallization or the release layer is crystallized, stress is applied to the release layer. However, since the buffer film is formed between the substrate and the release layer in the present invention, it is possible to suppress the release layer from being peeled from the substrate before the semiconductor element is completed.

  Note that a semiconductor device using the manufacturing method of the present invention includes various kinds of semiconductor devices such as an integrated circuit such as a microprocessor and an image processing circuit, a semiconductor display device, and the like. The semiconductor display device includes a liquid crystal display device, a light-emitting device including a light-emitting element typified by an organic light-emitting element (OLED) in each pixel, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display). And other display devices having a circuit element using a semiconductor film in a driver circuit are included in the category.

  One of semiconductor devices that can be formed using the manufacturing method of the present invention is an ID chip. An ID chip is a semiconductor device capable of transmitting and receiving data such as identification information wirelessly, and its practical use is being promoted in various fields. The ID chip is also called a wireless tag, an RFID (Radio frequency identification) tag, or an IC tag.

  An ID chip using the manufacturing method of the present invention has an integrated circuit using a thin semiconductor film. In addition, an ID chip using the manufacturing method of the present invention can take a form having an antenna in addition to the integrated circuit. The integrated circuit operates using an alternating voltage generated by the antenna and modulates the alternating voltage applied to the antenna, thereby transmitting a signal to the reader / writer. Note that the antenna may be formed together with the integrated circuit, or may be formed separately from the integrated circuit and electrically connected later.

  According to the present invention, with the above structure, the peeling layer can be prevented from peeling from the substrate in a stage before the semiconductor element is completed, and the semiconductor element can be peeled more rapidly.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

  A method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. First, as shown in FIG. 1A, a buffer film 101 is formed to relieve stress of a peeling layer 102 to be formed later so as to be in contact with a heat-resistant substrate (first substrate) 100. The buffer film 101 may be an insulating film that can relieve the stress of the separation layer 102 and improve the adhesion between the first substrate 100 and the separation layer 102, and is formed of, for example, silicon oxide or silicon oxynitride. It is possible.

  Note that in this specification, silicon oxynitride is a material of an insulating film represented by SiOxNy (x> y) and is distinguished from silicon nitride oxide represented by SiNxOy (x> y).

  Next, the separation layer 102 is formed so as to be in contact with the buffer film 101. The release layer 102 is preferably formed using a material that can be crystallized together when the semiconductor film 104 is laser-crystallized later and can be removed by etching. Specifically, for example, silicon, silicon oxide, silicon germanium, or the like can be used.

  Next, a base film 103 is formed over the peeling layer 102. The base film 103 is provided to prevent an alkali metal such as Na or an alkaline earth metal from diffusing into the semiconductor film 104 to be formed later and adversely affecting the characteristics of a semiconductor element such as a TFT. The base film 103 also has a role of protecting the semiconductor element in a semiconductor element peeling process performed later.

  Next, the semiconductor film 104 is formed over the base film 103. The semiconductor film 104 may be an amorphous semiconductor, a semi-amorphous semiconductor, or a polycrystalline semiconductor. For the semiconductor film 104, not only silicon but also silicon germanium can be used.

  Next, as shown in FIG. 1B, the semiconductor film 104 is laser crystallized. For laser crystallization, in addition to a continuous wave laser, a pulsed laser having an oscillation frequency of 10 MHz or more can be used. When the semiconductor film 104 is laser crystallized, the peeling layer 102 is also crystallized.

  Next, as illustrated in FIG. 1C, a semiconductor element is formed using the crystallized semiconductor film 104. Although FIG. 1C illustrates an example in which the TFTs 105 to 107 are formed as semiconductor elements, the present invention is not limited to this. Semiconductor elements other than TFT, such as a memory element, a diode, a photoelectric conversion element, a resistance element, a coil, a capacitor element, and an inductor, can also be formed.

  The TFTs 105 to 107 are covered with an interlayer insulating film 108, and wirings 109 to 113 are formed on the interlayer insulating film 108. The wirings 109 to 113 are connected to the TFTs 105 to 107 through contact holes formed in the interlayer insulating film 108.

  Next, as illustrated in FIG. 1D, a protective layer 114 is formed so as to cover the TFTs 105 to 107 and the wirings 109 to 113. The protective layer 114 is a material that can protect the semiconductor element and wirings connected thereto (here, the TFTs 105 to 107 and the wirings 109 to 113) in the semiconductor element peeling process performed later, and can be removed after the peeling process. It is desirable to form with. For the protective layer 114, for example, an epoxy-based, acrylate-based, or silicon-based resin that is soluble in water or alcohols can be used.

Next, as shown in FIG. 2A, a peeling step is performed in which the peeling layer 102 is removed by etching, and the first substrate 100 and the buffer film 101 are peeled off from the TFTs 105 to 107. For example, in the case where silicon is used for the peeling layer 102, a gas or a liquid containing a halide can be typically used as the etchant. Specifically, for example, ClF ₃ (chlorine trifluoride), NF ₃ (nitrogen trifluoride), BrF ₃ (bromine trifluoride), HF (hydrogen fluoride), or ClF ₃ , NF ₃ , BrF ₃ , A gas in which nitrogen is mixed with HF can be used. Note that when HF is used, a silicon oxide film is used for the separation layer.

  Then, as shown in FIG. 2B, the TFTs 105 to 107 are attached to the second substrate 115 using an adhesive 116, and the protective layer 114 is removed.

  By using the above-described series of manufacturing methods, semiconductor elements such as TFTs 105 to 107 can be formed over the second substrate 115 even when the second substrate 115 is inferior in heat resistance.

  Note that in the peeling step, in order to shorten the time spent for removing the peeling layer 102, grooves are formed in the interlayer insulating film 108, the protective layer 114, and the base film 103 so that the peeling layer 102 is partially exposed. You may do it. Dicing, scribing, photolithography, or the like can be used for forming the groove.

  In the above-described manufacturing method, the separation layer 102 is crystallized together when the semiconductor film 104 is laser-crystallized, which is excellent in terms of reducing the number of steps and simplifying the steps. However, the present invention is not limited to the structure in which the separation layer 102 is laser crystallized together with the semiconductor film 104. The separation layer 102 having crystallinity may be formed in advance, or the separation layer 102 may be crystallized before the semiconductor film 104 is formed. For example, a pulsed laser with an oscillation frequency of less than 10 MHz, which has excellent throughput, and a laser with a pulsed oscillation with an oscillation frequency of 10 MHz or higher, which can crystallize the peeling layer 102 and can significantly improve crystallinity, or a continuous oscillation The semiconductor film 104 may be laser-crystallized with this laser. However, when the release layer 102 is laser crystallized, it is desirable to perform laser beam irradiation after forming the base film 103 in order to prevent the formation of protrusions (ridges) at the grain boundaries of the crystal grains.

  In addition, when the separation layer 102 having crystallinity is formed in advance or when the separation layer 102 is crystallized before the semiconductor film 104 is formed, the semiconductor film 104 is crystallized by a pulse oscillation laser having an oscillation frequency of 10 MHz or more. Alternatively, the present invention is not limited to laser crystallization using a continuous wave laser. For example, a laser crystallization method using a pulsed laser with an oscillation frequency of less than 10 MHz, a crystallization method using a catalytic element, or a crystallization method combining a crystallization method using a catalytic element and a laser crystallization method is used. Can do. When a substrate having excellent heat resistance such as quartz is used as the first substrate 100, a thermal crystallization method using an electric furnace, a lamp annealing crystallization method using infrared light, and a crystallization using a catalytic element. A crystal method combining the method and high-temperature annealing at about 950 ° C. may be used.

  In the case where silicon is used for the peeling layer 102, p-type impurities (eg, B) or n-type impurities (eg, P) are added to the peeling layer 102 by doping or the like and activated, thereby further increasing the peeling layer 102. The etching rate can be increased.

  The base film 103 may be formed using a single insulating film or a plurality of insulating films. In order to prevent alkali metal such as Na or alkaline earth metal from diffusing into the semiconductor film 104, it is effective to use silicon nitride or silicon nitride oxide having a high barrier property. However, silicon nitride or silicon nitride oxide is inferior to silicon oxide or silicon oxynitride in terms of adhesion to silicon. Therefore, in the case where silicon is used for the peeling layer 102, silicon oxide or silicon oxynitride is used for the insulating film in contact with the peeling layer 102 among the plurality of insulating films of the base film 103, and any of the remaining insulating films of the base film 103 is used. It is desirable to use silicon nitride or silicon nitride oxide. With the above structure, adhesion between the separation layer 102 and the base film 103 can be improved, and further, alkali metal or alkaline earth metal can be prevented from diffusing into the semiconductor film 104.

  In the case where silicon is used for the semiconductor film 104, silicon oxide or silicon oxynitride is used for the insulating film in contact with the semiconductor film 104 among the plurality of insulating films included in the base film 103, and any of the remaining insulating films of the base film 103 is used. It is desirable to use silicon nitride or silicon nitride oxide. With the above structure, adhesion between the semiconductor film 104 and the base film 103 can be improved, and further, alkali metal or alkaline earth metal can be prevented from diffusing into the semiconductor film 104.

  Alternatively, in the case where silicon is used for the separation layer 102 and silicon is used for the semiconductor film 104, silicon oxide is used for the insulating film in contact with the separation layer 102 and the insulating film in contact with the semiconductor film 104 among the plurality of insulating films included in the base film 103. Alternatively, silicon oxynitride is preferably used, and silicon nitride or silicon nitride oxide is preferably used for any of the remaining insulating films in the base film 103. With the above structure, the adhesion between the separation layer 102 and the base film 103 is improved, the adhesion between the semiconductor film 104 and the base film 103 is improved, and alkali metal or alkaline earth metal is diffused into the semiconductor film 104. Can be prevented.

  Next, in this embodiment, a detailed manufacturing method of an ID chip which is one of semiconductor devices using the manufacturing method of the present invention will be described. Note that in this embodiment, an isolated TFT is shown as an example of a semiconductor element; however, a semiconductor element used for an integrated circuit is not limited to this, and any circuit element can be used.

  First, as shown in FIG. 3A, a buffer film 501 is formed so as to be in contact with the first substrate 500 having heat resistance. As the first substrate 500, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Further, a metal substrate including a stainless steel substrate or a semiconductor substrate may be used. A substrate made of a synthetic resin having flexibility such as plastic generally tends to have a lower heat resistant temperature than the above substrate, but can be used as long as it can withstand the processing temperature in the manufacturing process. .

The buffer film 501 may be any insulating film that can relieve stress of the peeling layer 502 to be formed later and improve the adhesion between the first substrate 500 and the peeling layer 502, for example, silicon oxide, oxynitride, and the like. It can be formed of silicon. In this embodiment, a buffer film 501 made of silicon oxynitride is formed by plasma CVD using a mixed gas of SiH ₄ / N ₂ O at a flow rate ratio of 4/800 sccm.

  In this embodiment, the buffer film 501 is formed of a single insulating film, but the present invention is not limited to this structure. The buffer film 501 may be formed of a plurality of insulating films.

  Next, a separation layer 502 is formed so as to be in contact with the buffer film 501. The separation layer 502 can be formed using a layer containing silicon as a main component, such as amorphous silicon, polycrystalline silicon, single crystal silicon, or microcrystalline silicon (including semi-amorphous silicon). The separation layer 502 can be formed by a sputtering method, a low pressure CVD method, a plasma CVD method, or the like. In this embodiment, amorphous silicon having a thickness of about 50 nm is formed by a plasma CVD method and used as the peeling layer 502. The peeling layer 502 can be prevented from containing dust in the peeling layer 502 by using the plasma CVD method rather than the sputtering method, and the amount of Ar contained in the peeling layer 502 can be prevented. Can be suppressed. Therefore, even when heat treatment including laser crystallization is applied to the separation layer 502 in a later manufacturing process, separation of the separation layer 502 from the buffer film 501 or the base film 503 due to dust or Ar can be suppressed. . In addition, when the separation layer 502 contains dust, minute unevenness may occur on the surface of the semiconductor film 504 to be formed later due to the dust. When unevenness due to dust exists on the surface of the semiconductor film 504, the semiconductor film 504 may be peeled off when the semiconductor film 504 is laser crystallized. In addition, when Ar is contained in the separation layer 502, the semiconductor film 504 may be separated by laser energy. Therefore, it can be said that the separation layer 502 is formed by a plasma CVD method, whereby the semiconductor film 504 can be prevented from being separated from the base film 503 during laser crystallization. Note that the material of the separation layer 502 is not limited to silicon and may be formed using a material that can be selectively removed by etching. The thickness of the peeling layer 502 is desirably 10 to 100 nm.

  Next, a base film 503 is formed over the peeling layer 502. The base film 503 is an alkali metal or alkaline earth metal such as Na contained in the first substrate 500 diffusing into the semiconductor film 504 to be formed later, which adversely affects the characteristics of a semiconductor element such as a TFT. Provide to prevent. In addition, the base film 503 has a role of protecting the semiconductor element in a process of peeling the semiconductor element later. For the base film 503, an insulating film such as silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide can be used, for example.

The base film 503 may be a single insulating film or a stack of a plurality of insulating films. In this embodiment, a base film 503 is formed by sequentially stacking a silicon oxynitride film having a thickness of 100 nm, a silicon nitride oxide film having a thickness of 50 nm, and a silicon oxynitride film having a thickness of 100 nm. The thickness and the number of stacked layers are not limited to this. For example, instead of the lower silicon oxynitride film, a siloxane-based resin having a thickness of 0.5 to 3 μm may be formed by a spin coating method, a slit coater method, a droplet discharge method, a printing method, or the like. Further, a silicon nitride film (SiNx, Si ₃ N ₄ or the like) may be used instead of the middle layer silicon nitride oxide film. Further, a silicon oxide film may be used instead of the upper silicon oxynitride film. Each film thickness is preferably 0.05 to 3 μm, and can be freely selected from the range.

  The droplet discharge method means a method of forming a predetermined pattern by discharging droplets containing a predetermined composition from the pores, and includes an ink jet method and the like in its category. The printing method includes a screen printing method and an offset printing method.

  Alternatively, the lower layer of the base film 503 closest to the peeling layer 502 may be formed using a silicon oxynitride film or a silicon oxide film, the middle layer may be formed using a siloxane-based resin, and the upper layer may be formed using a silicon oxide film.

  Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond and has an organic group containing at least hydrogen (eg, an alkyl group or aromatic hydrocarbon) as a substituent. Alternatively, it may have a fluoro group as a substituent. Alternatively, an organic group containing at least hydrogen as a substituent and a fluoro group may be included.

The silicon oxide film can be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, or bias ECRCVD using a mixed gas such as SiH ₄ / O ₂ , TEOS (tetraethoxysilane) / O ₂ or the like. The silicon nitride film can be typically formed by plasma CVD using a mixed gas of SiH ₄ / NH ₃ . The silicon oxynitride film and the silicon nitride oxide film can be typically formed by plasma CVD using a mixed gas of SiH ₄ / N ₂ O.

  Next, a semiconductor film 504 is formed over the base film 503. The semiconductor film 504 is preferably formed without being exposed to the air after the base film 503 is formed. The thickness of the semiconductor film 504 is 20 to 200 nm (desirably 40 to 170 nm, preferably 50 to 150 nm). Note that the semiconductor film 504 may be an amorphous semiconductor, a semi-amorphous semiconductor, or a polycrystalline semiconductor. For the semiconductor film 504, not only silicon but also silicon germanium can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%.

  Next, the semiconductor film 504 is laser crystallized. In the case of performing laser crystallization, it is preferable to perform heat treatment at 550 ° C. for 4 hours on the semiconductor film 504 in order to increase the resistance of the semiconductor film 504 to the laser before laser crystallization. For laser crystallization, a continuous wave laser or a pulsed laser having an oscillation frequency of 10 MHz or more can be used.

Specifically, a known continuous wave gas laser or solid-state laser can be used. Examples of gas lasers include Ar laser and Kr laser, and solid-state lasers include YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, Y ₂ O ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser. Etc.

If pulse oscillation can be performed at a frequency of 10 MHz or more, an Ar laser, a Kr laser, an excimer laser, a CO ₂ laser, a YAG laser, a Y ₂ O ₃ laser, a YVO ₄ laser, a YLF laser, a YAlO ₃ laser, a glass laser Ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser or gold vapor laser can be used.

For example, when a solid-state laser capable of continuous oscillation is used, a crystal with a large grain size can be obtained by irradiating the semiconductor film 504 with laser light of second to fourth harmonics. Typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of a YAG laser (fundamental wave 1064 nm). Specifically, laser light emitted from a continuous wave YAG laser is converted into a harmonic by a non-linear optical element to obtain, for example, laser light with an output of about 4 to 8 W. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the semiconductor film 504 is irradiated. Energy density of about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec. In this embodiment, crystallization is performed with an energy of 5 W, a beam spot size of 400 μm in the major axis, 10 to 20 μm in the minor axis, and a scanning speed of 35 cm / sec.

  By the laser crystallization, crystal grains having a width in the direction perpendicular to the scanning direction of about several hundred μm and growing so as to extend in the scanning direction can be obtained.

  Note that as the beam spot of the laser beam is shorter in the scanning direction, the minimum value of the laser beam energy density at which the semiconductor film 504 is peeled off by laser crystallization, and the energy density value for obtaining a crystal as designed. The difference (margin) can be increased. Therefore, even when unevenness is generated on the surface of the semiconductor film 504 due to dust or the like, the semiconductor film 504 can be crystallized without being peeled off. Therefore, it is desirable to make the width of the beam spot in the scanning direction as narrow as possible to adjust the optical system.

  Further, as the thickness of the base film 503 is increased, the stress of the semiconductor film 504 to be formed later can be relieved, so that the energy density margin of the laser light can be increased. In the following Table 1 and FIG. 8, in a sample formed by sequentially stacking a buffer film, a release layer, a base film, and a semiconductor film on a glass substrate, the energy of the semiconductor film when crystallized with a continuous wave laser is shown. Indicates the margin. In this specification, the margin is compared in terms of W (watts) for convenience. However, since the beam spot of the laser beam is the same size in all the samples, the magnitude relationship of the energy margin between the samples means the relative size relationship of the energy density margin.

  Specifically, each sample is formed of a 100 nm silicon oxynitride buffer film on a glass substrate using a plasma CVD method, and the buffer film is formed of 50 nm amorphous silicon using a plasma CVD method. A peeling layer is formed, and an insulating film made of silicon oxide is formed on the peeling layer by a plasma CVD method. An insulating film made of 50 nm silicon nitride oxide is formed on the insulating film made of silicon oxide by plasma CVD, and 100 nm is formed on the insulating film made of silicon nitride oxide by plasma CVD. An insulating film made of silicon oxynitride is formed. The insulating film made of silicon oxide, the insulating film made of silicon nitride oxide, and the insulating film made of silicon oxynitride correspond to a base film. A semiconductor film made of 66 nm amorphous silicon is formed on the insulating film made of silicon oxynitride using a plasma CVD method.

  In FIG. 8, the thickness of the insulating film made of silicon oxide is shown on the horizontal axis, and the margin for laser crystallization of the semiconductor film is shown on the vertical axis. Note that sample A uses only laser crystallization, and sample B uses laser crystallization after crystallization using a catalytic element. From Table 1 and FIG. 8, it can be seen that when the thickness of the insulating film made of silicon oxide is 600 nm or less, the larger the thickness, the larger the margin. It can be seen that there is a sufficient margin when the thickness of the insulating film made of silicon oxide is 600 nm or more. Therefore, it can be seen that the thicker the insulating film made of silicon oxide is, the more uniformly the semiconductor film can be crystallized even if the surface of the substrate is uneven.

  Since the margin of the laser beam energy density increases as the semiconductor film thickness increases, the semiconductor film is crystallized more uniformly as the semiconductor film thickness increases, even if the substrate surface is wavy. it can.

  In addition, when a continuous wave laser is used, regions where crystal grains are extremely small and crystallinity is inferior to the center of the beam spot at both ends of the beam spot in the direction perpendicular to the scanning direction (microcrystalline region) ) Is formed. The area of the microcrystalline region could be reduced as the thickness of the semiconductor film was increased. In addition, the thinner the release layer, the smaller the area of the microcrystalline region. Therefore, in order to suppress the area of the microcrystalline region, it is preferable to adjust the thickness of the semiconductor film and the thickness of the separation layer. Alternatively, without adjusting the thickness of the semiconductor film and the thickness of the release layer, a region where the energy density of the beam spot is low can be shielded with a slit or the like so that the area of the microcrystalline region can be suppressed.

  Further, the buffer film 501, the separation layer 502, the base film 503, and the semiconductor film 504 can be continuously formed over the first substrate 500 without being exposed to the atmosphere. By continuously forming without opening to the atmosphere, dust or impurities in the atmosphere can be prevented from entering between each layer or film. However, if the amount of hydrogen contained in the separation layer 502 is large, the separation layer 502 is easily separated when a heat treatment such as laser crystallization is applied later. Therefore, if importance is attached to prevention of peeling of the peeling layer 502, it is preferable to perform heat treatment after the peeling layer 502 is formed to suppress the amount of hydrogen contained in the peeling layer 502.

  Laser crystallization may be performed by irradiating a semiconductor film with a continuous-wave fundamental laser beam and a continuous-wave harmonic laser beam in parallel, or with a continuous-wave fundamental laser beam and a pulse. You may make it irradiate a semiconductor film in parallel with the laser beam of the harmonic of oscillation.

  Alternatively, the semiconductor film may be irradiated with a laser beam in an inert gas atmosphere such as a rare gas or nitrogen. Thus, the surface roughness of the semiconductor film due to laser light irradiation can be suppressed, and variations in the threshold voltage of the TFT caused by variations in the interface state density can be suppressed.

  The crystallinity of the semiconductor film 504 is increased by the above-described laser light irradiation. Note that a polycrystalline semiconductor may be formed in advance by a sputtering method, a plasma CVD method, a thermal CVD method, or the like.

An amorphous semiconductor can be obtained by glow discharge decomposition of a silicide gas. Typical silicide gases include SiH ₄ and Si ₂ H ₆ . This silicide gas may be diluted with hydrogen, hydrogen and helium.

Note that a semi-amorphous semiconductor is a film including a semiconductor having an intermediate structure between an amorphous semiconductor and a semiconductor having a crystal structure (including single crystal and polycrystal). This semi-amorphous semiconductor is a semiconductor having a third state which is stable in terms of free energy, and is a crystalline one having a short-range order and having a lattice strain, and having a grain size of 0.5 to 20 nm. It can be dispersed in a single crystal semiconductor. The semi-amorphous semiconductor has its Raman spectrum shifted to a lower wavenumber than 520 cm ⁻¹ , and diffraction peaks of (111) and (220), which are considered to be derived from the Si crystal lattice in X-ray diffraction, are observed. . Further, at least 1 atomic% or more of hydrogen or halogen is contained as termination of dangling bonds (dangling bonds). Here, for convenience, such a semiconductor is referred to as a semi-amorphous semiconductor (SAS). Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a good semi-amorphous semiconductor can be obtained.

SAS can be obtained by glow discharge decomposition of silicide gas. A typical silicide gas is SiH ₄ , and in addition, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4 and the} like can be used. In addition, it is easy to form a SAS by diluting and using this silicide gas with hydrogen or a gas obtained by adding one or more kinds of rare gas elements selected from helium, argon, krypton, and neon to hydrogen. It can be. It is preferable to dilute the silicide gas at a dilution rate in the range of 2 to 1000 times. Furthermore, a carbide gas such as CH ₄ or C ₂ H ₆ , a germanium gas such as GeH ₄ or GeF ₄ , F ₂ or the like is mixed in the silicide gas, so that the energy bandwidth is 1.5-2. You may adjust to 4 eV or 0.9-1.1 eV.

For example, when using a gas added with H ₂ to SiH _4, or the case of using the added gas F ₂ to SiH _4, when TFT is formed by using the formed semi-amorphous semiconductor, the subthreshold coefficient of the TFT (S Value) can be 0.35 V / sec or less, typically 0.25 to 0.09 V / sec, and the mobility can be 10 cm ² / Vsec. When a TFT using the semi-amorphous semiconductor, for example, a 19-stage ring oscillator is formed, characteristics with an oscillation frequency of 1 MHz or more, preferably 100 MHz or more can be obtained at a power supply voltage of 3 to 5 V. In addition, at a power supply voltage of 3 to 5 V, the delay time per inverter stage can be 26 ns, preferably 0.26 ns or less.

  Next, as illustrated in FIG. 3B, the crystallized semiconductor film 504 is patterned to form island-shaped semiconductor films 505 to 507. Then, a gate insulating film 508 is formed so as to cover the island-shaped semiconductor films 505 to 507. The gate insulating film 508 can be formed using a single layer or a stack of films containing silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride by a plasma CVD method, a sputtering method, or the like. In the case of stacking, for example, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film is preferable from the substrate side.

  Next, as shown in FIG. 3C, gate electrodes 510 to 512 are formed. In this embodiment, silicon, WN, and W doped with an impurity imparting n-type are sequentially stacked by sputtering, and then etching is performed using the resist 513 as a mask, whereby the gate electrodes 510 to 512 are formed. Form. Needless to say, the material, structure, and manufacturing method of the gate electrodes 510 to 512 are not limited to these, and can be selected as appropriate. For example, a stacked structure of silicon and NiSi (nickel silicide) doped with an impurity imparting n-type, a stacked structure of Si and WSix doped with an impurity imparting n-type, TaN (tantalum nitride) and W ( (Tungsten) may be stacked. Alternatively, the gate electrodes 510 to 512 may be formed as a single layer using various conductive materials.

  A mask made of silicon oxide or the like may be used instead of the resist mask. In this case, a step of patterning to form a mask (referred to as a hard mask) of silicon oxide, silicon oxynitride, or the like is added, but since the film thickness of the mask during etching is less than that of the resist mask, a gate having a desired width is formed. Electrodes 510-512 can be formed. Alternatively, the gate electrodes 510 to 512 may be selectively formed using a droplet discharge method without using the resist 513.

  As the conductive material, various materials can be selected depending on the function of the conductive film. In the case where the gate electrode and the antenna are formed at the same time, materials may be selected in consideration of their functions.

Note that a mixed gas of CF ₄ , Cl ₂ , and O ₂ or a Cl ₂ gas is used as an etching gas for forming the gate electrodes 510 to 512 by etching, but the etching gas is not limited to this.

Next, as shown in FIG. 3D, an island-shaped semiconductor film 506 to be a p-channel TFT is covered with a resist 514, and the gate-shaped electrodes 510 and 512 are used as masks to form island-shaped semiconductor films 505 and 507. An impurity element imparting a mold (typically P (phosphorus) or As (arsenic)) is doped at a low concentration (first doping step). The conditions of the first doping process are a dose of 1 × 10 ^{13 to} 6 × 10 ¹³ / cm ² and an acceleration voltage of 50 to 70 keV, but the conditions of the doping process are not limited to this. In this first doping step, doping is performed through the gate insulating film 508, and a pair of low-concentration impurity regions 516 and 517 are formed in the island-shaped semiconductor films 505 and 507. Note that the first doping step may be performed without covering the island-shaped semiconductor film 506 to be a p-channel TFT with a resist.

Next, as shown in FIG. 3E, after removing the resist 514 by ashing or the like, a resist 518 is newly formed so as to cover the island-shaped semiconductor films 505 and 507 to be n-channel TFTs. Using the electrode 511 as a mask, the island-shaped semiconductor film 506 is doped with an impurity element imparting p-type (typically B (boron)) at a high concentration (second doping step). The conditions for the second doping step are a dose amount of 1 × 10 ^{16 to} 3 × 10 ¹⁶ / cm ² and an acceleration voltage of 20 to 40 keV. In the second doping step, doping is performed through the gate insulating film 508, and a pair of p-type high concentration impurity regions 519 are formed in the island-shaped semiconductor film 506.

Next, as shown in FIG. 4A, after removing the resist 518 by ashing or the like, an insulating film 520 is formed so as to cover the gate insulating film 508 and the gate electrodes 510 to 512. In this embodiment, a silicon oxide film having a thickness of 100 nm is formed by a plasma CVD method. After that, the insulating film 520 and the gate insulating film 508 are partially etched by an etch back method, and the sidewalls 522 to 524 are formed so as to be in contact with the sidewalls of the gate electrodes 510 to 512 as shown in FIG. Self-aligned (self-aligned). As an etching gas, a mixed gas of CHF ₃ and He is used. Note that the sidewalls 522 to 524 are not limited to these.

  When the insulating film is formed on the back surface of the first substrate 500 when the insulating film 520 is formed, the insulating film formed on the back surface is selectively etched and removed using a resist. Anyway. In this case, the resist used may be removed by etching together with the insulating film 520 and the gate insulating film 508 when the sidewalls 522 to 524 are formed by the etch back method.

Next, as shown in FIG. 4C, a resist 525 is newly formed so as to cover the island-shaped semiconductor film 506 to be a p-channel TFT, and the gate electrodes 510 and 512 and the sidewalls 522 and 524 are masked. As described above, an impurity element imparting n-type conductivity (typically P or As) is doped at a high concentration (third doping step). The conditions of the third doping step are a dose amount of 1 × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 60 to 100 keV. By this third doping step, a pair of n-type high concentration impurity regions 527 and 528 are formed in the island-shaped semiconductor films 505 and 507.

  Note that the sidewalls 522 and 524 function as masks when a low concentration impurity region or a non-doped offset region is formed below the sidewalls 522 and 524 by doping with an impurity imparting a high concentration n-type later. is there. Therefore, in order to control the width of the low-concentration impurity region or the offset region, the conditions of the etch-back method when forming the sidewalls 522 and 524 or the film thickness of the insulating film 520 are changed as appropriate. Just adjust the size.

  Next, after removing the resist 525 by ashing or the like, the impurity region may be activated by heat treatment. For example, after a 50 nm silicon oxynitride film is formed, heat treatment may be performed in a nitrogen atmosphere at 550 ° C. for 4 hours.

Further, after a silicon nitride film containing hydrogen is formed to a thickness of 100 nm, a heat treatment is performed in a nitrogen atmosphere at 410 ° C. for 1 hour to hydrogenate the island-shaped semiconductor films 505 to 507. May be. Alternatively, a process of hydrogenating the island-shaped semiconductor films 505 to 507 may be performed by performing heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing hydrogen. Further, plasma hydrogenation (using hydrogen excited by plasma) may be performed as another means of hydrogenation. By this hydrogenation step, dangling bonds can be terminated by thermally excited hydrogen. In addition, after a semiconductor element is attached to the flexible second substrate 548 in a later step, the flexible second substrate 548 is bent to form the island-shaped semiconductor films 505 to 507. Even if a defect is formed, the hydrogen concentration in the island-shaped semiconductor films 505 to 507 is set to 1 × 10 ¹⁹ to 1 × 10 ²² atoms / cm ^3, preferably 1 × 10 ^{19 to} 5 × 10 ^{20 by} hydrogenation. By setting atoms / cm ³ , the defects can be terminated by hydrogen contained in the island-shaped semiconductor films 505 to 507. In order to terminate the defect, the island-shaped semiconductor films 505 to 507 may contain halogen.

  Through the series of steps described above, an n-channel TFT 529, a p-channel TFT 530, and an n-channel TFT 531 are formed. In the above manufacturing process, a TFT having a channel length of 0.2 μm to 2 μm can be formed by appropriately changing the conditions of the etch back method or the thickness of the insulating film 520 and adjusting the size of the sidewalls 522 to 524. . In this embodiment, the n-channel TFTs 529 and 531 and the p-channel TFT 530 have a top gate structure, but may have a bottom gate structure (reverse stagger structure).

  Further, a passivation film for protecting the n-channel TFTs 529 and 531 and the p-channel TFT 530 may be formed thereafter. As the passivation film, silicon nitride, silicon nitride oxide, aluminum nitride, aluminum oxide, silicon oxide, or the like which can prevent alkali metal or alkaline earth metal from entering the n-channel TFTs 529 and 531 and the p-channel TFT 530 is used. Is desirable. Specifically, for example, a silicon oxynitride film with a thickness of about 600 nm can be used as the passivation film. In this case, the hydrogenation process may be performed after the silicon oxynitride film is formed. As described above, a three-layer insulating film in which silicon oxynitride, silicon nitride, and silicon oxynitride are stacked in this order is formed over the n-channel TFTs 529 and 531 and the p-channel TFT 530. The materials are not limited to these. By using the above structure, the n-channel TFTs 529 and 531 and the p-channel TFT 530 are covered with the base film 503 and the passivation film, so that an alkali metal such as Na or an alkaline earth metal is used for the semiconductor element. Diffusion into the island-shaped semiconductor films 505 to 507 can be further prevented from adversely affecting the characteristics of the semiconductor element.

  Next, as shown in FIG. 4D, a first interlayer insulating film 533 is formed so as to cover the n-channel TFTs 529 and 531 and the p-channel TFT 530. For the first interlayer insulating film 533, an organic resin having heat resistance such as polyimide, acrylic, or polyamide can be used. In addition to the organic resin, a low dielectric constant material (low-k material), a siloxane-based material, or the like can be used. Siloxane resins have an organic group containing at least hydrogen as a substituent (for example, an alkyl group or an aromatic hydrocarbon). Alternatively, it may have a fluoro group as a substituent. Alternatively, an organic group containing at least hydrogen as a substituent and a fluoro group may be included. For the formation of the first interlayer insulating film 533, depending on the material, spin coating, dipping, spray coating, droplet discharge method (ink jet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater A knife coater or the like can be employed. In addition, an inorganic material may be used. In that case, silicon oxide, silicon nitride, silicon oxynitride, PSG (phosphorus glass), BPSG (phosphorus boron glass), an alumina film, or the like can be used. Note that the first interlayer insulating film 533 may be formed by stacking these insulating films.

  Further, in this embodiment, a second interlayer insulating film 534 is formed on the first interlayer insulating film 533. As the second interlayer insulating film 534, a film containing carbon such as DLC (diamond-like carbon) or carbon nitride (CN), a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like can be used. As a manufacturing method, a plasma CVD method, an atmospheric pressure plasma method, or the like can be used. Alternatively, a photosensitive or non-photosensitive organic material such as polyimide, acrylic, polyamide, resist, or benzocyclobutene, a siloxane resin, or the like may be used.

  Note that the first interlayer insulating film 533 or the second interlayer insulating film 534 and the first interlayer insulating film are caused by a stress generated from a difference in thermal expansion coefficient between the conductive material or the like that forms wirings 535 to 539 to be formed later. In order to prevent film peeling or cracking of the film 533 or the second interlayer insulating film 534, a filler may be mixed in the first interlayer insulating film 533 or the second interlayer insulating film 534.

Next, as shown in FIG. 4D, contact holes are formed in the first interlayer insulating film 533 and the second interlayer insulating film 534, and wirings 535 connected to the n-channel TFTs 529 and 531 and the p-channel TFT 530 are formed. ˜539. As the etching gas for opening the contact hole, a mixed gas of CHF ₃ and He is used, but the etching gas is not limited to this. In this embodiment, the wirings 535 to 539 are made of Al. Note that the wirings 535 to 539 may have a five-layer structure in which Ti, TiN, Al—Si, Ti, and TiN are stacked in this order, and may be formed using a sputtering method.

  In addition, by mixing Si in Al, generation of hillocks in resist baking at the time of wiring patterning can be prevented. Further, instead of Si, about 0.5% Cu may be mixed. Further, the hillock resistance is further improved by sandwiching the Al—Si layer with Ti or TiN. Note that it is desirable to use the hard mask made of silicon oxynitride or the like for patterning. Note that the wiring material and the manufacturing method are not limited to these, and the material used for the gate electrodes 510 to 512 described above may be used.

  Note that the wirings 535 and 536 are in the high-concentration impurity region 527 of the n-channel TFT 529, the wirings 536 and 537 are in the high-concentration impurity region 519 of the p-channel TFT 530, and the wirings 538 and 539 are the high-concentration impurity region of the n-channel TFT 531. 528, respectively.

  Next, as illustrated in FIG. 4E, a third interlayer insulating film 540 is formed over the second interlayer insulating film 534 so as to cover the wirings 535 to 539. The third interlayer insulating film 540 has an opening through which a part of the wiring 535 is exposed. The third interlayer insulating film 540 can be formed using an organic resin film, an inorganic insulating film, or a siloxane-based insulating film. For example, acrylic resin, polyimide, polyamide, or the like can be used for the organic resin film, and silicon oxide, silicon nitride oxide, or the like can be used for the inorganic insulating film. Note that a mask used for forming the opening can be formed by a droplet discharge method or a printing method. Alternatively, the third interlayer insulating film 540 itself can be formed by a droplet discharge method or a printing method.

  Next, the antenna 541 is formed over the third interlayer insulating film 540. The antenna 541 is formed using a conductive material including one or more metals such as Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, Al, Fe, Co, Zn, Sn, and Ni, or a metal compound. Can do. The antenna 541 is connected to the wiring 535. Note that in FIG. 4E, the antenna 541 is directly connected to the wiring 535; however, the ID chip using the manufacturing method of the present invention is not limited to this structure. For example, the antenna 541 and the wiring 535 may be electrically connected using a separately formed wiring.

  The antenna 541 can be formed by a printing method, a photolithography method, a plating method, an evaporation method, a droplet discharge method, or the like. In this embodiment, the antenna 541 is formed of a single-layer conductive film; however, an antenna 541 in which a plurality of conductive films are stacked can be formed.

  By using a printing method or a droplet discharge method, the antenna 541 can be formed without using an exposure mask. In addition, unlike the photolithography method, there is no waste of material that is removed by etching in the droplet discharge method and the printing method. In addition, since it is not necessary to use an expensive exposure mask, the cost for manufacturing the ID chip can be suppressed.

  In the case of using a droplet discharge method or various printing methods, for example, conductive particles in which Cu is coated with Ag can be used. Note that in the case where the antenna 541 is formed by a droplet discharge method, it is preferable to perform treatment on the surface of the third interlayer insulating film 540 so that the adhesion of the antenna 541 is increased.

  Specifically, as a treatment for enhancing the adhesion, for example, a method of attaching a metal or a metal compound capable of enhancing the adhesion of the conductive film or the insulating film to the surface of the third interlayer insulating film 540 by catalytic action, An organic insulating film having high adhesion to the conductive film or insulating film to be formed, a method of attaching a metal or a metal compound to the surface of the third interlayer insulating film 540, and a large amount on the surface of the third interlayer insulating film 540 Examples thereof include a method of performing surface modification by performing plasma treatment under atmospheric pressure or reduced pressure. Examples of the metal having high adhesion to the conductive film or insulating film include titanium, titanium oxide, 3d transition elements such as Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, and Zn. Is mentioned. Examples of the metal compound include the above-described metal oxides, nitrides, and oxynitrides. Examples of the organic insulating film include polyimide and siloxane resin.

  When the metal or metal compound attached to the third interlayer insulating film 540 has conductivity, the sheet resistance is controlled so that the normal operation of the antenna 541 is not hindered. Specifically, the average thickness of the conductive metal or metal compound is controlled to be, for example, 1 to 10 nm, or the metal or metal compound is partially or entirely insulated by oxidation. You can do it. Alternatively, the deposited metal or metal compound may be selectively removed by etching except for the region where the adhesion is desired to be improved. Alternatively, the metal or the metal compound may be selectively attached only to a specific region by using a droplet discharge method, a printing method, a sol-gel method, or the like, instead of attaching the metal or the metal compound to the entire surface of the substrate in advance. Note that the metal or metal compound does not need to be a completely continuous film on the surface of the third interlayer insulating film 540, and may be dispersed to some extent.

  Next, as illustrated in FIG. 5A, a protective layer 543 is formed over the third interlayer insulating film 540 so as to cover the antenna 541. The protective layer 543 is formed using a material that can protect the n-channel TFTs 529 and 531, the p-channel TFT 530, and the wirings 535 to 539 when the peeling layer 502 is removed later by etching. For example, the protective layer 543 can be formed by applying an epoxy resin, an acrylate resin, or a silicon resin soluble in water or alcohols to the entire surface.

In this example, a water-soluble resin (manufactured by Toagosei Co., Ltd .: VL-WSHL10) was applied by spin coating so as to have a film thickness of 30 μm, and after exposure for 2 minutes to perform temporary curing, ultraviolet rays were applied from the back surface. The protective layer 543 is formed by performing exposure for 2.5 minutes and 10 minutes from the surface for a total of 12.5 minutes. In addition, when laminating | stacking several organic resin, there exists a possibility that it may melt | dissolve partially at the time of application | coating or baking with the solvent currently used between organic resins, or adhesiveness may become high too much. Therefore, when both the third interlayer insulating film 540 and the protective layer 543 are made of an organic resin that is soluble in the same solvent, the third interlayer insulating film is removed so that the protective layer 543 can be removed smoothly in the subsequent process. An inorganic insulating film (a silicon nitride film, a silicon nitride oxide film, an AlN _x film, or an AlN _x O _y film) is preferably formed so as to cover 540.

  Next, as shown in FIG. 5B, a groove 546 is formed in order to separate the ID chips. The groove 546 only needs to have a depth such that the peeling layer 502 is exposed. The groove 546 can be formed by dicing, scribing, photolithography, or the like. Note that the groove 546 is not necessarily formed when the ID chip formed over the first substrate 500 does not need to be separated.

Next, as shown in FIG. 5C, the peeling layer 502 is removed by etching. In this embodiment, halogen fluoride is used as an etching gas, and the gas is introduced from the groove 546. In this embodiment, for example, ClF ₃ (chlorine trifluoride) is used under the conditions of temperature: 350 ° C., flow rate: 300 sccm, pressure: 799.8 Pa, time: 3 h. Alternatively, a gas in which nitrogen is mixed with ClF ₃ gas may be used. By using halogen fluoride such as ClF ₃ , the separation layer 502 is selectively etched, and the first substrate 500 can be separated from the n-channel TFTs 529 and 531 and the p-channel TFT 530. The halogen fluoride may be either a gas or a liquid.

  Next, as shown in FIG. 6A, the peeled n-channel TFTs 529 and 531 and the p-channel TFT 530 are attached to the second substrate 548 with an adhesive 547, and the protective layer 543 is removed. As the adhesive 547, a material capable of bonding the second substrate 548 and the base film 503 is used. As the adhesive 547, for example, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

  As the second substrate 548, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, or an organic material such as flexible paper or plastic can be used. Alternatively, a flexible inorganic material may be used for the second substrate 548. As the plastic substrate, ARTON (manufactured by JSR) made of polynorbornene with a polar group can be used. Polyester represented by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), nylon, polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide Examples thereof include plastic substrates made of (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, and the like. The second substrate 548 preferably has a high thermal conductivity of about 2 to 30 W / mK in order to diffuse the heat generated in the integrated circuit.

  Next, as illustrated in FIG. 6B, an adhesive 552 is applied over the antenna 541 and the third interlayer insulating film 540, and the cover material 553 is attached. The cover material 553 can be formed using a material similar to that of the second substrate 548. The thickness of the adhesive 552 may be, for example, 10 to 200 μm.

  The adhesive 552 is formed using a material that can bond the cover material 553 to the antenna 541 and the third interlayer insulating film 540. As the adhesive 552, for example, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

  In this embodiment, the cover material 553 is bonded to the antenna 541 and the third interlayer insulating film 540 using the adhesive 552. However, the present invention is not limited to this structure, and the ID chip is not necessarily a cover material. There is no need to use 553. For example, the mechanical strength of the ID chip may be increased by covering the antenna 541 and the third interlayer insulating film 540 with a resin or the like. Or it is good also as completion | finish by the process shown to FIG. 6 (A), without using the cover material 553. FIG.

The ID chip is completed through the above-described steps. By the above manufacturing method, an extremely thin integrated circuit having a total film thickness of 0.3 μm to 3 μm, typically about 2 μm, can be formed between the second substrate 548 and the cover material 553. Note that the thickness of the integrated circuit includes not only the thickness of the semiconductor element itself but also the thicknesses of various insulating films and interlayer insulating films formed between the adhesive 547 and the adhesive 552 and does not include the thickness of the antenna. Shall. The area occupied by the integrated circuit included in the ID chip, 5 mm square (25 mm ²⁾ or less, and more preferably may be 0.3mm square (0.09 mm ²⁾ to 4 mm square (16 mm ²⁾ degree.

  Note that the mechanical strength of the ID chip can be increased by positioning the integrated circuit at a more central position between the second substrate 548 and the cover member 553. Specifically, when the distance between the second substrate 548 and the cover material 553 is d, the distance x between the center of the integrated circuit in the thickness direction and the second substrate 548 is expressed by the following formula 1. It is desirable to control the thicknesses of the adhesive 547 and the adhesive 552 so as to satisfy the expression shown.

  In addition, preferably, the thicknesses of the adhesive 547 and the adhesive 552 are controlled so that the distance x satisfies the following equation (2).

In addition, as shown in FIG. 7, the distance (t _under ) from the island-shaped semiconductor films 505 to 507 of the TFT in the integrated circuit to the lower base film 503, and the upper third from the island-shaped semiconductor films 505 to 507. Of the base film 503, the first interlayer insulating film 533, the second interlayer insulating film 534, or the third interlayer insulating film 540 so that the distances (t _over ) to the interlayer insulating film 540 are equal or substantially equal. The thickness may be adjusted. In this manner, by placing the island-shaped semiconductor films 505 to 507 in the center of the integrated circuit, stress on the semiconductor film can be relieved and generation of cracks can be prevented.

  In order to ensure the flexibility of the ID chip, when an organic resin is used for the adhesive 547 in contact with the base film 503, a silicon nitride film or a silicon nitride oxide film is used as the base film 503, so that the organic resin can be replaced with Na or the like. The alkali metal or alkaline earth metal can be prevented from diffusing into the island-shaped semiconductor films 505 to 507.

  Further, the surface of the object has a curved surface, so that the second substrate 548 of the ID chip bonded to the curved surface is bent so as to have a curved surface drawn by the movement of the generating line such as a cone surface or a column surface. In this case, it is desirable to align the direction of the bus with the direction in which the carriers of the n-channel TFTs 529 and 531 and the p-channel TFT 530 move. With the above structure, even when the second substrate 548 is bent, it can be prevented that the characteristics of the n-channel TFTs 529 and 531 and the p-channel TFT 530 are affected. Further, the ratio of the area occupied by the island-shaped semiconductor films 505 to 507 in the integrated circuit is 1 to 30%, so that even if the second substrate 548 is bent, the n-channel TFTs 529, 531, p The influence on the characteristics of the channel type TFT 530 can be further suppressed.

  In general, the frequency of radio waves used in an ID chip is 13.56 MHz and 2.45 GHz, and it is very important to increase the versatility to form an ID chip so that radio waves of that frequency can be detected. Is important to.

In addition, the ID chip of this embodiment has an advantage that radio waves are less shielded than an ID chip formed using a semiconductor substrate, and the signal can be prevented from being attenuated by shielding the radio waves. Therefore, it is not necessary to use a semiconductor substrate, so that the cost of the ID chip can be significantly reduced. For example, a case where a semiconductor substrate having a diameter of 12 inches is used is compared with a case where a glass substrate having a size of 730 × 920 mm ² is used. The area of the former semiconductor substrate is about 73000 mm ² , but the area of the latter glass substrate is about 672000 mm ² , and the glass substrate corresponds to about 9.2 times the semiconductor substrate. When the area of the latter glass substrate is about 672,000 mm ² , ignoring the area consumed by dividing the substrate, it is calculated that about 672,000 1 mm square ID chips can be formed, and the number is about 9.2 times that of the semiconductor substrate. It is equivalent to the number of The capital investment for mass production of ID chips requires fewer steps when using a 730 × 920 mm ² glass substrate than when using a 12-inch diameter semiconductor substrate. It can be done in a third. Further, in the present invention, the glass substrate can be used again after the integrated circuit is peeled off. Therefore, cost can be significantly reduced as compared with the case of using a semiconductor substrate, even in view of the expense of filling a damaged glass substrate and cleaning the surface of the glass substrate. Even if the glass substrate is discarded without being reused, the cost of a 730 × 920 mm ² glass substrate is about half that of a semiconductor substrate having a diameter of 12 inches, thus greatly reducing the cost of the ID chip. You can see that

Therefore, it can be seen that when a glass substrate of 730 × 920 mm ² is used, the price of the ID chip can be reduced to about 1/30 compared to the case of using a semiconductor substrate having a diameter of 12 inches. Since the ID chip is expected to be used on the premise that it is disposable, the ID chip using the manufacturing method of the present invention, which can significantly reduce the cost, is very useful for the above application.

  In this example, an optical microscope photograph of a sample obtained by crystallizing a peeling layer by crystallizing a semiconductor film with a continuous wave laser and then etching the peeling layer will be described.

  In the sample used in this example, a buffer film, a release layer, a base film, and a semiconductor film are stacked in this order on a glass substrate, and then the semiconductor film is crystallized using a catalytic element, and the semiconductor film is formed using a continuous wave laser. The semiconductor film partially crystallized and then crystallized by etching is removed. Then, the release layer is exposed by forming a groove by scribing, and the release layer is partially etched.

  Specifically, for each sample, a buffer film made of 100 nm silicon oxynitride is formed on a glass substrate using a sputtering method, and peeling is made of 50 nm amorphous silicon using a plasma CVD method on the buffer film. Forming a layer. A base film in which an insulating film made of silicon oxynitride, an insulating film made of silicon nitride oxide, and an insulating film made of silicon oxynitride are sequentially stacked is formed over the release layer. Each of the insulating films used as the base film is formed by using a plasma CVD method, and the film thicknesses are 100 nm, 50 nm, and 100 nm in this order. A semiconductor film made of amorphous silicon is formed on the base film using a plasma CVD method.

The etching gas was ClF ₃ diluted with N ₂ , and the etching gas was introduced from the groove. The ClF ₃ flow rate was 100 sccm, the partial pressure was 799.8 Pa, the N ₂ flow rate was 250 sccm, the partial pressure was 226.6 Pa, and the etching temperature was 100 ° C. and the time was 0.5 h.

9 to 11 show optical micrographs of each sample after the release layer is partially etched. The magnification of the photograph is 200 times, FIG. 9 corresponds to a sample with a semiconductor film thickness of 66 nm, FIG. 10 corresponds to a sample with a semiconductor film thickness of 100 nm, and FIG. 11 corresponds to a sample with a semiconductor film thickness of 150 nm. . Laser crystallization of the semiconductor film uses a continuous wave Nd: YVO ₄ laser, the laser beam is the second harmonic (532 nm), the scanning speed is 35 cm / sec, the size of the beam spot is 400 μm in the major axis, 10 to 10 in the minor axis. It was 20 μm. The energy of the laser beam was 5.0 W for the sample of FIG. 9, 6.1 W for the sample of FIG. 10, and 6.1 W for the sample of FIG.

  9 to 11, a region A corresponds to a region irradiated with continuous wave laser light, and a region B corresponds to a region not irradiated with laser light. A straight groove is formed in the horizontal direction of the photograph, and the black part that spreads out from the groove corresponds to the region 801 where the peeling layer is peeled off by etching, and the peeling layer is peeled off in other regions. This corresponds to the area 802 that is not.

  9 to 11, in the region 801 where the release layer is peeled in the region A, the width in the direction perpendicular to the groove is Wa, and in the region 801 where the release layer is peeled in the region B, The width in the direction perpendicular to the groove is Wb. In the case of FIG. 9, Wa / Wb≈2.29, in the case of FIG. 10, Wa / Wb≈3.36, and in the case of FIG. 11, Wa / Wb≈3.36. Accordingly, it can be seen from FIGS. 9 to 11 that the region 801 where the release layer is peeled is wider in the region A than in the region B in all the samples. Therefore, it was found that the lower peeling layer was crystallized by crystallization of the semiconductor film, thereby improving the etching rate.

  A structure of an ID chip in the case where a wiring connected to a TFT and an antenna are formed together by patterning a conductive film will be described with reference to FIG. FIG. 12A shows a cross-sectional view of the ID chip of this embodiment.

  12A, the TFT 1401 includes an island-shaped semiconductor film 1402, a gate insulating film 1403 in contact with the island-shaped semiconductor film 1402, and an island-shaped semiconductor film 1402 with the gate insulating film 1403 interposed therebetween. And an overlapping gate electrode 1404. The TFT 1401 is covered with a first interlayer insulating film 1405 and a second interlayer insulating film 1406. Note that in this embodiment, the TFT 1401 is covered with two interlayer insulating films, ie, a first interlayer insulating film 1405 and a second interlayer insulating film 1406, but this embodiment is not limited to this structure. The TFT 1401 may be covered with a single-layer interlayer insulating film, or may be covered with three or more interlayer insulating films.

  Then, the wiring 1407 formed over the second interlayer insulating film 1406 is formed on the island-shaped semiconductor film 1402 through contact holes formed in the first interlayer insulating film 1405 and the second interlayer insulating film 1406. It is connected.

  An antenna 1408 is formed over the second interlayer insulating film 1406. The wiring 1407 and the antenna 1408 can be formed together by forming a conductive film over the second interlayer insulating film 1406 and patterning the conductive film. By forming the antenna 1408 together with the wiring 1407, the number of manufacturing steps of the ID chip can be reduced.

  Next, the structure of the ID chip in the case where the TFT gate electrode and the antenna are formed together by patterning the conductive film will be described with reference to FIG. FIG. 12B shows a cross-sectional view of the ID chip of this embodiment.

  12B, an TFT 1411 includes an island-shaped semiconductor film 1412, a gate insulating film 1413 overlapping with the island-shaped semiconductor film 1412, and an island-shaped semiconductor film 1412 with the gate insulating film 1413 interposed therebetween. And an overlapping gate electrode 1414. An antenna 1418 is formed over the gate insulating film 1413. The gate electrode 1414 and the antenna 1418 can be formed together by forming a conductive film over the gate insulating film 1413 and patterning the conductive film. By forming the antenna 1418 together with the gate electrode 1414, the number of manufacturing steps of the ID chip can be suppressed.

  In this embodiment, a structure of an ID chip in which an antenna formed over another substrate and an integrated circuit are electrically connected is described.

  FIG. 13 shows a cross-sectional view of the ID chip of this example. In FIG. 13, an adhesive 1203 is applied over the third interlayer insulating film 1204 so as to cover the wiring 1202 electrically connected to the TFT 1201. Then, the cover material 1205 is bonded to the third interlayer insulating film 1204 with an adhesive 1203.

  An antenna 1206 is formed on the cover material 1205 in advance. In this embodiment, the anisotropic conductive resin is used for the adhesive 1203 so that the antenna 1206 and the wiring 1202 are electrically connected.

  An anisotropic conductive resin is a material in which a conductive material is dispersed in a resin. As the resin, for example, those having thermosetting properties such as epoxy-based, urethane-based, and acrylic-based materials, thermoplastic materials such as polyethylene-based and polypropylene-based materials, and siloxane-based resins can be used. As conductive materials, for example, plastic particles such as polystyrene and epoxy are plated with Ni, Au, metal particles such as Ni, Au, Ag, and solder, particulate or fibrous carbon, and fibrous Ni. A material plated with Au can be used. The size of the conductive material is preferably determined in accordance with the pitch between the antenna 1206 and the wiring 1202.

  Further, between the antenna 1206 and the wiring 1202, the anisotropic conductive resin may be pressed while applying ultrasonic waves, or may be pressed while being cured by irradiation with ultraviolet rays.

  Note that although an example in which the antenna 1206 and the wiring 1202 are electrically connected with an adhesive 1203 using an anisotropic conductive resin is described in this embodiment, the present invention is not limited to this structure. Instead of the adhesive 1203, an anisotropic conductive film may be used, and the antenna 1206 and the wiring 1202 may be electrically connected by pressing the anisotropic conductive film.

  In this example, a structure of an ID chip manufactured using the manufacturing method of the present invention will be described.

  FIG. 14A is a perspective view illustrating one mode of an ID chip. Reference numeral 920 denotes an integrated circuit, and 921 denotes an antenna. The antenna 921 is electrically connected to the integrated circuit 920. Reference numeral 922 denotes a substrate, and 923 denotes a cover material. The integrated circuit 920 and the antenna 921 are sandwiched between the substrate 922 and the cover material 923.

  Next, FIG. 14B is a block diagram illustrating one mode of a functional structure of the ID chip illustrated in FIG.

  In FIG. 14B, 900 corresponds to an antenna, and 901 corresponds to an integrated circuit. Reference numeral 903 corresponds to a capacitance formed between both terminals of the antenna 900. The integrated circuit 901 includes a demodulation circuit 909, a modulation circuit 904, a rectification circuit 905, a microprocessor 906, a memory 907, and a switch 908 for applying load modulation to the antenna 900. Note that the memory 907 is not limited to one, and a plurality of memories 907 may be used, such as SRAM, flash memory, ROM, or FRAM (registered trademark).

  A signal transmitted as a radio wave from the reader / writer is converted into an AC electrical signal by electromagnetic induction in the antenna 900. The demodulation circuit 909 demodulates the alternating electrical signal and transmits it to the subsequent microprocessor 906. The rectifier circuit 905 generates a power supply voltage using an alternating electrical signal and supplies the power supply voltage to the subsequent microprocessor 906. The microprocessor 906 performs various arithmetic processes according to the input signal. The memory 907 stores programs and data used in the microprocessor 906, and can also be used as a work area during arithmetic processing.

  When data is sent from the microprocessor 906 to the modulation circuit 904, the modulation circuit 904 controls the switch 908 and can apply load modulation to the antenna 900 in accordance with the data. The reader / writer can read the data from the microprocessor 906 as a result of receiving the load modulation applied to the antenna 900 by radio waves.

  Note that the ID chip does not necessarily have the microprocessor 906. Further, the signal transmission method is not limited to the electromagnetic coupling method as shown in FIG. 14B, and an electromagnetic induction method, a microwave method, or other transmission methods may be used.

  In this embodiment, a structure of a TFT of a semiconductor device manufactured using the manufacturing method of the present invention will be described.

  FIG. 15A shows a cross-sectional view of the TFT of this example. Reference numeral 701 corresponds to an n-channel TFT, and 702 corresponds to a p-channel TFT. A more detailed configuration will be described by taking an n-channel TFT 701 as an example.

  The n-channel TFT 701 includes an island-shaped semiconductor film 705 used as an active layer. The island-shaped semiconductor film 705 includes impurity regions 703a and 703b used as a source region or a drain region, and the impurity regions 703a and 703b. Channel formation region 704 sandwiched between them, and LDD (Light Doped Drain) regions 710a and 710b sandwiched between impurity regions 703a and 703b and channel formation region 704. The n-channel TFT 701 includes a gate insulating film 706 covering the island-shaped semiconductor film 705, a gate electrode 707, and two sidewalls 708 and 709 formed of the insulating film.

  In this embodiment, the gate electrode 707 includes two conductive films 707a and 707b. However, the present invention is not limited to this structure. The gate electrode 707 may be formed of a single conductive film or may be formed of two or more conductive films. The gate electrode 707 overlaps with a channel formation region 704 included in the island-shaped semiconductor film 705 with the gate insulating film 706 interposed therebetween. The sidewalls 708 and 709 overlap with the LDD regions 710a and 710b included in the island-shaped semiconductor film 705 with the gate insulating film 706 interposed therebetween.

  The sidewall 708 can be formed by etching a silicon oxide film with a thickness of 100 nm, for example, and the sidewall 709 can be formed by etching an LTO film (Low Temperature Oxide) with a thickness of 200 nm, for example. . In this embodiment, a silicon oxide film used for the sidewall 708 is formed by a plasma CVD method, and an LTO film used for the sidewall 709 is formed by a low pressure CVD method. Note that the silicon oxide film may contain nitrogen, but the number of nitrogen atoms is less than the number of oxygen atoms.

  The impurity regions 703a and 703b and the LDD regions 710a and 710b are formed by doping the island-shaped semiconductor film 705 with an n-type impurity using the gate electrode 707 as a mask, and then forming sidewalls 708 and 709. The island-shaped semiconductor film 705 can be formed separately by doping an n-type impurity as a 709 mask.

  Note that the p-channel TFT 702 has almost the same configuration as the n-channel TFT 701, but differs only in the configuration of the island-shaped semiconductor film 711 included in the p-channel TFT 702. The island-shaped semiconductor film 711 does not have an LDD region, but has impurity regions 712a and 712b and a channel formation region 713 sandwiched between the impurity regions 712a and 712b. The impurity regions 712a and 712b are doped with p-type impurities. Note that FIG. 15A illustrates an example in which the p-channel TFT 702 does not have an LDD region; however, the present invention is not limited to this structure. The p-channel TFT 702 may have an LDD region.

  FIG. 15B illustrates the case where the TFT illustrated in FIG. 15A has one sidewall. The n-channel TFT 721 and the p-channel TFT 722 illustrated in FIG. 15B each have one sidewall 728 and 729. The sidewalls 728 and 729 can be formed by etching a silicon oxide film having a thickness of 100 nm, for example. In this embodiment, a silicon oxide film used for the sidewall 728 is formed by a plasma CVD method. Note that the silicon oxide film may contain nitrogen, but the number of nitrogen atoms is less than the number of oxygen atoms.

  Next, FIG. 15C illustrates a structure of a bottom-gate TFT. 741 corresponds to an n-channel TFT, and 742 corresponds to a p-channel TFT. A more detailed configuration will be described by taking an n-channel TFT 741 as an example.

  In FIG. 15C, an n-channel TFT 741 includes an island-shaped semiconductor film 745. The island-shaped semiconductor film 745 includes impurity regions 743a and 743b used as a source region or a drain region, and the impurity regions. A channel formation region 744 sandwiched between 743a and 743b; and LDD (Light Doped Drain) regions 750a and 750b sandwiched between the impurity regions 743a and 743b and the channel formation region 744. The n-channel TFT 741 includes a gate insulating film 746, a gate electrode 747, and a channel protective film 748 formed of an insulating film.

  The gate electrode 747 overlaps with a channel formation region 744 included in the island-shaped semiconductor film 745 with the gate insulating film 746 interposed therebetween. The gate insulating film 746 is formed after the gate electrode 747 is formed, and the island-shaped semiconductor film 745 is formed after the gate insulating film 746 is formed. The channel protective film 748 overlaps with the gate insulating film 746 with the channel formation region 744 interposed therebetween.

  The channel protective film 748 can be formed by etching a 100 nm-thickness silicon oxide film, for example. In this embodiment, a silicon oxide film used for the channel protective film 748 is formed by a plasma CVD method. Note that the silicon oxide film may contain nitrogen, but the number of nitrogen atoms is less than the number of oxygen atoms.

  The impurity region 743 and the LDD region 750 are formed by doping an island-shaped semiconductor film 745 with an n-type impurity using a resist mask and then forming a channel protective film 748, and using the channel protective film 748 mask as an island shape The semiconductor film 745 can be formed separately by doping an n-type impurity.

  Note that the p-channel TFT 742 has almost the same configuration as the n-channel TFT 741, but differs only in the configuration of the island-shaped semiconductor film 751 included in the p-channel TFT 742. The island-shaped semiconductor film 751 does not have an LDD region, but has impurity regions 752a and 752b and a channel formation region 753 sandwiched between the impurity regions 752a and 752b. The impurity regions 752a and 752b are doped with p-type impurities. Note that FIG. 15C illustrates an example in which the p-channel TFT 742 does not have an LDD region; however, the present invention is not limited to this structure. The p-channel TFT 742 may have an LDD region. Further, the n-channel TFT 741 does not have to have an LDD region.

  In this embodiment, a method for manufacturing a plurality of semiconductor devices using a large substrate will be described. In this embodiment, an ID chip which is one of semiconductor devices will be described as an example.

  First, the integrated circuit 401 and the antenna 402 are formed over a heat-resistant substrate, and then peeled off, and then attached to a separately prepared substrate 403 with an adhesive 404 as shown in FIG. Note that FIG. 16A illustrates a state where the integrated circuit 401 and the antenna 402 are bonded to the substrate 403 one by one, but the present invention is not limited to this structure. The set of the integrated circuit 401 and the antenna 402 may be peeled off in a state where they are connected to each other and attached to the substrate 403 at a time.

  Next, as illustrated in FIG. 16B, a cover material 405 is attached to the substrate 403 so that the integrated circuit 401 and the antenna 402 are sandwiched therebetween. At this time, an adhesive 406 is applied on the substrate 403 so as to cover the integrated circuit 401 and the antenna 402. A state shown in FIG. 16C is obtained by attaching the cover material 405 to the substrate 403. Note that in FIG. 16C, the integrated circuit 401 and the antenna 402 are illustrated so as to be seen through the cover member 405 in order to clarify the positions of the integrated circuit 401 and the antenna 402.

  Next, as shown in FIG. 16D, the integrated circuit 401 and the antenna 402 are separated from each other by dicing or scribing, whereby the ID chip 407 is completed.

  Note that although an example in which the antenna 402 is peeled off together with the integrated circuit 401 is shown in this embodiment, this embodiment is not limited to this structure. The antenna 402 may be formed over the substrate 403 in advance, and the integrated circuit 401 and the antenna 402 may be electrically connected when the integrated circuit 401 is attached to the substrate 403. Alternatively, after the integrated circuit 401 is attached to the substrate 403, the antenna 402 may be attached so as to be electrically connected to the integrated circuit 401. Alternatively, the antenna 402 may be formed over the cover material 405 in advance, and the integrated circuit 401 and the antenna 402 may be electrically connected when the cover material 405 is attached to the substrate 403.

  Note that an ID chip using a glass substrate can be referred to as an IDG chip (Identification Glass Chip), and an ID chip using a flexible substrate can be referred to as an IDF chip (Identification Flexible Chip).

  This embodiment can be implemented in combination with the first to sixth embodiments.

  In this embodiment, the shape of a groove formed when a plurality of semiconductor devices formed on one substrate is peeled will be described. FIG. 17A shows a top view of a substrate 603 over which a groove 601 is formed. FIG. 17B is a cross-sectional view taken along line A-A ′ in FIG.

  The semiconductor device 602 is formed over the separation layer 604, the separation layer 604 is formed over the buffer film 606, and the buffer film 606 is formed over the substrate 603. The groove 601 is formed between the semiconductor devices 602 and has a depth to the extent that the release layer 604 is exposed. In this embodiment, the plurality of semiconductor devices 602 are not completely separated but partially separated by the grooves 601.

  Next, a state after etching gas is flowed from the groove 601 shown in FIGS. 17A and 17B and the peeling layer 604 is removed by etching is shown in FIGS. 17C and 17D. . FIG. 17C corresponds to a top view of the substrate 603 in which the groove 601 is formed, and FIG. 17D corresponds to a cross-sectional view taken along line A-A ′ in FIG. It is assumed that the etching of the peeling layer 604 has progressed from the groove 601 to the region indicated by the broken line 605 by etching. As shown in FIGS. 17C and 17D, the peeling layer 604 is etched by separating the plurality of semiconductor devices 602 by the grooves 601 in a state of being partially connected to each other, not completely. It is possible to prevent each semiconductor device 602 from moving without support later.

  After the state shown in FIGS. 17C and 17D is formed, a tape, a substrate, or the like to which an adhesive is attached is separately prepared, and the semiconductor device 602 is peeled from the substrate 603. The plurality of separated semiconductor devices 602 are bonded to a separately prepared substrate before or after being separated from each other.

  Note that this embodiment shows an example of a manufacturing method of an ID chip, and a manufacturing method of an ID chip using the manufacturing method of the present invention is not limited to the structure shown in this embodiment.

  This embodiment can be implemented in combination with the first to seventh embodiments.

  Semiconductor devices manufactured using the manufacturing method of the present invention include, for example, cameras such as video cameras and digital cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, audio components, etc.), computers Playing a recording medium such as a game machine, a portable information terminal (mobile computer, cellular phone, portable game machine, electronic book, etc.), an image reproducing device (specifically a DVD: Digital Versatile Disc) equipped with a recording medium, etc. , An apparatus provided with a display capable of displaying the image). In particular, a flexible substrate can be easily reduced in weight and thickness compared to a glass substrate or the like, and when a peeled semiconductor element is bonded to the flexible substrate, a semiconductor device It is easy to realize light weight, downsizing and thinning. Therefore, a semiconductor device formed using the manufacturing method of the present invention is particularly suitable for a portable electronic device or a display device having a relatively large screen. Specific examples of these electronic devices are shown in FIGS.

  FIG. 18A illustrates a portable information terminal, which includes a main body 2001, a display portion 2002, operation keys 2003, a modem 2004, and the like. Although FIG. 18A shows a portable information terminal in which the modem 2004 is removable, the modem may be built in the main body 2001. According to the present invention, a portable information terminal can be completed by manufacturing the display portion 2002 or other signal processing circuits. According to the present invention, the yield of portable information terminals can be increased, and as a result, the price per portable information terminal that is a good product can be suppressed.

  FIG. 18B illustrates an IC card, which includes a main body 2201, a display portion 2202, a connection terminal 2203, and the like. According to the present invention, an IC card can be completed by manufacturing the display portion 2202 or other signal processing circuits. According to the present invention, the yield of IC cards can be increased, and as a result, the price per IC card that is a good product can be suppressed. Note that FIG. 18B shows a contact-type electronic card; however, the semiconductor device of the present invention can be used for a non-contact type IC card or an IC card having both a contact type and a non-contact type function. Can do.

  FIG. 18C illustrates a display device, which includes a housing 2101, a display portion 2102, a speaker portion 2103, and the like. According to the present invention, the display portion can be completed by manufacturing the display portion 2102 or other signal processing circuits. According to the present invention, the yield of display devices can be increased, and as a result, the price per display device that is a non-defective product can be suppressed. The display device includes all information display devices such as a computer, a television broadcast receiver, and an advertisement display.

  FIG. 18D illustrates a computer, which includes a main body 2301, a housing 2302, a display portion 2303, a keyboard 2304, a mouse 2305, and the like. The computer may be a computer in which a monitor and a main body having a CPU are integrated (for example, a notebook computer), or a computer in which the monitor and the main body having a CPU are separated (for example, a desktop computer). There may be. According to the present invention, the display portion 2303 or other signal processing circuits can be manufactured to complete the computer. According to the present invention, the yield of computers can be increased, and as a result, the price per good computer can be suppressed.

  FIG. 18E shows an image reproduction device (specifically, a DVD reproduction device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion 2403, a recording medium (DVD etc.) reading portion 2404, and operation keys 2405. , Speaker portion 2406 and the like. The image reproducing device provided with the recording medium includes a home game machine and the like. According to the present invention, the display portion 2403 or other signal processing circuits can be manufactured to complete the image reproducing device. According to the present invention, it is possible to increase the yield of image reproduction apparatuses, and as a result, it is possible to suppress the price per image reproduction apparatus that is a good product.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic apparatus of this embodiment may use any of the configurations shown in Embodiments 1 to 8.

4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. Sectional drawing of the semiconductor device of this invention. The graph which shows the margin of energy at the time of crystallizing a semiconductor film with a continuous wave laser. Photomicrograph after etching. Photomicrograph after etching. Photomicrograph after etching. FIG. 13 is a cross-sectional view of a semiconductor device using a manufacturing method of the present invention. FIG. 13 is a cross-sectional view of a semiconductor device using a manufacturing method of the present invention. 4A and 4B illustrate a structure of an ID chip using a manufacturing method of the present invention. Examples of TFTs included in a semiconductor device using the manufacturing method of the present invention. 4A and 4B illustrate a method for manufacturing a plurality of semiconductor devices of the present invention using a large substrate. The figure which shows the shape of the groove | channel formed when peeling the several semiconductor device formed on one board | substrate. FIG. 16 is a diagram of an electronic device using a semiconductor device.

Explanation of symbols

100 First substrate 101 Buffer film 102 Release layer 103 Base film 104 Semiconductor film 105 TFT
106 TFT
107 TFT
108 Interlayer insulating film 109 Wiring 110 Wiring 111 Wiring 112 Wiring 113 Wiring 114 Protective layer 115 Second substrate 116 Adhesive 500 First substrate 501 Buffer film 502 Release layer 503 Base film 504 Semiconductor film 505 Semiconductor film 506 Semiconductor film 507 Semiconductor Film 508 Gate insulating film 510 Gate electrode 511 Gate electrode 512 Gate electrode 513 Resist 514 Resist 516 Low concentration impurity region 517 Low concentration impurity region 518 Resist 519 High concentration impurity region 520 Insulating film 522 Side wall 523 Side wall 524 Side wall 525 Resist 527 High concentration impurity region 528 High concentration impurity region 529 n-channel TFT
530 p-channel TFT
531 n-channel TFT
533 First interlayer insulating film 534 Second interlayer insulating film 535 Wiring 536 Wiring 537 Wiring 538 Wiring 539 Wiring 540 Third interlayer insulating film 541 Antenna 543 Protective layer 546 Groove 547 Adhesive 548 Second substrate 552 Adhesive 553 Cover material 801 Peeled area 802 Peeled area 1401 TFT
1402 Semiconductor film 1403 Gate insulating film 1404 Gate electrode 1405 First interlayer insulating film 1406 Second interlayer insulating film 1407 Wiring 1408 Antenna 1411 TFT
1412 Semiconductor film 1413 Gate insulating film 1414 Gate electrode 1418 Antenna 1201 TFT
1202 Wiring 1203 Adhesive 1204 Third interlayer insulating film 1205 Cover material 1206 Antenna 920 Integrated circuit 921 Antenna 922 Substrate 923 Cover material 900 Antenna 901 Integrated circuit 903 Capacitance 904 Modulation circuit 905 Rectification circuit 906 Microprocessor 907 Memory 908 Switch 909 Demodulation circuit 701 n-channel TFT
702 p-channel TFT
703 Impurity region 704 Channel formation region 705 Semiconductor film 706 Gate insulating film 707 Gate electrode 707a Conductive film 707b Conductive film 708 Side wall 709 Side wall 710 LDD (Light Doped Drain) region 711 Semiconductor film 712 Impurity region 713 Channel formation region 721 n channel Type TFT
722 p-channel TFT
728 Side wall 729 Side wall 741 n-channel TFT
742 p-channel TFT
743 Impurity region 744 Channel formation region 745 Semiconductor film 746 Gate insulating film 747 Gate electrode 748 Channel protective film 750 LDD (Light Doped Drain) region 751 Semiconductor film 752 Impurity region 753 Channel formation region 401 Integrated circuit 402 Antenna 403 Substrate 404 Adhesive 405 Cover material 406 Adhesive 407 ID chip 601 Groove 602 Semiconductor device 603 Substrate 604 Release layer 605 Broken line 606 Buffer film 2001 Main body 2002 Display unit 2003 Operation key 2004 Modem 2201 Main body 2202 Display unit 2203 Connection terminal 2101 Housing 2102 Display unit 2103 Speaker unit 2301 Main body 2302 Housing 2303 Display unit 2304 Keyboard 2305 Mouse 2401 Main body 2402 Housing 2403 Display unit 2404 Reading See section 2405 operation key 2406 a speaker portion

Claims (7)

On the first substrate , a buffer film having a function of relaxing stress applied to the release layer during heat treatment is formed so as to be in contact with the first substrate,
A release layer is formed on the buffer film so as to be in contact with the buffer film,
A base film is formed on the release layer so as to be in contact with the release layer,
Forming a semiconductor film on the base film;
The semiconductor film is crystallized using a continuous wave laser or a pulsed laser having an oscillation frequency of 10 MHz or more,
A semiconductor element is formed using the crystallized semiconductor film,
By removing the peeling layer by etching, the base film and the semiconductor element are peeled from the first substrate and the buffer film,
Bonding the peeled base film and the semiconductor element to a second substrate,
A method for manufacturing a semiconductor device, characterized in that when the semiconductor film is crystallized, the release layer is also crystallized. On the first substrate , a buffer film having a function of relaxing stress applied to the release layer during heat treatment is formed so as to be in contact with the first substrate,
A release layer is formed on the buffer film so as to be in contact with the buffer film,
A base film is formed on the release layer so as to be in contact with the release layer,
Forming a semiconductor film on the base film;
The semiconductor film is crystallized using a continuous wave laser or a pulsed laser having an oscillation frequency of 10 MHz or more,
A plurality of semiconductor elements are formed using the crystallized semiconductor film,
Forming a groove such that the release layer is exposed between the plurality of semiconductor elements;
By removing the peeling layer by etching by introducing an etching agent from the groove, the base film and the plurality of semiconductor elements are peeled from the first substrate and the buffer film,
Bonding the peeled base film and the plurality of semiconductor elements to a second substrate,
A method for manufacturing a semiconductor device, characterized in that when the semiconductor film is crystallized, the release layer is also crystallized.   3. The method for manufacturing a semiconductor device according to claim 1, wherein the second substrate has flexibility.   4. The method for manufacturing a semiconductor device according to claim 1, wherein silicon is used for the release layer.   5. The method for manufacturing a semiconductor device according to claim 1, wherein a gas or a liquid containing a halide is used as the etching agent.   6. The method for manufacturing a semiconductor device according to claim 1, wherein the buffer film is formed using silicon oxide or silicon oxynitride.   7. The method for manufacturing a semiconductor device according to claim 1, wherein the base film is formed using silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide.