JP5003070B2 - Digital signal processor - Google Patents

Description

  The present invention relates to a digital signal processing apparatus suitable for audio equipment and the like.

As is well known, a DSP (Digital Signal Processor) performs various kinds of arithmetic processing such as a product-sum operation for convolving a predetermined coefficient sequence with an input audio sample sequence every sampling period of a predetermined time length. Is used for an effector or the like that gives various sound field effects to an input audio sample sequence. This type of DSP is disclosed in, for example, Patent Documents 1 and 2. Recently, DSPs have been installed in small devices such as mobile phones. For this reason, there is a demand for a DSP that is small and capable of executing various signal processing. In order to satisfy such a requirement, a program for controlling signal processing is stored in the RAM, and while executing the program stored in the RAM, the program in the RAM can be rewritten from the outside in parallel. A DSP having a possible configuration or a coefficient sequence used for signal processing is stored in a RAM, and signal processing is executed using the coefficient sequence stored in the RAM, and at the same time, the coefficient sequence in the RAM is rewritten from the outside. It has come to be provided with a DSP having a configuration that can be used. According to this type of DSP, a program or coefficient sequence in the RAM can be rewritten from the outside, so that various signal processing can be executed even when the storage capacity of the RAM is small.
JP-A-8-263297 JP 2002-73341 A

  By the way, in the above-mentioned conventional DSP, in order to be able to rewrite the program and coefficient sequence stored in the RAM in parallel with reading the program and coefficient sequence from the RAM for executing signal processing, A dual port RAM is used as a RAM for storing the columns. For this reason, the area required for the RAM on the DSP chip is widened, which is an obstacle to further downsizing and cost reduction of the DSP.

  The present invention has been made in view of the circumstances described above. A RAM having a small single port configuration can be used as a RAM for storing a program and a coefficient sequence, and data (programs and coefficients) in the RAM can be used. An object of the present invention is to provide a DSP capable of rewriting data in a RAM in parallel with the execution of signal processing using a column.

The present invention performs a process using a memory having a plurality of areas each storing a plurality of data, a read control means for repeatedly reading a plurality of data from the memory, and a process using the data read from the memory Processing means and at least a part of the plurality of data read from the memory between the time when the plurality of data is read from the memory and the time when the next plurality of data is read from the memory Data supply control means for sequentially supplying data to the processing means, and write control means for performing control to write data into the memory using a period during which data is not read from the memory. A digital signal processing apparatus is provided.
According to this invention, the read control unit repeats the control of reading a plurality of data from the memory, and after the data supply control unit reads the plurality of data from the memory, the next plurality of data from the memory At least a part of the plurality of data read from the memory until the reading is performed is sequentially supplied to the processing means. Then, the write control means controls to write data to the memory using a period during which data is not read from the memory. Therefore, even when a small single-port RAM is used as the memory, the data in the memory can be rewritten in parallel with the execution of the signal processing using the data (program or coefficient sequence) in the memory.

  Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing the configuration of a DSP according to the first embodiment of the present invention.
In FIG. 1, a clock generator 1 is a circuit that generates a clock φ having a predetermined frequency. This clock φ is used for timing control of each part of the DSP. The program memory 2 is a memory for storing a series of instructions that are components of a program executed by the DSP, and is configured by a single port RAM having one data input port, one data output port, and one address port. Has been.

  The program memory 2 has a plurality of areas (128 areas in this example) each having a storage capacity of 2N bits (N is a predetermined plurality). Each of these areas has a unique memory address (memory addresses “0” to “127” in this example).

  In each area of the program memory 2, two N-bit instructions are stored. Each of these instructions has a unique instruction address. As shown in the drawing, in the area where the memory address is k (k = 0, 1, 2,...), The instruction # 2k (k = 0, 1, 2,. ) And the instruction # 2k + 1 (k = 0, 1, 2,...) Of the instruction address 2k + 1 is stored as the lower N bits of data.

  Data reading from the program memory 2 can be executed in area units (2N bit units). That is, when memory address data ADRc (in this example, 7-bit memory address data) specifying the memory address of the area to be read is applied to the address port and an active level read command RE is applied, The memory 2 outputs 2N-bit data in the memory address area specified by the memory address data ADRc from the data output port. The read command RE is set to the active level in synchronization with the clock φ. However, except for exceptional cases such as when a jump instruction is executed, the read command RE is set to the active level once every time the clock φ is generated twice. The

  On the other hand, data writing to the program memory 2 can be executed in units of instructions (in units of N bits). More specifically, when writing data to the program memory 2, the memory address data ADRc is applied to the address port of the program memory 2, the N-bit write data WD is applied to the data input port of the program memory 2, and the program memory 2, an active level write command WE and a region designation signal U / L are given. When area designating signal U / L is at L level, write data WD is written into the upper N bits of the memory address area designated by memory address data ADRc, and area designating signal U / L is at H level. In some cases, the write data WD is written to the lower N bits of the memory address area specified by the address data ADRc. The write command WE is set to an active level in synchronization with the clock φ when there is data WD to be written to the program memory 2 and data reading from the program memory 2 is not performed.

  The signal processing unit 3 is a circuit that performs signal processing such as effecting on an input signal given from the outside in accordance with a sequentially given command, and outputs a signal obtained by this signal processing to the outside. Similar to a known DSP, the signal processing unit 3 stores a coefficient memory that stores a filter coefficient sequence for applying an effect, a calculation unit for performing a convolution operation of the filter coefficient sequence on an input signal, and an intermediate result of the calculation. RAM and the like are provided. The signal processing unit 3 and an address setting unit 62 in the read control unit 6 to be described later are processes using data (commands in this embodiment) read from the memory (program memory 2 in the present embodiment). And more specifically, an instruction execution means for executing an instruction read from the memory.

  Between the data output port of the program memory 2 and the signal processing unit 3, a register 4 and a selector 5 as data selection means are interposed as shown. An instruction read from the data output port of the program memory 2 is supplied to the signal processing unit 3 as an execution target instruction OPe through a portion including the register 4 and the selector 5.

  More specifically, the instruction OP0 occupying the upper N bits of the 2N-bit data output from the data output port of the program memory 2 is supplied to the selector 5, and the instruction OP1 occupying the lower N bits is supplied to the selector 5. And supplied to the register 4. The register 4 is supplied with a clock φ. The register 4 holds the instruction OP1 at the rising edge of the clock φ, and outputs the held instruction OP1 to the selector 5 as the instruction OP1d.

  The selector 5 is provided with a 2-bit selection signal SEL2 from the selection control unit 10. The selector 5 receives an instruction OP0 output from the data output port of the program memory 2 when the selection signal SEL2 is “0” (= 00B), and from the register 4 when the selection signal SEL2 is “1” (= 01B). When the selection signal SEL2 is “2” (= 10B), the instruction OP1 output from the data output port of the program memory 2 is selected, and the selected instruction is output as the execution target instruction OPe.

  The register 4 and the selector 5 described above and the selection control unit 10 read a plurality of data (instructions in this embodiment) from the memory (in the case of this embodiment, the program memory 2), and then At least a part of the plurality of data read from the memory before the reading of the plurality of data from the memory is performed on the processing means (in this embodiment, the signal processing unit 3 and the address setting unit 62). Data supply control means for supplying sequentially is configured.

  The read control unit 6 includes an address counter 61, an address setting unit 62, and a read command generation unit 63. The address counter 61 is an 8-bit up counter capable of presetting a count value, counts the clock φ, and outputs the count value as a read instruction address ADRa. The read instruction address ADRa is an instruction address that specifies an instruction to be read from the program memory 2. The address setting unit 62 is a circuit that forms part of the instruction execution means. When a jump instruction is output from the selector 5, the address setting unit 62 is synchronized with the next rising edge of the clock φ and the jump destination included in the jump instruction. This is a circuit for presetting an instruction address in the address counter 61.

  The read command generation unit 63 is a circuit that generates the above-described read command RE and generates a write permission signal EN that informs the write control unit 8 of a period during which the read command RE does not occur. The read command generator 63 generates a read command RE and a write enable signal EN as follows.

a. When the clock φ becomes H level, the read command address ADRa becomes an odd number, and the command output from the selector 5 at that time is not a jump command. In this case, the read command generator 63 determines that the next clock φ is When the read instruction address ADRa becomes an even number and rises, the read command RE is set to the active level (H level) for a predetermined period, and the write enable signal EN is set to the inactive level for a period corresponding to one cycle of the clock φ. (L level).

b. When the clock φ becomes H level, the read command address ADRa is an even number, and the command output from the selector 5 is not a jump command. In this case, the read command generator 63 causes the next clock φ to rise When the read instruction address ADRa becomes an odd number, the write enable signal EN is set to an active level (H level) for a period corresponding to one cycle of the clock φ.

c. When the clock φ becomes H level and the instruction output from the selector 5 is a jump instruction In this case, the read command generator 63 sets the read command address ADRa to an odd number when the clock φ rises next time. Regardless of whether or not it has become an even number, the read command RE is set to an active level (H level) for a predetermined period, and the write enable signal EN is set to an inactive level (L) for a period corresponding to one cycle of the clock φ. Level).

  The write data receiving unit 7 is a device that receives data to be written to the program memory 2 (that is, a group of instructions constituting the program) from an external CPU (not shown) that controls the DSP. The write data receiving unit 7 includes a FIFO (First-In First-Out) for temporarily storing received data. When the amount of received data remaining in the FIFO decreases, the write data receiving unit 7 sends a data request to the external CPU, receives data from the external CPU, and stores it in the FIFO.

  The write control unit 8 is a circuit that receives data to be written to the program memory 2 by the write data receiving unit 7 when receiving a program rewrite request from the external CPU and performs control for writing to the program memory 2. Here, the program rewrite request includes the instruction address ADRs of the first instruction in the instruction group to be written in the program memory 2 and the number Ncom of instructions constituting this instruction group. Upon receiving the program rewrite request, the write control unit 8 stores the instruction address ADRs and the number of instructions Ncom in a built-in register, and starts receiving data from the external CPU in the write data receiving unit 7 and storing it in the FIFO. Let Thereafter, the write control unit 8 performs control for writing the data received from the external CPU by the write data receiving unit 7 to the program memory 2 every time the write enable signal EN becomes the active level (H level).

  More specifically, the write control unit 8 sequentially generates Ncom write command addresses ADRb starting from ADRs one by one every time the write enable signal EN becomes an active level (H level), and a write data receiving unit. The read clock RDCK is sent to the FIFO 7 and the received data in the FIFO is read in order from the oldest, and supplied to the data input port of the program memory 2 as the write data WD. Here, the write command address ADRb is an 8-bit address, and the LSB thereof is supplied to the program memory 2 as the region designation signal U / L described above. The write control unit 8 generates the write command address ADRb and supplies the write command WE for a predetermined period in synchronization with the clock φ when supplying the write data WD to the data input port of the program memory 2. The active level (H level). The write control unit 8 sets the selection signal SEL1 to be supplied to the selector 9 to the H level only when the write command address ADRb is generated and the write data WD is supplied to the data input port of the program memory 2. During other periods, the selection signal SEL1 is set to L level.

  The selector 9 selects the read command address ADRa output from the address counter 61 when the selection signal SEL1 is at the L level, and the write command address output from the write control unit 8 when the selection signal SEL1 is at the H level. This is a circuit that selects ADRb and supplies the upper 7 bits of the selected 8-bit read instruction address ADRa or write instruction address ADRb to the program memory 2 as memory address data ADRc.

  The selector 9 and the above-described read control unit 6 constitute read control means for repeatedly controlling a plurality of data (commands in this embodiment) to be read from the memory (program memory 2 in this embodiment). ing. Further, the selector 9 and the write control unit 8 described above use a period in which data (instruction in this embodiment) is not read from the memory (in the case of this embodiment, the program memory 2), Write control means for controlling writing data into the memory is configured.

The selection control unit 10 is a circuit that monitors the read instruction address ADRa and performs switching control of the selector 5 based on the monitoring result. Except when the jump instruction is executed, the read instruction address ADRa output from the address counter 61 increases by “1” in synchronization with the clock φ. In this case, if the read instruction address ADRa after the increase is an even number, the selection control unit 10 sets the selection signal SEL2 to “0” and causes the selector 5 to select the instruction OP0 output from the data output port of the program memory 2. If the read instruction address ADRa after the increase is an odd number, the selection signal SEL2 is set to “1”, and the instruction OP1d output from the register 4 is selected by the selector 5. When the jump instruction is executed and the address setting unit 62 presets the jump destination instruction address in the address counter 61, the read instruction address ADRa output from the address counter 61 changes by an amount larger than “1”. In this case, if the read instruction address ADRa after the change is an even number, the selection control unit 10 sets the selection signal SEL2 to “0” and causes the selector 5 to select the instruction OP0 output from the data output port of the program memory 2. If the read instruction address ADRa after the change is an odd number, the selection signal SEL2 is set to “2”, and the instruction OP1 output from the data output port of the program memory 2 is selected.
The above is the detailed configuration of the DSP according to the present embodiment.

  2 to 5 are time charts showing an operation example of the present embodiment. In each operation example, a series of instructions starting from the instruction address “128” is rewritten in parallel with the instructions being sequentially read from the program memory 2 and executed. In each operation example, a jump instruction is executed.

  In the present embodiment, for example, as shown in FIG. 2, the read command address ADDR output from the address counter 61 by the read command generator 63 is an even number (in the example of FIG. 2, ADRa = “98”, “100”, When “12”, “14”, “16”), the read command RE is set to the active level (H level).

  Here, when the read command RE becomes an active level (H level), the write enable signal EN is set to an inactive level, so that the selection signal SEL1 is set to L level by the write control unit 8 and the selector 9 is set to the read command address ADRa. Are output as memory address data ADRc. For this reason, when the read instruction address ADRa is an even number, the memory address data ADRc (1/2 in the read instruction address ADRa) (ADRc = “49”, “50”, “6”, “ 7 "and" 8 ") are supplied from the selector 9 to the program memory 2, and two instructions in the area specified by the memory address data ADRc (in the example of FIG. 2, a set of instructions # 98 and # 99, Instruction # 100 and # 101, instruction # 12 and # 13, instruction # 14 and # 15, instruction # 16 and # 17) are sequentially read from the program memory 2 as instructions OP0 and OP1.

  Of the two instructions OP0 and OP1 read from the program memory 2, the instruction OP0 is selected by the selector 5 immediately after being read from the program memory 2 and is processed as the execution target instruction OPe (more specifically, It is supplied to the signal processing unit 3 and the address setting unit 62 (instruction execution means) (in the example of FIG. 2, OPe = # 98, # 100, # 12, # 14, # 16). On the other hand, the instruction OP1 is read as the instruction OP1d by the register 4 after being read from the program memory 2, and is selected by the selector 5 with a delay corresponding to one cycle of the clock φ from the instruction OP0, and is processed as the execution target instruction OPe. The signal is supplied to the signal processing unit 3 and the address setting unit 62 (more specifically, the instruction execution unit) (OPe = # 99, # 101, # 13, # 15, # 17 in the example of FIG. 2).

  Unless the jump instruction is executed and the instruction address ADRa of the jump destination instruction is odd, the read instruction address ADRa is odd (in the example of FIG. 2, ADRa = “99”, “ 101 ”,“ 13 ”,“ 15 ”,“ 17 ”), the instruction OP1d held in the register 4 (OP1d = # 99, # 101, # 13, # 15, # 17 in the example of FIG. 2) Is selected as the execution target instruction OPe by the selector 5 and supplied to the signal processing unit 3 and the address setting unit 62. During this time, the read command RE is set to the inactive level (L level) by the execution read command generator 63, and the command is not read. On the other hand, during a period in which this command is not read, the read command generation unit 63 sets the write enable signal EN to the active level (H level). When the command to be written to the program memory 2 is in the FIFO of the write data receiving unit 7, the write control unit 8 uses the period during which the write enable signal EN is at the active level, from the FIFO of the write data receiving unit 7. Control for reading out the instruction and writing it into the program memory 2 is performed.

  In the operation example shown in FIG. 2, a series of commands # 128, # 129, # 130, and # 131 are sent from the FIFO of the write data receiving unit 7 using a period in which the write enable signal EN is at the active level (H level). It is read and supplied to the program memory 2 as write data WD. Further, the write control unit 8 generates instruction addresses ADRb = “128”, “129”, “130”, “131” of those instructions, and at this time, the selection signal SEL1 is set to the H level. Memory address data ADRc = “64”, “64”, “65”, “65”, which is the upper 7 bits of the instruction address ADRb, is given from the selector 9 to the program memory 2. Further, the LSB of the instruction address ADRb is given to the program memory 2 as the area designation signal U / L. Then, during each period when the write data WD = # 128, # 129, # 130, and # 131 is given to the program memory 2, the write command WE is set to the active level (H level) for a certain time, and the memory address data ADRc = “64”, “64”, “65”, “65” and the area designation signal U / L = “1”, “0”, “1”, “0” in the program memory 2 designated respectively Write data WD = # 128, # 129, # 130, # 131 is written in each area.

  If there is no jump instruction in the instruction read from the program memory 2, the read instruction address ADRa is alternately repeated even and odd, and the read command RE is set to the active level when the instruction address ADRa is even. The regularity is maintained. If the instruction address ADRa of the jump instruction is an odd number and the instruction address ADRa of the jump destination instruction is an even number as in the operation example shown in FIG. 2, even if the jump instruction is executed, the jump instruction The same regularity is maintained as when no is executed. Therefore, data reading from the program memory 2 and data writing to the program memory 2 can be alternately performed in synchronization with the clock φ. However, depending on the combination of the instruction address of the jump instruction and the instruction address of the jump destination instruction, the above regularity is lost due to the execution of the jump instruction, and the timing of writing data to the program memory 2 is as shown in FIG. This is different from the operation example 2.

  In the operation example illustrated in FIG. 3, a jump is performed from an instruction having an even address “102” to an instruction address ADRa having an even address “12”. In this case, since reading of the jump instruction with the instruction address ADRa = “102” from the program memory 2 and reading of the instruction with the instruction address ADRa = “12” as the jump destination are continuously performed, The write enable signal EN is set to an inactive level (L level) over two periods of φ, and data writing is not performed.

  In the operation example illustrated in FIG. 4, a jump is performed from an instruction having an odd instruction address “ADRa” to an instruction having an odd instruction address “DRa”. In this case, the instruction OP1d = # 101 held in the register 4 is selected as the execution target instruction OPe by the selector 5 and executed as the jump instruction of the odd instruction address “101”. Accordingly, during the period in which the instruction OP1d = # 101 is executed, the write enable signal EN is set to the active level (H level), and the write data WD (= # 128) is written to the program memory 2. However, the subsequent instruction # 14 at the odd instruction address “13” is a jump destination instruction and is not yet held in the register 4, and therefore needs to be read from the program memory 2. Further, since the next instruction is the instruction # 14 of the even instruction address “14”, it is also necessary to read from the program memory 2. For this reason, the reading of the instruction # 13 from the program memory 2 and the reading of the instruction # 14 from the program memory 2 are continuously performed, and the write enable signal EN is inactive for two cycles of the clock φ. (L level) and no data is written.

  In the operation example shown in FIG. 5, a jump is performed from an instruction whose instruction address ADRa is an even number “102” to an instruction whose instruction address ADRa is an odd number “13”. In this case, the jump instruction at the even instruction address “102” is read from the program memory 2, the instruction at the odd instruction address “13” as the jump destination is read from the program memory 2, and the next even instruction address “14”. ”Is continuously read from the program memory 2, the write enable signal EN is set to the inactive level (L level) over three cycles of the clock φ, and data writing is not performed.

  As described above, when a jump instruction is executed, there may occur a period during which data cannot be written to the program memory 2 over two or three cycles of the clock φ. However, since it is generally not possible for jump instructions to be executed many times in succession, the program in the program memory 2 can be rewritten without any trouble in parallel with the reading and execution of instructions in the program memory 2. Can do.

  The operation of the selector 5 during execution of the jump destination instruction differs depending on whether the instruction address of the jump destination instruction is an even number or an odd number. In the operation example shown in FIGS. 2 and 3, since the instruction address of the jump destination instruction is an even number “12”, the selection signal SEL2 is set to “0” when reading two instructions including this instruction, and the program The instruction OP0 (= # 12) read from the memory 2 is selected as the execution target instruction OPe. In the operation example shown in FIGS. 4 and 5, since the instruction address of the jump destination instruction is an odd number “13”, the selection signal SEL2 is set to “2” when reading two instructions including this instruction. The instruction OP1 (= # 13) read from the program memory 2 is selected as the execution target instruction OPe.

  As described above, according to the present embodiment, two instructions are stored in each area of the program memory 2, two instructions are read from the program memory 2 at a time, and the two read instructions are sequentially executed. As a result, even if the program memory 2 is composed of a single port RAM, the instruction in the program memory 2 can be rewritten using a period in which the instruction is not read from the program memory 2. It can be carried out.

Second Embodiment
FIG. 6 is a block diagram showing a configuration of a DSP according to the second embodiment of the present invention. In this figure, parts corresponding to those in the first embodiment (FIG. 1) are denoted by the same reference numerals, and description thereof is omitted.

  In the first embodiment, as the program memory 2, a single port RAM having a configuration in which 2N-bit data in the area of the same memory address can be divided into upper N bits and lower N bits and rewritten in units of N bits is used. .

  On the other hand, in the present embodiment, the program memory 2A is configured such that data can be rewritten only in area units (2N bit units) designated by the memory address data ADRc. With the adoption of the program memory 2A having such a configuration, a write control unit 8A having a partially different control content from the write control unit 8 in the first embodiment is provided, and an OR gate 21 is further added. Has been.

  The difference between the present embodiment and the first embodiment lies in the control contents at the time of data writing to the program memory 2A. In the present embodiment, as shown in FIG. 7, when rewriting a series of instructions from an instruction having an odd instruction address to an instruction having an even instruction address, the write control unit 8A performs program memory 2A as follows. Rewrite the instruction inside.

  First, the write control unit 8A rewrites instructions in the program memory 2A by the rewrite method (1) described below for each area in which both the upper N bits and the lower N bits in the area are to be rewritten. That is, the rewrite control unit 8A uses the period in which the write enable signal EN is at the active level, and supplies 2N-bit write data WD including the instruction of the even instruction address and the instruction of the odd instruction address following to the program memory 2A. Then, the instruction address ADRb, which is an even instruction address, is supplied to the selector 9, the selection signal SEL1 is set to the H level, and the write command WE is set to the active level over a predetermined time. As a result, 2N-bit data consisting of two instructions is stored in an area corresponding to the memory address data ADRc = ADRb / 2 in the program memory 2A.

  Then, for the area where only the lower N bits in the area are to be rewritten and the area in which only the upper N bits in the area are to be rewritten, the rewrite control unit 8A performs the program memory 2A by the rewriting method (2) described below. Rewrite the instruction inside.

  FIG. 8 is a diagram showing the procedure of the rewriting method (2). In this rewriting method (2), one instruction in the program memory 2A is rewritten using two periods in which the write enable signal EN is at the active level. For example, when rewriting instruction # 100 whose instruction address is “100” or instruction # 101 whose instruction address is “101”, the write control unit 8A outputs the instruction address ADRb = “100”. 9, and the memory address data ADRc = “50” is supplied from the selector 9 to the program memory 2 </ b> A. Then, the write control unit 8A sets the read command RE2 to the active level. The read command RE2 is supplied to the program memory 2A via the OR gate 21. This OR gate 21 supplies the program memory 2A with the read command RE2 generated by the write control unit 8A in this way in addition to the read command RE generated by the read control unit 6 as in the first embodiment. It is the gate provided in.

  When the 2N-bit data consisting of the instructions # 100 and 101 is read from the area of the memory address “50” in the program memory 2A by the supply of the read command RE2 at the active level, the write control unit 8A reads the 2N-bit data. Load into the built-in register. When the rewrite target is the instruction # 100, the upper N bits of 2N bits in this register are rewritten to a new instruction # 100. When the rewrite target is the instruction # 101, 2N in this register The lower N bits of the bit are rewritten to a new instruction # 101.

  Then, the write control unit 8A uses the period in which the write enable signal EN is at the next active level, and uses the 2N-bit data in the rewritten register in the area corresponding to the memory address “50” in the program memory 2A. Control is performed to write the data. That is, the write control unit 8A gives the 2N-bit data in the register that has been rewritten to the program memory 2A as the write data WD, outputs the instruction address ADRb = “100”, causes the selector 9 to select, and writes The command WE is set to the active level over a certain period. In this way, one of the instructions # 100 or # 101 in the program memory 2A is rewritten with new contents.

  In the case of this embodiment, when only an instruction with an odd instruction address or only an instruction with an even instruction address is rewritten, two periods are required for the write enable signal EN to become an active level in order to rewrite the instruction. Therefore, the efficiency is not good as compared with the first embodiment. However, when 2N-bit data in each area is rewritten for many areas, the 2N-bit data in one area may be rewritten during the period when the write enable signal EN is at the active level. Therefore, rewriting can be performed efficiently.

<Other embodiments>
Although the first and second embodiments of the present invention have been described above, other embodiments are conceivable for the present invention. For example:

(1) In the first and second embodiments, two instructions are stored in each area of the program memory 2 or 2A, but three or more instructions are stored in each area, and those instructions are stored in area units. May be read out. In this case as well, in the same manner as in the above-described embodiments, the program is read after a plurality of instructions are read from the program memory 2 or 2A until the next data is read from the program memory 2 or 2A Instructions for program memory 2 or 2A are controlled using a period in which a plurality of instructions read from memory 2 or 2A are sequentially executed and a plurality of instructions are not read from program memory 2 or 2A Should be written.

(2) In the first and second embodiments, the present invention is applied to the program memory 2 or 2A and a circuit for performing read control and write control thereof. However, the present invention can also be applied to a RAM other than the program memory in the DSP and a circuit that performs read control and write control thereof. For example, in the first and second embodiments, the signal processing unit 3 performs a calculation using a coefficient memory that stores a coefficient for signal processing such as filter processing and the coefficient read from the coefficient memory. Arithmetic means for performing signal processing. Here, in order to realize a small-scale configuration of the DSP and various filter processes, the coefficients in the coefficient memory are read in parallel with the reading of the coefficients from the coefficient memory for signal processing. A function for performing rewriting is required of the DSP. Therefore, as in the first and second embodiments, a plurality of coefficients are stored in each area of the coefficient memory, and a plurality of coefficients are read from the coefficient memory in area units. A plurality of coefficients read out from the coefficient memory are used for signal processing after the reading of the plurality of coefficients from the coefficient memory until the next reading of the plurality of coefficients from the coefficient memory. Control is performed so that the coefficients are sequentially used in the calculation, and the coefficient is written into the coefficient memory using a period during which the plurality of coefficients are not read from the coefficient memory. In this way, even when a single-port RAM is used as the coefficient memory, it is possible to write the coefficient into the coefficient memory in parallel with the reading of the coefficient from the coefficient memory, and the DSP can be reduced in scale. It becomes possible to realize various filter processes and the like.

It is a block diagram which shows the structure of DSP which is 1st Embodiment of this invention. It is a time chart which shows the 1st operation example of the embodiment. It is a time chart which shows the 2nd operation example of the embodiment. It is a time chart which shows the 3rd operation example of the embodiment. It is a time chart which shows the 4th operation example of the embodiment. It is a block diagram which shows the structure of DSP which is 2nd Embodiment of this invention. It is a figure which illustrates the mode of rewriting of the instruction in program memory 2 in the embodiment. It is a figure explaining the procedure of the rewriting method (2) of the instruction in the program memory 2 performed in the same embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Clock generation part, 2, 2A ... Program memory, 3 ... Signal processing part, 4 ... Register, 5, 9 ... Selector, 6 ... Reading control part, 61 ... Address counter, 62 ... Address setting unit, 63... Read command generation unit, 7... Write data reception unit, 8, 8A... Write control unit, 10.

Claims (4)

A memory for storing two each of a series of signal processing instructions applied to an input signal ;
And read control means for repeatedly controlling reading said memory or Rainochi Ordinance two by two the clock every second
Processing means for executing an instruction read from said memory,
Supplied to the processing means at least one of the two instructions read from said memory until instruction of reading the instruction read from then the memory from being performed is carried out from said memory A data supply control means for storing a command to be executed later among the two instructions read from the memory, the two instructions read from the memory, and the register and data supply control means comprises a data selection unit that executes processing by selecting the stored or found one instruction in the instruction is supplied to the processing means in synchronization with a clock, and
When the instruction selected by the data selection means is a jump instruction, the read control means performs control to read the memory at the next clock,
When the instruction selected by the data selection means is a jump instruction and the jump destination is the instruction executed after one of the two instructions stored in the memory as a pair, the memory Of the two instructions read out from the memory, the instruction to be executed later is selected by the data selection means. In other cases, the instruction is executed first out of the two instructions read out from the memory. Selection control means for causing the data selection means to select an instruction to be stored, and further causing the data selection means to select an instruction stored in the register at a next clock;
Write control means for performing control to write an instruction to the memory using a period during which no instruction is read from the memory ,
A digital signal processing device.   When rewriting one of the two instructions stored in the memory as a pair, the write control means reads the two instructions from the memory and rewrites one of the two instructions. The digital signal processing apparatus according to claim 1, wherein the two rewritten instructions are written back to the memory as a pair.   A coefficient memory for storing two coefficients corresponding to each of the instructions stored in the memory, which are coefficients used in signal processing applied to the input signal;
  The read control means reads the coefficient corresponding to each of the two instructions from the coefficient memory when reading the instructions two by two from the memory,
  The processing means performs signal processing using a coefficient read from the coefficient memory,
  The data supply control means further includes a coefficient register for storing a coefficient corresponding to an instruction to be executed later, out of the two coefficients read from the coefficient memory,
  When the data selection means supplies an instruction to the processing means, one coefficient corresponding to the instruction is selected from the two coefficients read from the coefficient memory and the coefficient stored in the coefficient register. To supply to the processing means,
  The write control unit performs control to write a coefficient into the coefficient memory using a period during which the coefficient is not read from the coefficient memory.
  The digital signal processing device according to claim 1, wherein the digital signal processing device is a digital signal processing device.   When rewriting one of the two coefficients stored in the coefficient memory as a pair, the write control means reads the two coefficients from the coefficient memory and rewrites one of the two coefficients. 4. The digital signal processing apparatus according to claim 1, wherein one of the two rewritten coefficients is written back to the coefficient memory as a pair.

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