JP4997167B2 - Image signal processing apparatus, method and program for image division processing - Google Patents

Description

  The present invention relates to image signal processing for image division processing, and in particular, an image for converting a high-resolution color image having a predetermined sampling structure used in a video image into a plurality of low-resolution color images having the sampling structure. The present invention relates to an image signal processing apparatus, method, and program for division processing.

  Conventionally, when performing signal processing and signal transmission of a high-resolution color television image known as, for example, Super Hi-Vision (ultra-high definition image), the amount of data to be processed almost in real time is high. For example, it is known that a resolution frame image is divided into, for example, four, and four divided image areas are processed in parallel. Thus, if it is the data amount of the frame image divided into four, it can process using the signal processing and transmission line for low resolution currently used generally. That is, in such a case, a high-resolution color video image is temporarily input and converted into a plurality of low-resolution sub-color video images (hereinafter referred to as a low-resolution processing), and the plurality of sub-color video images are parallelized. After processing (eg, gain correction or black level adjustment), the original high resolution color video image can be displayed or reconstructed.

  FIG. 6 shows a specific example of a signal processing apparatus 101 used for resolution reduction processing that has been conventionally known. The signal processing apparatus 101 illustrated in FIG. 6 inputs a high-resolution image frame Sin, and the input image frame Sin is, for example, a plurality of low-resolution sub-images corresponding to four screen regions (first region to fourth region). Divide into Further, the signal processing apparatus 101 distributes and stores the image data of each divided area in the first to fourth frame memories 102, 103, 104, and 105, and reads the time data from each frame memory stored for each sub-image. And sub-images subSout1 to subSout4 are output in synchronization with each other in parallel. As a result, it is possible to disperse the processing load of signal processing and signal transmission of high-resolution color television images.

  On the other hand, as shown in FIG. 7, as another example of reducing the resolution of an input high-resolution image frame Sin, each pixel S of the image frame Sin is divided into one horizontal (row) pixel × vertical (column ) Method of generating sub-images S′out1 to S′out4 by sequentially assigning to a plurality of low-resolution images in a pixel block U (referred to as a 1 × 2 pixel block in the example of FIG. 7) consisting of two pixels. (For example, refer nonpatent literature 1).

  Regarding solid-state image sensors, there is also known a method of dividing a high-resolution image into columns or rows and converting it into a low-resolution sub-image based on the configuration of the output signal terminal of the solid-state image sensor. A method of processing an image signal according to this output format is also often used.

National Film and Television Engineers Association Standard, Society of Motion Picture and Television Engineers (SMPTE) 435-1

  However, in the conventional method shown in FIG. 6 described above, since it is usually necessary to align the processing timing of the spatial region, a plurality of low resolution sub-images can be processed at the same timing from each frame memory. Time adjustment must be performed at the time of reading, and a time delay due to this time adjustment occurs. For example, the delay in signal time when an interface or the like is configured using such a division method is extremely large when devices are connected in multiple stages or when the image is divided into a large number of image areas as the screen becomes higher in definition. It becomes a problem.

  Further, in the conventional method shown in FIG. 7, the resolution is lowered in the case of a video format of an image sampling structure having a 4: 2: 0 type as a sampling pattern, or in the case of a video format known as, for example, a single-panel color camera. The sampling pattern of the previous high-resolution image does not match the sampling pattern of the divided sub-images after the resolution reduction, and the sampling pattern also differs for each sub-image. Gain correction and black level adjustment for each sub-image In order to perform signal processing such as the above, it is necessary to exchange information between the sub-images, or a division method or a signal processing method according to the sampling pattern. This means that the resolution reduction processing is performed with a different division method for each high-resolution image of various sampling patterns, and the processing setting is changed according to the type of video format at the time of the resolution reduction processing. Is required.

  In addition, as a method of dividing in units of columns or rows from the configuration of the output signal terminal of the solid-state imaging device, etc., when dividing an input high resolution image into a plurality of low resolution images, signal processing that divides each column (column) There is a signal processing method for dividing each line (row). However, when the sampling pattern of one frame of red, green and blue signals, which is often used for color video images of a solid-state image sensor, is different (the image sensor output signal of a single-plate video color camera using a Bayer type color filter) Or when the sampling pattern is different between the luminance and the color difference signal (the sampling structure of the luminance and the color difference signal is 4: 2: 2 type, 4: 2: 0 type, 4: 1: 1 type, 4: 1: 0 type) For each sub-image generated, the sampling pattern between each color signal is different, and in the subsequent signal processing, different signal processing (adapted to different pixel positions) for each sub-image. Processing) is required.

  The object of the present invention is to solve the above-mentioned problems and to convert an image signal processing apparatus and method for converting a high-resolution image of an arbitrary video format into a plurality of low-resolution sub-images having the same sampling structure as that of the high-resolution image. And providing a program.

The image signal processing apparatus according to the present invention has a row pixel number m * (a * 2 ^k ) × a column pixel number n * (b as an integer a, b, m, n of 1 or more and an integer k, l of 0 or more. * 2 An image signal processing apparatus for performing a resolution reduction process for dividing and processing in parallel a high-resolution image of ultra-high definition consisting of ¹ ), wherein the high-resolution image has a pixel configuration adjacent to each other. A first dividing means for dividing the block area consisting of the number of row pixels (a * 2 ^k ) × the number of column pixels (b * 2 ^l ) into m × n, and each of the m × n block areas A pixel block having a row pixel number 2 ^k × column pixel number 2 ^{l in} a pixel configuration adjacent to each other, a second dividing means for dividing the pixel block into a × b pieces, and each of the m × n block regions. sequentially extracts, a × b rows the same position in the row pixel count 2 ^k × column pixel number 2 ^l of pixel blocks for Characterized in that it comprises a means for delivering a low-resolution signal for generating a low resolution image composed of prime numbers m * 2 ^k × row pixel number n * 2 ^l.

  In the image signal processing apparatus according to the present invention, the sampling structure of the high-resolution image may be a 4: 4: 4 type, 4: 2: 2 type, 4: 2: 0 type of RGB method or luminance and color difference signal method, It is suitable for any sampling structure in the 4: 1: 1 type, the 4: 1: 0 type, the Bayer type in the single plate color system, and the four-color filter type.

  In the image signal processing apparatus according to the present invention, k and l are set to k = 0 and l = 0, respectively, in order to perform resolution reduction processing in units of one pixel.

  Further, in the image signal processing apparatus according to the present invention, k = 1 and l = 0 are set in order to reduce the resolution in pixel block units each having 2 row pixels × 1 column pixel. It is characterized by being set.

  In the image signal processing apparatus according to the present invention, k = 1 and l = 1 are set for k and l, respectively, in order to perform a resolution reduction process in units of pixel blocks each having 2 row pixels × 2 column pixels. It is characterized by being set.

  Further, in the image signal processing apparatus according to the present invention, k and l are set to k = 0 and l = 1, respectively, in order to perform resolution reduction processing in units of pixel blocks each having 1 row pixel number × 2 column pixel number. It is characterized by being set.

  Further, in the image signal processing apparatus according to the present invention, k and l are set to k = 0 and l = 2, respectively, in order to perform a resolution reduction process in units of pixel blocks having 1 row pixels × 4 column pixels. It is characterized by being set.

  Further, in the image signal processing apparatus according to the present invention, k = 1 and l = 2 are set so that k and l are reduced in pixel block units each having 2 row pixels × 4 column pixels. It is characterized by being set.

In the image signal processing apparatus according to the present invention, the high resolution image has a predetermined effective range, and the means for dividing the high resolution image is always 2 ^k × 2 with respect to the pixel signal in the effective range. ^In order to ensure the division of the ^l pixel in the basic pixel block, there is provided means for inserting an arbitrary value into the pixel value of the region other than the effective pixel.

  In the image signal processing apparatus according to the present invention, for the combination of (k, l) for dividing the high resolution image, the video format ID added to the high resolution image is extracted to generate the low resolution image. And a control parameter setting means for adding the ID to each of the signals with reduced resolution.

Furthermore, the image signal processing method according to the present invention uses the number of row pixels m * (a * 2 ^k ) × number of column pixels n * as integers a, b, m, n of 1 or more and integers k, l of 0 or more. An image signal processing method for dividing a high resolution image of (b * 2 ^l ) and performing a resolution reduction process for parallel processing, wherein the high resolution image is connected to adjacent pixels. A block area composed of the number of row pixels (a * 2 ^k ) × the number of column pixels (b * 2 ^l ), and dividing each of the m × n block areas adjacent to each other. In the pixel block having the row pixel number 2 ^k × column pixel number 2 ^l in a continuous pixel configuration, the step of dividing the pixel block into a × b and the m × n block regions are at the same position sequentially removed pixel block line pixel number 2 ^k × column pixel number 2 ^l, a × b number number of rows of pixels * Characterized in that it comprises a step of delivering a low-resolution signal for generating a low resolution image composed of 2 ^k × row pixel number n * 2 ^l.

Further, the present invention provides the number of row pixels m * (a * 2 ^k ) × the number of column pixels n * (b * 2 ^l as integers a, b, m, n of 1 or more and integers k, l of 0 or more. ), A computer having a pixel configuration that is adjacent to the computer and configured as an image signal processing apparatus that performs a resolution reduction process for parallel processing. A block area composed of the number of pixels (a * 2 ^k ) × the number of column pixels (b * 2 ^l ), divided into m × n blocks, and each of the m × n block areas is connected adjacently. A pixel block having a pixel configuration of 2 ^k × column pixel number 2 ^l and a step of dividing the pixel block into a × b and a row pixel at the same position with respect to each of the m × n block regions the number sequentially removed 2 ^k × column pixel number 2 ^l of the pixel block, a × b number number of rows of pixels m Also characterized as an image signal processing program for executing a step of delivering a low-resolution signal for generating a low resolution image composed of 2 ^k × row pixel number n * 2 ^l.

  According to the present invention, a high-resolution image in an arbitrary video format is converted into a plurality of low-resolution sub-images having the same sampling structure as that of the high-resolution image. Regardless of the sampling structure, it becomes possible to operate in the same signal processing process, so that a parallel signal processing device of any video format used for low-resolution images or an interface device for transmission can be used. become.

The image signal processing apparatus according to the present invention has the number of row pixels m * (a * 2 ^k ) × the number of column pixels n * (1 as integers a, b, m, n of 1 or more and integers k, l of 0 or more. b * 2 ^l ) is a device for dividing a high-resolution image of ultra-high definition and performing a resolution reduction process for parallel processing.

The image signal processing apparatus divides a high-resolution image into m × n blocks in a block area composed of the number of row pixels (a * 2 ^k ) × the number of column pixels (b * 2 ^l ) of adjacent pixel configurations. (Referred to as the first dividing means), each of the m × n block areas is a pixel block having a row pixel number 2 ^k × column pixel number 2 ^{l in} a pixel configuration adjacent to each other. (Referred to as a second dividing means), and sequentially take out pixel blocks having the number of row pixels 2 ^k × number of column pixels 2 ^l located at the same position in each of the m × n block regions, and a A signal capable of generating a low-resolution image consisting of × b number of row pixels m * 2 ^k × number of column pixels n * 2 ^l is sent.

  According to the image signal processing apparatus, the sampling structure of the high-resolution image has the RGB method or the 4: 4: 4 type, 4: 2: 2 type, 4: 2: 0 type, or 4: 1 of the luminance and color difference signal method. The resolution reduction processing can be performed by adapting to any sampling structure in the 1 type, 4: 1: 0 type, the Bayer type in the single plate color system, and the 4 color filter type.

  For example, in order to perform a resolution reduction process in units of one pixel, k and l are set to k = 0 and l = 0, respectively, by a control parameter setting unit 17 described later.

  For example, in order to reduce the resolution of each pixel block consisting of 2 row pixels × 1 column pixel, k and l are set to k = 1 and l = 0, respectively, by a control parameter setting unit 17 described later. .

  For example, in order to reduce the resolution of each pixel block consisting of 1 row pixel number × 2 column pixel number, k and l are set to k = 0 and l = 1, respectively, by the control parameter setting means 17 described later. .

  For example, in order to reduce the resolution of each pixel block consisting of 2 row pixels × 2 column pixels, k and l are set to k = 1 and l = 1, respectively, by the control parameter setting unit 17 described later. . As a processing device of pixel block unit composed of 2 × 2 pixel pixels, JPEG, MPEG-1, MPEG-2 and consumer DVC 4: 2: 0 type signal processing devices are known. .

  For example, in order to achieve a resolution reduction process in units of pixel blocks having 1 row pixel number × 4 column pixel number, k and l are set to k = 0 and l = 2, respectively, by a control parameter setting unit 17 described later. . A 4: 1: 1 type signal processing device in a consumer video format (DV format) is known as a processing device in pixel block units having 1 row pixels × 4 column pixels.

  For example, in order to achieve a resolution reduction process in units of pixel blocks having 2 row pixels × 4 column pixels, k and l are set to k = 1 and l = 2, respectively, by a control parameter setting unit 17 described later. . A 4: 1: 0 type signal processing device in a consumer video format (DV format) is known as a processing device in pixel block units composed of 2 row pixels × 4 column pixels.

  The control parameter setting means 17 extracts the video format ID added to the ultra-high definition video for the combination of (k, l) for dividing the input ultra-high definition video, and divides the low resolution image. Is further provided with a function of adding the ID to each of the low-resolution signals for generating the video, and the video format of the divided low-resolution image is divided while dividing the above-described arbitrary format in the same processing mode. Can be communicated to subsequent processing.

  The image signal processing apparatus according to the first embodiment of the present invention will be described below. The first embodiment is compatible with any sampling structure in the 4: 4: 4 type, 4: 2: 2 type, 4: 2: 0 type, and the Bayer type and the four-color filter type in the single plate color system. An example in which two pixels are used as a pixel block unit will be described.

Example 1
FIG. 1 is a schematic operation diagram of an image signal processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram of an image signal processing apparatus according to an embodiment of the present invention. The image signal processing apparatus 1 according to the present embodiment generates 2 × 2 pixels (2 row pixels × columns) in order to generate a plurality of low resolution images having the same sampling structure as that of the input high resolution image. This is a device that divides the high-resolution image into two units) as a basic unit. In FIG. 1, the image signal processing apparatus 1 includes a basic pixel composed of 2 × 2 pixels in each pixel S (illustrated, S ₁ , S ₂ , S ₃ , S ₄ ,..., S _b , S _c ). In each block U, each basic pixel block U can be assigned to a plurality of sub-images in a predetermined order to generate low-resolution images Sout1 to Sout4.

  FIG. 1 illustrates an example in which an input video image of 2m × 2n pixels is supplied to the image signal processing apparatus 1 and is divided into four m × n pixel sub-video images having the same frame frequency. Note that the number of pixels in the horizontal direction (number of row pixels in one image frame) Nx is m <Nx <2m, and the number of pixels in the vertical direction (number of column pixels in one image frame) Ny is n. When an input video image of a predetermined effective pixel (Nx, Ny) satisfying <Ny <2n is supplied, the image signal processing apparatus 1 always has an effective pixel (in order to ensure a basic pixel block of 2 × 2 pixels). An arbitrary value is inserted into the pixel value in the region other than (Nx, Ny). The specific block size is expressed as “number of row pixels × number of column pixels”, and the image range including the specific number of pixels is expressed as (number of row pixels, number of column pixels).

  Therefore, the image signal processing apparatus 1 sets the effective pixels as the input video image having the number of pixels in one frame as 2m × 2n, and assigns 2 × 2 pixels as a unit pixel to a plurality of sub-images in a predetermined order. Thus, for example, at least four rows of pixels are stored in a temporary memory for pixel signals of a high-resolution image sequentially input in the horizontal direction, and then read in parallel from each temporary memory and processed simultaneously. Can do. Here, each low-resolution image read out in parallel holds the sampling structure of the input high-resolution image, and the subsequent processing at each low-resolution can be made the same. For example, the processing after the reduction in resolution is not shown, but there are various uses. For example, using the image signal processing device 1 of the present embodiment, a plurality of ultra-high definition moving images having a resolution exceeding the high-definition are used. If the image is divided into high-definition video, the same number of high-definition video processing devices are used, gain correction, black level adjustment, and color balance adjustment are performed in parallel. By reconstructing one ultra-high definition moving image in units of 2 × 2 pixels in the reverse process (reconstruction process), real-time processing of video having a resolution exceeding that of high-definition can be realized.

  The image signal processing apparatus 1 will be specifically described with reference to FIG. The image signal processing apparatus 1 includes a high-resolution image signal input unit 11, a pixel block allocation unit 12, and N (N is an integer equal to or greater than 2) low-resolution image temporary memories 13-1, 13-2,. . . , 13 -N, pixel block readout control means 14, low resolution image construction means 15, and low resolution image signal output unit 16.

  The high-resolution image signal input unit 11 outputs a pixel signal of a high-resolution image in an arbitrary video format (which may be any of video formats having five types of sampling structures described later) as an image frame to be processed in parallel for each row in the horizontal direction. After sequentially inputting the pixels and inputting all the horizontal row pixels, the next row pixels shifted in the vertical direction are sequentially input to repeat the pixel signals of the high-resolution image in a predetermined order. To enter. Here, the pixel signal can be, for example, a 4: 4: 4 type of sampling pattern in which a set of RGB is one set. However, the present invention is not limited to this.

  The pixel block allocating unit 12 can function as the above-described first dividing unit. For example, the input pixel signal is converted into a 2 × 2 pixel block unit that holds a sampling structure of a high resolution image in a predetermined order. , N low-resolution image temporary memories 13-1, 13-2,. . . , 13-N. Here, in this embodiment, as a resolution reduction repair, description will be made on the assumption that each temporary memory is sequentially assigned and sequentially read by the pixel block read control unit 14 described later, but only the read control of the pixel block read control unit 14 is performed. It is also possible to realize a low resolution repair. The pixel block allocating means 12 is also provided at the end of the effective pixel (Nx, Ny) when the input video image of the predetermined effective pixel (Nx, Ny) is supplied as the pixel signal of the input high resolution image. In order to always secure a basic pixel block of 2 × 2 pixels, an arbitrary value is inserted and assigned to pixel values in regions other than the effective pixels (Nx, Ny).

  The pixel block readout control unit 14 can function as the above-described second dividing unit. For example, a pixel signal of a high resolution image input in a predetermined order in the horizontal direction is paralleled as a low resolution image. At the time when processing is possible, that is, when the number of pixels for at least 2 × b lines (the number of pixels for four rows in this embodiment) is stored in the temporary memory, N low resolution images are used. Temporary memories 13-1, 13-2,. . . , 13 -N, the signals of the 2 × 2 pixel blocks in the order stored in the respective temporary memories are read out in parallel and sent to the low-resolution image construction means 15 in synchronization. As will be described later, when a high-resolution image is composed of a frame having the number of pixels (a × 2m) × (b × 2n), N is (a × b) (a and b are 1). And an integer of 1 or more).

  The low-resolution image constructing unit 15 optionally selects 2m × 2n pixel low-resolution images, each of which is a pixel block of each low-resolution image that is input by the control of the pixel block readout control unit 14. And output to the outside through the low-resolution image signal output unit 16. Here, the pixel signal of the low resolution image of 2m × 2n pixels holds the sampling structure of the high resolution image. Further, the low resolution image construction means 15 may output the signal of the pixel block of each temporary memory via the low resolution image signal output unit 16 without reconstructing the low resolution image.

  The plurality of low resolution images output from the low resolution image signal output unit 16 can be used for any image processing that requires the parallel processing.

  The control parameter setting unit 17 determines the effective pixels (Nx, Ny) and the division number N of the input high resolution image, the pixel block allocation unit 12, the pixel block readout control unit 14, and an optional low resolution image configuration. It has a function to set for the means 15. It should be noted that the control parameter setting unit 17 does not need to input or set information on the sampling structure.

  Next, the effective number of pixels in one frame is set as an input video image of the number of row pixels (a × 2m) × the number of column pixels (b × 2n) by the image signal processing apparatus 1, and 2 × 2 pixel block units In the following description, it will be described that parallel processing can be performed when a plurality of sub-images are assigned.

  For example, in the image signal processing apparatus 1, the high-resolution image has a pixel size composed of the number of row pixels (a × 2m) × the number of column pixels (b × 2n) as arbitrary integers a, b, m, and n. In this case, it is possible to generate a low-resolution image having 2m × 2n row pixels × 2n column pixels by dividing the basic pixel block unit of 2 × 2 pixels.

  At present, as a video format of a high-resolution image to be processed or transmitted, the 4: 4: 4 type, 4: 2: 2 type, and 4: 2: 0 type are used in the RGB or YCrCb method (luminance and color difference signal method). In the single-plate color system, a Bayer type and a four-color filter type are known. In the low resolution processing of the image signal processing apparatus 1 of the present embodiment, the sampling structure of the input high resolution image is 4: 4: 4 type, 4: 2: 2 type of RGB system or luminance and color difference signal system, Any of the sampling structures of the 4: 2: 0 type, the Bayer type in the single-plate color system, and the four-color filter type are compatible, and it is not necessary to set information on the sampling structure in the image signal processing apparatus 1. As will be apparent from the following description, the pixel signal of the input high-resolution image is a single-plate color provided with on-chip color filters having different color filter characteristics of four colors within adjacent 2 × 2 pixels. It can consist of the output signal of an image sensor.

  As shown in FIG. 1, the pixel S can be considered as a sampling pattern of one pixel. Therefore, in the video format corresponding to the 4: 4: 4 sampling pattern of the G, B, and R video signals, α, β, and γ shown in FIG. Equivalent to. In this case, FIG. 3A shows that three pixel data 100a, 101a, and 102a of α (R), β (G), and γ (B) exist at one pixel position.

  When the sampling pattern of the G, B, and R video signals is 4: 2: 2 or 4: 2: 0, as shown in FIGS. 3B and 3C, respectively, α, β , Γ corresponds to a pattern corresponding to R, G, B. In this case, the B and R data exist every other pixel in the horizontal direction or every other pixel in the horizontal and vertical directions. Whether the B and R sampling positions are the same as the G signal sampling positions or between adjacent G signals does not matter. This is because the image signal processing apparatus 1 according to the present embodiment performs the resolution reduction processing by 2 × 2 pixel block allocation, and therefore can hold the sampling structure of the input high resolution image.

  The pixel positions shown in FIG. 1 can be similarly applied to the luminance signal Y and the two color difference signals Cb and Cr by associating α, β, and γ with Cr, Y, and Cb. If there is a 4: 4: 4 type sampling pattern of the Cb, Cr video signal and the sampling pattern of the Y, Cb, Cr video signal is 4: 2: 2 type, 4: 2: 0 type, As shown in FIGS. 3B and 3C, Cb and Cr data exist every other pixel in the horizontal direction or every other pixel in the horizontal and vertical direction. Similarly, in this case, since the image signal processing apparatus 1 of the present embodiment performs the resolution reduction processing by 2 × 2 pixel block allocation, it can be understood that the sampling structure of the input high resolution image can be held.

  Furthermore, the image signal processing apparatus 1 of the present embodiment can be applied to the sampling pattern of the Bayer type shown in FIGS. 3D and 3E or a single plate color camera using a four-color filter. it can. As apparent from the sampling structure shown in FIGS. 3D and 3E, the image signal processing apparatus 1 according to the present embodiment performs the resolution reduction processing by allocation in units of 2 × 2 pixel blocks. It can be seen that the sampling structure of the high-resolution image to be stored can be maintained.

  FIG. 4 shows a relationship between a high resolution image input in the image signal processing apparatus 1 and a plurality of generated low resolution images. The numerical value in one pixel shown in FIG. 4 indicates the horizontal or vertical address (or row or column address) of the pixel, and is assigned to and output from any low resolution output video image with respect to the high resolution input video image. This address value indicates whether or not In the example illustrated in FIG. 4, the image signal processing device 1 divides an input high-resolution image Sin into four video signals Sout1, Sout2, Sout3, and Sout4 assigned in units of 2 × 2 pixels.

  The pixel block allocating unit 12 in the image signal processing apparatus 1 performs the low resolution processing in units of 2 × 2 pixels according to a sequence defined as follows.

  2 × 2 pixels (2p−1, 2q−1), (2p−1, 2q), (2p, 2q−1), and (2p, 2q) are allocated to the sub-image 1.

  2 × 2 pixels (2p−1, 4q−1), (2p−1, 4q), (2p, 4q−1), and (2p, 4q) are allocated to the sub-image 2.

  2 × 2 pixels (4p−1, 2q−1), (4p−1, 2q), (4p, 2q−1), and (4p, 2q) are allocated to the sub-image 3.

  2 × 2 pixels (4p−1, 4q−1), (4p−1, 4q), (4p, 4q−1), and (4p, 4q) are allocated to the sub-image 4.

  As described above, the low-resolution images are arranged in order from the upper left. Here, p indicates a line number and q indicates a column number. The ranges of p and q are 1 ≦ p ≦ m and 1 ≦ q ≦ n.

  By dividing the input high-resolution image in this way, the four sub-images obtained as outputs regardless of the input image having any sampling pattern shown in FIG. The low-resolution images having the same sampling pattern between the sub-images are held, and the four sub-images can be subsequently processed using the same arbitrary signal processing algorithm.

  Next, an image signal processing apparatus according to a second embodiment of the present invention will be described. The second embodiment will explain that the image signal processing apparatus of the first embodiment can be used even in the pixel block unit suitable for the sampling structures of the 4: 1: 1 type and the 4: 1: 0 type. .

(Example 2)
The image signal processing apparatus according to the second embodiment of the present invention can be realized by using the same components as those of the image signal processing apparatus according to the first embodiment shown in FIG. 1, and detailed description of each unit will be omitted. However, in the second embodiment, the control parameter setting unit 17 extracts the video format ID added to the ultra-high definition video for the combination of (k, l) for dividing the input ultra-high definition video, The difference is that it further has a function of adding the ID to each of the low resolution signals for generating the divided low resolution images.

  FIG. 5 shows examples of sampling structures in the 4: 1: 1 type and the 4: 1: 0 type. Here, as described above, α, β, and γ are replaced according to the RGB method or the luminance and color difference signal method.

  In the second embodiment, the input ultra high-definition video includes RGB type or luminance and color difference signal type 4: 4: 4 type, 4: 2: 2 type, 4: 2: 0 type, and 4: 1: 1. Assumes a case where an ID (identifier) of a video format for identifying a sampling structure in a type, 4: 1: 0 type, a Bayer type in a single-plate color system, or a four-color filter type is attached. is doing. In such a case, the control parameter setting unit 17 determines a unit block to be reduced in resolution according to the ID of the video format, and controls the pixel block allocation unit 12, the pixel block read control unit 14, and the low resolution image 15. To construct a low-resolution image. Further, the control parameter setting unit 17 adds the ID of the video format for each generated low resolution image.

  As a result, the image signal processing apparatus according to the second embodiment of the present invention can identify which video format has been processed in the subsequent processing, and can perform a resolution reduction process suitable for an arbitrary video format. Can be applied.

  In the embodiment described above, each means has been described as an individual means for convenience of explanation. However, it is obvious that they can be appropriately combined or configured by one control means. Further, for example, the image signal processing device 1 can be realized by a plurality of devices or computers. Furthermore, one or more computers that constitute the image signal processing device 1 can be realized by the control of a central processing unit (CPU) and include at least one or more memories in order to realize the above-described processes. it can. Furthermore, in order for the computer to function as the image signal processing apparatus 1, a program to be executed by the CPU can be stored in a predetermined area of the memory. In addition, data required for realizing each process described above can be temporarily or permanently stored in a memory. Such a memory can be constituted by a ROM, a RAM, a hard disk or the like inside the computer as appropriate, or can be constituted by using an external storage device (for example, an external hard disk). Therefore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  According to the present invention, for example, the same sampling structure is used when performing a signal processing of a high-resolution color television image known as a super high-definition (ultra-high-definition image) or a low-resolution process when performing signal transmission. Since the retained low-resolution image is generated to enable later signal processing independent of the video format, it is useful for applications in which high-resolution images are processed in parallel.

FIG. 5 is a schematic operation diagram of an image signal processing apparatus according to an embodiment of the present invention. 1 is a block diagram of an image signal processing apparatus according to an embodiment of the present invention. It is a figure which shows the example of a video format of the high resolution image processed or transmitted. It is a figure which shows the relationship between the high resolution image input in the image signal processing apparatus 1, and the some low resolution image produced | generated. It is a figure which shows the other video format example of the high resolution image processed or transmitted. It is a block diagram of the conventional image signal processing apparatus. It is a figure which shows the example of another conventional image signal process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image signal processing apparatus 11 High resolution image signal input part 12 Pixel block allocation means 13-1, 13-2, 13-N Temporary memory for low resolution images 14 Pixel block readout control means 15 Low resolution image construction means 16 Low resolution image Signal output unit 17 Control parameter setting means 101 Signal processor 102, 103, 104, 105 Frame memory

Claims (12)

Super high definition consisting of the number of row pixels m * (a * 2 ^k ) × the number of column pixels n * (b * 2 ^l ) as integers a, b, m, n of 1 or more and integers k, l of 0 or more. An image signal processing device that performs low-resolution processing for dividing and processing parallel high-resolution images,
First dividing means for dividing the high-resolution image into m × n blocks in a block region having the number of row pixels (a * 2 ^k ) × the number of column pixels (b * 2 ^l ) in a pixel configuration adjacent to each other. When,
A second dividing unit that divides each of the m × n block regions into a × b in a pixel block having a row pixel number 2 ^k × column pixel number 2 ^{l in} a pixel configuration adjacent to each other;
A pixel block having a row pixel number 2 ^k × column pixel number 2 ^{l in} the same position with respect to each of the m × n block regions is sequentially extracted, and a × b row pixel number m * 2 ^k × column. An image signal processing apparatus comprising: a means for transmitting a low-resolution signal for generating a low-resolution image having the number of pixels n * 2 ^l .   The sampling structure of the high resolution image is RGB type or luminance and color difference signal type 4: 4: 4 type, 4: 2: 2 type, 4: 2: 0 type, 4: 1: 1 type, 4: 1: 2. The image signal processing apparatus according to claim 1, wherein the image signal processing apparatus is suitable for any sampling structure in a 0 type, a Bayer type in a single-plate color system, and a four-color filter type.   3. The image signal processing apparatus according to claim 2, wherein k and l are set to k = 0 and l = 0, respectively, in order to perform resolution reduction processing in units of one pixel.   The k and l are set to k = 1 and l = 0, respectively, in order to achieve a resolution reduction process in units of pixel blocks each having 2 row pixels × 1 column pixel. 3. The image signal processing device according to 2.   The k and l are set to k = 1 and l = 1, respectively, in order to perform a resolution reduction process in units of pixel blocks each having 2 row pixels × 2 column pixels. 3. The image signal processing device according to 2.   The k and l are set to k = 0 and l = 1, respectively, in order to achieve a resolution reduction process in units of pixel blocks each having 1 row pixel number × 2 column pixel number. 3. The image signal processing device according to 2.   The k and l are set to k = 0 and l = 2, respectively, in order to perform a resolution reduction process in units of pixel blocks each having 1 row pixel number × 4 column pixel number. 3. The image signal processing device according to 2.   The k and l are set to k = 1 and l = 2, respectively, in order to obtain a resolution reduction process in units of pixel blocks each having 2 row pixels × 4 column pixels. 3. The image signal processing device according to 2. The high resolution image has a predetermined effective range;
The means for dividing the high-resolution image may arbitrarily set pixel values in regions other than the effective pixels in order to ensure division in the basic pixel block of 2 ^k × 2 ^l pixels with respect to the pixel signals in the effective range. The image signal processing apparatus according to claim 1, further comprising means for inserting a value of.   For a combination of (k, l) for dividing the high resolution image, a video format ID added to the high resolution image is extracted, and each of the reduced resolution signals for generating the low resolution image is extracted. The signal processing apparatus according to claim 1, further comprising control parameter setting means for adding the ID. Super high definition consisting of the number of row pixels m * (a * 2 ^k ) × the number of column pixels n * (b * 2 ^l ) as integers a, b, m, n of 1 or more and integers k, l of 0 or more. An image signal processing method for dividing a high-resolution image at a time and performing a low-resolution process for parallel processing,
Dividing the high-resolution image into m × n blocks in a block area consisting of the number of row pixels (a * 2 ^k ) × the number of column pixels (b * 2 ^l ) in a pixel configuration adjacent to each other;
Dividing each of the m × n block regions into a × b with pixel blocks each having a row pixel number 2 ^k × column pixel number 2 ^{l in} a pixel configuration adjacent to each other;
A pixel block having a row pixel number 2 ^k × column pixel number 2 ^{l in} the same position with respect to each of the m × n block regions is sequentially extracted, and a × b row pixel number m * 2 ^k × column. And a step of transmitting a low-resolution signal for generating a low-resolution image having n * 2 ^l pixels. Super high definition consisting of the number of row pixels m * (a * 2 ^k ) × the number of column pixels n * (b * 2 ^l ) as integers a, b, m, n of 1 or more and integers k, l of 0 or more. A computer configured as an image signal processing device for dividing a high-resolution image at a time and performing a low-resolution processing for parallel processing;
Dividing the high-resolution image into m × n blocks in a block area consisting of the number of row pixels (a * 2 ^k ) × the number of column pixels (b * 2 ^l ) in a pixel configuration adjacent to each other;
Dividing each of the m × n block regions into a × b with pixel blocks each having a row pixel number 2 ^k × column pixel number 2 ^{l in} a pixel configuration adjacent to each other;
A pixel block having a row pixel number 2 ^k × column pixel number 2 ^{l in} the same position with respect to each of the m × n block regions is sequentially extracted, and a × b row pixel number m * 2 ^k × column. An image signal processing program for executing a step of sending a signal with reduced resolution for generating a low-resolution image having n * 2 ^l pixels.

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