JP4978550B2 - Mixer and ΔΣ modulator - Google Patents

Description

  The present invention relates to a mixer and a delta-sigma (ΔΣ) modulator, and more particularly to a mixer and a ΔΣ modulator when a time-division multiplexed analog signal is input.

Conventionally, a ΔΣ modulator is known as a circuit that can realize a relatively small and highly accurate AD converter. There are several types of this ΔΣ modulator. Generally, the low-pass ΔΣ modulator has a low maximum frequency included in a signal to be AD converted (for example, the maximum frequency is the operation of the switched capacitor circuit in the ΔΣ modulation circuit). The bandpass ΔΣ modulator is used for AD conversion of a signal on a carrier wave that is somewhat high. Patent Document 1 discloses an example in which a bandpass ΔΣ modulator is used for a transceiver.
JP-T-2002-521554

Assume that there is an analog input signal A that is transmitted with a signal C (frequency f _C ) on a certain carrier B (frequency f _B ) (f _B > f _C ). When AD conversion is performed on the signal C included in the analog input signal A by the bandpass ΔΣ modulator, the analog input signal A is converted into digital data by the bandpass ΔΣ modulator, and the digital data after the conversion is frequency converted by the digital mixer. Is done. However, the band-pass ΔΣ modulator generally has a larger circuit scale than the low-pass ΔΣ modulator having the same order.

On the other hand, when the signal C is AD-converted by the low-pass ΔΣ modulator, the maximum frequency of the signal A is f _B , so that oversampling ratio (= sampling frequency / (2 × analog input) In order to increase the maximum frequency of the signal)), it is necessary to sample at a sampling frequency higher than the maximum frequency (for example, several tens to several hundreds). In order to avoid this, the frequency of the analog input signal A is often lowered by an analog mixer and then input to the low-pass ΔΣ modulator to perform AD conversion.

  However, since the conventional analog mixer is generally composed of analog components such as a diode and a transformer, the circuit scale and the like are increased as compared with the digital mixer.

  As a result, although the circuit scale of the low-pass ΔΣ modulator is smaller than the band-pass ΔΣ modulator of the same order, the combination of the “conventional analog mixer and low-pass ΔΣ modulator” is the “bandpass ΔΣ modulator and digital mixer”. In some cases, the circuit scale may be larger than the combination.

  In addition, when AD conversion is performed on two signals included in the time-division multiplexed input signal, a splitter is generally required, which further increases the circuit scale.

  Therefore, an object of the present invention is to provide a mixer and a ΔΣ modulator that can reduce the size of a circuit for AD-converting two signals included in an input signal that is time-division multiplexed.

To achieve the above Symbol purpose, a mixer according to the present invention,
A voltage corresponding to the first analog signal based on a first synchronization signal synchronized with the division frequency from an input signal obtained by time-division multiplexing the first analog signal and the second analog signal at a predetermined division frequency A first signal generating means for generating a third analog signal composed of a voltage section having an amplitude value of and a complementary section in which the amplitude value of a section other than the voltage section is supplemented with a first reference voltage;
The first reference voltage at a sampling frequency of ^2b times (b is an integer equal to or greater than 0) from the amplitude value of the first periodic function that is ^2a times (a is an integer equal to or greater than 0) of the division frequency. By multiplying the amplitude value of the third analog signal in order by the first sample value sampled to include at least an amplitude value other than the amplitude value of the fourth analog signal. Second signal generating means for generating an analog signal;
Based on a second synchronization signal synchronized with the divided frequency, a voltage interval having a voltage corresponding to the second analog signal as an amplitude value and an amplitude value in a region other than the voltage interval are second from the input signal. Third signal generating means for generating a fifth analog signal composed of a complementary section supplemented with a reference voltage of
The second reference voltage at a sampling frequency 2 ^d times (d is an integer greater than or equal to 2) the division frequency from the amplitude value of the second periodic function that is 2 ^c times the division frequency (c is an integer greater than or equal to 0). By multiplying the amplitude value of the fifth analog signal in order by the second sample value sampled to include at least an amplitude value other than the amplitude value of the sixth analog signal. Fourth signal generating means for generating an analog signal,
A phase difference between the first synchronization signal and the second synchronization signal is ½ of the reciprocal of the division frequency.

In order to achieve the above object, a ΔΣ modulator according to the present invention includes:
An integrator;
A third analog signal generated from an input signal obtained by time-division multiplexing a first analog signal and a second analog signal at a predetermined division frequency based on a synchronization signal synchronized with the division frequency. At least connected to an input terminal to which a third analog signal composed of a voltage section having a voltage corresponding to an analog signal as an amplitude value and a complementary section in which the amplitude value of a section other than the voltage section is supplemented with a reference voltage is input. A capacitor having a possible first electrode and a second electrode connectable to at least the input of the integrator;
A quantizer that outputs an output signal of the integrator that is obtained by integrating a voltage of an input unit of the integrator with reference to the reference voltage and is compared with a predetermined threshold;
A DA converter that converts the output signal of the quantizer into an analog signal and outputs the analog signal;
A state in which the connection destination of the first electrode is the input terminal and the connection destination of the second electrode is the reference potential is a first state,
A state in which the connection destination of the first electrode is the output side of the DA converter and the connection destination of the second electrode is an input unit of the integrator is a second state,
A state in which the connection destination of the first electrode is the reference potential and the connection destination of the second electrode is the reference potential is a third state,
The state that switches from the first state to the second state is a first transition state,
When the state that switches from the third state to the second state is the second transition state,
The 2 ^b times the split frequency (b is an integer of 0 or more) a switching operation of one cycle of the reciprocal of the frequency of said first transition condition, the second transition state, the first transition state The switching operation in which the transition state is switched in the order of the second transition state is repeated.

In order to achieve the above object, a ΔΣ modulator according to the present invention includes:
An integrator;
A third analog signal generated from an input signal obtained by time-division multiplexing a first analog signal and a second analog signal at a predetermined division frequency based on a synchronization signal synchronized with the division frequency. At least connected to an input terminal to which a third analog signal composed of a voltage section having a voltage corresponding to an analog signal as an amplitude value and a complementary section in which the amplitude value of a section other than the voltage section is supplemented with a reference voltage is input. A capacitor having a possible first electrode and a second electrode connectable to at least the input of the integrator;
A quantizer that outputs an output signal of the integrator that is obtained by integrating a voltage of an input unit of the integrator with reference to the reference voltage and is compared with a predetermined threshold;
A DA converter that converts the output signal of the quantizer into an analog signal and outputs the analog signal;
A state in which the connection destination of the first electrode is the input terminal and the connection destination of the second electrode is the reference potential is a first state,
A state in which the connection destination of the first electrode is the output side of the DA converter and the connection destination of the second electrode is an input unit of the integrator is a second state,
A state in which the connection destination of the first electrode is the reference potential and the connection destination of the second electrode is the reference potential is a third state,
The state that switches from the first state to the second state is a first transition state,
When the state that switches from the third state to the second state is the second transition state,
The 2 ^b times the split frequency (b is an integer of 0 or more) a switching operation of one cycle of the reciprocal of the frequency of said first transition condition, the second transition condition, the second transition state The switching operation in which the transition state is switched in the order of the second transition state is repeated.

  According to the present invention, it is possible to reduce the size of a circuit for AD-converting two signals included in a time-division multiplexed input signal.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings. This embodiment is an oversampling AD converter that performs frequency conversion after separating a waveform obtained by multiplexing two analog signals in a time division manner, and AD converts each of the two analog signals. An embodiment for reducing the circuit scale constituting the AD converter will be described below.

FIG. 1 is a block diagram of an AD converter 100 according to an embodiment of the present invention. AD converter 100, a division multiplexed signal D when the second signal of the second analog signal B is time-division multiplexed by a rectangular wave C of the frequency f _C of the first analog signal A and the frequency f _B of the frequency f _A After the separation into the first analog signal A and the second analog signal B, each signal is AD-converted (f _C > f _A , f _B ).

The AD converter 100 converts a first splitter 10A for separating the signal A from the analog signal D and a third analog signal generated by the splitter 10A into a path for AD-converting the analog signal A, and a sampling frequency f _S. in a first multiplication unit for generating a first sampling unit 11A for sampling, the fourth analog signal by a sampling signal sampled by the sampling unit 11A for mixing with twice the frequency 2f _C of the frequency f _C 13A, a low-pass filter 21A to which a fourth analog signal that is a mixed signal mixed by the multiplier 13A is input, and a first AD converter 22A to which the analog signal filtered by the low-pass filter 21A is input AD conversion unit 22A The digital data and a first digital filter 23A outputs by performing a filtering process.

Similarly, the AD converter 100 samples the fifth analog signal generated by the splitter 10B and the second splitter 10B for separating the signal B from the analog signal D on the path for AD conversion of the analog signal B. a second sampling portion 11B sampled at frequency f _S, the second to generate a sixth analog signal by a sampling signal sampled by the sampling unit 11B for mixing with twice the frequency 2f _C of the frequency f _C Multiplication unit 13B, a low-pass filter 21B to which a sixth analog signal that is a mixed signal mixed by the multiplication unit 13B is input, and a second AD conversion to which the analog signal filtered by the low-pass filter 21B is input Section 22B and AD conversion section 22B And a second digital filter 23B for outputting by performing a filtering process on AD converted digital data.

  The low-pass filter 21 (21A, 21B) is provided as necessary. The low-pass filter 21 can appropriately remove the noise of the input signal input to the AD converter 22 (22A, 22B).

  The AD conversion unit 22 is, for example, a ΔΣ modulator. The ΔΣ modulator is an AD converter architecture that realizes a high resolution of, for example, 14 bits or more. An input signal is converted into a 1-bit digital signal by a ΔΣ modulator, and digital filter processing is performed on the signal to obtain a highly accurate AD conversion output. For example, in a secondary ΔΣ AD converter, if the oversampling ratio is 500 or more, a resolution of more than 16 bits and several tens of μV or less can be sufficiently realized.

  A fixed characteristic digital filter having a fixed filter characteristic may be provided between the AD converter 22 and the digital filter 23. Further, thinning processing (decimation) at a constant data interval may be performed after filtering by the fixed characteristic digital filter. In particular, when a moving average filter is applied as the fixed characteristic digital filter, efficient decimation processing with a reduced circuit scale can be performed. For example, assuming that the load is high for processing all 1-bit data of 4 MHz, decimation processing is performed at 62.5 kHz, which is 1/64.

  The AD converter 22 outputs a 1-bit digital data string. The digital filter 23 performs a moving average filter process on the digital data string to convert it into multi-bit data, and then performs a thinning (decimation) process, thereby lowering the internal processing frequency of subsequent calculations. Further, it is possible to reduce the subsequent digital filter calculation processing amount and simplify the circuit scale thereafter. Thereafter, based on the output data of the digital filter 23, a detection logic unit (not shown) detects the value of the signal A, the value of the signal B, and the like multiplexed on the input signal D in a time division manner.

  An example of the AD converter 22 (22A, 22B) is shown in FIGS. FIG. 5 is a block diagram of the first-order ΔΣ modulator 40. The primary ΔΣ modulator 40 outputs a subtractor 41 that outputs a signal obtained by subtracting a feedback signal from an analog input signal, an integrator 42 that integrates and outputs the output signal of the subtractor 41, and an output signal of the integrator 42. A comparator (quantizer) 43 that outputs a comparison with a predetermined threshold, a delay device (for example, a D flip-flop) 44 that is a delay element that delays the output signal of the comparator 15 for a unit time, and a delay device 44 And a 1-bit digital-analog converter (DAC) 45 that converts the digital output signal into an analog signal as the feedback signal and outputs the analog signal.

FIG. 6 is a circuit diagram of the primary ΔΣ modulator 40. The primary ΔΣ modulator 40 includes a switched capacitor to which an analog input signal is input (a capacitor 57 and a changeover switch 51 and a changeover switch 52 provided at both ends thereof), and an operational amplifier 53 that amplifies the output signal of the switched capacitor. And an integration capacitor 54, a comparator 55 to which the output signal of the integrator is input, and a digital signal output from the comparator 55 as a feedback signal to the switching signals of the switched capacitors 51 and 52. As a 1-bit DA converter 56. By the changeover switch is turned on / off according to the switching signal [Phi _A and [Phi _B, connection of the input electrode and the output electrode of the capacitor 57 is selectively changed. [Phi _A is the [Phi _B when on and off, [Phi _A is the [Phi _B when off is turned on. Capacitor 57 for sampling, when the switching signal [Phi _A, samples the analog input signal, when the clock signal [Phi _B is an inverted signal of the clock signal [Phi _A, the difference between the output of the 1-bit DA converter 56 It is configured as an input-side capacitor of an integrator connected to the CMOS operational amplifier 53 side.

Further, the AD converter 100 outputs a first switching signal having the same frequency (that is, f _C ) as the frequency of the rectangular wave C that time-divides the signal D, and a frequency that is twice the frequency of the rectangular wave C. A switching signal control unit 12 that outputs a second switching signal (that is, 2f _C ) is provided. That is, the switching signal control unit 12 can change the frequency of the switching signal according to the frequency f _C of the rectangular wave C that time-divides the input signal D. The switching signal control unit 12 outputs a first synchronization signal corresponding to the first switching signal itself to the splitter 10A in order to separate the signal A, and a logic inversion circuit to separate the signal B. The second synchronization signal obtained by inverting the first switching signal by 1B is output to the splitter 10B. In addition, the switching signal control unit 12 outputs a second switching signal to each of the multiplication units 13A and 13B in order to perform mixing.

FIG. 2 is a waveform for explaining the operation of the AD converter 100. FIG. 2 (a) shows the signal D to be transmitted in a time division two signals of the analog signal B of the analog signal A and the frequency _{f B} of the frequency _{f A} by the Hi / Lo of the rectangular wave C of the frequency _{f C} ( f _C > f _A , f _B ). That is, the signal D is a time-division multiplexed signal of the signal A and B in each sub-section which is divided by the division frequency f _C. The reciprocal (that is, the period) of the division frequency fc corresponds to the total time of the time in the section where the signal A exists and the time in the section where the signal B exists. This signal D is efficiently divided into signals A and B, and AD conversion is performed.

  The signal D is separated into signals A and B by the above-mentioned first and second synchronization signals synchronized with the rectangular wave C. Since the signal D is time-division multiplexed data, the signal B data does not exist in the section where the signal A data exists, and the signal A data does not exist in the section where the signal B data exists. The splitter 10A supplements a section in which the data of the signal B does not exist with a reference voltage (first reference voltage) such as a GND voltage (0V) or a 1/2 voltage of the circuit power supply. The splitter 10B The non-existing section is supplemented with a reference voltage (second reference voltage) such as a GND voltage (0 V) or a 1/2 voltage of the circuit power supply.

The switching signal control unit 12 synchronizes with the edge (rising edge or falling edge) of the rectangular portion generated on the signal D by time-division multiplexing with the rectangular wave C, for example, to thereby change the frequency of the rectangular wave C. A pulse-shaped first switching signal having the same frequency f _C is output. In this case, for example, the first switching signal is a pulse signal having a high level during the period from the rising edge to the falling edge of the signal D and a low level during the period from the falling edge to the rising edge of the signal D. The splitter 10A separates the portion of the signal A from the signal D during the high level period of the first switching signal, and complements the reference voltage during the low level period of the first switching signal. That is, as shown in FIG. 2B, the splitter 10 </ b> A includes a voltage section in which the voltage corresponding to the signal A is an amplitude value, and a complementary section in which the amplitude value in a section other than the voltage section is supplemented with the reference voltage. A third analog signal is generated and output. Similarly, the splitter 10B operates in accordance with the inverted signal of the first switching signal (that is, the above-described second synchronization signal), and thereby the voltage section having the voltage corresponding to the signal B as the amplitude value and the voltage A fifth analog signal composed of a complementary section in which the amplitude value of a section other than the section is supplemented with a reference voltage is generated and output.

  After the signals are separated, each signal is AD converted. Sampling is performed on the third analog signal corresponding to the signal A after the separation and the fifth analog signal corresponding to the signal B after the separation.

Sampling unit 11A, sampling a third analog signal corresponding to the signal A (FIG. 2 (b)) at a sampling frequency _{f S.} The sampling frequency f _S in the sampling unit 11A may be set to 2 ^b times the division frequency f _C (b is an integer of 0 or more, preferably 0, 1, 2, 3, 4) (f _S = ² b _f C).

Since the number of samplings increases as the value of b increases, the accuracy of AD conversion increases. On the other hand, the circuit scale increases, so that an appropriate value is set to b from the relationship between the required AD conversion accuracy and circuit scale. You only have to set it. In the case of FIG. 2, the case where b = 2 is illustrated as a preferable value of b. When b = 2, the number of samples during the time (1 / f _C ) is 4 points.

A sampled multi-level signal output from the sampling unit 11A is referred to as A _SAMPLE . As shown in FIG. 2C, the multilevel signal A _SAMPLE has discrete amplitude values.

Similarly, the sampling portion 11B samples the fifth analog input signal corresponding to the signal B at the sampling frequency f _S. The sampling frequency f _S in the sampling unit 11B may be set to 2 ^d times the division frequency f _C (d is an integer of 0 or more, preferably 0, 1, 2, 3, 4) (f _S = ² d _f C). b and d may be the same value or different values. That is, the sampling frequencies fs in the sampling units 11A and 11B may be the same or different from each other. By the same sampling frequency fs to each other, the multiple of the time of multiplying the divided frequency f _C since it identical with 11A and 11B, can be miniaturized simplification and circuit of the control logic.

Multiplying unit 13A, ^{2 a} times (a is an integer of 0 or more) sampling frequency of ^{2 b} times the divided frequency _{f C} from the amplitude value of the first periodic function of (b is an integer of 0 or more) of the divided frequency _{f C} The fourth analog is obtained by multiplying the amplitude value of the multi-value signal A _SAMPLE in order by the sample value sampled so as to include at least an amplitude value other than the reference voltage at the amplitude value. Generate a signal.

That is, the multiplication unit 13A mixes the multilevel signal A _SAMPLE according to the second switching signal having the frequency 2f _C output from the switching signal control unit 12. Since the multi-value signal A _SAMPLE is sampled at the frequency f _S , the amplitude value of the multi-value signal A _SAMPLE depends on the time (1 / f _S ) according to the displacement of the third analog input signal (FIG. 2B). ) Changes every second (see FIG. 2C). Therefore, the signal to be mixed with the multilevel signal A _SAMPLE in the multiplication unit 13A is set not to a continuous time signal but to a discrete time signal (sampled-data sequence) only corresponding to the multilevel signal A _SAMPLE. . That is, mixing can be performed by multiplying the sample value of the discrete-time signal and the multilevel signal A _SAMPLE .

In order to generate a sample value of a discrete-time signal, the reciprocal of a value obtained by multiplying the divided frequency f _C by 2 ^a (a is an integer equal to or greater than 0, preferably 0, 1, 2, 3, 4) is a period. A first periodic function is set. The first periodic function is, for example, a square wave periodic function including a reference voltage as an amplitude value. In order to reduce the circuit scale, the minimum amplitude value is set to a constant reference voltage (for example, 1 / of the circuit power supply). More preferably, it is a square wave periodic function with two voltages, preferably 0, and a maximum amplitude value of a predetermined constant voltage (for example, a positive voltage, preferably 1). The switching signal control unit 12 outputs a second switching signal having ^a frequency of 2 ^a f _{C in} accordance with the first periodic function (FIG. 2D). FIG. 2 illustrates the case of a square wave periodic function with a = 1 as a preferable value of a and a periodic function.

In FIG. 2D, in order to simplify the circuit scale, “1”, “0”, “1”, “0” are assumed to be four points at equal intervals in time on the square wave value of the frequency 2f _C. Are selected as sample values. That is, in the case of sample values of “1”, “0”, “1”, “0”, the sample values are accurately generated by resistance voltage division, arithmetic circuit, etc., compared to the case of sample values including a decimal point. This is advantageous in that the circuit scale is reduced by the amount that is not necessary.

The multiplication unit 13A adds the multilevel signal A _SAMPLE to
(1) _Multiply “1”: Output multi-value signal A _{SAMPLE as it} is (2) _Multiply “0”: Repeat two output operations as one cycle in the order of outputting a reference potential (eg, 0) such as ground. (Period: 1/2 f _C ). Each output operation is switched every time (1 / f _S ).

Therefore, the multiplier 13A is sampled value to the amplitude value of the multilevel signal _{A SAMPLE} "1" and "0" and the time by multiplying (1 / _{f S)} is switched for each time (1 _{/ f} S) Analog data (multilevel signal) whose value changes every time is output as a fourth analog signal. If necessary, the analog data output from the multiplier 13A is input to the AD conversion unit 22A after an unnecessary frequency band is cut by a filter 21A such as a low-pass filter (LPF). The AD conversion unit 22A converts the data into a 1-bit stream, and the digital data after the filter processing by the digital filter 23A such as a moving average filter is output as output data of the AD converter 100.

On the other hand, since the output of the multiplier 13B and the subsequent output are the same as those on the signal A side, the description will be simplified. However, the multiplier 13B has ^2c times the division frequency f _C (c is an integer of 0 or more). 2 ^d times (d is an integer of 0 or more) sampling part the sampled sample value to include at least the amplitude values other than the reference voltage at the sampling frequency of the second amplitude value from the divided frequency f _C of the periodic function By multiplying the amplitude value of the sampled multi-value signal B _SAMPLE output from 11B in order, a sixth analog signal having the multiplication result of the multiplication as an amplitude value is generated. Here, the second periodic function may be the same function as the first periodic function or a different function.

  Incidentally, it is possible to simply arrange the first-order ΔΣ modulator 40 as illustrated in FIGS. 5 and 6 after the multiplier 13 (13A, 13B) as illustrated in FIG. By using both the capacitor for realizing the operation of the unit 11 and the multiplier 13 and the capacitor 57 of the switched capacitor circuit of the first-order ΔΣ modulator 40, the circuit can be further reduced in scale. In addition, by performing switching control of the changeover switch arranged in the front and rear stages of the shared capacitor as described later, the sampling operation in the sampling unit 11 and the mixing operation in the multiplier 13 can be realized simultaneously. The three functions of the operation function and the subtraction function between the input signal and the feedback signal in the ΔΣ modulator can be realized by a single capacitor. That is, in FIG. 1, a small circuit having a function that combines the functions of the sampling unit 11 and the multiplier 13 and the function of the AD conversion unit 22 can be realized.

  FIG. 7 is a circuit diagram of a primary ΔΣ modulator 60 including a capacitor 67 that doubles as a capacitor for realizing the function of the multiplier 13 and the like and a capacitor 57 of the switched capacitor circuit of the primary ΔΣ modulator 40. FIG. 9 is a block diagram of a first-order ΔΣ AD converter including a first-order ΔΣ modulator 60 in the subsequent stage of the splitter 10. The primary ΔΣ modulator 60A for AD converting the signal A and the primary ΔΣ modulator 60B for AD converting the signal B have the same circuit configuration.

  In FIG. 7, the primary ΔΣ modulator 60 has an input terminal IN to which an analog signal output from the splitter 10 is input as an input signal of the primary ΔΣ modulator 60, and 1 as an output signal of the primary ΔΣ modulator 60. And an output terminal OUT from which a bit digital output signal is output. The first-order ΔΣ modulator 60 includes a switched capacitor (a capacitor 67 and a change-over switch 61 and a change-over switch 62 provided at both ends thereof) to which a analog signal output from the splitter 10 is input, and a switched capacitor. An integrator having an operational amplifier 63 and an integrating capacitor 64 for amplifying the output signal, a comparator 65 to which the output signal of the integrator is input, and an analog signal obtained by converting the digital signal output from the comparator 65 as a feedback signal And a 1-bit DA converter 66 for supplying to the connection terminals of the switch 61, 62 of the switched capacitor.

  The integrator of the primary ΔΣ modulator 60 includes an operational amplifier 63 and an integration capacitor 64 inserted between the inverting input terminal and the output terminal of the operational amplifier 63. The non-inverting input terminal of the operational amplifier 63 is connected to the reference potential. The reference potential may be ground or a predetermined positive potential (for example, a voltage that is half the power supply voltage of the operational amplifier 63).

  The changeover switch 61 includes an input terminal IN (input terminal 61b), a terminal 61c connected to the same reference potential as the non-inverting input terminal of the operational amplifier 63, and a terminal connected to the output side of the 1-bit DA converter 66. Switching means for selectively switching and connecting the first electrode of the capacitor 67 to the three terminals 61d. The changeover switch 62 has two terminals, a terminal 62 a connected to the inverting input terminal of the operational amplifier 63 and a terminal 62 b connected to the reference potential of the same potential as the non-inverting input terminal of the operational amplifier 63. Switching means for selectively switching and connecting the second electrodes.

  FIG. 8 is a diagram for explaining the operation of the first-order ΔΣ modulator 60. The above-described sampling operation of the analog input signal is realized by the circuit connection state of odd numbers (1) and (3) shown in FIG. 8, and the circuit connection state of even numbers (2) and (4) shown in FIG. An operation of integrating the analog input signal by taking the difference between the analog input signal and the output of the 1-bit DA converter 66 while realizing the above-described multiplication operation of the analog input signal is realized. Since (2) and (4) in FIG. 8 are the same circuit connection, the number of states of repeated switch operations is three.

In FIG. 8A, the first electrode which is the input terminal IN side electrode of the capacitor 67 is connected to the input terminal IN, and the second electrode which is the inverting input terminal side electrode of the operational amplifier 63 of the capacitor 67 is the reference potential. By sampling, the input voltage of the analog input signal is sampled. In FIG. 8 (2), the sampling value sampled in FIG. 8 (1) and the 1-bit DA converter are obtained by connecting the first electrode to the terminal 61d and connecting the second electrode to the terminal 62a. The difference with the output value of 66 is integrated. The transition state (a) from (1) to (2) corresponds to performing integration after multiplying the multilevel signal A _SAMPLE by “1”.

In FIG. 8C, the first electrode that is the input terminal IN side electrode of the capacitor 67 is connected to the reference potential, and the second electrode that is the inverting input terminal side electrode of the operational amplifier 63 of the capacitor 67 is set to the reference potential. By connecting, the reference potential is sampled. 8 (4), the first electrode is connected to the terminal 61d and the second electrode is connected to 62a, so that the sampling value sampled in FIG. 8 (3) and the 1-bit DA converter 66 can be obtained. Integrate the difference from the output value of. The transition state (b) from (3) to (4) corresponds to performing integration after multiplying the multilevel signal A _SAMPLE by “0”.

8 is repeated in the order of transition states (a), (b), (a), (b),..., The above-described sampling operation in the sampling unit 11 and “0” in the multiplier 13. , 1, 0, 1, 0, 1, 0, 1,..., And the integration and subtraction operations of the ΔΣ modulator can be realized. Each transition state transitions every time (1 / f _S ) (f _S = 4f _C ).

  Then, as described above, the 1-bit digital data string output from the ΔΣ modulator 60 is filtered by the digital filter 23, and the input signal D is input to the detection logic unit based on the output data of the digital filter 23. The values of the included signals A and B can be detected by AD conversion.

  FIG. 10 is a diagram showing operation timings of the change-over switches sw1, 2, 3, and 4 of the primary ΔΣ modulators 60A and 60B of FIG. The operation timing number of each changeover switch in FIG. 10 corresponds to the number in the frame marked beside the terminal of the changeover switch sw in FIG. During the period of the operation timing number in FIG. 10, a terminal having the same in-frame number as that number is connected to the electrode of the capacitor 67. As shown in FIG. 10, in order to AD-convert the signals A and B, the control is performed with the same control signal without changing the control timing of the ΔΣ modulators 60A and 60B (that is, the switch timing of the changeover switch sw). (Sw1 and sw3 may be the same control signal having the same phase, and sw2 and sw4 may be the same control signal having the same phase).

  Therefore, the first embodiment is shown in FIGS. 7 and 9 by adding the connection destination of the electrode of the switched capacitor of the primary ΔΣ modulator 40 shown in FIG. 6 and repeating the operation shown in FIGS. The primary ΔΣ modulator 60 can have a function in which the sampling function in the sampling unit 11 and the mixing function in the multiplication unit 13 in FIG. In addition, the low-pass ΔΣ modulator 60 that combines these functions and the function of the ΔΣ modulator has a “configuration in which a conventional analog mixer using a diode or a transformer and a low-pass ΔΣ modulator are combined” or “band”. The circuit scale can be reduced as compared with a configuration in which a path ΔΣ modulator and a digital mixer are combined. In particular, by complementing the reference voltage in the splitter 10 and multiplying the discrete values according to a rectangular wave periodic function including the reference potential, an analog mixer can be configured with a simple operation of the switched capacitor circuit, resulting in a large circuit scale. Can be small. Also, by combining an analog mixer with a ΔΣ modulator, both can be integrated and the circuit scale can be reduced.

FIG. 3 is a block diagram of an AD converter 200 according to an embodiment of the present invention. AD converter 200, like the AD converter 100, a time division multiplexing the first second 2 signal of the analog signal B of the analog signal A and the frequency _{f B} of the frequency _{f A} is a rectangular wave C of the frequency _{f C} The time-division multiplexed signal D is separated into a first analog signal A and a second analog signal B, and each signal is AD converted (f _C > f _A , f _B ). Description of the same parts as those of the AD converter 100 is omitted.

The AD converter 200 has a first splitter 10A for separating the signal A from the analog signal D and a third analog signal generated by the splitter 10A on the path for AD-converting the analog signal A, and a sampling frequency f _S. The first sampling unit 11A that generates the fourth analog signal by sampling at the frequency f _C and the fourth analog signal that is the post-mixing signal mixed by the sampling unit 11A is input. The filter 21A, the first AD converter 22A to which the analog signal filtered by the low-pass filter 21A is input, and the first digital filter that performs the filtering process on the digital data AD-converted by the AD converter 22A and outputs the digital data With 23A .

Similarly, the AD converter 200 samples the fifth analog signal generated by the splitter 10B and the second splitter 10B for separating the signal B from the analog signal D on the path for AD conversion of the analog signal B. A second sampling unit 11B that generates a sixth analog signal by sampling at the frequency f _S and mixing at the frequency f _C , and a sixth analog signal that is a mixed signal mixed by the sampling unit 11B The input low-pass filter 21B, the second AD converter 22B to which the analog signal filtered by the low-pass filter 21B is input, and the digital data AD-converted by the AD converter 22B are subjected to filter processing and output. Two digital filters 23 Provided with a door.

  The low-pass filter 21 (21A, 21B) is provided as necessary. The low-pass filter 21 can appropriately remove the noise of the input signal input to the AD converter 22 (22A, 22B).

The AD converter 200 outputs a first switching signal having the same frequency (that is, f _C ) as the frequency of the rectangular wave C that time-divides the signal D, and a half cycle of the period of the first switching signal. A switching signal control unit 12 that outputs a second switching signal having a frequency fc with a phase difference shifted is provided. The switching signal control unit 12 outputs the first switching signal as the first synchronization signal to the splitter 10A in order to separate the signal A, and as the second synchronization signal to separate the signal B. The second switching signal is output to the splitter 10B.

  In the first embodiment, it is indicated that “1, 0, 1, 0” may be sequentially multiplied by a discrete value when mixing. However, the same effect can be obtained by multiplying the multiplier “1,0,0,0” instead of the multiplier “1,0,1,0”. This is because, as shown in FIG. 2, even if 1 is multiplied by the portion supplemented with the reference voltage of 0 V, the multiplication result remains the same 0.

In this case, it is necessary to change the timing at which the signal A and the signal B are multiplied by the multiplier 1 so as to coincide with the section where the data of the signal to be AD-converted exists. Data interval of the signal A and signal B, the phase only 1 / 2f _C is shifted, the timing to apply a "1" may be shifted the phase by 1 / 2f _C. That is, when compared at the same timing, if the signal “D” is multiplied by the multiplier “1, 0, 0, 0”, the signal A can be mixed, and the signal “D” is multiplied by the multiplier “0, 0, 1, 0”. If so, the signal B can be mixed. In this way, multiplication of the signal “A” and the signal “B” is always performed by a multiplier “0” in a section where there is no data.

  This is because when the time-division multiplexed signal D is divided into the signal A and the signal B, the splitter function of the first embodiment that complements “0” in the interval where there is no data is based on the multiplication function in the multiplication unit of the first embodiment. It shows that it can be realized. That is, the signal separation function of the splitter and the multiplication function of the multiplication unit can be realized simultaneously.

Therefore, the splitter 10 directly receives the signal D.
(1) Multiply "1": Output signal D as it is (2) Multiply "0": Output ground reference potential (for example, 0) (3) Multiply "0": ground ground reference potential ( For example, 0) is output (4) "0" is applied: Four output operations may be repeated as one cycle in the order of outputting a reference potential (eg, 0) such as ground (period: 1 / f _C ). Each output operation is switched every time (1 / f _S ).

That is, for the signal D, multiplied in the coefficient "1,0,0,0" multiplies the coefficient "0,0,1,0" in the waveform of the rectangular wave of 25% duty ratio and periodic function with a frequency _{f C} The sample value sampled from can be used. By devising the control timing of the splitter in this way, the splitter can be provided with a mixing function without adding special hardware.

FIG. 4 is a waveform for explaining the operation of the AD converter 200. FIGS. 4 (a) shows the signal D to be transmitted in a time division two signals of the analog signal B of the analog signal A and the frequency _{f B} of the frequency _{f A} by the Hi / Lo of the rectangular wave C of the frequency _{f C} ( f _C > f _A , f _B ).

The signal D is separated into signals A and B by the above-described first and second synchronization signals that are synchronized with the rectangular wave C and that are out of phase with each other by a half period. In order to generate the first and second synchronization signals, the reciprocal of a value obtained by multiplying the divided frequency f _C by 2 ^a (where a is an integer equal to or greater than 0, preferably 0, 1, 2, 3, 4). A periodic function with a period is set. The periodic function is, for example, a square wave periodic function including a reference voltage as an amplitude value, and in order to reduce the circuit scale, the minimum amplitude value is set to a constant reference voltage (for example, a 1/2 voltage of a circuit power supply) Further, it is more preferable that it is a square wave periodic function, preferably 0) and having a maximum amplitude value of a predetermined constant voltage (for example, a positive voltage, preferably 1). The switching signal control unit 12 outputs the first and second synchronization signals having the frequency 2 ^a f _C according to the periodic function. FIG. 4 illustrates the case of a square wave periodic function with a = 1 as a preferable value of a and a periodic function.

The switching signal control unit 12 outputs a first synchronization signal to the splitter 10A as a pulse-shaped switching signal with a frequency f _C and a duty ratio of 25% (FIG. 4D), and a duty ratio 25 with a frequency f _C. The second synchronization signal is output to the splitter 10B as a% pulse-like switching signal (FIG. 4E). The pulse width (high level) corresponds to 25% of the period.

The switching signal control unit 12 synchronizes with the edge (rising edge or falling edge) of the rectangular portion generated on the signal D by time-division multiplexing with the rectangular wave C, for example, to thereby change the frequency of the rectangular wave C. The first and second synchronization signals in the form of pulses having the same frequency f _C are output. In this case, for example, the first synchronization signal is a pulse signal having a pulse width shorter than the time (1 / (2f _C )) synchronized with the rising edge of the signal D, and the second synchronization signal is This is a pulse signal having a pulse width shorter than the time (1 / (2f _C )) synchronized with the falling edge. The splitter 10A separates the portion of the signal A from the signal D during the high level period of the first synchronization signal, and complements with the reference voltage during the low level period of the first synchronization signal. The portion of the signal B is separated from the signal D during the high level period of the second synchronization signal, and complementation with the reference voltage is performed during the low level period of the second synchronization signal. That is, as shown in FIG. 2B, the splitter 10 </ b> A includes a voltage section in which the voltage corresponding to the signal A is an amplitude value, and a complementary section in which the amplitude value in a section other than the voltage section is supplemented with the reference voltage. The configured third analog signal is generated and output (similarly, the splitter 10B generates and outputs the fifth analog signal).

Sampling unit 11A, sampling a third analog signal corresponding to the signal A (FIG. 2 (b)) at a sampling frequency _{f S.} The sampling frequency f _S in the sampling unit 11A may be set to 2 ^b times the division frequency f _C (b is an integer of 0 or more, preferably 0, 1, 2, 3, 4) (f _S = ² b _f C). In the case of FIG. 4, the case where b = 2 is illustrated as a preferable value of b. The sampling unit 11A generates and outputs the sampled multi-level signal A _SAMPLE as a fourth analog signal (FIG. 4C). Similarly, the sampling unit 11B generates and outputs the sampled multilevel signal B _SAMPLE as a sixth analog signal.

  As in the case of the first embodiment, the first-order ΔΣ modulator 60 in FIG. 7 in which the signal separation function and the multiplication function (mixing function) in the splitter 10 and the sampling function in the sampling unit 11 are combined with one common capacitor is provided. By using it, the circuit can be miniaturized. FIG. 11 is a block diagram of a primary ΔΣ AD converter including a primary ΔΣ modulator 60 including the function of the splitter 10.

In the second embodiment, the switching operation of each switch is repeated in the order of the transition states (a), (b), (b), (b)... In FIG. The above-described signal separation operation and mixing operation of “1, 0, 0, 0,...” And the sampling operation in the sampling unit 11 can be realized, and the integration and subtraction operations of the ΔΣ modulator can also be realized. Each transition state transitions every time (1 / f _S ) (f _S = 4f _C ).

FIG. 12 is a diagram showing operation timings of the change-over switches sw1, 2, 3, and 4 of the primary ΔΣ modulators 60A and 60B of FIG. The operation timing number of each changeover switch in FIG. 12 corresponds to the number in the frame marked beside the terminal of the changeover switch sw in FIG. In the period of the operation timing number in FIG. 12, the terminal having the same in-frame number as that number is connected to the electrode of the capacitor 67. As shown in FIG. 11, the timing difference between the ΔΣ modulator 60A on the signal A side and the ΔΣ modulator 60B on the signal B side is that the timing “1” of sw1 and sw3 is half the signal period of the frequency f _C. By shifting by a period, the signal A is simultaneously operated as “1,0,0,0” as one cycle and the signal B as “0,0,1,0” as one cycle.

  Accordingly, the second embodiment is shown in FIGS. 7 and 11 by adding the connection destination of the electrode of the switched capacitor of the primary ΔΣ modulator 40 shown in FIG. 6 and repeating the operation shown in FIGS. The primary ΔΣ modulator 60 can have a function in which the signal separation function and the mixing function in the splitter 10 in FIG. 3 are combined with the sampling function in the sampling unit 11. In addition, the low-pass ΔΣ modulator 60 that combines these functions and the function of the ΔΣ modulator has a “configuration in which a conventional analog mixer using a diode or a transformer and a low-pass ΔΣ modulator are combined” or “band”. The circuit scale can be reduced as compared with a configuration in which a path ΔΣ modulator and a digital mixer are combined. In particular, by complementing the reference voltage in the splitter 10 and multiplying the discrete values according to a rectangular wave periodic function including the reference potential, an analog mixer can be configured with a simple operation of the switched capacitor circuit, resulting in a large circuit scale. Can be small. Also, by combining an analog mixer with a ΔΣ modulator, both can be integrated and the circuit scale can be reduced.

As described above, the AD converters of Examples 1 and 2 are
A voltage corresponding to the first analog signal based on a first synchronization signal synchronized with the division frequency from an input signal obtained by time-division multiplexing the first analog signal and the second analog signal at a predetermined division frequency A first signal generating means for generating a third analog signal composed of a voltage section having an amplitude value of and a complementary section in which the amplitude value of a section other than the voltage section is supplemented with a first reference voltage;
The first reference voltage at a sampling frequency of ^2b times (b is an integer equal to or greater than 0) from the amplitude value of the first periodic function that is ^2a times (a is an integer equal to or greater than 0) of the division frequency. By multiplying the amplitude value of the third analog signal in order by the first sample value sampled to include at least an amplitude value other than the amplitude value of the fourth analog signal. Second signal generating means for generating an analog signal;
Based on a second synchronization signal synchronized with the divided frequency, a voltage interval having a voltage corresponding to the second analog signal as an amplitude value and an amplitude value in a region other than the voltage interval are second from the input signal. Third signal generating means for generating a fifth analog signal composed of a complementary section supplemented with a reference voltage of
The second reference voltage at a sampling frequency 2 ^d times (d is an integer greater than or equal to 2) the division frequency from the amplitude value of the second periodic function that is 2 ^c times the division frequency (c is an integer greater than or equal to 0). By multiplying the amplitude value of the fifth analog signal in order by the second sample value sampled to include at least an amplitude value other than the amplitude value of the sixth analog signal. Fourth signal generating means for generating an analog signal,
The mixer includes a phase difference between the first synchronization signal and the second synchronization signal that is ½ of the reciprocal of the division frequency.

  Here, the first periodic function is preferably a square wave function including the first reference voltage as an amplitude value, and the second periodic function includes the second reference voltage as an amplitude value. It is preferably a square wave function. Further, the first reference voltage and the second reference voltage may be the same voltage. Further, a mixer with b = 2 and / or d = 2 is more preferable.

  In the mixer, it is preferable that a = 1 and / or c = 1. In these cases, the first sample value is an amplitude value 1, 0, 1, 0 of the first periodic function. More preferably, the second sample value is more preferably an amplitude value 1, 0, 1, 0 of the second periodic function.

  In the mixer, a = 0 and / or c = 1 is preferable. In these cases, the first sample value is an amplitude value 1, 0, 0, 0 of the first periodic function. More preferably, the second sample value is more preferably an amplitude value 1, 0, 0, 0 of the second periodic function.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  For example, although a sine wave is illustrated as a reference signal represented by a periodic function, a square wave, a triangular wave, a sawtooth wave, or a similar waveform thereof may be used.

  Further, although the first-order ΔΣ modulator has been exemplified, the same effect can be obtained by performing the same control with the same configuration in the second-order or higher-order delta-sigma modulator.

  FIG. 13 is a diagram for explaining the operation of the secondary ΔΣ modulator 70. The second-order ΔΣ modulator 70 includes a switched capacitor (capacitor 77 and both ends thereof) to which the output signal of the operational amplifier 63 of the first-stage integrator is input in addition to the configuration of the first-order ΔΣ modulator 60 of FIGS. And an integrator provided with an operational amplifier 73 and an integrating capacitor 74 for amplifying the output signal of the switched capacitor, and an output signal from the 1-bit DA converter 66. A multiplier 78 that multiplies an analog signal as a feedback signal by a predetermined multiplier and supplies it to the connection terminal of the changeover switch 71 is provided between the operational amplifier 63 and the comparator 65.

  The changeover switch 71 selectively switches and connects the first electrode of the capacitor 77 to two terminals, a terminal 71 a connected to the output terminal of the operational amplifier 63 and a terminal 71 b connected to the output side of the multiplier 78. It is the switching means to do. The changeover switch 72 has two terminals: a terminal 72a connected to the inverting input terminal of the operational amplifier 73 and a terminal 72b connected to the reference potential of the same potential as the non-inverting input terminals of the operational amplifiers 63 and 73. 77 is a switching means for selectively switching and connecting the 77 second electrodes.

Since the operation of the first-order ΔΣ modulator 70 is the same as that in FIG. 8 and the description thereof is simplified, the transition states (a) (b) (b) (b) (a) (b) (b in FIG. ) (B)... By repeating the switch operation of each switch in the order of “1, 0, 0, 0, 1, 0, 0, 0,. In addition, the above-described sampling operation in the mixing operation and the sampling unit 11 can be realized, and also the integration and subtraction operation of the ΔΣ modulator can be realized. Each transition state transitions every time (1 / f _S ) (f _S = 4f _C ).

It is a block diagram of AD converter 100 which is one embodiment of the present invention. 4 is a waveform for explaining the operation of the AD converter 100. It is a block diagram of AD converter 200 which is one embodiment of the present invention. 5 is a waveform for explaining the operation of the AD converter 200. 2 is a block diagram of a first-order ΔΣ modulator 40. FIG. 2 is a circuit diagram of a primary ΔΣ modulator 40. FIG. FIG. 3 is a circuit diagram of a primary ΔΣ modulator 60 including a capacitor 67 that doubles as a capacitor for realizing the function of the multiplier 13 and the like and a capacitor 57 of a switched capacitor circuit of the primary ΔΣ modulator 40. FIG. 6 is a diagram for explaining the operation of the primary ΔΣ modulator 60. 3 is a block diagram of a first-order ΔΣ AD converter including a first-order ΔΣ modulator 60 at the subsequent stage of the splitter 10. FIG. FIG. 10 is a diagram illustrating operation timings of the change-over switches sw1, 2, 3, and 4 of the primary ΔΣ modulators 60A and B in FIG. 9. 3 is a block diagram of a first-order ΔΣ AD converter including a first-order ΔΣ modulator 60 including the function of the splitter 10. FIG. FIG. 12 is a diagram illustrating operation timings of the change-over switches sw1, 2, 3, and 4 of the primary ΔΣ modulators 60A and B in FIG. 11. FIG. 6 is a diagram for explaining the operation of the secondary ΔΣ modulator 70.

Explanation of symbols

10 (10A, 10B) Splitter 11 (11A, 11B) Sampling unit 12 Switching signal control unit 13 (13A, 13B) Multiplying unit 22 (22A, 22B) AD conversion unit 40, 60, 70 ΔΣ modulator 51, 52, 61 , 62, 71, 72 selector switch 57, 67, 77 Capacitor 100, 200 ΔΣ AD converter

Claims (3)

A voltage corresponding to the first analog signal based on a first synchronization signal synchronized with the division frequency from an input signal obtained by time-division multiplexing the first analog signal and the second analog signal at a predetermined division frequency A first signal generating means for generating a third analog signal composed of a voltage section having an amplitude value of and a complementary section in which the amplitude value of a section other than the voltage section is supplemented with a first reference voltage;
The first reference voltage at a sampling frequency of ^2b times (b is an integer equal to or greater than 0) from the amplitude value of the first periodic function that is ^2a times (a is an integer equal to or greater than 0) of the division frequency. By multiplying the amplitude value of the third analog signal in order by the first sample value sampled to include at least an amplitude value other than the amplitude value of the fourth analog signal. Second signal generating means for generating an analog signal;
Based on a second synchronization signal synchronized with the divided frequency, a voltage interval having a voltage corresponding to the second analog signal as an amplitude value and an amplitude value in a region other than the voltage interval are second from the input signal. Third signal generating means for generating a fifth analog signal composed of a complementary section supplemented with a reference voltage of
The second reference voltage at a sampling frequency 2 ^d times (d is an integer greater than or equal to 2) the division frequency from the amplitude value of the second periodic function that is 2 ^c times the division frequency (c is an integer greater than or equal to 0). By multiplying the amplitude value of the fifth analog signal in order by the second sample value sampled to include at least an amplitude value other than the amplitude value of the sixth analog signal. Fourth signal generating means for generating an analog signal,
The mixer, wherein a phase difference between the first synchronization signal and the second synchronization signal is ½ of the reciprocal of the division frequency. An integrator;
A third analog signal generated from an input signal obtained by time-division multiplexing a first analog signal and a second analog signal at a predetermined division frequency based on a synchronization signal synchronized with the division frequency. At least connected to an input terminal to which a third analog signal composed of a voltage section having a voltage corresponding to an analog signal as an amplitude value and a complementary section in which the amplitude value of a section other than the voltage section is supplemented with a reference voltage is input. A capacitor having a possible first electrode and a second electrode connectable to at least the input of the integrator;
A quantizer that outputs an output signal of the integrator that is obtained by integrating a voltage of an input unit of the integrator with reference to the reference voltage and is compared with a predetermined threshold;
A DA converter that converts the output signal of the quantizer into an analog signal and outputs the analog signal;
A state in which the connection destination of the first electrode is the input terminal and the connection destination of the second electrode is the reference potential is a first state,
A state in which the connection destination of the first electrode is the output side of the DA converter and the connection destination of the second electrode is an input unit of the integrator is a second state,
A state in which the connection destination of the first electrode is the reference potential and the connection destination of the second electrode is the reference potential is a third state,
The state that switches from the first state to the second state is a first transition state,
When the state that switches from the third state to the second state is the second transition state,
The 2 ^b times the split frequency (b is an integer of 0 or more) a switching operation of one cycle of the reciprocal of the frequency of said first transition condition, the second transition state, the first transition state A ΔΣ modulator that repeats a switching operation in which transition states are switched in the order of the second transition states. An integrator;
A third analog signal generated from an input signal obtained by time-division multiplexing a first analog signal and a second analog signal at a predetermined division frequency based on a synchronization signal synchronized with the division frequency. At least connected to an input terminal to which a third analog signal composed of a voltage section having a voltage corresponding to an analog signal as an amplitude value and a complementary section in which the amplitude value of a section other than the voltage section is supplemented with a reference voltage is input. A capacitor having a possible first electrode and a second electrode connectable to at least the input of the integrator;
A quantizer that outputs an output signal of the integrator that is obtained by integrating a voltage of an input unit of the integrator with reference to the reference voltage and is compared with a predetermined threshold;
A DA converter that converts the output signal of the quantizer into an analog signal and outputs the analog signal;
A state in which the connection destination of the first electrode is the input terminal and the connection destination of the second electrode is the reference potential is a first state,
A state in which the connection destination of the first electrode is the output side of the DA converter and the connection destination of the second electrode is an input unit of the integrator is a second state,
A state in which the connection destination of the first electrode is the reference potential and the connection destination of the second electrode is the reference potential is a third state,
The state that switches from the first state to the second state is a first transition state,
When the state that switches from the third state to the second state is the second transition state,
The 2 ^b times the split frequency (b is an integer of 0 or more) a switching operation of one cycle of the reciprocal of the frequency of said first transition condition, the second transition condition, the second transition state A ΔΣ modulator that repeats a switching operation in which transition states are switched in the order of the second transition states.

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