JP4973254B2 - Evaluation method and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to an evaluation method and a method for manufacturing a semiconductor device, and in particular, an evaluation method for evaluating the performance of a static random access memory (SRAM) and a semiconductor device including an SRAM using such an evaluation method. The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, semiconductor devices have been miniaturized and highly integrated, and in a semiconductor device including a large number of transistors, there may be variations in performance of individual transistors due to variations in dimensions and impurity concentration distribution.

  In an SRAM, which is one of the memories, each cell includes a plurality of transistors, for example, a driver transistor, a transfer transistor, and a load transistor, each of which includes six transistors. In such an SRAM, if the transistor performance variation occurs, the margin of the read / write operation of each cell becomes small. Therefore, in forming the SRAM, it is important to measure and analyze such an operation margin.

Conventionally, various measurement / analysis methods have been proposed for a margin (static noise margin (SNM)) during a read operation of an SRAM cell (see, for example, Patent Documents 1, 2, and 3). In addition, a method for improving SNM by performing voltage control during a read operation has been proposed (see, for example, Patent Document 4).
Japanese Patent Laid-Open No. 2005-117037 Japanese Patent Laying-Open No. 2005-310242 JP 2006-134477 A JP 2003-123482 A

  However, on the other hand, the margin (write noise margin (WNM)) at the time of the write operation of the SRAM cell is a very important index for forming the SRAM as in the case of the SNM. There are few proposals for analysis methods.

For example, the following WNM measurement / analysis methods have been proposed.
In the SRAM cell, for example, two inverters each composed of a load transistor and a driver transistor form a flip-flop circuit, and the input / output terminals (output terminals of the inverters) of the inverter are connected to a common word line. The transfer transistors are connected to a pair of bit lines.

  In such an SRAM, with each inverter biased to a predetermined voltage, with one bit line at the power supply voltage and the other bit line at 0 V, the voltage at one node of the flip-flop is swept to reverse the voltage at the opposite node. Measure the voltage. The same measurement is performed for both nodes, two curves indicating the relationship between the swept voltage and the measured voltage are obtained, and the size of the square inscribed in the obtained two curves is used to evaluate the size of the WNM. .

  However, with this method, there is a region where the obtained WNM distribution deviates from the normal distribution, and it is pointed out that it is difficult to estimate the worst case of WNM. Furthermore, measurement using a PCM tester is difficult, and it is difficult to apply it to actual product evaluation.

  In addition to this, a method for obtaining a WNM that has a normal distribution by reviewing the definition of WNM so far has been proposed (IEEE ISSCC, 2006, p.630). According to this method, since WNM is in a normal distribution, it is possible to estimate the worst case of WNM by actually measuring a small number of SRAM cells. However, a dedicated circuit is required for the measurement.

The present invention has been made in view of such a point, and an object thereof is to provide an evaluation method capable of appropriately and easily evaluating an SRAM cell.
It is another object of the present invention to provide a method for manufacturing a semiconductor device including an SRAM using such an evaluation method.

According to one aspect of the present invention, the first and second inverters include flip-flop circuits configured by first and second inverters, and gates are connected to word lines in the first and second inverters, respectively. In an evaluation method of an SRAM cell to which the first and second bit lines are connected via two transistors, the first and second transistors are made conductive and the first bit line is set to a low voltage. In the state where the second bit line is set to a high voltage, the voltage of the internal node of the first inverter is changed to measure the current of the internal node, and the SRAM cell is measured using the current of the internal node. evaluation method is provided that to evaluate the write operation margin of.

  According to such an evaluation method, the first bit line of the SRAM cell is set to a low voltage, the second bit line is set to a high voltage, and the first and second bit lines are respectively connected to the first and second bit lines. The internal nodes of the first and second inverters connected via the second transistor are set to different electrical states. Then, a voltage is applied to the internal node of the first inverter connected to the low-voltage first bit line, and the current of the internal node is measured. The write operation margin of the SRAM cell is evaluated using the current thus obtained.

According to another aspect of the present invention , there is provided a first flip-flop circuit including first and second inverters, each having a gate connected to a word line in each of the first and second inverters. In the manufacturing method of the semiconductor device including the SRAM cell to which the first and second bit lines are connected via the second transistor, the step of forming the SRAM cell, and the SRAM cell formed With the first and second transistors conducting, the first bit line set to a low voltage, and the second bit line set to a high voltage, the voltage at the internal node of the first inverter the varied to measure the current of said internal node, a manufacturing method of a semi-conductor device that Yusuke a step, the evaluating the write operation margin of the SRAM cell using a current of said internal node is provided .

  According to such a semiconductor device manufacturing method, the write operation margin is evaluated for the formed SRAM cell. In that case, the first bit line of the SRAM cell is set to a low voltage, the second bit line is set to a high voltage, and the first inverter connected to the low voltage first bit line. A voltage is applied to the internal node, and the current of the internal node measured at that time is used to evaluate the write operation margin of the SRAM cell.

First and second bit lines of each low voltage S RAM cell is set to a high voltage, by changing the voltage of the internal node of the first inverter connected to the first bit line, measured at that time is the assess the write operation margin by using a current of its internal nodes. This makes it possible to evaluate the SRAM cell appropriately and simply. In addition, it is possible to obtain the SRAM capacity with high accuracy using the evaluation result.

It will be described in detail with reference to FIG surface.
FIG. 1 is a circuit diagram of an SRAM cell. FIG. 1 exemplifies voltage conditions during the write operation of the SRAM cell.

  The SRAM cell shown in FIG. 1 is configured using a total of six transistors: driver transistors Dr1, Dr2, transfer transistors Tr1, Tr2, and load transistors Lo1, Lo2. Here, n-channel MOS transistors (nMOS) are used for the driver transistors Dr1, Dr2 and transfer transistors Tr1, Tr2, and p-channel MOS transistors (pMOS) are used for the load transistors Lo1, Lo2. .

  The load transistor Lo1 and the driver transistor Dr1 are connected in series and are connected to each other's gates to constitute a first inverter. In the first inverter, the end on the load transistor Lo1 side is connected to the power supply line (Vdd), and the end on the driver transistor Dr1 side is grounded (Vss). Similarly, the load transistor Lo2 and the driver transistor Dr2 constitute a second inverter, the end on the load transistor Lo2 side is connected to the power supply line (Vdd), and the end on the driver transistor Dr2 side is grounded ( Vss).

  The output terminal of the first inverter is connected to the input terminal of the second inverter, and is connected to the bit line BL1 via the transfer transistor Tr1. The gate of the transfer transistor Tr1 is connected to the word line WL. Similarly, the output terminal of the second inverter is connected to the input terminal of the first inverter and to the bit line BL2 via the transfer transistor Tr2, and the gate of the transfer transistor Tr2 is connected to the word line. Connected to WL.

  The output terminal and input terminal of the first inverter are the internal nodes N1 and N2 of the SRAM cell, respectively, and the output terminal and input terminal of the second inverter are the internal nodes N2 and N1 of the SRAM cell, respectively.

  In such SRAM cell writing, as shown in FIG. 1, the word line WL is in a high voltage state (High) to turn on the transfer transistors Tr1 and Tr2, and the bit line BL1 is in a low voltage state. (Low), and the bit line BL2 is set to High. As a result, the driver transistor Dr1 is turned on and the load transistor Lo1 is turned off, and the driver transistor Dr2 is turned off and the load transistor Lo2 is turned on. Therefore, Low, that is, 0 is written in the internal node N1, and High, that is, 1 is written in the internal node N2. On the other hand, when the bit line BL1 is High and the bit line BL2 is Low, 1 is written to the internal node N1 and 0 is written to the internal node N2.

  Note that when reading the SRAM cell, when the word line WL is set to High, whether the bit line BL1 is High and the bit line BL2 is Low, or the bit line BL1 is Low and the bit line BL2 is High. This is done by detecting. The data of the internal nodes N1 and N2 is held by setting the word line WL to Low and turning off the transfer transistors Tr1 and Tr2.

Next, a method for evaluating WNM using such SRAM cells will be described.
Here, in order to evaluate WNM, first, the word line WL, the end portion of the first inverter on the load transistor Lo1 side, the end portion of the second inverter on the load transistor Lo2 side, and the substrate of the load transistors Lo1 and Lo2 ( n well) is set to the power supply voltage. The end portion on the driver transistor Dr1 side of the first inverter, the end portion on the driver transistor Dr2 side of the second inverter, and the substrate (p well) of the driver transistors Dr1 and Dr2 are grounded. One bit line BL1 is set to 0V, and the other bit line BL2 is set to the power supply voltage.

  At this time, a terminal (SMU terminal) is connected to the internal node N1 on the bit line BL1 side set to 0 V, and the voltage V1 of the internal node N1 is forcibly changed from 0 V to the power supply voltage, and enters and exits the terminal. The current I (V1) to be monitored is monitored. Note that the measurement is performed under a predetermined temperature environment.

  FIG. 2 is a diagram showing the relationship between the voltage V1 and the current I (V1). FIG. 3 is a diagram showing the relationship between the voltage V1 and the current I (V1) when the threshold voltage Vth of the transfer transistor Tr1 is changed.

  As shown in FIG. 2, the current I (V1) changes so as to increase once and then decrease through the maximum value and then gradually increase again through the minimum value as the voltage V1 of the internal node N1 increases. To do.

  WNM can be affected by the threshold voltages Vth of the load transistors Lo1 and Lo2, the driver transistors Dr1 and Dr2, and the transfer transistors Tr1 and Tr2 that constitute the SRAM cell. Sensitive to the value voltage Vth. FIG. 3 shows the respective voltages when the threshold voltages Vth of the transfer transistors Tr1 and Tr2 are changed to five types (conditions A, B, C, D, and E) and the occurrence of variation between cells is assumed. The relationship between V1 and current I (V1) is shown.

  3, even when the threshold voltage Vth of the transfer transistors Tr1 and Tr2 is changed, the current I (V1) changes in the same manner as in FIG. 2 along with the change of the voltage V1 of the internal node N1. However, the method of changing the current I (V1) differs depending on the conditions A, B, C, D, and E of the threshold voltage Vth, and the maximum value and the minimum value thereof are different.

Here, the minimum current Imin in a voltage region higher than the voltage V1 at which the current I (V1) is maximized is used as an evaluation index for WNM.
FIG. 4 is a diagram showing a simulation result of the minimum current Imin when the threshold voltages Vth of the transfer transistors Tr1 and Tr2 of the 90 nm generation SRAM cell are varied. Here, the threshold voltage Vth varies three times larger than the value measured in a normal 90 nm generation SRAM cell.

  From FIG. 4, the distribution of the minimum current Imin is on a normal distribution in a wide range (until the current I (V1) becomes 0). From this simulation result, it can be said that the minimum current Imin can be used as an evaluation index of WNM. Furthermore, it can be said that WNM can be evaluated by evaluating WNM from the number of devices that can be actually measured, that is, by measuring the minimum current Imin of a small number of SRAM cells.

  As described above, while sweeping the voltage V1 of the internal node N1 on the bit line BL1 side set to 0 V of the SRAM cell, the current I (V1) flowing therethrough is monitored, and the voltage V1 and the current I (V1) are monitored. By setting the minimum current Imin obtained from the above relationship to WNM, it is possible to accurately estimate the WNM of the SRAM cell.

In addition, when the minimum current Imin that can be estimated as WNM is used as described above, it is possible to predict the maximum capacity of the writable SRAM.
That is, for some cells of a certain SRAM, the minimum current Imin is measured as described above, the distribution of the minimum current Imin is obtained, and a value obtained by dividing the average of the minimum current Imin by the standard deviation is obtained. By using the value obtained in this way as the σ value at which a defective bit appears in the write operation, the maximum writable SRAM capacity can be obtained. For example, in the case of an SRAM having a capacity of 10 mega, a value of 6σ or more is required to operate all the cells. By using the σ value, it is possible to obtain the maximum writable SRAM capacity, and it is possible to determine whether or not the target write capacity can be obtained.

  Furthermore, the same SRAM used for evaluation of the maximum capacity of such a writable SRAM may be used, and the SNM at the time of the read operation may be estimated to obtain the maximum capacity of the readable SRAM.

  In order to estimate the SNM, the bit lines BL1 and BL2 are both set to the power supply voltage for several SRAM cells, and the voltage V1 of the internal node N1 is forcibly changed from 0 V to the power supply voltage. The flowing current I (V1) is monitored. The measurement is performed under a predetermined temperature environment.

  Also in this case, as the voltage V1 of the internal node N1 increases, the current I (V1) of each SRAM cell once increases, then decreases through the maximum value, and increases again through the minimum value. Change. Here, the maximum value (maximum value) of the current I (V1) measured in this way is set as SNM, its distribution is obtained, and a value obtained by dividing the average by the standard deviation appears as a defective bit during the read operation. As the σ value, the maximum capacity of the readable SRAM is obtained.

  By using the maximum readable SRAM capacity obtained in this way and the maximum writable SRAM capacity obtained as described above, it is possible to obtain the SRAM capacity considering both WNM and SNM. .

FIG. 5 is an explanatory diagram of SRAM capacity prediction.
The relationship shown in FIG. 5 is obtained by plotting both σ values with the σ value at the time of read operation obtained as described above on the horizontal axis and the σ value at the time of write operation on the vertical axis.

  In FIG. 5, an area that exceeds the σ value during the read operation and exceeds the σ value during the write operation, that is, the upper right area from the plot point in FIG. This is a complete operation region that can be operated (illustrated by a dotted line in FIG. 5, but is not limited to the region within the dotted line in FIG. 5). Therefore, by using such a σ value of the complete operation region, it is possible to obtain the SRAM capacity in consideration of both the SNM and the WNM for each target device.

  In the above description, when evaluating WNM, when changing the voltage V1 of the internal node N1 in order to obtain the minimum current Imin, the upper limit of the voltage V1 is set based on the rated voltage of the SRAM. Good. For example, the voltage V1 is changed so as to include a voltage range above or below the rated voltage. The same applies to the case of evaluating SNM.

  In the above description, when evaluating WNM, the voltage V1 of the internal node N1 is changed from 0V to obtain the minimum current Imin on the high voltage region side. However, the voltage V1 at which the minimum current Imin is obtained. In such a case, the minimum current Imin may be obtained by changing the voltage V1 of the internal node N1 within the range. Similarly, when evaluating the SNM, the voltage V1 of the internal node N1 may be changed from 0 V to a range in which the maximum value of the current I (V1) can be obtained.

  Further, when measuring the current I (V1) by changing the voltage V1 of the internal node N1, it is desirable to perform the measurement under a controlled predetermined temperature environment as described above. This is because both the WNM and SNM of the SRAM cell change depending on the temperature environment. WNM tends to be large in a relatively high temperature environment and small in a relatively low temperature environment. Conversely, SNM tends to be large in a relatively low temperature environment and small in a relatively high temperature environment. The temperature at the time of measurement may be set based on the specification temperature of the SRAM. For example, in the evaluation of WNM, the measurement is performed in a range including a temperature lower than the specification temperature, and in the evaluation of SNM. Measure in a range that includes a temperature higher than the specified temperature.

(Supplementary note 1) A flip-flop circuit composed of first and second inverters is provided, and the first and second inverters are respectively connected via first and second transistors whose gates are connected to a word line. In the evaluation method of the SRAM cell to which the first and second bit lines are connected,
With the first and second transistors conducting, the first bit line set to a low voltage, and the second bit line set to a high voltage, the voltage at the internal node of the first inverter To measure the current of the internal node,
An evaluation method comprising: evaluating a write operation margin of the SRAM cell using a current of the internal node.

(Supplementary Note 2) When evaluating the write operation margin of the SRAM cell using the current of the internal node,
The evaluation method according to claim 1, wherein a minimum value of the current of the internal node obtained in a predetermined voltage range when the voltage of the internal node is changed is used.

(Supplementary Note 3) When the voltage of the internal node is increased, the current of the internal node changes to show a minimum value after showing a maximum value,
When evaluating the write operation margin of the SRAM cell using the current of the internal node,
The evaluation method according to appendix 1 or 2, wherein a minimum value of the current of the internal node obtained on a higher voltage side than a voltage at which the maximum value is obtained is used.

  (Supplementary Note 4) The current value of the internal node is measured for a plurality of the SRAM cells, and the σ value at the time of write operation in which a defective bit appears is a value obtained by dividing the measured average value of the current distribution of the internal node by the standard deviation The evaluation method according to any one of appendices 1 to 3, wherein a writable SRAM capacity is obtained using the σ value at the time of the write operation.

(Supplementary Note 5) With respect to a plurality of the SRAM cells, the first and second transistors are turned on, and both the first and second bit lines are set to a high voltage. The voltage of the internal node is measured to measure the current of the internal node, a value obtained by dividing the average value of the current distribution of the internal node by the standard deviation is a σ value at the time of read operation in which a defective bit appears,
The evaluation method according to appendix 4, wherein an SRAM capacity is obtained using the σ value during the write operation and the σ value during the read operation.

(Appendix 6) When measuring the current of the internal node,
The evaluation method according to any one of appendices 1 to 5, wherein a voltage of the internal node is changed in a voltage range set based on a rated voltage of the SRAM cell, and a current of the internal node is measured. .

(Appendix 7) When measuring the current of the internal node,
The evaluation method according to any one of appendices 1 to 6, wherein a current of the internal node is measured by changing a voltage of the internal node under a temperature environment set based on a specification temperature of the SRAM cell. .

(Supplementary Note 8) A flip-flop circuit composed of first and second inverters is provided, and the first and second inverters are respectively connected via first and second transistors whose gates are connected to a word line. In the manufacturing method of the semiconductor device including the SRAM cell to which the first and second bit lines are connected,
Forming the SRAM cell;
With respect to the formed SRAM cell, the first and second transistors are turned on, the first bit line is set to a low voltage, and the second bit line is set to a high voltage. Measuring a current of the internal node by changing a voltage of an internal node of one inverter, and evaluating a write operation margin of the SRAM cell using the current of the internal node;
A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 9) When evaluating the write operation margin of the SRAM cell using the current of the internal node,
9. The method of manufacturing a semiconductor device according to claim 8, wherein a minimum value of the current of the internal node obtained in a predetermined voltage range when the voltage of the internal node is changed is used.

(Supplementary Note 10) When the voltage of the internal node is increased, the current of the internal node changes to show a local minimum after showing a local maximum,
When evaluating the write operation margin of the SRAM cell using the current of the internal node,
10. The method of manufacturing a semiconductor device according to appendix 8 or 9, wherein the minimum value of the current of the internal node obtained on a higher voltage side than the voltage at which the maximum value is obtained is used.

  (Supplementary Note 11) The current value of the internal node is measured for a plurality of the SRAM cells, and the σ value at the time of a write operation in which a defective bit appears is a value obtained by dividing the measured average value of the current distribution of the internal node by the standard deviation 11. The method of manufacturing a semiconductor device according to any one of appendices 8 to 10, wherein a writable SRAM capacity is obtained using the σ value at the time of the write operation.

(Supplementary Note 12) With respect to a plurality of the SRAM cells, the first and second transistors are turned on, and both the first and second bit lines are set to a high voltage. Measure the current of the internal node by changing the voltage of, the value obtained by dividing the measured average value of the current distribution of the internal node by the standard deviation as the σ value at the time of read operation in which a defective bit appears,
12. The method of manufacturing a semiconductor device according to appendix 11, wherein an SRAM capacity is obtained using the σ value during the write operation and the σ value during the read operation.

(Supplementary Note 13) When measuring the current of the internal node,
13. The semiconductor device according to any one of appendices 8 to 12, wherein a voltage of the internal node is changed in a voltage range set based on a rated voltage of the SRAM cell, and a current of the internal node is measured. Manufacturing method.

(Supplementary Note 14) When measuring the current of the internal node,
14. The semiconductor device according to any one of appendices 8 to 13, wherein a current of the internal node is measured by changing a voltage of the internal node under a temperature environment set based on a specification temperature of the SRAM cell. Manufacturing method.

It is a circuit diagram of an SRAM cell. It is a figure which shows the relationship between a voltage and an electric current. It is a figure which shows the relationship between the voltage and electric current when changing the threshold voltage of a transfer transistor. It is a figure which shows the simulation result of the minimum electric current at the time of varying the threshold voltage of the transfer transistor of a 90 nm generation SRAM cell. It is explanatory drawing of SRAM capacity prediction.

Explanation of symbols

BL1, BL2 Bit line Dr1, Dr2 Driver transistor Lo1, Lo2 Load transistor N1, N2 Internal node Tr1, Tr2 Transfer transistor WL Word line

Claims (4)

A flip-flop circuit composed of first and second inverters, the first and second inverters having first and second transistors each having a gate connected to a word line; In the evaluation method of the SRAM cell to which the second bit line is connected,
With the first and second transistors conducting, the first bit line set to a low voltage, and the second bit line set to a high voltage, the voltage at the internal node of the first inverter To measure the current of the internal node,
An evaluation method comprising: evaluating a write operation margin of the SRAM cell using a current of the internal node. The current of the internal node changes to show a minimum value after showing a maximum value when the voltage of the internal node is increased,
When evaluating the write operation margin of the SRAM cell using the current of the internal node,
2. The evaluation method according to claim 1, wherein a minimum value of the current of the internal node obtained on a higher voltage side than a voltage at which the maximum value is obtained is used.   A flip-flop circuit composed of first and second inverters, the first and second inverters having first and second transistors each having a gate connected to a word line; In a method for manufacturing a semiconductor device including an SRAM cell to which a second bit line is connected,
  Forming the SRAM cell;
  With respect to the formed SRAM cell, the first and second transistors are turned on, the first bit line is set to a low voltage, and the second bit line is set to a high voltage. Measuring a current of the internal node by changing a voltage of an internal node of one inverter, and evaluating a write operation margin of the SRAM cell using the current of the internal node;
  A method for manufacturing a semiconductor device, comprising:   The current of the internal node changes to show a minimum value after showing a maximum value when the voltage of the internal node is increased,
  When evaluating the write operation margin of the SRAM cell using the current of the internal node,
  4. The method of manufacturing a semiconductor device according to claim 3, wherein a minimum value of the current of the internal node obtained on a higher voltage side than a voltage at which the maximum value is obtained is used.

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