JP4963220B2 - Filter calculator and motion compensation device - Google Patents

Description

  The present invention relates to a filter processing apparatus suitable for executing a filter operation in a motion compensation process used for compression coding / decoding of a moving image, and a motion compensation processing apparatus including the filter processing apparatus.

  H. has been decided to be adopted for the next generation DVD (Digital Versatile Disk) and DTV (digital television). There are new codecs such as H.264 / AVC and VC-1. In these decoding apparatuses, the filter operation of the motion compensation prediction filter in the motion compensation unit may be configured by a multiplier to which Booth's algorithm is applied.

  The operation time of the multiplier is the sum of the time required to add the partial products and the time required to absorb the carry signal. In order to increase the operation speed, the processing time can be shortened. It becomes a problem. As a countermeasure, it is necessary to reduce the number of partial products in order to reduce the number of adder circuits. For this purpose, partial products can be reduced by grouping together a plurality of bits having consecutive multipliers and generating a partial product corresponding to this group. Therefore, the secondary booth is used to reduce the partial product number. The secondary booth is a partial product reduction technique to which an algorithm is applied in which a multiplier is divided every 2 bits, and a total of 3 bits of the most significant bits of each group and the lower group are combined.

  However, when the codec filter operation as described above is performed by a multiplier to which the Booth algorithm is applied, a large number of multipliers are required and the circuit scale increases. Similarly, H. When the filter operation used to generate a predicted image in the H.264 intra-screen prediction is applied by a multiplier to which the Booth algorithm is applied, the circuit scale increases.

  By the way, Patent Document 1 discloses a discrete cosine transformer in which the number of multipliers is reduced as much as possible and the circuit scale is reduced. FIG. 13 is a diagram illustrating a discrete cosine transformer described in Patent Document 1. In FIG. The discrete cosine transformer includes adders 612, 640, and 642, a difference unit 610, a register 614, multiplexers 616 and 652, multiplexer multipliers 618, 620, 622, and 634, butterfly adders 626, 628, 630, 632, and 644. , 646, 648, 650, multipliers 624, 636, 638, and a quantizer 654. Difference data by the difference unit 610 is obtained as an AC component of the image data, and DCT is performed on the difference data. Since the number of necessary coefficients is reduced by using the DCT for the difference, the number of multipliers can be reduced. Further, when multiplying different data by the same coefficient, multiplexer multipliers 618, 620, 622, and 634 are used to perform multiplication in a time division manner. For this reason, the number of multipliers can be further reduced. In addition, since the coefficient to be multiplied is previously multiplied with the quantization table of the quantizer 654, the number of multiplications can be reduced. As described above, the discrete cosine transformer described in Patent Document 1 uses the characteristics of the discrete cosine transform and performs the same operation at high speed using multiplication and butterfly operations.

Patent Document 2 discloses a signal processing apparatus that performs image signal processing such as spatial filtering in a time series. This signal processing apparatus reduces the circuit scale of a multiplier by repeatedly using the same partial product multiplier. FIG. 14 is a diagram illustrating a processor, a register circuit, and a coefficient register in the information processing apparatus described in Patent Document 2. The information processing apparatus includes an input / output buffer circuit 740, a coefficient register 711 that holds _five coefficients W _{1 to} W ₅ , and a processor 710. The input / output buffer circuit 740 includes a RAM 746 that holds pixel data for five rows and five registers 741 to 745 that respectively hold pixel data D _{1 to} D ₅ on the bus 820. The processor 710 includes two multipliers 710a and 710b, an adder 710c, a register 710d, a gate circuit 710e, multiplexers 710f and 710g on the data input side, and multiplexers 710h and 710i on the coefficient input side.

In this information processing apparatus, multipliers 710a and 710b calculate partial products P ₁ = W ₁ × D ₁ and P ₂ = W ₂ × D ₂ , respectively. The partial products P ₁ and P ₂ and the value of the register 710d are input to the adder 710c through the gate circuit 710e, the sum is obtained, and the result is held in the register 710d. A gate signal is applied to the gate circuit 710e from a control circuit (not shown), and the value in the register 710d is added to the partial product. Next, multipliers 710a and 710b calculate partial products P ₃ = W ₃ × D ₃ and P ₄ = W ₄ × D ₄ , respectively, and add them to the sum of the previous partial products. Further, the partial product P ₅ = W ₅ × D ₅ is calculated by the multiplier 710a, and zero is input to the multiplier 710b. Therefore, is added to the sum of partial products only up to the last P _5, it is held in the register 710d. The contents of the register 710d are stored in a memory cell unit (not shown) through the gate 717 and the bus 810. In this way, a fifth-order vector convolution integral can be obtained for the data D ₂ , D ₁ , D ₄ , and D ₅ adjacent to the data of interest D ₃ . Thus, in the information processing apparatus described in Patent Document 2, two multipliers 710a and 710b can be used for the degree 5 of vector convolution.
JP-A-6-44291 JP-A-62-105287

  However, the discrete cosine transformer described in Patent Document 1 has a problem that the circuit scale is large because a large-scale multiplier is used to perform multiplication at high speed. In addition, since image processing is not particularly used for general-purpose processing, when computing accuracy is required, the computing unit and the circuit scale are increased by that amount, which increases power consumption. Connected.

  In addition, the information processing apparatus described in Patent Document 2 has a problem that the computation time is three times longer than that in the case where five multipliers are provided in the processor.

  A filter arithmetic unit according to the present invention is a filter arithmetic unit that performs a product-sum operation on input data and filter coefficients using a Booth algorithm, and calculates a difference between current data and previous data, and the subtraction A partial product multiplier that multiplies the subtraction result from the filter by the filter coefficient, a number determination unit that determines the number of iterations in the partial product multiplier based on the subtraction result, and a cumulative result up to the previous data; And a cumulative adder for adding the multiplication result of the current data.

  A motion compensation processing apparatus according to the present invention is a motion compensation processing apparatus that generates a predicted image, and includes a first filter operation unit that performs a filter operation on input data in the vertical direction, and the input data in the horizontal direction. A second filter operation unit that performs a filter operation; and a weighting operation unit that performs weighting on the operation results of the first and second filter operation units or the input data input to the first and second filter operations. The first and second filter arithmetic units are filter arithmetic units that perform a product-sum operation on the input data and the filter coefficients using a Booth algorithm, and a subtractor that obtains a difference between the current data and the previous data; A partial product multiplier that multiplies the subtraction result from the subtracter by a filter coefficient, and a circuit that determines the number of iterations in the partial product multiplier based on the subtraction result. A determination unit, the cumulative result of the up previous data and has a cumulative adder for adding the multiplication result of the current data.

  In the present invention, a difference between the current data and the previous data is obtained, and this difference is subjected to a filter operation by repeatedly using one partial product multiplier. By repeatedly using the partial product multiplier, the operation circuit scale can be significantly reduced, and by using the difference signal, the number of repetitions can be minimized and the operation processing time can be shortened.

  According to the present invention, it is possible to provide a filter arithmetic unit and a motion compensation device using a booth algorithm that can reduce the amount of hardware and power consumption.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the present embodiment, the scale of a computing unit is drastically reduced by repeatedly performing computation in a filter computing unit using a booth algorithm. In addition, even if the calculation is performed repeatedly using the nature of the image and the fact that the difference in pixel values between adjacent pixels is small, the calculation processing time is shortened.

  First, an image decoding apparatus to which the filter arithmetic unit according to this embodiment can be applied will be described. Here, as an example, a case will be described in which the present invention is applied to a filter computing unit that executes filter computation in motion compensation processing in H.264 and VC-1. In addition, this invention is H.264. A motion compensation circuit capable of performing a filter operation in both H.264 and VC-1 standards will be described. Of course, the present invention can also be applied to a motion compensation circuit that performs a filter operation of only H.264, a motion compensation circuit that performs a filter operation of only VC-1, or other filter operation units such as MPEG (Moving Picture Experts Group) 2, 4 and the like. It is.

  First, an H.264, VC-1 image decoding apparatus will be described. 1 and 2 are block diagrams illustrating a decoding device that decodes a compressed image encoded in accordance with H.264 and VC-1. H. H.264 is also referred to as MPEG4 AVC (Advanced Video Coding), and is a compression encoding method that can make the data compression rate more than twice that of MPEG-2 and 1.5 times that of MPEG-4. VC-1 (Windows Media Video (WMV) 9) (registered trademark) is a video compression technology developed by Microsoft Corporation. The data compression rate is about the same as H.264. These advanced codecs (high compression codecs) are applied to next-generation DVD standards such as HD DVD (High Definition DVD) or Blu-ray Disc.

  As shown in FIG. 1, the H.264 image decoding apparatus 100 includes a variable length decoding unit 102, an inverse quantization unit 103, an inverse Hadamard transform unit 104, an adder 105, a deblocking filter 106, a motion The compensation unit 112, the weighted prediction unit 111, the in-screen prediction unit 110, and the monitor 109 that displays the decoded image 108 are included.

  The variable length decoding unit 102 performs variable length decoding on the compressed data that is input with the compressed data 101 and is variable length encoded based on the conversion table. The decoded data subjected to variable length decoding is inversely quantized by the inverse quantization unit 103, inverse Hadamard transform is performed by the inverse Hadamard transform unit 104, and sent to the adder 105. The output of the adder 105 is subjected to block distortion removal by the deblocking filter 106 to obtain a decoded image 108, which is displayed via the monitor 109.

  Here, the output of the adder 105 is also input to the in-screen prediction unit 110, and a predicted image 113 is generated. In addition, the motion compensation unit 112 performs motion compensation processing on the decoded image, and the weighted prediction unit 111 weights the decoded image to generate the predicted image 113. The adder 105 adds a prediction error to the prediction image 113 from the intra-screen prediction unit 110 and outputs it when performing I frame processing. On the other hand, in the P and B frame processing, switching is performed by the switching unit 107, and a prediction error is added to the predicted image 113 sent from the weighted prediction unit 111 and output.

As shown in FIG. 2, the VC-1 image decoding apparatus 200 is also configured in substantially the same manner as the image decoding apparatus 100, and includes a variable length decoding unit 202, an inverse quantization unit 203, an inverse DCT conversion unit 204, an adder. 205, a loop filter 206, a weighted prediction unit 209, a motion compensation unit 210, and a monitor 208 that displays a decoded image 207. The VC-1 image decoding apparatus 200 is different in that intra-screen prediction is not performed, motion compensation processing is performed after weighted prediction, and a loop filter 206 is used instead of the deblocking filter 106.
(3-2) Motion compensation unit

  FIG. 3 is a block diagram showing a motion compensation (MC) unit that executes a motion compensation process including a filter operation conforming to the standards of H.264 and VC-1. This motion compensation unit 300 is an H.264 standard. H.264 and VC-1 motion compensators can be used. That is, it can be shared by both standards. The motion compensation unit 300 includes filter calculation units 302 and 303, selectors 301, 304, 307, 310, and 313, multipliers 304 and 312, adders 306, 308, and 311, and a line memory 309.

H. In H.264, after the filter calculation is performed by the filter calculation units 302 and 303, the weighted interpolation signal is obtained using the above-described weighting coefficient, and the predicted image 213 is obtained. Here, the pixel value of the reference picture R0 input from the input IN is subjected to a filter operation using a vertical filter in the filter operation unit 302, and a filter operation using a horizontal filter is performed in the filter operation unit 303. The generated filter-calculated data is stored in the line memory 309. Next, when the pixel value of the reference picture R1 is input from the input IN, the filter calculation units 302 and 303 are similarly subjected to the filter calculation, and the multiplier 305 multiplies the filter-calculated data by the weight coefficient. Then, the adder 306 adds the offset value. On the other hand, the data stored in the line memory is multiplied by the weighted coefficient by the multiplier 312 via the selector 313 and added by the adder 308, and the weighted interpolation signal W ₀ X ₀ + W ₁ X with offset is added. ₁ + D is generated. The generated data is output from the output OUT via the line memory 309.

In the case of VC-1, data from the input IN is input to the filter arithmetic units 302 and 303 via the selector 313 and the selector 310, and further from the selector 304 via the multiplier 305 and the adder 306, and via the selector 301. The The result of the filter operation unit 303 is stored as it is in the line memory 309 via the selector 304 and the selector 307 and is output from the output OUT. In the multiplier 312, the adder 311, the multiplier 305, and the adder 306, the following weighting is executed.
H = (iScale × F + iShift + 32) >> 6
Here, F is an input value, and iScale and iShift are weighting factors.

  The motion compensator 300 configured in this way is selected by the selectors 301, 304, 307, 310, and 313 so that the inputs and outputs to the filter calculators 302 and 303 are appropriately selected. Even if it is H.264, even if it is VC-1 which performs weighting before a filter calculation, it is applicable to any calculation.

  Next, a filter calculation unit that can be used for such a motion compensation unit will be described in detail. In addition, in the above, H.H. The H.264 and VC-1 have been described as examples, but the filter calculator according to the present embodiment can also be used as a filter calculator in MPEG4, 2. FIG. 4 is a diagram showing details of the filter calculation units 302 and 303, and is a block diagram showing the filter calculation unit according to the present embodiment. Since the filter calculation units 302 and 303 have the same configuration, the filter calculation unit 302 will be described here. Table 1 below shows H.264. The filter coefficients for the luminance signal Gy and the color difference signal Gc in H.264 and VC-1 are shown.

  As shown in Table 1, H.P. In H.264, the luminance signal Gy is a 6-tap filter, and the color difference signal Gc is a 2-tap filter. The luminance signal Gy of VC-1 is a 4-tap filter, and the color difference signal Gc is a 2-tap filter. For this reason, the filter calculation unit 302 shown in FIG. 4 includes, for example, six filter calculation units 10a, 10b, 10c,. It should be noted that the calculation may be repeated with one filter operation unit. The calculation results of the filter calculation units 10a, 10b, 10c,... Are added by the adder 30 and output. Since the filter arithmetic units 10a, 10b, 10c,... Have the same configuration, the filter arithmetic units 10a, 10b, 10c,.

  FIG. 5 is a block diagram showing the filter calculator 10. The filter arithmetic unit 10 according to this exemplary embodiment uses one circuit part including a booth decoder and a partial product generation unit, and reduces the circuit scale by repeatedly using the circuit part. Further, the subtractor 13 takes the difference between the current image data and the previous image data and performs a filter operation to reduce the amount of calculation, thereby shortening the calculation time.

  Here, the filter arithmetic unit according to the present embodiment is a filter arithmetic unit that performs multiplication using Booth's algorithm. In order to facilitate understanding of the filter arithmetic unit according to the present embodiment, first, a multiplier using a second order Booth algorithm will be described.

Multiplier Y is a signed 8-bit integer Y = −y [7] · 2 ⁷ + y [6] · 2 ⁶ + y [5] · 2 ⁵ + y [4] · 2 ⁴ + y [3] · 2 ³ + y [2]・ 2 ² + y [1] ・ 2 ¹ + y [0] ・ 2 ⁰
Then, the product P = X × Y with the multiplicand X, which is an arbitrary integer, is as follows.

What calculates (−2 · y [2i + 1] + y [2i] + y [2i-1]) is a booth decoder, X × (−2 · y [2i + 1} + y [2i] + y [2i-1]) × 2 ²ⁱ is called partial product. In this specification, the decode value (−2 · y [2i + 1] + y [2i] + y [2i−1]) obtained by the Booth decoder is referred to as code data. In addition, a circuit for generating X × (−2 · y [2i + 1} + y [2i] + y [2i−1]) × 2 ²ⁱ (partial product) is a partial product generation unit, and X × (−2 · y [2i + 1} + Y [2i] + y [2i-1]) × 2 ²ⁱ , a circuit that generates a partial product corresponding to each i is represented by a partial product generation unit, code data (−2 · y [2i + 1] + y [2i] + y [ 2i-1]) is a booth decoder, a circuit that performs an operation consisting of code data × multiplicand to obtain a partial product is a multiplication unit, and a portion of the partial product that is to execute an operation of × 2 ²ⁱ is a bit shift unit. And

Here, as shown in Table 2 below, there are only eight combinations of values of the code data (−2 · y [2i + 1] + y [2i] + y [2i−1]), and 0, ± 1, ± 2 Takes only a value. Therefore, the multiplier can calculate a value (partial product) obtained by multiplying 0, ± X, ± 2X by 2 ²ⁱ and write it as a correspondence (truth table) of combinations of values to be added. Further, since there are only 8 values of the code data, the booth decoder can be obtained by a simple combinational logic circuit.

Of 0, ± X, and ± 2X, 2X can be generated by a 1-bit shift. On the other hand, since the multiplicand X is expressed in the complement of 2 when generating the negative number, it is only necessary to invert each bit of X and add 1 to the least significant bit. In order to realize this, for example, a circuit (Booth decoder) that generates code data (−2 · y [2i + 1] + y [2i] + y [2i−1]) Three signals including two signals for selecting an absolute value (0, X, 2X) and one signal for selecting inversion are generated. Further, the multiplication unit receives these three signals, and when the absolute value is 0, it is 0, and when it is X, the multiplicand X In the case of 2X, the multiplicand X shifted by 1 bit is selected, and if the inversion is necessary, the value can be inverted to generate a partial product. Furthermore, the bit shift unit that executes x2 ²ⁱ may simply shift the bit line by 2i.

  FIG. 6 is a block diagram illustrating a multiplier that performs multiplication according to such a second order Booth algorithm. The multiplier 400 includes a register F0 that outputs a multiplicand X and a register F7 that outputs a multiplier Y. Furthermore, a partial product generation unit 401 that receives a multiplier Y and a multiplicand X and generates a partial product, and an adder 450 that adds the partial products generated by the partial product generation unit 401 are provided. The partial product generation unit 401 includes four partial product generation units 410, 420, 430, and 440.

  As described above, each partial product generator receives a predetermined bit of the multiplier Y, generates a code data (0, ± 1, ± 2) according to Booth's algorithm, and the obtained code data It is assumed that a multiplication unit that outputs a multiplication result with the multiplicand X and a bit shift unit that performs a bit shift of a calculation result of the multiplication unit.

Each partial product generator corresponds to “i” of X × (−2 · y [2i + 1} + y [2i] + y [2i−1]) × 2 ²ⁱ . For example, the multiplier Y is 8 bits. (Y _{0 to} y ₇ ), i = 0 to 3, and X × (−2 · y ₁ + y ₀ +0) × 2 ⁰ and X × (−2 · y ₃ + y ₂ + y _{1, respectively.} ) × 2 ² , X × (−2 · y ₅ + y ₄ + y ₃ ) × 2 ⁴ , and X × (−2 · y ₇ + y ₆ + y ₅ ) × 2 ⁶ are obtained. In FIG. 6, the partial product generation units for obtaining these partial products are 410, 420, 430, and 440, respectively. In the present embodiment, the multiplier Y decoded by the Booth decoder is described by taking 8 bits as an example, but it is needless to say that the multiplier Y may be less than or more than this. In that case, what is necessary is just to adjust the number of partial product production | generation parts suitably.

Next, the operation of the multiplier 400 will be described using an actual calculation as an example. The 8-bit multiplier Y can be expressed as shown in FIG. The multiplier is divided every 2 bits, and the code data is obtained from the data of a total of 3 bits (however, y ₋₁ = 0) of the most significant bit of each group and the lower group. A partial product can be generated by multiplying these by the multiplicand X and calculating the corresponding bit shift (× 2 ⁱ ). For this reason, as shown in FIG. 7B, the register F7 is formed of a shift register that outputs 8 bits, and outputs a multiplier Y {y _{0 to} y ₇ }. At this time, the partial product generator 410 has the lower two bits {y ₀ , y ₁ } of the multiplier Y, and the partial product generators 420, 430, and 440 have {y ₁ , y ₂ , y ₃ }, { Enter y ₃ , y ₄ , y ₅ }, {y ₅ , y ₆ , y ₇ }. The partial product generation unit 410 generates a code data from these inputted predetermined bits, a booth decoder 411, a multiplication unit 412 that multiplies the obtained code data and the multiplicand X, and shifts the multiplication result by a predetermined bit. A bit shift unit 413. The other partial product generation units 420, 430, and 440 are similarly configured. Here, the multiplication of the multiplicand X = 358 (166H) and the multiplier Y = 123 (7BH) will be described. Table 3 below shows each output value in the calculation process.

X × Y = 358 × 123 = 44034 (AC02H)
Y = 123 (7BH)
= (-2 ・ 0 + 1 + 1) ・ 2 ⁶
+ (− 2 · 1 + 1 + 1) · 2 ⁴
+ (-2 · 1 + 0 + 1) · 2 ²
+ (-2 · 1 + 1 + 0) · 2 ⁰
= 2 · 2 ⁶ + 0 · 2 ⁴ + (− 1) · 2 ² + (− 1) · 2 ⁰
Therefore, it becomes the following.
X × Y = {(2 × 358) × 2 ⁶ }... Operation by partial product generation unit 410 + {(0 × 358) × 2 ⁴ }... Operation by partial product generation unit 420 + {( −1 × 358) × 2 ² }... Operation by partial product generation unit 430 + {(− 1 × 358) × 2 ⁰ }... Operation by partial product generation unit 440

First, “358” is input to each partial product generation unit 410, 420, 430, 440 from the multiplicand input unit F0. From the multiplier input unit F7, each partial product generation unit 410, 420, 430, 440 receives {y ₀ , y ₁ } = {1, 1}, {y ₁ , y ₂ , y ₃ } = {1, 0, 1}, {y ₃ , y ₄ , y ₅ } = {1, 1, 1}, {y ₅ , y ₆ , y ₇ } = {1, 1, 0} are input. The booth decoders 411, 421, 431, and 441 respectively receive (−2 · y [2i + 1} + y [2i] + y [2i−1]) = (− 2 · y ₁ + y ₀ +0), ( Code data corresponding to the calculation of (−2 · y ₃ + y ₂ + y ₁ ), (−2 · y ₅ + y ₄ + y ₃ ), (−2 · y ₇ + y ₆ + y ₅ ) is output. From the above equation, in this example, each booth decoder 411, 421, 431, 441 outputs “−1”, “−1”, “0”, “2”, respectively.

  Each of the multipliers 412, 422, 432, 442 calculates the code data × the multiplicand X and inputs them to the bit shift units 413, 423, 433, 443, respectively. The bit shift unit 413 outputs it to the adder 450 as it is. In this example, the bit shift unit 413 is provided for clarity of explanation, but it is not necessary to provide it. Bit shift sections 423, 433, and 443 shift the received results by 2 bits, 4 bits, and 6 bits, respectively, and input the result to adder 450.

  The adder 450 of this example includes full adders (full adders) 451 and 452, half adders (half adders) 453, and a register 454 for receiving the result. The values input from the bit shift units 413, 423, 433, and 443 are added by the adder 450 and output as the multiplication result P.

In this way, when the second-order Booth algorithm is used, the multiplier is set to 0, ± 1, ± 2 code data × 2 ²ⁱ and the calculation is performed with the multiplicand, so that the number of partial products is substantially halved. Therefore, the number of partial products to be added by the adder can be substantially halved, so that the multiplier can be reduced in size.

  When such a partial product generating unit is used, the filter arithmetic unit shown in FIG. 5 becomes an arithmetic circuit as shown in FIG. FIG. 8 is a diagram illustrating a filter arithmetic unit having a conventional configuration. That is, as described above, for example, if it is 8 bits, four partial product generators are required, and if it is 10 bits, for example, five partial product generators are required. In FIG. 8, only three partial product generators are shown for simplicity.

  Briefly describing FIG. 8, the filter arithmetic unit 501 includes registers (flip-flops: FFs) 502, 510, 511, 513, 516, partial product generation units 503 to 505, an adder 509, adders 512, 514, and a limiter circuit. 515. The partial product generators 503 to 505 have booth decoders 506 to 508, respectively. Pixel data is input as a multiplier Y and held in the FF 502. A value is input from the FF 502 to the partial product generation units 506 to 508 corresponding to each bit to generate a partial product. The adder 509 adds them and inputs the upper and lower bits to the FFs 512 and 511, respectively. The adder 512 adds the values from the FF 510 and the FF 511 and outputs the result to the FF 513. The adder 514 adds the value from the FF 513 and the filter coefficient B. The limiter circuit 515 sets the value of the adder 514 to 0 to 255, for example. Limit to the range and output to FF516.

This filter operator
[Output pixel] = Lim ([Input pixel] × A + B)
Execute the operation. Here, A indicates a filter coefficient. B is a predetermined constant added as needed in each filter operation. In a conventional filter arithmetic unit, data read from an external memory or the like is read in bursts. At this time, in general, when high-speed computation is performed, the pipeline processing is performed by a large-scale multiplier. For this reason, for example, if the input pixel data is 10 bits, five partial product generation units are required, which results in a large circuit scale and thus high power consumption.

On the other hand, in the present embodiment, the partial product generation units 506 to 508 are used as one partial product generation unit, and the circuit scale is reduced and power consumption is reduced by repeatedly using one partial product generation unit. To do. Returning to FIG. 5, the filter arithmetic unit 1 according to the present exemplary embodiment includes a register (FF) 11 that holds data in order to obtain a difference from the previous data, and a subtractor 13 that obtains a difference between the current data and the previous data. From the output result from the subtractor 13, the iteration number determination unit 15 that determines the number of multiplications by the partial product generation unit 18, the partial product generation unit 18 that multiplies the subtraction result from the subtractor 13 by a certain coefficient A, and the previous data And the output of the current partial multiplication result, an adder 23 for adding a constant B to the multiplication result, and a limiter circuit 24. The filter calculator 1 performs the following calculation.
[Output pixel] = Lim ([Input pixel] × A + B)

  Since the data from the external memory is normally transferred in bursts in the filter computing unit 1, the data is not always input continuously. In addition, since the image data has a relatively correlation between adjacent pixels, the difference between the pixels is also relatively small. By utilizing the above features, the circuit scale can be greatly reduced using a small partial product generator. At the same time, when the difference from the previous data is small, the data is output almost continuously, and even if the difference is large and the multiplication time is extended, there is a little time between burst data, so there is a considerable performance degradation. Processing can be made without Furthermore, power consumption can be reduced by reducing the circuit scale.

  Hereinafter, the filter computing unit 1 according to the present embodiment will be described in more detail. The subtracter 13 subtracts the previous image data held in the FF 11 from the input current image data to obtain difference data. The reason for this will be described. FIG. 9 is a diagram illustrating an amplitude distribution of a difference signal between adjacent pixels in the horizontal direction for an image (image information compression, Television Society bias, P71). The horizontal axis represents amplitude and the vertical axis represents frequency. The difference signal is concentrated in a narrow range near zero. Therefore, a value close to 0 can be obtained by obtaining the difference signal by the subtractor 13. By setting the input as the difference data to a value close to 0, it is possible to minimize the number of repeated calculations described later, and to shorten the calculation processing time. This value is held in FF14.

Next, the iteration number determination unit 15 determines the number of iterations in the partial product generation unit 18 based on the value of the FF 14. The repetition number determination method of the repetition number determination unit 15 will be described. FIG. 10 is a schematic diagram illustrating 10-bit image data, and FIG. 11 is a diagram illustrating a configuration of the repetition count determination unit 15. First, as shown in FIG. 10, the image data has 10 bits y _{0 to} y ₉ (where y ₉ is a sign bit). Here, as described above, in the Booth algorithm, the image data (multiplier Y) is divided into 2 bits, and a total of 3 bits of data groups (groups) S0 to S4 of each set and the most significant bit of the lower set are used. Code data is obtained. A set of y ₀ and y ₁ is assumed to be a data group (group) S 0 assuming a bit with y ₋₁ = 0.

10-bit data, for example, -1 is _{(y 9 y 8 y 7 y} 6 y 5 y 4 y 3 y 2 y 1 y 0 y -1) = (11111111110), -2 is the (11111111100) .

The code data is obtained by y _2i-1 + y _2i -2y _{2i + 1. If} all 3 bits constituting the data group are the same code, that is, (111) or (000), the code data is “0”. That is, since the value output from the booth decoder 17 is “0”, the partial product is always “0”, and there is no need to perform an operation. In the present embodiment, the number of iterations of the partial product generation unit is reduced by omitting the computation of the data group in which the code data is “0”.

  As a method for determining the number of repetitions, there is a method described below. For example, the number of repetitions is determined according to the arrangement of 10 bits, but a table in which the number of repetitions corresponding to the arrangement of 10 bits is associated in advance is prepared, and this table 41 is referred to as shown in FIG. There is a method of outputting the number of repetitions.

As another method, there is a method in which a code is determined from higher bits and a change point of the code is detected. For example, if -1, as shown in FIG. 10, are all the high-order bits _{y 9} to _{y 0 1,} to become zero at _{y -1,} change point is included in the data group S0. In this case, only the calculation of the data group S0 needs to be performed, and the number of repetitions is one. If it is −2, the upper bits y ₉ to y ₁ are all 1 and y ₀ becomes 0, so the change point is included in the data group S0. Also in this case, it is only necessary to perform the operation on the data group S0, and the number of repetitions is one. Further, if 65 are all the high-order bits _{y 9} to _{y 7} 0, since the 1 _{y 6,} the change point is included in the data group S3. In this case, four groups of operations from the data group S0 to the data group S3 may be performed, and the number of repetitions is four.

As another method, in 65, there is a method in which the search is continued for all the bits up to the least significant bit even if a change point is detected. In this case, there is a transition point between y ₆ and y ₅ , and y ₅ to y ₁ are 0. Then, between _{y 1} and _{y 0,} there is a change point between _{y 0} and _{y -1.} In this case, the data group including the change point is only the data groups S3 and S0. Therefore, the number of repetitions can be set to 2. In the case described above, the number of repetitions is determined when a change point is found, so that the number of repetitions can be determined earlier. On the other hand, the method of searching all bits from the most significant bit to the least significant bit to detect the change point can further reduce the number of repetitions. In this case, although starting from the upper bit, when the change point is detected to the end, it may be detected from the lower bit. For example, in the case of −128, y ₋₁ to y ₆ is “0”, y ₇ to y ₉ is “1”, and there is a change point between y ₆ and y ₇ . In this case, only the data group S3 needs to be calculated.

  Furthermore, as another method, for each data group, it may be detected whether the data group is (000) or (111). The reason is to make the secondary booth decoding result 0. In this case, the processing may be performed from the upper bit side, the lower bit side, or all the bits simultaneously. For example, in the case of 127, the data groups S0 and S3 are calculation targets, and the number of repetitions is two. If it is 2, only the data group S0 is the object of calculation and the number of repetitions is 1. If it is 1, only the data group S0 is a calculation target and the number of repetitions is 1.

  FIG. 11B is a diagram illustrating an example of a circuit that detects whether the data group is (000) or (111). The 10-bit data is divided into data groups S0 to S4 and input to the determination units 51 to 55, respectively, and it is determined whether the data is (000) or (111). For example, if (000) or (111), 0 is output, otherwise 1 is output. The table 56 outputs the number of repetitions according to the output of the determination units 51 to 55. At this time, information on which data group is operated (hereinafter referred to as data group information) is output together.

  FIG. 11C is a diagram illustrating an example of a specific circuit that determines the number of repetitions by detecting where the change point is located. Image data is input to the FF 61 from the upper bits. The higher order bit held in the FF 61 is compared with the next lower order input bit by the comparator 62, and for example, “0” is output if they match, and “1” is output if they do not match. The counter 63 is a down counter and counts the count value from 9 to 0. The number-of-times determination unit 64 outputs the number of repetitions to the MUXs 16 and 19 based on the counter value when “1” is input.

  As described above, the repetition count determination unit 15 outputs at least the repetition count. When it is detected whether or not all data groups are (000) or (111), the number of repetitions and data group information indicating which data group needs to be calculated are output to the MUXs 16 and 19. To do.

When only the number of repetitions is input, the MUX 16 outputs a data group corresponding to the number of repetitions to the partial product generation unit 18. For example, when the number of repetitions is 3, first, (y ₁ , y ₀ , 0) is input, (y ₃ , y ₂ , y ₁ ) is input at the next timing, and (y ₅ , y at the next timing). ₄ , y ₃ ).

When the repetition count and data group information are input, the data group is output to the partial product generator 18 based on the data group information. For example, in the case of 65 described above, change points are detected in the data groups S0 and S3. In this case, (y ₁ , y ₀ , 0) is input at the first timing, and (y ₇ , y ₆ , y ₅ ) is input at the next timing.

  The partial product generator 18 and the booth decoder 17 perform the above-described calculation. That is, the booth decoder 17 obtains code data from the data group, and the partial product generation unit multiplies the code data by the filter coefficient A. Here, the bit shift is not performed and the data is output to the MUX 19.

Similar to the MUX 16, the number of repetitions is also input to the MUX 19. Therefore, when the number of repetitions is 1, the bit shift is not performed (because it is x1) and is output to the adder 20 as it is. When the number of repetitions 2, shifted by 2 bits (for × 2 ^2), and outputs to the adder 20. Similarly, (for × 2 ⁴⁾ repeat count 4 bit shift when the 3, (for × 2 ⁶⁾ repeat count 6 bit shift when the 4, 8-bit shift when the number of repetitions of 5 ( × for ^{2 8)} and outputs to the adder 20.

  When the number of repetitions and data group information are input to MUX19 and MUX16, bit shift is performed based on the data group information. For example, in the case of 65 described above, the operation result of the data group S0 is output without being bit-shifted, and the value of 6-bit shift is added to the adder 20 in the operation of the data group S3 at the next timing. Output to. The MUX 16, the partial product generator 18 and the MUX 19 constitute a partial product multiplier that multiplies the subtraction result from the subtracter and the filter coefficient.

  The adder 20 adds the output from the MUX 19 and the previously output value held in the FF 21 and stores it again in the FF 21 until the repetition operation is completed. The selector 22 selects 0 for the first iterative calculation, and otherwise selects and outputs the value of the FF 21. The adder 20 adds the partial products obtained from the data groups S0 to S4, and adds the current addition result to the previous addition result, thereby obtaining the filter operation result of the current pixel data. it can. That is, both the previous addition result and the current addition result are composed of partial product sums obtained by multiplying the difference data by the filter coefficient A, and by adding these, the filter operation result of pixel data that is not difference data is obtained. Can do.

  The adder 23 adds the coefficient B if necessary, and outputs the calculation result to the limiter circuit 24. For example, the limiter circuit 24 limits the calculation result to fall within the range of 0 to 255 and outputs the result to the FF 25.

  FIG. 12 is a diagram for explaining the effect of the filter arithmetic unit according to this embodiment. FIG. 12A shows calculation timings of the filter calculator according to the present embodiment. FIG.12 (b) shows the calculation timing of the conventional filter calculator shown in FIG. As shown in FIG. 12 (b), the conventional filter calculator does not repeatedly perform calculations, so that it can quickly calculate from input to output at a predetermined timing. On the other hand, as shown in FIG. 12A, the filter arithmetic unit according to the present embodiment requires four times the calculation time of the conventional method because, for example, the data F00 performs four repetitive calculations. On the other hand, as described above, if the image data is a difference signal, the data gathers in the vicinity of 0. Therefore, in the first and subsequent calculations, the data in the vicinity of 0 increases. For this reason, even if the number of repetitive calculations is determined by the above-described method, the number of repetitive calculations is about 1 to 2, and the calculation processing time is not prolonged.

  Furthermore, for example, when image data is read from the SDRAM, a waiting time T occurs between the input timing of the image data and the image data due to CAS latency and RAS latency, as shown in FIG. The filter arithmetic unit according to the present embodiment may repeatedly perform calculations, but in addition to using the difference image signal, the filter arithmetic unit according to the present embodiment effectively uses such a waiting time, and does not perform repeated calculations. Compared with the filter calculator, the calculation processing time is not so long.

  In the present embodiment, since the image data has a relatively correlation between adjacent pixels, the difference between the pixels is also relatively small. Using this fact, the difference between the current data and the next data is calculated for the input image data, multiplied by the filter coefficient, and added to perform the filter operation. At this time, since the input data obtained by the difference becomes a value near 0, the number of repetitions can be drastically reduced. Also, since data from the external memory is normally transferred in bursts, data is not always input continuously. In other words, since there is a waiting time for data input, even if repetitive calculation is included, it can be performed during the waiting time.

  Therefore, the circuit scale can be greatly reduced by using a small partial product generation unit. In addition, when the difference with the previous data is small, the data can be output almost continuously, and even when the difference is exceptionally large and the number of repeated operations increases, the waiting time between data transfers is used. Therefore, the processing time is not prolonged so much. Furthermore, power consumption can be reduced by reducing the circuit scale.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the above-described embodiment, the hardware configuration has been described. However, the present invention is not limited to this, and arbitrary processing may be realized by causing a CPU (Central Processing Unit) to execute a computer program. Is possible. In this case, the computer program can be provided by being recorded on a recording medium, or can be provided by being transmitted via the Internet or another transmission medium.

It is a block diagram which shows the decoding apparatus which decodes the compressed image encoded based on H.264. It is a block diagram which shows the decoding apparatus which decodes the compressed image encoded based on VC-1. It is a block diagram which shows the motion compensation (MC) part which performs the motion compensation process containing the filter calculation based on the specification of H.264 and VC-1. It is a block diagram which shows the filter arithmetic unit concerning embodiment of this invention. It is a block diagram which shows the detail of the filter arithmetic unit concerning embodiment of this invention. FIG. 3 is a block diagram illustrating a multiplier that performs multiplication according to a second order Booth algorithm. (A) is a figure explaining the bit used for code | cord | chord data generation by Booth's algorithm, (b) is a figure which shows the detail of the partial product production | generation unit of the multiplier shown in FIG. It is a figure which shows the conventional filter calculator. It is a figure which shows the amplitude distribution of the difference signal between the adjacent pixels of the horizontal direction about an image. It is a schematic diagram which shows 10-bit image data. It is a figure which shows the structure of the repetition frequency determination part in the filter arithmetic unit concerning embodiment of this invention. (A) is a figure which shows the calculation timing of the filter arithmetic unit concerning this Embodiment, (b) is a figure which shows the calculation timing of the conventional filter arithmetic unit shown in FIG. It is a figure which shows the discrete cosine transformer of patent document 1. FIG. 11 is a diagram illustrating a processor, a register circuit, and a coefficient register in the information processing apparatus described in Patent Document 2.

Explanation of symbols

1, 10 Filter operation unit 13 Subtractor 15 Number determination unit 17, 411, 421, 431, 441 Booth decoder 18, 410, 420, 430, 440 Partial product generation unit 20, 23, 30, 105, 205, 306, 308 311, 450 Adder 21, 25, 61, 454 Register 22, 301, 304, 307, 310, 313 Selector 24 Limiter circuit 41, 56 Table 51 -55 Judgment unit 62 Comparator 63 Counter 64 Count determination unit 100, 200 Image decoding apparatus 101 Compressed data 102, 202 Variable length decoding unit 103, 203 Inverse quantization unit 104 Inverse Hadamard transform unit 106 Deblocking filter 107 Switching unit 108, 207 Decoded image 109, 208 Monitor 110 In-screen prediction unit 111, 209 Weighting Prediction unit 112, 210300 Compensation unit 113 predicted image 204 inverse DCT transform unit 206 loop filter 302, 303 filter operation unit 304, 305, 312 multiplier 309 line memory 401 partial product generation unit 412, 422, 432, 442 multiplier 413, 423, 433, 443 bit shift section

Claims (8)

A filter arithmetic unit that performs a product-sum operation on input data and filter coefficients using a Booth algorithm,
A subtractor that calculates the difference between the current data and the previous data;
A partial product multiplier for multiplying the subtraction result from the subtracter by the filter coefficient;
A number-of-times determining unit that determines the number of iterations in the partial product multiplying unit based on the subtraction result;
A filter arithmetic unit comprising: a cumulative adder that adds a cumulative result up to the previous data and a multiplication result of the current data. 2. The filter arithmetic unit according to claim 1, wherein the number determination unit searches a position where the bit value is changed from the upper bits of the subtraction result, and determines the number of multiplications based on the search result. The number-of-times deciding unit searches for a position where the value of the bit is changed for all the bits from the lower bit to the upper bit of the subtraction result, and decides the number of multiplications based on the search result. The filter arithmetic unit according to 1. The number determination unit divides the subtraction result into 2 bits from the lower order to form groups of 3 bits in total, each set and the most significant bit of the lower set, and whether or not the values of all bits are the same for each group. The filter arithmetic unit according to claim 1, wherein the number of multiplications is determined based on the determination result. The number-of-times determination unit divides the subtraction result into two bits from the lower order, and groups each set and the most significant bit of the lower group into a total of 3 bits, and all the bits from the lower bit to the upper bit of the subtraction result 2. The filter arithmetic unit according to claim 1, wherein a search is performed as to whether or not there is a change in a bit value in each group, and the number of multiplications is determined based on the search result. The number determination unit, together with the number of multiplications, divides the subtraction result into 2 bits from the lower order, and when each group and the most significant bit of the lower set are grouped in groups of 3 bits, 3 bits constituting the group 6. The filter arithmetic unit according to claim 1, wherein order information indicating the number of groups from the lower order of groups whose values are not the same is output. The partial product multiplication unit includes a data selection unit to which the number of multiplications is input, a partial product generation unit that calculates a partial product based on the data selected by the data selection unit, and a portion generated by the partial product generation unit The filter arithmetic unit according to claim 1, further comprising: a bit shift unit that shifts a product by a predetermined bit. A motion compensation processing device for generating a predicted image,
A first filter operation unit that performs a filter operation on vertical input data;
A second filter operation unit that performs a filter operation according to horizontal input data;
A weighting calculation unit that performs weighting on calculation results of the first and second filter calculation units or input data input to the first and second filter calculations;
The first and second filter arithmetic units are filter arithmetic units that perform a product-sum operation on input data and filter coefficients using a Booth algorithm,
A subtractor that calculates the difference between the current data and the previous data;
A partial product multiplier for multiplying the subtraction result from the subtracter by the filter coefficient;
A number-of-times determining unit that determines the number of iterations in the partial product multiplying unit based on the subtraction result;
A motion compensation processing apparatus comprising: a cumulative adder that adds a cumulative result up to the previous data and a multiplication result of the current data.

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