JP4958407B2 - Organic EL drive circuit and organic EL display device - Google Patents

Description

  The present invention relates to an organic EL drive circuit and an organic EL display device. More specifically, the consumption of an organic EL circuit is reduced by reducing the power consumption of a reset circuit that performs constant voltage reset on a capacitor of a pixel circuit in an active matrix organic EL display panel. The present invention relates to an improvement in an organic EL driving circuit that can reduce power and can reset a capacitor of a pixel circuit in a short time.

A drive circuit for a passive matrix type organic EL element that drives an organic EL element arranged in a matrix and resets the anode and cathode of the organic EL element to the ground is described in Japanese Patent Laid-Open No. 9-232074 Already known.
On the other hand, in a liquid crystal display device, a drive circuit is known in which a D / A for converting a digital signal into an analog signal is provided and a data line is driven by this D / A. When this is applied to a pixel circuit in an active matrix type organic EL display panel and built in the display panel, there is a problem that it is difficult to reduce the size, and this point is described in Japanese Patent Laid-Open No. 2000-276108. .
Japanese Patent Application Laid-Open No. 9-232074 JP 2000-276108 A

However, if an organic EL driving circuit for driving this active matrix type organic EL display panel is provided as an external circuit of the display panel, the organic EL display panel can be reduced in size accordingly. In this case, the drive current value is normally written by charging a capacitor of a pixel circuit of several hundred pF with a current of about 0.1 μA to 10 μA. However, when controlling the display luminance of the active matrix type organic EL display panel in gradation, a highly accurate current value is required such that the minimum drive current is about 1 nA to 30 nA. There are two types of current directions, a sink type and a source type, and the power supply voltage + Vcc is about 10V to 20V at present in both the active matrix type organic EL display panel and the passive matrix type organic EL panel.
In the current sink type, it is necessary to configure the D / A with a relatively high withstand voltage element because the voltage for resetting the capacitor of the pixel circuit is at or near the power supply voltage + Vcc. Therefore, the occupied area of each element becomes large, and there is a problem that the occupied area in the IC of the entire D / A provided corresponding to the terminal pin or the column pin of the organic EL display panel increases.

In addition, since the light emission period is desired to be as long as possible in order to ensure light emission luminance, the reset period corresponding to the blanking period of horizontal scanning is shortened. Therefore, the reset circuit is required to be reset at high speed. In addition, the reset circuit must simultaneously reset the capacitors of one horizontal display line corresponding to the horizontal scanning direction or a number of pixel circuits. The latter is a case where a plurality of column drivers handle one horizontal display line, and a large number of pixels corresponding to the number of terminal pins (the number of terminal pins for each of R, G, and B in the case of color display). The circuit capacitors are reset simultaneously. Thus, such a reset circuit requires a large drive current.
When trying to operate such a reset circuit during the reset period, it takes time to enter the reset operation, and there is a problem that the entire reset period is extended. In order to avoid this problem, the reset circuit is set in an operating state during a display period other than the reset period. As a result, there is a drawback that the power consumption of the reset circuit increases as the number of capacitors and organic EL elements of the pixel circuit that must be reset simultaneously increases.
An object of the present invention is to solve such problems of the prior art, and to reduce the power consumption of the organic EL circuit by reducing the power consumption of the reset circuit in the organic EL drive circuit, and An object of the present invention is to provide an organic EL driving circuit or an organic EL display device capable of resetting a capacitor of an organic EL element or a pixel circuit in a short time.

In order to achieve such an object, the structure of the organic EL drive circuit or organic EL display device of the present invention includes a display period corresponding to a scanning period of one horizontal line and a reset between this display period and the next display period. In an organic EL driving circuit for performing constant voltage resetting of an organic EL element or a capacitor of a pixel circuit via a terminal pin of an organic EL panel in a reset period in a timing control signal having a predetermined frequency for dividing the period,
An amplifier circuit for generating a predetermined constant voltage for the constant voltage reset;
Of the timing control signal provided between the output terminal of the amplifier circuit and the terminal pin, the timing control signal similar to the timing control signal and other pulses generated in the reset period in synchronization with the signal a reset switch for oN / OFF receiving any of the signals, the operating current of the amplifying circuit to the display period receiving said one signal and the current value of the idling state, the reset period or the other pulse, And an operating current switching circuit that sets the operating current to a current value in a steady operation state that is required when the reset operation is performed.
Further, the operating current switching circuit has a constant current circuit for flowing the operating current, and the current value of the constant current circuit is changed from the current value in the idling state according to any one of the signals to the steady operation. The constant current circuit includes a current mirror circuit having a plurality of output-side transistors serving as operating current sources of the amplifier circuit, and at least one of the plurality of output-side transistors. A switching circuit provided corresponding to one of the switching circuits, and the switching circuit is turned on / off in response to one of the signals so that the operating current value of the amplifier circuit is the current value in the idling state. It can be switched to any one of the current values in the steady operation state.

The present invention provides an amplifier circuit that generates a predetermined constant voltage for resetting a constant voltage, and the operating current switching circuit sets the operating current of the amplifier circuit to an idling state current value during the display period, and resets During the period, the current value required for the reset operation (hereinafter, the current value in the steady operation state) is switched. As a result, the amplifying circuit requires a short rise time to enter the steady operation state from the idling state, and can generate a constant voltage for resetting the constant voltage early in the initial period of the reset period.
As a result, according to the present invention, when a plurality of column drivers handle a constant voltage reset or one horizontal display line for one horizontal line, the number of terminal pins handled by itself (each column driver) (R, G for color display) , The number of terminal pins for each B), constant voltage reset for a large number of organic EL elements or capacitors of a large number of pixel circuits can be performed simultaneously and at high speed. Since only an idling current flows through the amplifier circuit during the display period, the power consumption of the reset circuit can be suppressed and the power consumption of the organic EL circuit can be reduced.

FIG. 1 is a block diagram of an organic EL driving circuit in an active matrix type organic EL panel to which an organic EL driving circuit of the present invention is applied, and FIG. 2 is a constant voltage reset timing chart.
In FIG. 1, 10 is an active matrix type organic EL panel, and 1 is an organic EL drive circuit integrated as a single driver IC, which is a current provided for the data line of the organic EL panel. Drive circuits 1a,..., 1i,. Reference numeral 2 denotes a transistor cell circuit constituting the D / A 11.
3 is a pixel circuit (display cell) provided in a matrix on the organic EL panel 10, 4 is an organic EL element (OEL element) provided in the pixel circuit 3, 5 is a write control circuit, 6a ,..., 6n are output terminals of the current drive circuits 1a,..., 1i, ..., 1n, 7 is a low-side scanning circuit, and 7a is a switch circuit of the low-side scanning circuit 7, respectively. Reference numeral 8 denotes a display data register for storing display data, which is provided corresponding to each of the current drive circuits 1a,..., 1i,. Reference numeral 9 denotes a voltage data register. Reference numeral 20 denotes a control circuit provided outside the IC of the organic EL drive circuit 1 , and 21 denotes an MPU similarly provided outside the IC of the organic EL drive circuit 1 .
The current drive circuits 1a,..., 1i,..., 1n built in the IC of the organic EL drive circuit 1 have the same circuit configuration, and each current drive circuit 1i (i = 1 to n) A 11, a constant current source 12 that generates a reference drive current Ir, and a reset switch 13. In the IC of the organic EL drive circuit 1, one reset voltage generation circuit 14 is provided as a circuit common to the current drive circuits 1a,..., 1i,.
The constant voltage reset circuit here includes a reset voltage generation circuit 14, each reset switch 13, and a precharge pulse PR output from the control circuit 20. The reset switch 13 of each of the current drive circuits 1a,..., 1i,. Thereby, each transistor which comprises D / A11 can be made into a transistor with a low pressure | voltage resistance.
In the following description, the current driving circuit 1a will be described, and the description of the other current driving circuits will be omitted because they are the same.

The D / A 11 includes a current mirror circuit including an input side transistor cell circuit TNa and output side transistor cell circuits TNb to TNn.
In each transistor cell circuit TNa to TNn, three N-channel transistors each having a drain terminal D, gate terminals G1, G2, an input terminal Din, and a source terminal S are serially connected in a vertical direction between a power supply line and a ground line. The transistor cell circuits 2 are connected to each other. Of the three transistor cell circuits 2, the transistor on the ground GND side is a switch circuit as shown in the figure.
The source terminals S of the respective transistor cell circuits 2 are commonly connected to the ground GND. The input terminal Din of the transistor cell circuit TNa is connected to the bias line Va and is turned on. The input terminals Din of the transistor cell circuits TNb to TNn are connected to the display data D0 to the display data D0 to the display data registers 8 corresponding to the current drive circuits 1a,..., 1i,. Each receives Dn-1. The switch circuits SW of the transistor cell circuits TNb to TNn are turned on / off according to the display data D0 to Dn-1. The display data D0 to Dn-1 are set from the MPU 21 to the display data registers 8 in accordance with the latch pulse LP of the control circuit 20, respectively.

The gate terminals G1 and G2 of the transistor cell circuits TNa to TNn are connected in common, and the drain D and the gate terminal G2 of the cell circuit 2 of the transistor cell circuit TNa are connected to the input terminal 11a of the D / A11. Yes. As a result, the middle transistor of the cell circuit 2 of the transistor cell circuit TNa is diode-connected, and this transistor becomes the input side transistor of the current mirror circuit and is driven by receiving the drive current Ir from the constant current source 12.
The constant current source 12 is connected to the bias line Vb and corresponds to the output current source of the reference current distribution circuit. The reference current distribution circuit is provided in parallel to correspond to the output terminals 6a,..., 6i,..., 6n of the organic EL drive circuit (column driver) 1 when the input side transistor constituted by a current mirror circuit receives the reference current. A reference current is generated as a mirror current for a large number of output side transistors. Thereby, the reference current or the reference drive current is distributed corresponding to the column pin (output terminal pin) of the organic EL panel.

The drain terminals D of the transistor cell circuits TNb to TNn are connected to the output terminal 11b of the D / A 11 respectively. The output terminal 11b is connected to an output terminal 6a connected to a column pin of the organic EL panel, and the output terminal 6a is connected to an output terminal 140 of the constant voltage reset circuit 14 via a reset switch 13.
The reset voltage generation circuit 14 is in the idling state during the display period D of the reset control pulse RS shown in FIG. 2A, and returns from the idling state to the operating state in the reset period RT to reset the constant voltage. The voltage VRS is generated. As a result, the reset voltage generation circuit 14 simultaneously resets the capacitors of the organic EL driving circuit (column driver) 1 at 6a,..., 6i,. When the reset period RT ends and the next display period D starts, the idling state is restored. Note that the reset control pulse RS here corresponds to a timing control signal having a predetermined frequency that separates a display period corresponding to a scanning period of one horizontal line and a reset period corresponding to a blanking period of horizontal scanning. The timing control signal itself may be used. In the passive matrix type, the timing control signal is the reset control pulse RS, and therefore, this will be described using the reset control pulse RS instead of the timing control signal.
The reset voltage generation circuit 14 includes an operational amplifier (OP) 141 as an amplifier circuit, an operating current switching circuit 142 that switches the operating current of the OP 141, a D / A conversion circuit (D / A) 143, and a constant current source 144. It is configured.

OP141 is a non-inverting amplifier that operates by receiving power supply from the power supply line + Vcc, and receives the output voltage of D / A1b at the (+) input and amplifies it with a predetermined amplification factor to reset the constant voltage. Is output to the output terminal 140. The voltage of the power supply line + Vcc is about 5V to 20V, and the predetermined voltage VRS at this time is a voltage lower by several V than the voltage of the power supply line + Vcc. Moreover, as shown in the figure, the OP 141 has a series circuit of a reference resistor and a feedback resistor connected to the power supply line + Vcc, and its operation reference potential is not the ground potential but the power supply line + Vcc.
The D / A 143 receives data set from the MPU 21 in the data register 9 in response to the latch pulse LP, D / A converts it, and generates an output voltage applied to the (+) input. As a result, the OP1a generates the output voltage VRS necessary for resetting, and the output voltage VRS can be adjusted in a programmable manner here. The MPU 21 sets data for resetting in the data register 9 when the power is turned on. This data is stored in a nonvolatile memory inside the MPU 21. In addition, when the reset period RT (FIG. 2A) of the reset control pulse RS is entered, the cathode side of the OEL element to be subjected to constant voltage reset is connected to the ground GND in accordance with the scanning of the low-side scanning line. The

The operating current switching circuit 142 receives the constant current i corresponding to the idling current value i from the constant current source 144 and the input side transistor TN1 of the current mirror generates the operating current of OP141. The current generated by the operating current switching circuit 142 is an idling state current value i generated in the output side transistor TN2 of the current mirror and a current value N × i in the steady state state generated in the output side transistor TN3 of the current mirror. There are two. In response to a precharge pulse PR (corresponding to a reset pulse) generated in synchronization with the rise of the reset control pulse RS (see FIG. 2A), the operating current of the OP 141 is changed from the current value i in the idling state to the state of the steady operation. The operating current value is switched to the current value N × i or in reverse to the falling of the current value. That is, except for the period when the precharge pulse PR is “H” (high level, HIGH level), the operating current of OP 141 becomes the idling state current value i, and the reset voltage generation circuit 14 enters the idling state.
In the driving of the active matrix type organic EL panel, the precharge pulse PR rises at the same time as the reset control pulse RS as shown in FIG. is there. In the reset period RT, a write start pulse (or write pulse) WR (see FIG. 2 (d)) for writing a drive current value into the capacitor C of the pixel circuit 3 is thereafter generated and the write start pulse WR is written. Is written as the voltage value of the capacitor, and at the end of this, the reset period RT ends.

By the way, in the passive type organic EL panel, since it is not necessary to write the drive current value, the reset control pulse RS is used as the reset pulse. Therefore, the reset switch 13 is normally turned ON during the reset period RT in response to the reset control pulse RS, and resets each output terminal via a large number of OEL elements. During the reset period RT, the reset voltage generation circuit 14 operates by flowing a current value N × i in a steady operation state, and during the display period D, the current value i in an idling state flows and enters an idling state.
The operating current switching circuit 142 described above includes a current mirror circuit 145 and an analog switch 146. The current mirror circuit 145 includes an N-channel input side transistor TN1 and output side transistors TN2 and TN3, and serves as an operating current source for OP141. Moreover, the current mirror circuit 145 is a constant current circuit when the input side transistor TN1 receives a constant current from the constant current source 144. The source of each transistor of the current mirror circuit 145 is grounded, and the transistor TN1 is diode-connected and its drain is driven by receiving a current having a current value i from the constant current source 144.
The drain of the output side transistor TN2 is connected to the output terminal 147 of the operating current switching circuit 142, and the drain of the output side transistor TN3 is connected to the current outflow terminal 147 of the operating current of the OP141 of the operating current switching circuit 142 via the analog switch 146. It is connected to the. The current outflow terminal 147 is a terminal that discharges the operating current (ground current) of the OP 141 to the ground.

The analog switch 146 is turned on when it receives the precharge pulse PR from the control circuit 20 and changes from “L” to “H”, and is turned on during the “H” period, and the precharge pulse PR is set to “H”. When it goes from "L" (low level, LOW level) to OFF. Therefore, the writing period and the display period D in the reset period RT are OFF.
The input side transistor TN1 and the output side transistor TN2 have a channel width ratio (gate width ratio) of 1: 1, and the input side transistor TN1 and the output side transistor TN3 have a channel width ratio (gate width ratio) of 1: N. However, N is an integer of 2 or more. Accordingly, the operating current ratio (strictly speaking, the operating current density ratio) between the input side transistor TN1 and the output side transistor TN3 is 1: N. Note that N in this case may be realized by connecting N cell transistors in parallel.
As a result, in the display period D in which the analog switch 146 is OFF, the operating current of OP141 becomes the current value i, and OP141 is in the idling state. During the reset period RT in which the analog switch 146 is ON (at least in the precharge period), the operating current of OP141 is (N + 1) × i, and (N + 1) times as much current as the idling current i is pre-charged. During the period of the charge pulse PR “H”, it flows as an operation current value (N + 1) × i in a steady operation state.

The above is an example in which the reset voltage generation circuit 14 receives the constant current i corresponding to the idling current value i from the constant current source 144 and operates. However, the current value of the constant current source 144 may be an operating current value N × i in a steady operation state. In this case, the channel width ratio (gate width ratio) between the input side transistor TN1 and the output side transistor TN3 is 1: 1, and the channel width ratio (gate width ratio) between the input side transistor TN1 and the output side transistor TN2 is 1: 1 / N. In this case, the current value in the steady operation state is N × i + i / N.
As a result, during the display period D, the OP 141 operates only with the idling current, so that the power consumption of the OP 141 is reduced and the operation state can be immediately entered when the reset period RT is entered.
In FIG. 1, the reset switch 13 for transmitting the output voltage VRS to the output terminal 6a receives the precharge pulse PR from the control circuit 20 in synchronism with the analog switch 146, and turns on when it changes from "L" to "H". During the “H” period (even during the reset period RT upon receiving the reset control pulse RS), it is turned ON. When the precharge pulse PR changes from “H” to “L”, the precharge pulse PR is turned off, and the display period D is turned off.
In this way, at the end of the scan for one horizontal line (display period D) of the low-side scan in the idling state, the OP 141 shifts from the idling state to the steady operation state and enters the reset period RT. A rising operation can be performed. Since the OP 141 is in the idling state during the display period D, only the idling current i is required, and the power consumption is reduced accordingly.

FIG. 2 is a constant voltage reset timing chart.
2A shows a reset control pulse RS (timing control signal) output from the control circuit 20, and FIG. 2B shows a light emission period of the OEL element 4 determined according to the reset control pulse RS. . FIG. 2C shows the precharge pulse PR output from the control circuit 20 . Since the reset control pulse RS is input to the write control circuit 5 (see the input signals RS, WR, etc. of the write control circuit 5 in FIG. 1), the write control is performed at the end of driving of the transistors TP3, TP4. At the timing when the scanning line Y2 is driven to "H" by the circuit 5, the scanning line Y1 (writing line) is driven to become the LOW level (described later), and during the precharge period for constant voltage resetting. Precharging is performed at least with the scanning line Y1 remaining at the LOW level. Then, a write start pulse WR Figure 2 (d) is outputted from the control circuit 20 after the end of the constant voltage reset by the precharge pulse PR to the write control circuit 5. In response to the write start pulse WR, the write control circuit 5 sets the scanning line Y1 to the LOW level (hereinafter referred to as “L”) (described later). FIG. 2E shows a drive current (sink output current) of the D / A 11.

Returning to D / A 11 in FIG. 1, the gate terminal G 1 connected in common to the transistor cell circuits TNa to TNn is connected to the constant voltage bias circuit 15. With the gate voltage VG set by the constant voltage bias circuit 15, the transistor on the upstream side of the cell circuit 2 is set to the ON state with a predetermined resistance value. Thereby, the voltage of the drain terminal D of each transistor cell circuit TNa-TNn can be set to a substantially equal value, and D / A conversion accuracy can be improved.
As a result, in the organic EL drive circuit (column driver) 1, variations in D / A conversion characteristics are reduced, and variations in output current between column pins (or data line terminals) are reduced. As a result, luminance unevenness and luminance variation of the display screen can be suppressed.
By the way, the numbers x1, x2, x4... Corresponding to each transistor cell circuit indicate the number of transistor cell circuits 2 connected in parallel. In the case of × 1, there is no parallel connection. Depending on the number of cell circuits, the output side transistor cell circuits TNb to TNn have digit weights attached to their outputs.

Reference numeral 3 denotes a pixel circuit (display cell) which is provided corresponding to a display pixel of the organic EL panel and is connected to the output terminal 6a via the data line X and the connection terminal 3a. The output terminal 11b of A11 and the output terminal 140 of the reset voltage generation circuit 14 are connected through the reset switch 13, respectively. The pixel circuit 3 is provided corresponding to the intersection of X and Y matrix wirings (data lines X, scanning lines Y1, Y2,...). In the pixel circuit 3, P-channel MOS transistors TP1 and TP2 having drains and gates connected to the intersections of the data lines X and the scanning lines Y are arranged. The OEL element 4 is driven by drive transistors TP3 and TP4 of P channel MOS provided in the pixel circuit 3. A capacitor C is connected between the source and gate of the transistor TP3.
The source of the transistor TP1 is connected to the gate of the transistor TP3, and the source of the transistor TP2 is connected to the drain of the transistor TP3. When the transistors TP1 and TP2 are turned on in response to the write start pulse WR, the gate and drain of the transistor TP3 are diode-connected, and the drive current (sink current) output from the D / A 11 is passed to the transistor TP3. A voltage value corresponding to the drive current is stored in the capacitor C with high accuracy.

The source of the transistor TP3 is connected to the power supply line + Vcc, and its drain side is connected to the anode of the OEL element 4 via the source-drain of the transistor TP4.
When entering the reset period RT, the cathode of the OEL element 4 to be subjected to the low side scanning is connected to the switch circuit 7a of the low side scanning circuit 7, and is connected to the ground GND through the switch circuit 7a.
The gates of the transistors TP1 and TP2 are connected to the write control circuit 5 through the scan line Y1 (write line), and the scan is performed by the write control circuit 5 in response to the write start pulse WR in FIG. Then, when the scanning line Y1 becomes "L", the transistors TP1 and TP2 are turned on. As a result, a predetermined driving current sinked by the D / A 11 flows from the power supply line + Vcc through the transistor TP3, the capacitor C, the transistors TP1, TP2, the data line X, the terminal 3a, and the output terminal 6a. The corresponding voltage value is written and stored. Then, the scanning line Y1 becomes HIGH level (hereinafter "H"), and the transistors TP1 and TP2 are turned OFF.

The gate of the transistor TP4 is connected to the write control circuit 5 through the scanning line Y2, and is scanned by the write control circuit 5 so that the scanning line Y2 (drive line) becomes "L", so that the transistor T4 Is turned on. In response to the fall of the write start pulse WR, the transistors TP3 and TP4 are maintained in the ON state, and a drive current is supplied to the anode of the OEL element 4. This scanning line Y2 corresponds to the pulse signal shown in FIG. 2 (b) which becomes "H" corresponding to the light emission period D.
At this time, the scanning line Y1 is "H", and the transistors TP1 and TP2 are OFF.
At the end of driving of the transistors TP3 and TP4, the scanning line Y2 becomes “H”, the transistor TP4 is turned OFF, and at that timing, the scanning line Y1 becomes “L”. The output terminal 140 is set to the output voltage VRS of the reset voltage generation circuit 14 by the reset switch 13 which is turned on by the charge pulse PR, and the voltage of the capacitor C is reset to the output voltage VRS by the transistor TPa through the output terminal 6a. .
At this time, the reset switch 13 that is turned on by the precharge pulse PR is provided corresponding to each of the current driving circuits 2a,..., 1i,..., 1n, and each corresponds to a terminal pin of the organic EL panel 10. ing. As a result, the capacitor C to be reset becomes a capacitor for the number of terminal pins handled by itself (each column driver) when a plurality of column drivers handle a horizontal line capacitor or a horizontal display line. In the case of color display of R, G, and B, the reset voltage generation circuit 14 may be provided so that the number of terminal pins that each column driver handles corresponds to each of R, G, and B. In such a case, the number of terminals to be reset is 30 pins or more.

By the way, the switch circuit 7a is a switch that is sequentially turned on / off in response to scanning of one horizontal line on the low side, but only one of them is shown in the drawing. Such a low-side scanning circuit 7 is required in the passive matrix type organic EL driving circuit, but in the active matrix type organic EL driving circuit, the driving transistor TP4 of the pixel circuit 3 in FIG. 1 is used as the switch circuit 7a. In other words, the switch circuit 7a can be deleted. This is because a drive transistor TP4 is provided in series upstream (or downstream) of the OEL element 4, and this transistor TP4 is turned on in the display period D and turned off in the reset period RT, and the switch circuit 7a. This is because the same operation is performed.
Although not shown in FIG. 1, the switch circuit SW of the cell 1 of the input side transistor cell circuit TNa of the D / A 11 can be turned off during a reset period in which the voltage of the capacitor C is reset. This can be done by adding an inverted signal of the reset control pulse RS to the input terminal Din of the bias line Va in the transistor cell circuit TNa to make it “L”. When the switch circuit SW is turned off, the transistor cell circuits TNb to TNn are also turned off. As a result, when the reset switch 13 is turned on by the reset control pulse RS, the current flowing through each of the transistor cell circuits TNa to TNn of the D / A 11 can be blocked to reduce current consumption.

As described above, in the embodiment, the switching from the idling state to the steady operation state is performed at the timing when the reset period RT starts. However, in consideration of the rising operation of the reset voltage generation circuit 14, the reset period RT It goes without saying that it may be performed at a timing just before the start. In this way, the reset voltage generation circuit 14 is surely in a steady operation state when the reset period RT starts.
In the embodiment, when the reset control pulse RS becomes “H”, the operational amplifier shifts from the idling state to the steady operation state, but when the reset control pulse RS is “L”, the reset period RT is entered. , When it becomes “L”, it shifts from the idling state to the steady operation state. “H” and “L” of the reset control pulse RS are logic signals indicating operation timing, and are not conditions for switching from the idling state to the steady operation state. The switching may be performed at the time of entering the reset period RT or before that time.

In the embodiment, an example of resetting the capacitor of the pixel circuit in the active matrix type organic EL display panel is described. However, the present invention resets the terminal voltage of the OEL element of the passive matrix type organic EL display panel at a constant voltage. It can also be applied to cases. In this case, the reset voltage generation circuit 14 generates a constant voltage, for example, several V higher than the ground GND.
Further, in the embodiment, a voltage for resetting a constant voltage is generated using OP having a predetermined amplification factor, but OP may be a general amplifier, and an amplifier such as a voltage follower having an amplification factor of 1 is used. Also good.
In the embodiment, D / A is used as the output stage current source. However, in the present invention, a current source such as a current mirror circuit may be further provided as the output stage. In this case, it is possible to drive the output stage current source with a D / A output current. In such a case, the pixel circuit or the OEL element is driven by the discharge current from the output stage current source.
Further, in the embodiment, a circuit mainly composed of N-channel MOS transistors is shown, but the present invention may be a P-channel MOS transistor or a circuit combining this and an N-channel MOS transistor. is there.
In the embodiment, a MOS transistor is used. However, in the present invention, it is needless to say that a bipolar transistor may be used instead of the MOS transistor.

FIG. 1 is a block diagram of an organic EL driving circuit in an active matrix organic EL panel according to an embodiment to which the organic EL driving circuit of the present invention is applied. FIG. 2 is a constant voltage reset timing chart.

Explanation of symbols

1 ... transistor cell circuit,
2 ... organic EL drive circuit, 3 ... pixel circuit (display cell),
4 ... Organic EL element (OEL element), 5 ... Write control circuit,
6, 11b ... output terminal, 7 ... low side scanning circuit,
7a ... switch circuit, 8 ... display data register,
9: Voltage data register,
10 ... Active matrix organic EL panel,
11, 143 ... D / A conversion circuit (D / A),
11a ... input terminal, 12, 144 ... constant current source,
13 ... Reset switch, 14 ... Reset voltage generation circuit,
15 ... Constant voltage bias circuit, 20 ... Control circuit,
21 ... MPU, 141 ... OP,
142 ... operating current switching circuit,
Q1-Q3 ... MOS transistors,
Tr1 to Tr7 ... MOS transistors,
TNa to TNn-1: MOS transistor.

Claims (12)

Via the terminal pin of the organic EL panel in the reset period in the timing control signal of a predetermined frequency that separates the display period corresponding to the scanning period of one horizontal line and the reset period between this display period and the next display period. In an organic EL drive circuit that resets a constant voltage of a capacitor of an organic EL element or pixel circuit,
An amplifier circuit for generating a predetermined constant voltage for the constant voltage reset;
A reset provided between an output terminal of the amplifier circuit and the terminal pin, which is turned on / off in response to any one of the timing control signal and other pulses generated in the reset period in synchronization with the signal. A switch,
In response to any of the signals, the operating current of the amplifier circuit is set to the idling state during the display period, and the operating current is reset during the reset period or the period when the other pulse is generated. and a operating current switching circuit for the current value of the state of steady operation which is required when,
The operating current switching circuit has a constant current circuit for flowing the operating current, and the current value of the constant current circuit is changed from a current value in the idling state to a state in the steady operation state according to any one of the signals. Switch to current value or vice versa,
The constant current circuit includes a current mirror circuit having a plurality of output side transistors serving as operating current sources of the amplifier circuit, and a switch circuit provided corresponding to at least one of the plurality of output side transistors. When the switch circuit is turned on / off in response to any one of the signals, the operating current value of the amplifier circuit is switched to either the current value in the idling state or the current value in the steady operation state. Organic EL drive circuit. Wherein any of the signals are low level, high level, changes to a low level, or a signal that changes its inverse to a high level, low level, high level, the operating current switching circuit, the high level of the one of the signal The current value in the idling state and the current value in the steady operation state are selected at the timing of the change from the low level to the low level or the timing before this change, and the low level of any one of the signals is changed to the high level. 2. The organic EL drive circuit according to claim 1 , wherein one of the other is selected at the timing of the change to the level or the timing before the change. The organic EL panel has a large number of the terminal pins, the amplifier circuit is an operational amplifier whose operating current is determined by the current value of the constant current circuit, and the reset switch is the large number of the terminals 3. The organic EL drive circuit according to claim 2, wherein the organic EL drive circuit is provided corresponding to each of at least a plurality of pins, and the plurality of reset switches are simultaneously turned on. The reset switch is an organic EL driving circuit according to claim 3, wherein is provided et respectively between the output terminal and each said terminal pin. Any one of the signals is a precharge pulse, and one of the plurality of output side transistors is 1: N (where N is 1 or more) than the input side transistor of the current mirror circuit. 5. The organic EL drive circuit according to claim 4 , wherein the switch circuit is connected in series to the one output side transistor and is turned on together with the reset switch in response to the precharge pulse. The first and second D / A conversion circuits further include a reset voltage generation circuit including the first D / A conversion circuit, the operational amplifier, and the operating current switching circuit. The voltage converted by the first D / A conversion circuit is received as an input voltage, and the reset voltage generation circuit generates the predetermined constant voltage as a reset voltage for resetting the capacitor of the organic EL element or the pixel circuit. The second D / A conversion circuit is connected to the terminal pin, receives display data, performs D / A conversion on the display data, and outputs a drive current to the capacitor of the organic EL element or the pixel circuit. 5. The organic EL drive circuit according to 5. One of the signals is a precharge pulse, and one of the plurality of output side transistors is 1: 1 / N with respect to the input side transistor of the current mirror circuit (where N is 1 or more) The other one has a 1: 1 operation current ratio with respect to the input side transistor, and the switch circuit is connected in series to the other one output side transistor. 5. The organic EL drive circuit according to claim 4 , wherein the organic EL drive circuit is turned on together with the reset switch in response to the precharge pulse. The organic EL drive circuit according to claim 6 , wherein the organic EL panel is an active matrix type, and the reset voltage generation circuit resets a voltage of a capacitor of the pixel circuit. The organic EL driving circuit according to claim 6 , wherein the organic EL panel is a passive matrix type, and the reset voltage generation circuit resets a terminal voltage of the organic EL element. Via the terminal pin of the organic EL panel in the reset period in the timing control signal of a predetermined frequency that separates the display period corresponding to the scanning period of one horizontal line and the reset period between this display period and the next display period. In an organic EL display device having an organic EL drive circuit for resetting a constant voltage of a capacitor of an organic EL element or a pixel circuit,
The organic EL drive circuit is provided between an amplifier circuit that generates a predetermined constant voltage for resetting the constant voltage, and an output terminal of the amplifier circuit and the terminal pin, and is synchronized with the timing control signal. A reset switch that is turned ON / OFF in response to any of the other pulses generated during the reset period;
In response to any of the signals, the operating current of the amplifier circuit is set to the idling state during the display period, and the operating current is reset during the reset period or the period when the other pulse is generated. e Bei the operating current switching circuit for the current value of the state of steady operation which is required when,
The operating current switching circuit has a constant current circuit for flowing the operating current, and the current value of the constant current circuit is changed from a current value in the idling state to a state in the steady operation state according to any one of the signals. Switch to current value or vice versa,
The constant current circuit includes a current mirror circuit having a plurality of output side transistors serving as operating current sources of the amplifier circuit, and a switch circuit provided corresponding to at least one of the plurality of output side transistors. When the switch circuit is turned on / off in response to any one of the signals, the operating current value of the amplifier circuit is switched to either the current value in the idling state or the current value in the steady operation state. Organic EL display device. Wherein any of the signals are low level, high level, changes to a low level, or a signal that changes its inverse to a high level, low level, high level, the operating current switching circuit, the high level of the one of the signal The current value in the idling state and the current value in the steady operation state are selected at the timing of the change from the low level to the low level or the timing before this change, and the low level of any one of the signals is changed to the high level. The organic EL display device according to claim 10 , wherein one of the other is selected at a timing of changing to a level or a timing before this change. The organic EL panel has a large number of the terminal pins, the amplifier circuit is an operational amplifier whose operating current is determined by the current value of the constant current circuit, and the reset switch is the large number of the terminals 12. The organic EL display device according to claim 11, wherein the organic EL display device is provided corresponding to each of at least a plurality of pins, and the plurality of reset switches are simultaneously turned on.

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