JP4956827B2 - 8-bit based data processing system - Google Patents

Description

  The present invention provides data processing for connecting a computer device (host / server, etc.) that processes data of 8 bits or more and a peripheral device (client / terminal, etc.) that processes data of 8 bits or more via an 8-bit bus. About the system.

  Personal computers (hereinafter abbreviated as PCs) are widely used worldwide and have been widely used in university laboratories. The evolution of the operating system (hereinafter abbreviated as OS) mounted on the PC is remarkable, and it started with 8-bit OS (CP / M) in the old days and supported 32 bits or more through 16-bit MS-DOS (registered trademark). OS is widely used. Windows (registered trademark), MacOS (registered trademark), UNIX (registered trademark), Linux (registered trademark), and the like are known as OSs corresponding to 32 bits or more.

  However, as the OS evolves (Windows 95, 98, Me, Win2000, etc., taking Windows as an example), old peripheral devices (clients / terminals) connected to PCs (hosts / servers) will become new OSs. Without the corresponding dedicated driver (peripheral device control program), it would stop working. As a result, legacy peripheral devices and software for the devices developed in the old OS era cannot be used, and the software creation method until then, which can be regarded as laboratory know-how, has been lost. In addition, input / output boards (I / O boards) for peripheral devices compatible with the new OS tend to be complicated and large in size and expensive, making it difficult to conduct experiments using a PC easily. . Due to such changes in the PC environment, the system based on the PC that has been constructed with the know-how of the laboratory is disappearing from the laboratory.

  Specific examples of the adverse effects caused by the change in the PC environment include the following. For example, assume that a PC (host) is connected to a control board (client) to be tested via a high-level bus such as PCI Express, and this control board is controlled by the PC. In this case, although the experimenter can easily create hardware after I / O of the control board, the driver who controls the hardware from the PC cannot write it unless he / she studies a lot. In other words, even if an idea is invented and an experimental device board is completed in a few days to check its operation, it may take several months (including study time) to write the driver. Even if you finally master how to write a driver for the new OS, there is a possibility that the same thing will be repeated if the next new OS appears (or if the OS to be used changes to another one).

  In other words, when the PC environment (connection environment with peripheral devices, etc.) changes due to the appearance of a new OS, even if the functions unique to the new OS are not required (when the previous OS is sufficient), Legacy peripherals can no longer be used each time. Then, software assets developed with legacy peripheral devices and their creation know-how are thrown away with legacy peripheral devices.

  Although not paying attention to the above-mentioned adverse effects, there is a known example that seems to be related (see Patent Document 1).

Registered Utility Model No. 3001008

  Patent Document 1 discloses a data conversion apparatus capable of exchanging information between a plurality of computers having different communication standards and protocols. In this data converter, the extension port 2 for inputting information and the extension port 2 for outputting information are selected by the inter-device connection instruction terminal 12. Then, information is input from the expansion port 2 of the input source, the communication standard or protocol of the input source is converted into the communication standard or protocol of the output destination using the CPU 5, ROM 6 and RAM 8, and output to the expansion port 2 of the output destination (See summary).

  In the device of Patent Document 1, even a heterogeneous computer adopting incompatible communication standards and protocols can directly exchange information. Furthermore, computers can be connected as many as the number of input / output ports, and information can be exchanged between any models as long as the installed input / output ports are compatible (paragraph). 0023). Here, various input / output ports are available (paragraph 0010).

  In the device of Patent Document 1, one of the computers connected to the inter-device connection instruction terminal 12 or the input / output port is a new OS compatible model (host), and the other computers are legacy peripheral devices (clients). Let's assume the case. In that case, by performing appropriate protocol conversion, there is a possibility that the host and the client can be connected without being spoiled due to the evolution of the OS on the host side. Even so, however, if the client connected to the host is a plurality of devices using different protocols (plural types of protocols), protocol conversion for each device is required, and the convenience of connection is lacking.

  One of the problems of the present invention is to enable connection between a host and a client regardless of environmental changes on the host side (OS changes, etc.) while maintaining the convenience of connection.

  A data processing system according to an embodiment of the present invention (tentatively referred to as simple 8) uses an external device (host / server) that uses a signal line for handling external data of 8 bits or more as internal data in units of 8 bits and N It has a configuration for connecting to one or more internal devices (client / terminal) using a bit (for example, 8 bits) internal address, and includes a conversion module and a connection unit.

  Here, the conversion module converts the external data into the internal data, or converts the internal data into the external data.

  The connection unit includes an 8-bit data signal line for handling the internal data, an N-bit (for example, 8 bits) address signal line for handling the internal address, a data read signal line, a data write signal line, and an input / output request. The conversion module is connected to one or more internal devices via a plurality of signal lines including signal lines. When a plurality of the internal devices are connected to the conversion module via the connection unit, one of the plurality of internal devices specified by the internal address (for example, a target I / O board) is converted to the conversion module. Configured to exchange information with modules.

  Here, the external device (for example, the host PC) designates one place in the N-bit space (256 spaces if 8 bits) of the internal address to the conversion module, and the data of the data is designated in the designated address space. Send and receive. An internal device (client, such as a legacy peripheral device or the latest CPU board) existing in the designated address space performs its own processing on the received data, and returns the processing result to the conversion module as appropriate. be able to.

  Here, the internal address does not specify an address in the memory of the internal device (client) but specifies which client it is.

  When the conversion module converts the external data into the internal data, the external data of 8 bits or more (for example, 32 bits) is divided into the internal data in units of 8 bits (for example, divided into 4). The divided external data is temporarily stored in one or more storage units (latch, dual port RAM, etc.) in units of 8 bits. At this time, which storage unit is used can be specified by using a part of the internal address (for example, A0 to A1 of A0 to A7).

  The conversion module appropriately uses a predetermined protocol corresponding to its communication means (USB, PCI Express, PCI-X, etc.) for communication with the external device. However, for the internal devices (clients that may include legacy devices), it is only necessary to send and receive data to the designated address space in units of 8 bits without using a complicated protocol as used in the communication means. (The conversion module performs simple operations such as designating one of simple 8 address spaces, input / output requests and read / write instructions, and sending and receiving data in units of 8 bits).

  Since 8-bit (byte) unit data can be handled by a computer device using any OS, the 8-bit unit data once taken into the conversion module from the external device is the latest peripheral device or a legacy peripheral device. But it can be handled without problems.

  According to the present invention, between the host (for example, a PC whose OS can be changed) and the client (for example, various I / O boards including legacy peripheral devices), the host side environment changes (OS changes) and the like. Can be tied.

The figure explaining an example (serial transmission between a host and a simple 8 conversion module) of the data processing system which concerns on one embodiment of this invention. The figure explaining the structural example of the simple 8 conversion module of FIG. The figure explaining the other example (parallel transmission between a host and a simple 8 conversion module) of the data processing system which concerns on one embodiment of this invention. The figure explaining the structural example of the simple 8 conversion module of FIG. FIG. 4 is a flowchart for explaining an example of processing performed on the host side in the system illustrated in FIG. 1 or FIG. 3. FIG. 4 is a flowchart for explaining an example of processing performed on the simple 8 conversion module side in the system illustrated in FIG. 1 or FIG. 3. FIG. 4 is a flowchart for explaining an example of processing performed on the client (target I / O board or the like) side in the system illustrated in FIG. 1 or FIG. 3. The figure explaining the further another example (example in which serial transmission and / or parallel transmission are performed between a host and several clients) of the data processing system which concerns on one embodiment of this invention. The figure explaining the further another example (example which provided the simple 8 conversion module inside the client) of the data processing system which concerns on one embodiment of this invention. The figure explaining the further another example (example which provided the simple 8 conversion module inside the host) of the data processing system which concerns on one embodiment of this invention. The figure explaining the example of the simple 8 bus connector used in the data processing system concerning one embodiment of this invention, and the example of the pin assignment of the connector. The timing chart figure explaining an example of read / write operation of simple 8 buses in the data processing system concerning one embodiment of this invention. An example of a processing circuit (corresponding to a part of the processing of FIG. 7) of a connection unit connected to a simple 8 bus on the client (target I / O board, etc.) side in the system exemplified in FIGS. Figure. The figure explaining an example of the simple 8 bus card used in the data processing system concerning one embodiment of this invention. The figure explaining other examples of the simple 8 bus card used in the data processing system concerning one embodiment of this invention. FIG. 16 is a diagram illustrating an example in which one or more simple 8-bus cards (clients) configured as illustrated in FIG. 14 or FIG. 15 are rack-mounted in the data processing system illustrated in FIG. 10 and the like.

Hereinafter, various embodiments of the present invention will be described with reference to the drawings.
<Simple 8 overview>
With the rapid evolution and development of PCs, PCs can be used for high-speed transfer with large file sizes. This is due to the fact that PC buses are increasing in speed and size, and 64-bit width, 32-bit address and higher performance have been realized. As the external I / O bus, a large serial high-speed bus PCI Express can be used, and the size can be as large as × 16 lanes. Transfer rate is possible). However, not only the most advanced but also a small I / O bus that is optimal for practical use is not standardized.

  The simple 8 bus 400 according to an embodiment of the present invention was considered as a parallel 8-bit address / data bus. The simple 8 bus has compatibility with Windows OS, and has a compact configuration that allows easy creation of DLL (Dynamic Link Library) application software. Moreover, it is a bus system that can convert data from any parallel bus / serial bus, and can easily convert data from a classic 16-bit PC or PCI Express of the latest PC to enable software support on the individual user side. .

  In particular, it makes sense to convert PCI Express to Simple 8. PCI Express is a key bus for future PCs with a small size of × 1 lane and small connectors and two differential data signals. However, when a user designs I / O and creates software, a large amount of work is required such as installation of an LSI (Large Scale Integrated circuit) for developing PCI (Peripheral Component Interconnect) and DLL creation. However, if PCI Express-Simple 8 conversion is performed, I / O can be easily installed and operated by a conventional method. Also, the I / O board can be designed and manufactured easily.

  FIG. 1 is a diagram for explaining an example of a data processing system (simple 8 data processing system) according to an embodiment of the present invention. In this example, the host PC 100 and the simple 8 conversion module 300S are connected by a serial transmission line 200S. For the serial transmission, for example, an existing technology such as USB 2.0 or PCI Express (abbreviated as PCI (e) as appropriate) can be used. The simple 8 conversion module 300 </ b> S is connected to a connection unit 500 having a configuration standardized for simple 8 via a simple 8 bus 400. A client (target I / O board) 600 is connected to the connection unit 500. (Or, the connection unit 500 is mounted on the client I / O board.) As the client 600, various peripheral devices or computer devices can be used. The devices that serve as hosts or clients include legacy devices that exist in the past and devices that will be developed in the future.

  FIG. 2 is a diagram illustrating a configuration example of the simple 8 conversion module 300S of FIG. The host PC 100 is connected to the serial I / F 220S of the simple 8 conversion module 300S via the serial I / F 210S and the serial transmission path 200S. In this example, an Express Card (existing technology) capable of handling USB 2.0 and PCI Express (PCI (e)) is used for the serial I / Fs 210S and 220S. With USB 2.0, a data transfer speed of only 480 Mbps (60 MB / s) can be obtained, but with PCI Express, for example, 4 GB / s can be transferred at a high speed of 4 GB / s. When data transfer may be slow, it is also possible to use a legacy low-speed serial port such as RS232C for the serial I / Fs 210S and 220S.

  Data from the serial I / F 220S is converted by the data conversion circuit 310 into 8-bit data D0 to D7. If the data from the host PC 100 is, for example, 32 bits, the 32-bit data is divided into four in units of 8 bits and sequentially transmitted to a simple 8-bus 400 having an 8-bit width. For example, 32-bit data (D0 to D31) from the host PC 100 is sequentially transmitted in units of 8 bits (D0 to D7, D8 to D15, D16 to D23, D24 to D31) by an 8-bit latch (not shown), a dual port RAM, or the like. The buffered and buffered 8-bit data is sequentially sent out to the simple 8 bus 400.

  If the data from the host PC 100 is 8 bits, it can be buffered once and sent to the simple 8 bus 400 as it is in the form of 8-bit parallel data. If the data from the host PC 100 is 16 bits, it is buffered, divided into two in units of 8 bits, and sent to the simple 8 bus 400. If the data from the host PC 100 is 32 bits, the data is divided into 4 units in units of 8 bits, and if the data is 64 bits, it is transmitted in units of 8 bits.

  When returning 8-bit unit data from the simple 8 bus 400 to the host PC 100, the reverse operation is performed. That is, when four data are sent from the simple 8 bus 400 in units of 8 bits, the data conversion circuit 310 sequentially buffers them and collects them into 8 × 4 = 32 bits (D0 to D7, D8 to D15). , D16 to D23 and D24 to D31 are sequentially written in a 32-bit register to be D0 to D31), and returned to the host PC 100 via the serial transmission path 200S.

  The number of address bits N of the simple 8 bus 400 can be determined according to the number of clients in the simple 8 address space. For example, if the maximum number of clients is 64, N is 6 bits. If the maximum number of clients is 256, N is 8 bits. If the maximum number of clients is 1024, N is 10 bits. In the following example, N = 8 and the address width is 8 bits, which is the same as the data width.

  For example, the host PC 100 designates any of the clients that can exist up to 256 by an 8-bit address. The designated address is converted into simple 8 addresses A0 to A7 via the address signal processing circuit 320 (referring to the conversion table, etc.) and sent to the simple 8 bus 400. As a result, the host PC 100 can designate a client (target I / O board) existing at an arbitrary location in the 256 address space of Simple 8.

  Further, the host PC 100 requests input / output from the designated client via the control signal processing circuit 330 and writes data to the designated client (passes data) or reads data from the designated client (data is read). Instructions). The control signal processing circuit 330 sends an input / output request signal IORL, a data write signal WDL, a data read signal RDL, and the like to the simple 8 bus 400 based on an instruction from the host PC 100.

  FIG. 3 is a diagram for explaining another example (parallel transmission between the host and the simple 8) of the data processing system according to the embodiment of the present invention. In this example, the host PC 100 and the simple 8 conversion module 300P are connected by a parallel transmission path 200P. For the parallel transmission, for example, an existing technology such as PCI or PCI-X can be used. With PCI, a data transfer rate of 533 MB / s can be obtained with the 64-bit / 66 MHz specification. With PCI-X, a data transfer rate of 1067 MB / s can be obtained with a specification of 64 bits / 133 MHz. The simple 8 conversion module 300 </ b> P is connected to a connection unit 500 having a configuration standardized for simple 8 via a simple 8 bus 400. A client (target I / O board) 600 is connected to the connection unit 500 (or the connection unit 500 is mounted on the client I / O board). As in the case of FIG. 1, various peripheral devices or computer devices can be used as the client 600. The devices that serve as hosts or clients include legacy devices that exist in the past and devices that will be developed in the future.

  FIG. 4 is a diagram illustrating a configuration example of the simple 8 conversion module 300P of FIG. The host PC 100 is connected to the parallel I / F 220P of the simple 8 conversion module 300P via the parallel I / F 210P and the parallel transmission path 200P. Here, a card (existing technology) that can handle PCI or PCI-X is used for parallel I / Fs 210P and 220P (in the following description, if either PCI or PCI-X may be used, it is represented by PCI). . The circuit functions of the data conversion circuit 310, the address signal processing circuit 320, and the control signal processing circuit 320 in FIG. 4 are the same as those in FIG. When high-speed data transfer is not required, a legacy parallel port conforming to IEEE 1284 can be used for the parallel I / Fs 210P and 220P.

  Conventionally, when making an I / O board using a PCI bus, an acquisition address necessary for I / O is determined from the PCI bus, and address / data bus timing is determined by combining various timings, which is necessary for I / O. Install LSI etc. Next, a code generation mechanism necessary for plug and play is also installed (a recent OS such as Windows supports plug and play). In addition to such hardware installation, DLLs required for plug and play and DLLs required for I / O LSIs are described. Creating a DLL and software necessary for such an API (Application Programming Interface) in a form suitable for the OS each time a PCI I / O board is created is a great effort.

  However, if the simple 8 conversion module 300P is first installed as a mechanism (adapter system) for converting data from the PCI bus 200P to the simple 8 bus 400, the above-described effort is greatly reduced. That is, the software description of the I / O board to be installed next on the simple 8 bus 400 first acquires an address (information specifying the 256 address space of simple 8) necessary for plug and play, You only need to write application software to use. Therefore, if Simple 8 is used, the addition of an I / O board (client) becomes extremely easy in terms of creating software.

  From the viewpoint of hardware, the I / O board only needs to have a decoder for Simple 8 (see FIG. 13). The required number of gates for the decoder is small, and the shape can be reduced.

  FIG. 5 is a flowchart illustrating an example of processing performed on the host PC 100 side in the system illustrated in FIG. 1 or FIG. First, the host PC 100 is connected to the simple 8 conversion module 300 (300S or 300P) by a predetermined communication method (USB, PCI Express, PCI, PCI-X, etc.) so that information can be transmitted and received between the two. (ST10). The software of the host PC 100 (such as an application written in Basic) can be automatically recognized by the client 600 to be used (CPU board connected to the target I / O, etc.) by plug and play. 1 or more of the simple 8 addresses) are designated (ST12).

  When the simple 8 address is an 8-bit address, there is a 256 address space from 00h to FFh. The address space of simple 8 may be allocated anywhere in the memory space on the host PC 100 side. When the host PC 100 designates a specific client 600, the simple 8-address space (00h to FFh) of the client is automatically allocated to the memory space of the host PC by the plug and play function of the OS on the host PC 100 side. The host PC 100 can access the simple 8 address space simply by specifying any of 00h to FFh.

  In this way, the host PC 100 can send and receive information to and from the designated client 600. Thereafter, communication is performed between the host PC 100 and the simple 8 conversion module 300 in accordance with a predetermined protocol used in the communication method to be used (PCI Express or the like) (ST14). Data transmitted and received by this communication can have a data size larger than that of 8-bit data handled by the simple 8 bus 400, and is, for example, 32 to 64 bits. For example, if PCI Express having x8 to x16 lanes is used, communication between the host PC 100 and the simple 8 conversion module 300 can be extremely speeded up.

  FIG. 6 is a flowchart illustrating an example of processing performed on the simple 8 conversion module 300 side in the system illustrated in FIG. 1 or 3. The processing of this flowchart can be executed by a logic circuit in the simple 8 conversion module 300 (corresponding to 300S in FIG. 1 and 300P in FIG. 3) and / or MPU + firmware ROM.

  First, when the data (data from the host PC 100) transmitted / received by the simple 8 conversion module 300 to / from the client 600 has a size of 8 bits or more, the data is divided in units of 8 bits (ST20). For example, if it is 32-bit data, it is divided into four in units of 8 bits (ST20).

  Here, the simple 8 conversion module 300 does not use a protocol used for communication with the host PC 100, and transmits data and control signals (RDL, WDL, IORL, etc.) in units of 8 bits to one or more specified clients 600. And requests the client 600 (CPU board or the like connected to the target I / O) for processing to be performed by the client (data write to the client from the host side) (ST22).

  Alternatively, the simple 8 conversion module 300 does not use the protocol used for communication with the host PC 100, and the processing result data of each client 600 (CPU board connected to the target I / O) in units of 8 bits. Get it back. The simple 8 conversion module 300 appropriately converts 8-bit data returned from the client 600 into a data unit (for example, 32 bits) on the host PC 100 side, and returns it to the host PC 100 (from the host side, data read from the client). (ST22).

  FIG. 7 is a flowchart for explaining an example of processing performed on the client 600 (target I / O board or the like) side in the system illustrated in FIG. 1 or FIG. The processing of this flowchart can be executed by cooperation between the client 600 and a logic circuit in the connection unit 500 (see FIG. 13 for an internal specific example).

  First, the client 600 (such as a CPU board connected to the target I / O) in the address space designated by the host PC 100 can perform simple 8 conversion by a control signal (IORL, RDL, WDL, etc.) from the simple 8 conversion module 300. Using the data sent from the module 300 in units of 8 bits, it performs its own processing (numerical calculation, image processing, image display, image capture, digital AV data encoding / decoding processing, printout, etc.). The processing result (data) of the client itself is appropriately returned to the simple 8 conversion module 300 based on the control signal (ST30). The data returned to the simple 8 conversion module 300 can be appropriately transferred to the host PC 100 via the transmission path (200S or 200P).

  Here, when the client is composed of a plurality of I / O board groups (for example, an arithmetic processing board group including a CPU / DSP / FPU or the like) (up to 256 in the 8-bit address space), the host PC 100 determines the I / O board group. Processing can be distributed and requested to the / O board group. If such distributed processing is used, even if the communication / processing speed of each I / O board on the simple 8 bus 400 is slow, the I / O board group as a whole is high-speed parallel when viewed from the host PC 100 side. (In this case, it may be considered that the host PC becomes a client and receives services from the I / O board group).

  FIG. 8 is a diagram for explaining still another example of the data processing system according to one embodiment of the present invention (an example in which serial transmission and / or parallel transmission is performed between a host and a plurality of clients). When the host PC 100 has communication I / O ports such as PCI, USB, printer I / O (IEEE1284), RS232C, LAN (IEEE802.3), etc., PCI-Simple8, USB for each of these I / O ports. -Conversion modules (300P, 300S) such as Simple8, printer-Simple8, RS232C-Simple8, and RS232C-Simple8 are connected. Then, most existing I / O can be converted to a simple 8-bus. When converted to simple 8, the same (simple 8 bus compliant) I / O board (client 600) can be used for those I / Os.

  For example, when simple 8 conversion is performed from the USB port of the host PC 100, a general-purpose simple 8 family board can be directly connected by USB, whereas a dedicated I / O is conventionally installed and operated. In this case, in creating application software using USB, if the user describes only the USB address (simple 8 address space), the I / O board connected by USB can be used.

  Conventionally, dedicated I / O and LSI are installed in the USB port, and dedicated DLL, system software, and application software are described. Compared to this, simple 8 conversion has a great merit. That is, conventionally, generalization of the I / O board connected to the USB port has not been considered. In contrast, if USB-simple 8 conversion is performed, the USB on the host (PC) side can be controlled from the client (I / O board) side as a general-purpose data port / control port. In terms of software as well, if a USB protocol is described, application software using USB and hardware I / O using USB can be used. USB ports are already widely used as general-purpose I / O ports, but it has been difficult for users to arbitrarily add functions and incorporate control mechanisms. On the other hand, Simple 8 can provide an I / O system whose functions can be easily changed.

  Conventionally, when user I / O is installed on an ISA (Industry Standard Architecture) bus, 24 address buses, 8 data buses, 8 control signals, etc. are decoded as necessary to obtain necessary addresses. And make control signals to secure the area. Next, it is necessary to create a DLL necessary for the I / O and to describe application software. On the other hand, when ISA-simple 8 conversion is performed, it is only necessary for the simple 8 bus to decode a large address, data, and control signal. The DLL is also common on the simple 8 bus. Therefore, when using an ISA board on a simple 8-bus, the user may write application software necessary for processing the board.

  If the legacy printer port is converted to simple 8, the printer port can be converted to a general-purpose bus. Since the legacy printer port can also be used as IEEE1284, various I / Os have been installed and used. However, in terms of hardware, it is used in individual standards and has not been generalized. On the other hand, according to the printer port-simple 8 conversion, a simple 8 family board made as a general-purpose board can be easily installed. Since the DLL is shared on the simple 8 bus, once the DLL is created, it can be used as it is. Legacy printer ports are almost standardized on older PCs, so you can renew and reuse your PC.

  RS-232C is convenient as a one-to-one communication means, but can also be used as a control target or a data logger. At this time, if various I / Os are configured to be controlled by simple 8, various I / O systems can be manufactured simply by changing the simple 8 family board.

  The main purpose of the Ethernet (registered trademark) LAN (IEEE802.3) LAN is to connect PCs, but it is also possible to make an adapter that can be used as a mere I / O to be controlled as viewed from the PC. For this purpose, if Ethernet LAN-Simple 8 conversion is performed, the Ethernet LAN terminal can be controlled as I / O if an instruction is sent with a simple protocol of "addressing and reading or writing data". Is possible. For example, control of an on / off switch system or the like can be easily performed using an Ethernet LAN terminal. The same applies to advanced processing such as a data logger using the Ethernet LAN terminal.

  FIG. 9 is a diagram for explaining still another example of the data processing system according to the embodiment of the present invention (an example in which a simple 8 conversion module is provided inside the client). PCI Express thinks that a single serial signal line that is differential will be in time because of the deadlock of the bus with the conventional PCI "64 addresses, 32 data, and about 160 signal lines in total control" It was. Even so, transfer speeds of about 2 to 4 times (500 MB / s per lane) are possible compared to PCI. Furthermore, if the serial signal is transferred with 16 lines of x16 lanes, it is possible to realize a speed of 50 times or more compared with conventional PCI (in the case of 32 bits / 33 MHz).

  Here, if PCI Express is converted to Simple 8, sufficient speed and performance can be secured even with low-speed I / O on the Simple 8 bus. In other words, PCI Express, by its nature, generates a 64-bit address and 32-bit data with a parallel latch mechanism when installing a conventional I / O, secures a necessary area, decodes it, Install LSI and driver for O.

  In contrast, in the I / O installation in the simple 8 conversion module 300S, PCI Express-simple 8 conversion may be performed once (see FIG. 2). A parallel conversion LSI from a PCI Express serial signal has a large number of gates and is expensive. However, in Simple 8, even if a large number of I / Os are used, only one expensive conversion LSI is required. Since the individual boards on the simple 8 bus 400 can exchange data with a simple buffer (such as a latch or a dual port RMA), the board can be created at low cost. Also, the DLL is simplified. Even with the same board size, the conversion mechanism of Simple 8 enables an epoch-making reduction in the price of the I / O board.

  In addition, the PCI Express conversion LSI has a large data transfer rate of 500 MB / s even with one lane, but generally I / O is often sufficient if it has a speed of about 1 MB / s. Trying to use PCI Express for each of these low-speed I / Os is equivalent to taking a road roller (PCI Express) to a ant that can be crushed by a finger (low-speed I / O). For example, when 100 files are compressed into a Zip file, even if only one of them is used, if all 100 files are decompressed, it takes a lot of wasted effort I can say that. In addition, since the PCI Express conversion LSI supports conversion at 500 MB / s, the DLL method is difficult as it is, and learning is performed every time I / O is made. On the other hand, if PCI Express-Simple 8 conversion is used, the basic DLL is the same on Simple 8, so once you learn it, you only need to create application software with the content you want to process via PCI Express. There is convenience to be able to do with.

  FIG. 10 is a diagram for explaining still another example of the data processing system according to the embodiment of the present invention (an example in which a simple 8 conversion module is provided inside the host). If a simple 8 bus 400 is installed from a client (CPU board equipped with DSP / FPU etc.) 600, the client will be a simple 8 family board on the simple 8 bus 400 (on a simple 8 bus network) as if it were a host. Can be used.

  Further, when controlling a DSP or an LPU (local processing CPU) board 600 with FPU from the host PC 100 or the like, if a dual port RAM (not shown) is installed in front of the simple 8 bus 400, the host PC 100 can be easily connected. Parallel processing can be performed by the CPU and the LPU of the board.

  For example, if the simple 8 bus 400 is configured to handle 2 bytes (16 bits) as one set, the simple 8 bus 400 can be used for reading / writing 8-bit data divided into an imaginary part and a real part, It is also possible to transmit / receive 8-bit data divided into a part and a scalar part.

  Further, since parallel processing is possible in a network using the simple 8-bus 400, the processing capability is greater than that of a grid computing array on a WAN (Wide Area Network) or LAN (Local Area Network).

  FIG. 11 is a diagram for explaining an example of a simple 8-bus connector 500C used in the data processing system according to the embodiment of the present invention and pin assignments of the connector. In Simple 8, a simple 8 bus connector 500C (FIG. 11A) using a common pin assignment is used to ensure compatibility between boards (clients) of the Simple 8 family. When the simple 8 is configured with an 8-bit address, the connector 500C has positive logic addresses A0 to A7, positive logic data D0 to A7, a negative logic I / O request IORL, and a negative logic interrupt. There are connection pins for handling the request IRQL, the negative logic write data strobe WDL, the negative logic read data strobe RDL, the positive logic enable clock E, and the negative logic reset RESL (FIGS. 11B and 11C). ). The connector 500C further has connection pins for handling a + 5V power supply line and a ground line (FIG. 11B). Among these connection pins, the pins (electrodes) that handle signals of the address buses A0 to A7, the data buses D0 to A7, the I / O request IORL, the write data strobe WDL, and the read data strobe RDL should be standardized. Although essential, the allocation of other pins (electrodes) including the power line can be optional (eg, the + 5V pin can be an open pin).

  FIG. 12 is a timing chart for explaining an example of a simple 8-bus read / write operation in the data processing system according to the embodiment of the present invention. Read data or write data of the data bus (D0 to D7) output from the data conversion circuit 310 of FIG. 2 or FIG. 4, the I / O request IORL output from the control signal processing circuit 330, and the write data strobe WDL Alternatively, the signal timing of the read data strobe RDL can be set as shown in FIG. 12, for example.

  The illustration of FIG. 12 is a case where the speed of the simple 8 bus is as slow as 1 MHz. However, when the speed of the simple 8 bus is as fast as, for example, 66 MHz, the illustrated time is shortened. For example, if the IOOR pulse width is 300 ns when the bus speed is 1 MHz, and the speed is increased to 66 MHz, the corresponding pulse width can be shortened from 300 ns to 66 ns (300 ns is impossible in the case of 66 MHz). However, the pulse width in that case may be defined as 300/66 ns or more).

  FIG. 13 shows a processing circuit (simple FIG. 7 processing) of a connection unit (simple 8 bus connector) 500C connected to a simple 8 bus on the client (target I / O board etc.) side in the system exemplified in FIGS. It is a figure explaining an example. For example, FIG. 11B shows how the connection electrodes of the connector 500C are allocated (pin assignment).

  The electrodes of data D0 to D7 of the simple 8-bus connector 500C are connected to a bus transceiver (or peripheral interface adapter PIA (Peripheral Interface Adapter)) 502. The electrodes of addresses A0 to A7 of the connector 500C are connected to the comparator 504. A part of address electrodes (A0 to A1) of connector 500C and electrodes of control signals (IORL, E, WDL, RDL) are connected to read / write control circuit 508. The bus transceiver 502 can be configured using a general-purpose IC (# 74245). Instead of # 74245, another general-purpose IC (# MC6821) can be used as the PIA. As the comparator 504, a general-purpose IC (# 74688) can be used. The read / write control circuit 508 can be configured using a general-purpose IC (# 74138: decoder / demultiplexer).

  A unique identification code 506 is set in advance as a simple 8 address for each client (I / O board), and this identification code 506 is input to the comparator 504. When the comparator 504 receives the addresses A0 to A7 that match the identification code 506, the comparator 504 determines that it has been designated and opens the gate of the bus transceiver 502.

  Further, when the gate of the bus transceiver 502 is opened, the read / write control circuit 508 has a part of the address (A0, A1) when the I / O request IORL is at the low level L and the enable clock E is at the high level H. ) Outputs a low level L write data strobe WDL (or a low level L read data strobe RDL). The storage units (8-bit latch or dual-port RAM) 521 to 524 that have received the write data strobe WDL (or read data strobe RDL) store the 8-bit data D0 to D7 from the transceiver 502 (or a client not shown). The 8-bit data D0 to D7 written from the I / O board is output).

  For example, if the original 32-bit data is divided into four parts and sent sequentially to D0 to D7 of the simple 8 connector 500C, after the target I / O board (client) is specified at A0 to A7, the WDL is low. If the combination of (A0, A1) at the level is (0, 0), D0 to D7 of the simple 8 data bus (D0 to D7 of the original 32-bit data) are stored (latched) in the storage unit 521. If WDL is at a low level and the combination of (A0, A1) is (0, 1), D0 to D7 of the simple 8 data bus (D8 to D15 of the original 32-bit data) are stored (latched) in the storage unit 522. . If WDL is at a low level and the combination of (A0, A1) is (1, 0), D0 to D7 of the simple 8 data bus (D16 to D23 of the original 32-bit data) are stored (latched) in the storage unit 523. . If WDL is low and the combination of (A0, A1) is (1, 1), D0 to D7 of the simple 8 data bus (D24 to D31 of the original 32-bit data) are stored (latched) in the storage unit 524. . The data latched in the storage units 521 to 524 is sent to a 32-bit device (I / O board of the client 600) (not shown) connected to the connection unit 500 in FIG.

  Or, for example, when the original 16-bit data is divided into two and sequentially sent to D0 to D7 of the simple 8 connector 500C, the target I / O board (client) is specified by A0 to A7, and then the WDL Is low level and (A0) is (0), D8 to D7 of the simple 8 data bus (D0 to D7 of original 16-bit data) are stored (latched) in the storage unit 511, and WDL is low level (A0) If (1), D0 to D7 of the simple 8 data bus (D8 to D15 of the original 16-bit data) are stored (latched) in the storage unit 512. The data latched in the storage units 511 to 512 is sent to a 16-bit device (I / O board of the client 600) (not shown) connected to the connection unit 500 in FIG.

  When data is read from a bit device (not shown) connected to the connection unit 500 in FIG. 13 (I / O board of the client 600), the RDL is at a low level, and is specified by a combination of (A0, A1) as described above. 8-bit data from the storage unit (latch or dual port RAM) is sequentially sent to the simple 8 bus 400 via the bus transceiver 502 and the simple 8 bus connector 500C.

  FIG. 14 is a diagram for explaining an example of a simple 8-bus card used in the data processing system according to the embodiment of the present invention. In this example, the appearance of a simple 8-bus card used in the system illustrated in FIG. 1 or FIG. 3 is illustrated. This card is provided with a 26 pin connector 500C for Simple 8. The pin assignment and card size of the simple 8 connector are standardized, and the simple 8 bus card can be arbitrarily connected to any simple 8 bus.

  FIG. 15 is a diagram for explaining another example of the simple 8-bus card used in the data processing system according to the embodiment of the present invention. Also in this example, the pin assignment and card size of the simple 8 connector are standardized. In this example, the connector portion of the connecting portion 500 is composed of a plurality of electrode groups 500e (such as comb-shaped gold-plated electrodes installed at the end of the card substrate) that handle signals similar to the 26-pin connector of FIG. . The electrode group 500e can be inserted into a slot (not shown) on a circuit board in which a standard size simple 8 card can be mounted.

  FIG. 16 is a diagram illustrating an example in which one or more simple 8-bus cards (clients) configured as illustrated in FIG. 14 or 15 are rack-mounted in the data processing system illustrated in FIG. 10 and the like. . In this example, a plurality of simple 8 connectors or a plurality of simple 8 card slots are provided in the DIN standard rack 700 so that the simple 8 boards (600-1 to 600-n) can be attached and detached arbitrarily. It has become. The data bus, address bus, and control signal group wiring of these simple 8 connectors or simple 8 card slots are connected in parallel, and the wiring (simple 8 parallel bus 400) is the simple 8 conversion module 300 (for example, 300S in FIG. 1). To be connected to.

  Any number of simple 8 family boards (clients) 600-1 to 600-n mounted on the rack 700 are bidirectionally connected to the host PC 100 via a simple 8 conversion module (not shown in FIG. 16). Each of the simple 8 family boards 600-1 to 600-n mounted on the rack 700 is mounted on the host PC 100 by the plug and play function of the OS, and can be accessed from the application software of the host PC 100.

<Summary>
A data processing system (simply called simple 8) according to an embodiment of the present invention is a bus (simple) that handles internal data in units of 8 bits (for example, D0 to D7) and internal addresses in N bits (for example, A0 to A7). (8 buses) to connect an external device (host / server) to one or more internal devices (client / terminal). This configuration includes a conversion module (simple 8 conversion module) and a connection unit (simple 8 connector) connected to the bus (simple 8 bus). Here, the external device (host / server) uses a signal line (serial transmission or parallel transmission, whether wireless or wired) that handles external data (eg, 32-bit data) of 8 bits or more, and It can be connected to a conversion module. Existing technology (USB, PCI Express, PCI-X, etc.) can be used for this signal line.

  The conversion module (simple 8 conversion module) converts the external data (for example, D0 to D31) into the internal data (D0 to D7) (D0 to D31 is divided into four to D0 to D7, etc.), or Internal data (D0 to D7) is converted into the external data (D0 to D31) (four D0 to D7 are combined into D0 to D31, etc.).

  The connection unit (simple 8 connector) includes an 8-bit data signal line (D0 to D7) for handling the internal data, an N-bit (for example, 8 bits) address signal line (A0 to A7) for handling the internal address, and data Via a plurality of signal lines (such as wiring on a circuit board or a 26-core flat cable) including a read signal line (RDL), a data write signal line (WDL), and an input / output request signal line (I / ORL) The conversion module is connected to one or more internal devices (clients).

  When a plurality of the internal devices (for example, I / O boards) are connected to the conversion module via the connection unit, one of the plurality of internal devices identified by the internal address (A0 to A7) is specified. One (target I / O board) is configured to exchange information with the conversion module.

  Here, the external device (for example, host PC) designates one place in the N-bit space (256 space if 8 bits) of the internal address to the conversion module, and designates the designated address space (target I / O). Data is sent to and received from the address space where the board exists. An internal device (target I / O board such as a legacy peripheral device or the latest CPU board) connected to the designated address space performs its own processing on the received data, and the processing result is appropriately displayed. , Can be returned to the conversion module.

That is, when viewed from the external device (host PC), one of the N-bit (8-bit) address spaces is designated for the conversion module (simple 8 conversion module) by a dedicated driver, and processing is performed in the address space. Just send the data you want. It is not necessary to rewrite the driver of the device (target I / O board: which may be the latest device or legacy device) in the address space on the external device (host PC) side. (If a legacy device in that address space already has its own device driver, it is not necessary to rewrite the device driver even if the host PC OS changes. However, the target I / O board on the host side does not need to be rewritten. If it is possible to write this driver, it is possible to directly control the target I / O board with that driver.)
The conversion module (simple 8 conversion module) appropriately uses a predetermined protocol corresponding to its communication means (USB, PCI Express, PCI-X, etc.) for communication with the external device (host PC). However, for the internal devices (clients that can include legacy devices), data is transferred to the designated address space in units of 8 bits without using a special (complex) protocol as used in the communication means. It only needs to be sent and received (no complicated protocol is used, but one of the simple 8 address spaces is specified, and I / O requests and read / write instructions are given).

  Since data in 8-bit (byte) units can be handled by a computer device using any OS, data in 8-bit units once taken into the conversion module (simple 8 conversion module) from the external device (host PC, etc.) Can handle the latest peripheral devices and legacy peripheral devices (computer devices) without any problems.

<Effect of Embodiment>
(1) The form between the simple 8 conversion module connected to the host (for example, a PC whose OS can change) and the client (for example, a legacy peripheral device or a future latest device) is not substantially affected by the evolution of the OS on the host side. Can be tied.

  (2) A simple 8 conversion module connected to a host and one or more clients can be connected without performing protocol conversion for each client.

  (3) From the viewpoint of the host, it is only necessary to designate one N-bit (8-bit) address space for the simple 8 conversion module and send the data to be processed to the device in the address space. It is not necessary to individually write drivers of devices in the address space on the host side.

  (4) Since 8-bit (byte) unit data can be handled by a computer device using any OS, the 8-bit unit data once taken into the simple 8 conversion module from a host PC or the like can be used by legacy computer devices. Can be handled without problems.

  (5) If a plurality of devices (clients) assigned to the N-bit space (256 spaces for 8 bits) perform parallel processing, the simple 8 conversion module is apparently a high-speed computer when viewed from the host PC or the like. Can also be handled. Using a super high-speed bus such as PCI Express for communication connection between the host and the simple 8 conversion module, and using many boards assembled with the latest high-speed CPU as individual clients, it has a processing capability similar to that of a supercomputer and is simple. It is also possible to construct an 8-grid computing system.

  (6) Standardize the physical structure (size, arrangement, etc. of multiple connection pins) and electrical structure (how to allocate signals to each connection pin, etc.) of the connection part (26-pin connector + 26-core flat cable, etc.) For example, by simply adding a board having the same standard connection (simple 8 family board), it is possible to add as many clients as possible within the N bit space (256 spaces if 8 bits).

  In addition, this invention is not limited to embodiment mentioned above, In the implementation stage, it can change variously in the range which does not deviate from the summary. For example, when the client is a digital AV device (digital TV or digital recorder), it is conceivable to use HDMI (High Definition Multimedia Interface) or IEEE 1394 for connection between the host and the simple 8 conversion module. It is also conceivable to use a digital game machine or a mobile phone for the host and / or client. In addition, the embodiments may be appropriately combined as much as possible, and in that case, the combined effect can be obtained. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.

  DESCRIPTION OF SYMBOLS 100 ... Host PC, 200 ... Signal line (transmission path) which handles external data of 8 bits or more, 200S ... Serial transmission path, 200P ... Parallel transmission path, 300 ... Simple 8 conversion module, 300S ... Simple 8 for serial I / F Conversion module, 300P ... Simple 8 conversion module for parallel I / F, 400 ... Simple 8 bus, 500 ... Connector, 500C ... Connector (connector standardized for Simple 8), 600 ... Client (target I / O) Board etc.).

Claims (9)

An external device as a computer device that can operate under an operating system that is not limited to one type as long as it uses serial signal lines that handle external data of 8 bits or more and can handle data in units of 8 bits ; In a data processing system for connecting one or more internal devices using internal data in units of 8 bits and an internal address of N bits,
The data processing system includes:
Converting the external data into the internal data, or converting the internal data into the external data;
Through a plurality of signal lines including an 8-bit data signal line for handling the internal data, an N-bit address signal line for handling the internal address, a data read signal line, a data write signal line, and an input / output request signal line, Comprising a connection part for connecting the conversion module to one or more internal devices;
When a plurality of the internal devices are connected to the conversion module via the connection unit, one of the plurality of internal devices specified by the internal address can be exchanged with the conversion module. ,
The external device is configured to designate the connection unit by the internal address,
One or more types of information exchange between the internal device and the conversion module connected to the one connection unit designated by the external device are used in communication between the external device and the conversion module. A data processing system that is configured to be protocol independent . An external device as a computer device capable of operating under an operating system that is not limited to one type as long as it uses parallel signal lines for handling external data of 8 bits or more and can handle data in units of 8 bits; In a data processing system for connecting one or more internal devices using internal data in units of 8 bits and an internal address of N bits,
The data processing system includes:
Converting the external data into the internal data, or converting the internal data into the external data;
Through a plurality of signal lines including an 8-bit data signal line for handling the internal data, an N-bit address signal line for handling the internal address, a data read signal line, a data write signal line, and an input / output request signal line, Comprising a connection part for connecting the conversion module to one or more internal devices;
When a plurality of the internal devices are connected to the conversion module via the connection unit, one of the plurality of internal devices specified by the internal address can be exchanged with the conversion module. ,
The external device is configured to designate the connection unit by the internal address,
One or more types of information exchange between the internal device and the conversion module connected to the one connection unit designated by the external device are used in communication between the external device and the conversion module. Configured to be protocol independent
Data processing system . The internal address identifies one of the one or more internal devices,
The conversion module sends the internal data in units of 8 bits to one specified internal device based on the logical state of the data read signal line or the data write signal line and the input / output request signal line. The data processing system according to claim 1 or 2, wherein the data is read or written.   When the conversion module converts the external data into the internal data, the external data of 8 bits or more is divided into the internal data in units of 8 bits, and the divided external data is one or more storage units in units of 8 bits. 4. The data according to claim 1, wherein the storage unit is used to specify which storage unit is used by at least a part of the internal address. 5. Processing system. External as a computer device that can operate under an operating system that is not limited to one type as long as it uses serial or parallel signal lines that handle external data of 8 bits or more and can handle data of 8 bits. A data processing system for connecting a device to one or more internal devices using internal data in 8-bit units and an N-bit internal address, wherein the data processing system converts the external data into the internal data or the internal data A conversion module for converting data into the external data; an 8-bit data signal line for handling the internal data; an N-bit address signal line for handling the internal address; a data read signal line; a data write signal line; The conversion module via a plurality of signal lines including signal lines A plurality of internal devices connected to the conversion module via the connection unit, the connection unit connected to the one or more internal devices specified by the internal address among the plurality of internal devices One is configured to exchange information with the conversion module, the external device is configured to designate the connection unit by the internal address, and is connected to the one connection unit designated by the external device Used in a data processing system configured to exchange information between an internal device and the conversion module without depending on one or more protocols used for communication between the external device and the conversion module In the method
After one of the one or more internal devices is specified by the internal address,
Based on the logical state of the data read signal line or the data write signal line and the input / output request signal line, the internal data is read or written in units of 8 bits to one specified internal device. Data conversion method to be performed . External as a computer device that can operate under an operating system that is not limited to one type as long as it uses serial or parallel signal lines that handle external data of 8 bits or more and can handle data of 8 bits. A data processing system for connecting a device to one or more internal devices using internal data in 8-bit units and an N-bit internal address, wherein the data processing system converts the external data into the internal data or the internal data A conversion module for converting data into the external data; an 8-bit data signal line for handling the internal data; an N-bit address signal line for handling the internal address; a data read signal line; a data write signal line; The conversion module via a plurality of signal lines including signal lines A plurality of internal devices connected to the conversion module via the connection unit, the connection unit connected to the one or more internal devices specified by the internal address among the plurality of internal devices One is configured to exchange information with the conversion module, the external device is configured to designate the connection unit by the internal address, and is connected to the one connection unit designated by the external device Used in a data processing system configured to exchange information between an internal device and the conversion module without depending on one or more protocols used for communication between the external device and the conversion module Information storage medium,
Based on the logical state of the data read signal line or the data write signal line and the input / output request signal line, a process for reading or writing the internal data in units of 8 bits is written to the internal device. Information storage media . External as a computer device that can operate under an operating system that is not limited to one type as long as it uses serial or parallel signal lines that handle external data of 8 bits or more and can handle data of 8 bits. A data processing system for connecting a device to one or more internal devices using internal data in 8-bit units and an N-bit internal address, wherein the data processing system converts the external data into the internal data or the internal data A conversion module for converting data into the external data; an 8-bit data signal line for handling the internal data; an N-bit address signal line for handling the internal address; a data read signal line; a data write signal line; The conversion module via a plurality of signal lines including signal lines A plurality of internal devices connected to the conversion module via the connection unit, the connection unit connected to the one or more internal devices specified by the internal address among the plurality of internal devices One is configured to exchange information with the conversion module, the external device is configured to designate the connection unit by the internal address, and is connected to the one connection unit designated by the external device Used in a data processing system configured to exchange information between an internal device and the conversion module without depending on one or more protocols used for communication between the external device and the conversion module Said conversion module
A data conversion circuit for converting data of a signal line that handles external data of 8 bits or more into internal data in units of 8 bits;
An address signal processing circuit for generating the internal address that identifies one of the internal devices in accordance with an instruction from the external device;
A control signal processing circuit that generates the data read signal line or the data write signal line and the input / output request signal line according to an instruction from the external device
It comprises . External as a computer device that can operate under an operating system that is not limited to one type as long as it uses serial or parallel signal lines that handle external data of 8 bits or more and can handle data of 8 bits. A data processing system for connecting a device to one or more internal devices using internal data in 8-bit units and an N-bit internal address, wherein the data processing system converts the external data into the internal data or the internal data A conversion module for converting data into the external data; an 8-bit data signal line for handling the internal data; an N-bit address signal line for handling the internal address; a data read signal line; a data write signal line; The conversion module via a plurality of signal lines including signal lines A plurality of internal devices connected to the conversion module via the connection unit, the connection unit connected to the one or more internal devices specified by the internal address among the plurality of internal devices One is configured to exchange information with the conversion module, the external device is configured to designate the connection unit by the internal address, and is connected to the one connection unit designated by the external device Used in a data processing system configured to exchange information between an internal device and the conversion module without depending on one or more protocols used for communication between the external device and the conversion module Hardware,
A connector used in the connection portion and connected to the plurality of signal lines;
Comparing the internal address obtained from the connector with predetermined identification data and detecting a match between the two,
One or more storage units for storing the internal data in units of 8 bits;
When the comparator detects the coincidence, the internal data of the 8-bit unit is converted into the data read signal line obtained from the connector or the data write signal line and the input / output request signal line according to the logical state of the 8-bit unit. Transfer control means for transferring between the connector and the one or more storage units
Hardware equipped with . The transfer control means is configured to identify the storage unit that is a transfer destination of the internal data of the 8-bit unit obtained from the connector, using at least a part of the internal address obtained from the connector. The hardware according to claim 8 .

Images