JP4944833B2 - Image coding apparatus and control method thereof - Google Patents

Description

  The present invention relates to an image encoding technique, and more particularly to a technique for generating encoded image data by converting image data into frequency space data and encoding the obtained conversion coefficient.

  Conventionally, as an image encoding method, transform encoding is used in which image data is converted into frequency space data and encoded. JPEG recommended as an international standard system for still image coding is a representative example of transform coding using DCT as a transform method to a frequency space. The JPEG encoding process will be briefly described below.

  The image data to be encoded is divided into rectangular area blocks, and a discrete cosine transform is applied to each block. The coefficient obtained by the conversion is quantized according to a desired image quality level and code amount, and the quantized conversion coefficient is entropy encoded. JPEG Baseline employs Huffman coding as a coefficient entropy coding method. Data of 8 × 8 = 64 frequency bands are encoded by being divided into one DC component and 63 AC components. The DC component is encoded as a difference value from the immediately preceding block, and the AC component is Huffman encoded by a combination of a zero consecutive number (zero run) and a non-zero coefficient value.

  As can be seen in JPEG Baseline, in an encoding method that encodes a continuous number of zeros, a coefficient that becomes 0 must exist to some extent in order to perform encoding efficiently. As an extreme example, when all 63 AC coefficients are non-zero, encoding is performed by combining run 0 and non-zero coefficient values, which is not efficient.

  For example, when JPEG encoding is performed with a small quantization step value, each coefficient is separated into an upper bit part and a lower bit part to efficiently perform the encoding, A method has been proposed in which run-length coding is applied only.

An example of an image processing apparatus and an image processing method using such a conventional technique is disclosed in Patent Document 1.
JP 2000-13797 A

  In the coding for separating the upper bit part and the lower bit part as described above, the bit position at which the coefficient is separated is an important factor that determines the compression performance. If the boundary bit position is set low, the length of the zero run is shortened and run-length encoding does not function effectively. On the other hand, if the boundary bit position is set too high, a lot of redundant data is included in the lower bit part, and the encoding performance of the lower bit part affects the overall performance. For example, in Patent Document 1 shown above, the lower bit part is not compressed, but in such a case, high encoding performance cannot be realized.

  The present invention has been made in view of the above-described problems. In an image encoding process in which frequency conversion and quantization are performed in units of pixel blocks, a technique for more efficiently encoding coefficients after quantization. It is something to be offered.

In order to solve this problem, for example, an image encoding device of the present invention has the following configuration. That is,
An image encoding device that performs frequency conversion and quantization processing in units of pixel blocks from multivalued image data, and encodes each multivalued coefficient obtained by the quantization processing,
Counting means for detecting the number of effective bits from the bit position that first becomes “1” from the most significant bit to the least significant bit to the least significant bit for each coefficient and counting the number of occurrences of each effective bit number; ,
The number of occurrences of the number of effective bits B is defined as N (B), the maximum number of effective bits with the number of occurrences of 1 or more is defined as bmax, and the summation function of the following equation for the variable b = 0, 1, 2,.
S (bmax−b) = ΣN (bmax−i) (i = 0, 1,..., B)
In relation to the preset threshold value Th,
S (bmax−b)> Th
Boundary bit position determination means for determining a boundary bit position based on the maximum integer b;
Separating means for separating the values of the respective coefficients into upper bit parts and lower bit parts with the boundary bit position calculated by the boundary bit position determining means as a boundary;
Upper bit encoding means for encoding the upper bit portion of each coefficient separated by the separation means;
Low-order bit encoding means for encoding the low-order bit part of each coefficient separated by the separation means;
Output means for generating and outputting encoded data of the pixel block of interest from encoded data obtained by the upper bit encoding means and the lower bit encoding means, respectively.

  ADVANTAGE OF THE INVENTION According to this invention, the technique which encodes the coefficient after quantization more efficiently can be provided in the image coding process which performs frequency conversion and quantization per pixel block.

  Embodiments according to the present invention will be described below in detail with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a block configuration diagram of an image encoding device according to the embodiment.

  The image encoding apparatus according to the present embodiment receives image data to be encoded from the outside, and performs sequence conversion such as frequency conversion (DCT) and quantization for each pixel block. Then, each quantized coefficient obtained from the pixel block of interest is separated into an upper bit part and a lower bit part and encoded. The input source of the image data is an image scanner, but it may be a storage medium that stores image data as a file, and the type thereof is not limited.

  The image data to be encoded is assumed to be monochrome multivalued image data having only a luminance component, and the luminance component is assumed to be 8 bits (256 gradations from 0 to 255). However, this is to simplify the description of the embodiment, and one pixel may be a plurality of components (for example, RGB or CMYK), the type of the color space is not limited, and the number of bits of one component is also The number of bits is not limited to 8 bits and may be more than 8 bits. Furthermore, the image to be encoded is composed of horizontal W pixels and vertical H pixels. For simplicity of explanation, it is assumed that W and H are multiples of 8.

  Hereinafter, the encoding process in the image encoding apparatus in FIG. 1 will be described.

  First, image data to be encoded is sequentially input from the image input unit 101. The input order of the pixel data is a raster scan order. One pixel is a non-negative integer value from 0 to 255 expressed by 8 bits. Let the upper left corner of the image be coordinates (0, 0), and let the value of the pixel at the pixel position x in the horizontal right direction and the pixel position y in the vertical down direction be represented by P (x, y). For example, when the pixel at the position (x, y) = (3,4) has a luminance value of 128, it is expressed as P (3,4) = 128. Further, in the following description, the expression “P (x, y)” is also used when expressing the “pixel” at the position (x, y).

  The block dividing unit 102 appropriately stores pixel data input from the image input unit 101 in an internal buffer (not shown), and sequentially outputs the rectangular blocks having a size of 8 × 8 pixels as a unit. The block at the upper left corner of the image is numbered 0, identification numbers are given in ascending order in the raster scan order, and rectangular block data is extracted and output in this order.

The series conversion unit 103 performs frequency conversion on the rectangular block data output from the block division unit 102. Here, the discrete cosine transform used in JPEG (ISO / IEC 15444-1) is applied as the series conversion process, and is converted into DCT coefficient data. In another embodiment of the present invention, in order to reduce the distortion of the block, the conversion to the frequency space can be performed using the overlapping orthogonal transformation, the overlapping bi-orthogonal transformation, or the like that performs the transformation process while overlapping the blocks. . Note that the JPEG discrete cosine transform processing is described in the following international standard recommendations and the like, and will not be described here.
ITU-T Recommendation T.81 | ISO / IEC 10918-1: 1994, Information technology-Digital compression and coding of continuous-tone still images: Requirements and guidelines.
As in the case of JPEG, level shift processing for subtracting the intermediate value is performed prior to the application of the discrete cosine transform. In this embodiment, since each pixel of the input image data to be encoded is 8-bit data in the range of 0 to 255, 128 is subtracted from the pixel value P (x, y).

  The coefficient quantization unit 104 performs quantization processing on the DCT coefficient data obtained by the series conversion unit 103 according to the required image quality level, and each coefficient value after quantization (64 in the embodiment) Is stored in the coefficient buffer 105. Hereinafter, when it is not particularly necessary to distinguish the presence or absence of quantization, a quantized coefficient value stored in the coefficient buffer 105 is simply referred to as a coefficient value. In the embodiment, one coefficient value is described as being represented by 9 bits (of which 1 bit is a positive or negative sign), but may be 10 bits or more in order to improve accuracy.

  The coefficient buffer 105 stores coefficient values for one rectangular block (64 in the case of the embodiment).

  The boundary bit position determination unit 116 examines the distribution of the number of effective bits, which will be described later, for each coefficient value for one rectangular block stored in the coefficient buffer 105, and determines the boundary bit position B used in the subsequent coefficient encoding unit 117. To do.

  The boundary bit position determination unit 116 includes a valid bit determination unit 106, a frequency table generation unit 107, a frequency table buffer 108, and a boundary bit selection unit 109.

The effective bit determination unit 106 sequentially reads each coefficient value Cn in the target rectangular block stored in the coefficient buffer 105, and obtains the effective bit number B (Cn). The number of effective bits indicates a bit position where “1” first appears when searching from the upper bit to the lower bit when the absolute value of the coefficient value Cn is expressed in a natural binary number. For example, when the coefficient value Cn of interest is “−5”, the natural value of the absolute value “5” is “0... 0101”. Since the most significant “1” is the third digit from the lower order, B (5) = 3. In other words, it can be said that the effective number of bits of the coefficient value having the absolute value “5” is 3 bits from the least significant bit. When Cn = 0, there is no “1” bit, so the number of effective bits B (Cn) is zero. In short, it can be said that the effective bit number B (Cn) is the smallest positive integer value P that satisfies the condition | Cn | <2 ^P with respect to the absolute value | Cn | of the coefficient.

  The frequency table generation unit 107 updates the occurrence frequency table held in the frequency table buffer 108 for B (Cn) output from the valid bit number determination unit 106. The frequency table buffer 108 has a capacity for storing the appearance frequencies N (0) to N (8) of the valid bit numbers 0 to 8, respectively. The frequency table buffer 108 is initialized with “0” when the frequency of one rectangular block is obtained. When the effective bit determination unit 106 determines the number of effective bits B (Cn) of the target coefficient value Cn, the frequency table generation unit 107 increases N (B (Cn)) in the frequency table buffer 108 by “1”. Let That is, the frequency table generation unit 107 updates the frequency table buffer 108 every time the valid bit determination unit 106 determines a valid bit of one coefficient value.

  FIG. 4 shows an example in which the appearance frequency of the effective bits of all the coefficient values in the block of interest obtained as described above is shown as a graph. FIG. 4 shows an example in which there are 0 to 7 effective bits and the number of occurrences of 8 effective bits is 0.

  When the effective bit number determination and the frequency table update processing are performed for all coefficient values of the target rectangular block, the boundary bit selection unit 109 selects the boundary bit B in the target rectangular block. Specifically, it is as follows.

The boundary bit selection unit 109 first calculates the number N (b) of occurrences of each effective bit number stored in the frequency table buffer 108 (b is an arbitrary integer value indicating the effective bit number) from the maximum value of the effective bit number. By performing cumulative addition toward the minimum value, conversion is made into a table S (b) of cumulative frequency as shown in FIG. In the rectangular block of interest, when the maximum value of the number of effective bits having an appearance count of 1 or more is bmax (bmax = 7 in the case of FIG. 4), the boundary bit selector 109 sets the variables b = bmax, bmax−1. , Bmax-2..., And a cumulative frequency table S (b) represented by the following equation is obtained.
S (b) = N (b) When b = bmax S (b) = N (b) + S (b + 1) When b ≠ bmax

Conversely, when the variable b = 0, 1, 2,..., Bmax is updated, it can be expressed as follows using the summation function Σ.
S (bmax−b) = ΣN (bmax−i) (i = 0, 1,..., B)

  In short, the cumulative frequency table S (b) indicates that when b ≠ 0, the cumulative frequency table S (b) represents the number of coefficient values whose absolute value is 2 ^ b or more. S (0) is equal to the number of all coefficient values in the target rectangular block.

  After obtaining the cumulative frequency table S (b), the boundary bit selection unit 109 checks the value of S (b) from the maximum value to the minimum value of the number of effective bits, that is, in descending order, and sets a preset threshold value. The maximum integer b exceeding Th is searched. Then, the boundary bit selection unit 109 outputs the obtained b as the boundary bit position B. Although details will become clear from the description to be described later, when S (1) does not exceed the threshold value Th, all the coefficients in the target rectangular block are not separated, and all are run-length encoded. .

  Here, the threshold Th is set to be a predetermined ratio with respect to the total number of coefficient values (in the case of the embodiment, the total number of coefficient values is 64 because the rectangular block has a size of 8 × 8 pixels). This threshold value Th can be set or selectable by the user as appropriate, but from a statistical viewpoint, this threshold value Th is suitably ¼ to ３ of the total number of coefficients in the rectangular block. is there. For example, if the ratio 1/3 is adopted, the threshold Th is “21” (≈64 / 3).

  As will be described later, in the encoding process of each coefficient value in the target rectangular block in the later-stage coefficient encoding unit 117, the coefficient value is separated into upper and lower by the boundary bit B, and zero is continuous with respect to the upper bit. Apply number coding, ie run-length coding. Therefore, the role of the threshold Th here is for adjusting the ratio of the coefficient value in which the higher-order bit part of the coefficient value is non-zero and the coefficient value of zero, and aims to make run-length encoding function effectively. It can be said that it is set as. In the example shown in FIG. 5, “5” corresponds to the maximum b exceeding the threshold Th, and “5” is output as the boundary bit position.

  When the boundary bit position determination unit 116 determines the boundary bit position B, the coefficient encoding unit 117 reads out each coefficient value stored in the coefficient buffer 105 in accordance with a preset order and performs an encoding process. .

  That is, the coefficient value stored in the coefficient buffer 105 is read (scanned) twice. The first scan is for the boundary bit position B determination process by the boundary bit position determination unit 116 already described. The second scan is for coefficient value encoding processing by the coefficient encoding unit 117 described below.

  In the present embodiment, the scan order of the first scan may be any order. On the other hand, the second scan performed by the coefficient encoding unit 117 is in a zigzag scan order from the viewpoint of encoding efficiency, but is not necessarily limited thereto. Although details will be described later, the coefficient encoding unit 117 in the subsequent stage encodes the higher-order bit part of the coefficient by a combination of the number of consecutive zeros and a non-zero coefficient value. At this time, any scan method may be used as long as the number of consecutive zeros is increased. For example, an appropriate method may be selected from several scan patterns. In addition, the scan order may be dynamically changed so that the coefficients are arranged in order from the largest to the smallest with reference to the coefficient distribution in the previously encoded block.

  The coefficient encoding unit 117 in this embodiment includes an upper / lower bit separation unit 110, an upper bit encoding unit 111, a lower bit encoding unit 112, and a code buffer 113.

  The upper / lower bit separation unit 110 removes the lower B bits in the code absolute value representation of the target coefficient value Cn read from the coefficient buffer 105, and the lower B bit part below the boundary bit position. And to separate. However, positive and negative sign bits are not processed. More specifically, the boundary bit selection unit 109 includes the upper bit part Un (= Cn >> B) and the lower bit part Ln (= | Cn | & ((1 << B) −) of the coefficient value Cn of interest. 1)). Here, Y >> X indicates that the value Y is shifted in the lower direction by X bits, and Y << X indicates that the value Y is shifted in the upper direction by X bits. | Y | represents the absolute value of the value Y, and X & Y represents the logical product (AND) of the value X and the value Y in bit units.

  The upper / lower bit separation unit 110 outputs the bit part Un of the target coefficient value Cn to the upper bit encoding unit 111 and outputs the lower bit part Ln to the lower bit encoding unit 112.

  For the coefficient Cn having the value of the upper bit part Un of “0”, the sign representing the sign of the coefficient Cn is also passed to the lower bit encoding part 112.

  FIG. 6 shows an example in which “−41, −7, 28, −1,...” Is input as an example of the coefficient value Cn, and the upper bit part Un and the lower bit part Ln are separated at the boundary bit position B = 4. .

  In the case illustrated, the upper / lower bit separation unit 110 outputs 64 upper bit units Un including one bit of the positive / negative code to the upper bit encoding unit 111.

  When the value represented by 4 bits excluding the sign bit of the input upper bit part Un is “0”, the upper bit coding unit 111 does not code the sign bit here. In the upper bit part Un, the value represented by 4 bits excluding the sign bit is “0” in the case of FIG. 6 in the coefficient values Cn = “− 7” and “−1”. When the value represented by 4 bits excluding the sign bit of the upper bit part Un is non- “0”, the upper bit part Un including the sign bit is directly subjected to run length encoding.

  Therefore, in the case of FIG. 6, the upper bit encoding unit 111 performs run-length encoding in the order of multi-value data “−2”, “0”, “1”, “0”. Become. As a result, the probability that the upper bit part is “0” is increased, and the encoding efficiency can be increased.

  Note that one DC coefficient and 63 AC coefficients are obtained from one rectangular block. The upper bit encoding unit 111 in the embodiment uses the same method as the encoding of DC and AC coefficients in JPEG Baseline. That is, when the upper bit part Un of the DC coefficient of the rectangular block of interest is encoded, the upper bit part Un of the DC coefficient of the immediately preceding block (which is also an already encoded block) is used as a predicted value. Then, the difference between the upper bit part Un of the block of interest and the predicted value is calculated, and Huffman coding is performed based on the difference. Then, the Huffman coding is performed on the upper bit part Un of the AC coefficient by combining the number of consecutive zeros and the non-zero coefficient. Similar to JPEG Baseline, a special code representing EOB (End Of Block) is used when the end of the block ends with a sequence of zeros.

  On the other hand, the upper / lower bit separation unit 110 outputs the 64 lower bit parts Ln of the target rectangular block to the lower bit encoding unit 112. However, as described above, the upper / lower bit separation unit 110, for the coefficient Cn whose 4-bit value except the sign bit of the upper bit part Un is “0”, converts the sign bit to the lower bit. It is added to the part Ln and output to the lower bit encoding part 112.

  In the example of FIG. 6, the coefficient values “−7” and “−1” indicate that the value of the upper bit part Un excluding the sign bit is “0”. Therefore, the addition position of the plus / minus sign bit is set to a position where “1” first appears from the high order to the low order of the low order bit part Ln. In the case of FIG. 6, the position indicated by the diagonal lines is the position where the positive and negative bits are inserted.

  The lower bit encoding unit 112 encodes the lower bit part Ln output from the upper / lower bit separation unit 110. Since the lower bit portion Ln is generally hard-to-compress data with respect to the upper bit portion Un, the lower bit encoding portion 112 of the present embodiment outputs the lower bit portion without compression (however, in the case of pursuing compression performance) Arithmetic codes etc. may be applied). Since the data is not compressed, the input data is basically encoded data as it is, but the bit data is arranged according to the degree of influence on the image quality, in other words, the decoding apparatus can perform progressive reproduction. Therefore, the data are rearranged in the order of bit planes and output.

  In the case of FIG. 6, the lower bit encoding unit 112 stores the input lower bit unit Ln in an internal buffer (not shown), and is configured with the most significant bit digit (Bth digit) of each lower bit unit Ln. Output a bit plane. This process is repeated up to the least significant bit digit (first digit).

  An example of data output by the lower bit encoding unit 112 in the case of the coefficient value sequence “−41, −7, 28, −1,...” (Boundary bit position B = 4) illustrated in FIG. Shown in

  The plane (bit information at the same bit position) output at the beginning of the lower bit part Ln is a B-digit bit plane “1010...”. The coefficient values “−41” and “28” correspond to “1”. Since the value represented by the upper bit part Un excluding the sign bits of the coefficient values “−41” and “28” is non-zero, the positive / negative sign bit is not inserted.

  Focusing on the next bit plane of B-1 digits, the first “1” bit representing the coefficient value “−7” appears (see FIG. 6). Further, the value of the upper bit part Un excluding the sign bit of the coefficient value “−7” is “0”. Therefore, as shown in the figure, positive and negative sign bits are inserted at positions following the first “1” representing the coefficient value “−7”. Hereinafter, the B-2 digit bit plane and the B-3 digit bit plane are output. In the B-3 digit bit plane, since the first “1” representing the coefficient value “−1” appears, the sign bit is inserted subsequently.

  The encoding buffer 113 stores encoded data in units of rectangular blocks output from the upper bit encoding unit 111 and the lower bit encoding unit 112.

  The code string forming unit 114 reads the encoded data of the target rectangular block stored in the code buffer 113 and generates encoded data in a predetermined format while storing the encoded data in a buffer included in the code forming unit 114. And output to the code output unit 115. The code output unit 115 generates a file header at an output destination (for example, a hard disk device) when inputting image data to be encoded, and then outputs the code sequence generated by the code sequence forming unit 114. Thus, one encoded data file is generated.

  FIG. 8 shows the structure of an encoded data file output from the image encoding apparatus of this embodiment. In the file header code string, the number of pixels in the horizontal direction of the image, the number of pixels in the vertical direction, the number of color components (the number of color components is 1 because it is an example of a monochrome image in the embodiment), the number of bits of each pixel, etc. Various information necessary for decoding is added as a header. This header includes boundary bit B information for all rectangular blocks. Therefore, the decoding apparatus can obtain the boundary bit position of each block by analyzing this header. After the file header, the encoded data of the upper bit part Un is arranged for all rectangular blocks of the image, and then the lower bit encoded data is arranged. In the figure, N represents the total number of blocks, and L represents the maximum value of the boundary bit position B searched for all blocks. The higher-order bit encoded data is configured by concatenating the higher-order bit portion encoded data of each rectangular block in the order of raster scan in units of rectangular blocks. The low-order bit encoded data is configured by arranging the low-order bit part encoded data of each rectangular block in the order of bit planes. The bit plane i is configured by collecting the data of the bit plane i of each block in the raster scan order, but does not include the data from the block where the boundary bit B <i, and therefore the data is not necessarily collected from all the blocks. It is not done.

  The code structure shown in FIG. 8 is merely an example, and any code may be used as long as it includes boundary bit position information and at least a part of higher-order bit encoded data. Further, FIG. 8 may be a macro block composed of a plurality of blocks or a data structure of a tile including a plurality of macro blocks.

  The encoded data generated by the image encoding apparatus of the present embodiment shifts the upper bit part to the upper part by the number of bits represented by the boundary bit position B, and restores the lower bit part according to the required image quality level. It can be reproduced by decoding in the reverse process of encoding.

  As described above, in the image coding apparatus according to the present embodiment, the effective bit number of the coefficient after series conversion and quantization in a pixel block (8 × 8 pixel size in the embodiment) composed of a plurality of pixels. Find the frequency distribution for. Then, boundary bits were obtained in which the number of non-zero upper bit portions Un is a predetermined ratio with respect to the number of coefficients of the entire rectangular block. Using this, the coefficient was separated into an upper bit part and a lower bit part, and the upper bit part was encoded by combining a continuous number of zeros and a non-zero coefficient. Thereby, run-length encoding can be made to function effectively and encoding efficiency can be improved.

[Modification of First Embodiment]
An example in which processing equivalent to that in the first embodiment is realized by a computer program will be described below as a modification of the first embodiment.

  FIG. 13 is a block configuration diagram of an information processing apparatus (for example, a personal computer) in the present modification.

  In the figure, reference numeral 1401 denotes a CPU which controls the entire apparatus using programs and data stored in a RAM 1402 and a ROM 1403 and executes image encoding processing and decoding processing described later. A RAM 1402 includes an area for storing programs and data downloaded from the external device via the external storage device 1407, the storage medium drive 1408, or the I / F 1409. The RAM 1402 also includes a work area used when the CPU 1401 executes various processes. Reference numeral 1403 denotes a ROM which stores a boot program, a setting program for the apparatus, and data. Reference numerals 1404 and 1405 denote a keyboard and a mouse, respectively. Various instructions can be input to the CPU 1401.

  A display device 1406 includes a CRT, a liquid crystal screen, and the like, and can display information such as images and characters. Reference numeral 1407 denotes a large-capacity external storage device such as a hard disk drive device. The external storage device 1407 stores an OS (operating system), a program for image encoding and decoding processing described later, image data to be encoded, encoded data of an image to be decoded, and the like as files. The CPU 1401 loads these programs and data into a predetermined area on the RAM 1402 and executes them.

  A storage medium drive 1408 reads programs and data recorded on a storage medium such as a CD-ROM or DVD-ROM and outputs them to the RAM 1402 or the external storage device 1407. In addition, a program for image encoding and decoding processing described later, image data to be encoded, encoded data of an image to be decoded, and the like may be recorded on the storage medium. In this case, the storage medium drive 1408 loads these programs and data into a predetermined area on the RAM 1402 under the control of the CPU 1401.

  Reference numeral 1409 denotes an I / F, which connects an external device to the present apparatus through the I / F 1409 and enables data communication between the present apparatus and the external apparatus. For example, image data to be encoded, encoded data of an image to be decoded, and the like can be input to the RAM 1402, the external storage device 1407, or the storage medium drive 1408 of this apparatus. A bus 1410 connects the above-described units.

  In the above configuration, when the power of this apparatus is turned on, the CPU 1401 loads the OS from the external storage device 1407 to the RAM 1402 in accordance with the boot program stored in the ROM 1403. As a result, the keyboard 1404 and the mouse 1405 can be input, and the GUI can be displayed on the display device 1406. When the user operates the keyboard 1404 or the mouse 1405 to give an instruction to start an application program for image encoding processing stored in the external storage device 1407, the CPU 1401 loads the program into the RAM 1402 and executes it. As a result, the present apparatus functions as an image encoding apparatus.

  Hereinafter, the processing procedure of the application program for image processing executed by the CPU 1401 will be described with reference to the flowchart of FIG. Basically, this program includes functions corresponding to the components shown in FIG. However, the areas of the coefficient buffer 105, the frequency table buffer 108, and the code buffer 113 in FIG. 1 are secured in the RAM 1402 in advance.

  First, in step S200, initialization processing before starting encoding is performed. Here, a variable i holding the number of the pixel block to be processed is initialized to 0.

  Next, in step S201, image data to be encoded is sequentially input from an external device connected by the I / F 1409, and the i-th block data is formed while being stored in the RAM 1402 (image input unit 101, block dividing unit). 101 equivalent). At this time, the total number of pixel blocks included in the image is calculated by referring to the header of the image data.

  Next, in step S202, the target pixel block MB (i) is subjected to series conversion processing such as discrete cosine transformation, and the corresponding DCT coefficient data (block coefficient value) is stored in the RAM 1402 (processing of the series conversion unit 103). Equivalent).

  Subsequently, in step S203, the DCT coefficient data is quantized and stored as a coefficient value in the RAM 1402 (corresponding to the process of the coefficient quantization unit 104).

  Next, in step S204, the boundary bit position B is obtained by referring to each coefficient value of the target block MB (i) (corresponding to the processing of the boundary bit position determination unit 116).

  FIG. 3 shows a processing flow for determining the boundary bit position B in step S204.

  Hereinafter, the flow of processing for determining the boundary bit position B of the coefficient value of the target block MB (i) will be described with reference to FIG.

  First, in step S301, the frequency table and the number n for identifying the coefficient inside the block MB (i) of interest are initialized. Specifically, the number of appearances is initially set to 0 for all effective bits, and 0 is set to the coefficient number n.

  Next, in step S302, the coefficient Cn represented by the number n is acquired from the RAM 1402.

  In the subsequent step S303, the effective bit number B (Cn) is obtained for the coefficient Cn of interest (corresponding to the processing of the effective bit number determination unit 106).

  In step S304, the number of valid bits B (Cn) obtained in step S303 is updated by incrementing the value of the corresponding frequency table N (B (Cn)) (corresponding to the processing of the frequency table generating unit 107).

  In step S305, it is determined whether or not the coefficient Cn of interest is the last coefficient of the block. If it is the last coefficient (yes), the process proceeds to step S307. If not (no), the process proceeds to step S307. The process moves to S306. Since the size of the pixel block is 8 × 8 pixels, whether the coefficient Cn is the last coefficient of the block can be determined by comparing the variable n with “64”.

  If the coefficient Cn is not the last coefficient in the block, the value of n is incremented and updated in step S306 in order to move the processing target to the next coefficient. After step S306, the process returns to step S302, and the process is performed for the coefficient Cn to be newly focused.

  On the other hand, if it is determined in step S305 that Cn is the last coefficient of the block, in step S307, the frequency table N (b) (b is an arbitrary integer representing the number of effective bits) is changed to the cumulative frequency table S (b). And convert. This corresponds to part of the processing of the boundary bit selection unit 109.

  Next, in step S308, b in the cumulative frequency table S (b) generated in step S307 is searched in order from the maximum value of the effective bits to the minimum value, and is selected as the boundary bit position B (of the boundary bit selection unit 109). Equivalent to part of the process).

  With the above processing, the boundary bit position B of the block MB (i) of interest is determined.

  Returning to the description of FIG. When the boundary bit position B of the block MB (i) of interest is determined as described above, the process proceeds to step S205, and the coefficient value of the block of interest MB (i) is converted to the upper bit portion Un and the lower bit portion. Separate into Ln and perform encoding respectively. This corresponds to the processing of the coefficient encoding unit 117.

  In step S206, it is determined whether or not the processed block is the last block of the image. If it is the last block, the process proceeds to step S208, and if not, the process proceeds to step S207.

  In step S207, in order to move the block to be processed to the next block, the variable i is updated by adding 1, and the encoding process is continued from step S201 for the next block.

  On the other hand, when the processing has been completed for all the blocks of the image, the process proceeds to step S208, where final encoded data is generated, and the I / F 1409 is solved and output to the external device (code string forming unit). 114, corresponding to the processing of the code output unit 115).

  As described above, it will be apparent that the present modification can also provide the same operational effects as those of the first embodiment. In other words, the frequency distribution of the number of effective bits of the coefficient value after quantization is obtained in units of blocks composed of a plurality of pixels, and appropriate boundary bit positions at which the coefficients whose non-zero upper bit part is non-zero have a desired ratio To decide. As a result, encoding efficiency can be improved.

[Second Embodiment]
In the first embodiment and the modification thereof, boundary bits are set for each block so that the number of coefficients for which the upper bit part of the coefficient value after quantization is zero is close to a predetermined ratio. Encoding was performed. However, although this boundary bit position selection can be expected to have a certain degree of efficiency, it cannot always be said that the minimum code amount is promised. This is because the efficiency of run-length encoding cannot be increased when the plurality of non-zero higher-order bit portions Un are not continuously located but at discrete positions.

  Therefore, in the second embodiment, an example in which encoding processing is performed at the boundary bit position B output from the boundary bit determination unit and the boundary bit position B-1 in the vicinity thereof and the one with the smaller code amount is selected. Will be described.

In the second embodiment, the image data to be encoded is monochrome image data for simplicity of explanation, but may be applied to RGB image data or CMYK color image data. The image is assumed to be composed of horizontal W pixels and vertical H pixels. Further, the description will be made assuming that the size of the rectangular block in the processing unit is also 8 × 8 pixel size.

FIG. 9 shows a block diagram of an image encoding apparatus according to the second embodiment. The difference between FIG. 9 and FIG. 1 is that the coefficient encoding unit 117 in FIG. 1 is replaced with the coefficient encoding unit 900 in FIG. Therefore, the description of the elements having the same reference numerals as those in FIG. 1 is omitted.

  The coefficient encoding unit 900 includes an upper bit / lower bit separation unit 901, two upper bit encoding units 902 and 903, a lower bit encoding unit 904, a code buffer 907, and a code selection unit 906. Similar to the coefficient encoding unit 117 described in the first embodiment, the coefficient encoding unit 900 uses the boundary bit position B from the boundary bit position determination unit 116 and the coefficient data Cn of the rectangular block from the coefficient buffer 105. input.

  In the upper / lower bit separation unit 901, for the coefficient data Cn of interest, the first upper bit part obtained by removing the lower B bits in the code absolute value expression, and the second obtained by removing the lower B-1 bits. Are divided into an upper bit portion and a lower B bit portion.

In the following description, it is assumed that the first upper bit part is represented as U1n and the second upper bit part is represented as U2n. U1n, U2n, and Ln can be represented by equations as follows.
U1n = Cn >> B
U2n = Cn >> (B-1)
Ln = | Cn | & ((1 << B) -1)

  The upper / lower bit separation unit 901 outputs the first upper bit unit U1n to the upper bit encoding unit 902, and outputs the second upper bit unit U2n to the upper bit encoding unit 903. Also, the upper / lower bit separation unit 901 outputs the lower bit part Ln to the lower bit encoding unit 904. For the coefficient Cn whose value represented by the upper bit part U1n excluding the positive / negative sign bits is 0, a sign indicating the sign of the coefficient Cn is passed to the lower bit encoding unit 904. This principle is the same as in the first embodiment.

  The upper bit encoding unit 902 inputs the 64 first upper bit units U1n in the target rectangular block and performs encoding. Also, the upper bit encoding unit 903 inputs 64 second upper bit units U2n in the target rectangular block and performs encoding. These two encoding units are assumed to use the same method as the encoding of DC and AC coefficients in JPEG Baseline, like the high-order bit encoding unit 111 in the first embodiment.

  The encoded data of the first upper bit unit U1n is output from the upper bit encoding unit 902 to the code buffer 905. Also, the upper bit encoding section 903 outputs the encoded data of the second upper bit section U2n to the code buffer 905.

  On the other hand, the lower bit encoding unit 904 encodes the lower bit part Ln of the coefficient output from the upper / lower bit separation unit 901 in the same manner as the lower bit encoding unit 112 in the first embodiment, The lower bit encoded data arranged in order is output to the code buffer 905.

  When the encoding process of all the coefficient values of the target rectangular block is completed as described above, the code selection unit 908 stores the encoded data of the first upper bit unit U1n stored in the code buffer 905, the first Whether the boundary bit position is set to B or B-1 is determined based on the encoded data of the encoded data of the second upper bit part U2n and the encoded data of the lower bit part Ln. Then, based on the determined boundary bit position, encoded data to be output is extracted.

  Now, the code amount of the encoded data of the first upper bit portion U1n is Ca, the code amount of the encoded data of the second upper bit portion U2n is Cb, and the code amount of the encoded data of the lower bit portion Ln is Cc. Define. Further, the code amount of the encoded data obtained by excluding the encoded data of the B-digit bit plane from the encoded data of the lower bit part Ln is defined as Cd.

  Therefore, “Ca + Cc” means the code amount of the rectangular block of interest when the boundary bit position is B. It is clear that “Cb + Cd” means the code amount of the rectangular block of interest when the boundary bit position is B-1.

Therefore, the code selection unit 908 compares “Ca + Cc” with “Cb + Cd”. In accordance with the comparison result, the code selection unit 908 executes the following processing.
When Ca + Cc ≦ Cb + Cd:
The code selection unit 906 selects the encoded data of the first upper bit part U1n and the encoded data of the lower bit part Ln stored in the code buffer 905, and outputs them to the code string forming unit 114. At this time, the code selecting unit 906 outputs a signal indicating that the boundary bit position is B to the code string forming unit 114.
・ When Ca + Cc> Cb + Cd:
The code selection unit 906 stores the encoded data of the second upper bit part U2n stored in the code buffer 905, and the encoded data excluding the encoded data of the B-digit bit plane from the encoded data of the lower bit part Ln. Is output to the code string forming unit 114. At this time, the code selecting unit 906 outputs a signal indicating that the boundary bit position is B-1 to the code string forming unit 114.

  As described above, according to the second embodiment, the upper bit part is encoded using the boundary bit position B and B-1 corresponding to the boundary bit position B, and the one with the smaller code amount of the block is selected. This makes it possible to generate encoded data with a higher compression rate than at least the first embodiment.

  In the second embodiment, the example of comparing the encoded data amounts by the two methods of the boundary bit positions B and B-1 has been described. However, the encoding is performed by the three methods of B + 1, B, and B-1. The encoded data may be compared and the minimum encoded data may be selected. When these three methods are used, B + 1 may be used as a boundary bit position, and the lower bit part may be encoded by the lower bit encoding part. This is because the encoded data of the lower bit portion in the case of the boundary bit positions B and B-1 can be selected from the encoded data obtained by the lower bit encoding portion. If another expression is used, when B ″ = B + 1, it is equivalent to comparing the encoded data amounts for B ″, B ″ −1, and B ″ −2, so this point can be easily understood. I can do it.

<Modification of Second Embodiment>
The processing of the second embodiment can also be realized by a computer program as in the modification of the first embodiment. The apparatus configuration may be the same as that shown in FIG. 13 as the modification of the first embodiment. The processing flow is basically the same as that of the modification of the first embodiment shown in FIG. The only difference is that the encoding process corresponding to the process of the coefficient encoding unit 909 described above is performed in the encoding of the block MB (i) in step S205, and thus detailed description is unnecessary here. Let's go.

  As described above, it is apparent that the present modification can achieve the same operational effects as those of the second embodiment. That is, the upper bit part is encoded using the boundary bit position B and B-1 corresponding to the boundary bit position B, and the one with the smaller code amount of the block is selected. As a result, it is possible to select a boundary bit position that is closer to the optimum, and the amount of code can be reduced.

[Third Embodiment]
In the image coding apparatuses according to the first and second embodiments, the zero coefficient of the upper bit part is calculated from the distribution of the effective bit number of the coefficient so that the run-length coding used for the encoding of the upper bit part functions effectively. Boundary bit B having a predetermined ratio is selected. However, as described above, even when the number of zero coefficients is the same, the encoding efficiency varies depending on whether the non-zero coefficients are solid or distributed, and thus the encoded data according to the second embodiment. Does not promise to be the most efficient. Thus, in the third embodiment, an example will be described in which the boundary bit position is determined in consideration of the distribution of zero coefficients and non-zero coefficients, instead of using only the threshold value derived from the ratio. That is, in the third embodiment, it is detected whether the non-zero coefficients are solid or distributed, and the number of non-zero run lengths (run length is not zero) is counted and used to determine the boundary bit B. A mounting form will be described.

  In the third embodiment, the image data to be encoded is monochrome image data for simplicity of description, but may be applied to RGB image data or CMYK color image data. In addition, the image will be described as having W pixels in the horizontal direction and H pixels in the vertical direction, both of which are integer multiples of 8.

  FIG. 10 shows a block configuration diagram of an image encoding device according to the third embodiment. The difference between FIG. 10 and FIG. 1 is that the boundary bit position determination unit 116 in FIG. 1 is replaced with the boundary bit position determination unit 1000 in FIG. The valid bit number determination unit 106, the frequency table generation unit 107, and the frequency table 108 in the boundary bit position determination unit 1000 are also the same as those in FIG.

  Hereinafter, processing of the boundary bit position determination unit 1000, which is a difference from the third embodiment, will be described. Note that the effective bit number determination unit 106 and the upper / lower bit separation unit 110 in the third embodiment will be described assuming that the order in which the coefficient values Cn are read from the coefficient buffer 105 (scan order) is the same order.

  The boundary bit position determination unit 1000 in FIG. 10 has a configuration in which a non-zero run counter update unit 1001 and a non-zero run counter 1002 are added to the boundary bit position determination unit 116 in FIG. As shown in FIG. 11, the non-zero run counter 1002 holds the number of non-zero runs when each bit position is a boundary bit. The number of non-zero runs at bit position b is denoted as NZ (b). At the start of reading the block, the non-zero run number NZ (b) is set to 0 for all b.

  When the effective bit number determination unit 106 obtains the effective bit number B (Cn) for the input coefficient of interest Cn, the frequency table generation unit 107 performs update processing of the frequency table stored in the frequency table buffer 108. Done.

  On the other hand, the effective bit number B (Cn) is also supplied to the non-zero run counter update unit 1001. The non-zero run counter update unit 1001 holds the number of effective bits B (Cn−1) for the immediately preceding coefficient Cn. When B (Cn)> B (Cn−1), NZ (b) held in the non-zero run counter 1002 is set to “1” for b satisfying B (Cn−1) ≦ b <B (Cn). "Increment only and update.

  For example, consider the case of coefficient values Cn-1 and Cn shown in FIG. When the boundary bit position B is set to 0-3, both upper bits are non-zero, and the upper bit part of Cn is encoded as a non-zero coefficient after a zero-length zero run. On the other hand, when the boundary bit position B is set to 4 or 5, the upper bits of Cn-1 are zero, but the upper bits of Cn are not zero, so Cn is after a zero run with a non-zero run length. It is encoded as a subsequent non-zero coefficient. Therefore, the non-zero run number NZ (b) is incremented for bits b = 4 and 5. When the boundary bit position B is set to 6 or more, the upper bits of both Cn-1 and Cn are zero and are not changed.

  By performing the above processing on the block of interest, the number of non-zero runs when each bit is a boundary bit is counted.

  The boundary bit selection unit 1003 first converts from the frequency table to the cumulative frequency table in the same manner as the boundary bit selection unit 109 described in the first embodiment, and the number of occurrences of non-zero coefficients in the upper bit part The provisional boundary bit position B ′ is determined by comparing with a threshold value represented by a desired ratio, and is not supplied to the coefficient encoding unit 117 at this stage (in the first embodiment, the boundary obtained at this stage) The bit position was supplied to the coefficient encoding unit 117).

  The boundary bit selection unit 1003 obtains NZ (B ′) by referring to the non-zero run counter 1002 using the provisional boundary bit position B ′. Then, the boundary bit selection unit 1003 compares the obtained NZ (B ′) with preset threshold values Th2 and Th3. Here, it is assumed that the relationship between the threshold values Th3 and Th2 is a relationship of Th3 <Th2.

  If NZ (B ′)> Th2, it is indicated that there is a state in which non-zero coefficients are dispersed when the boundary bit position B ′ is a boundary bit. In other words, if more boundary bits are set in the lower direction, it means that efficient run-length encoding cannot be performed. Therefore, when NZ (B ′)> Th2, the boundary bit selection unit 1003 supplies B ′ + 1 to the coefficient encoding unit 117 as the final boundary bit position B.

  Further, assuming that NZ (B ′) <Th3, the coefficients that are non-zero when the temporary boundary bit position B ′ is a boundary bit are dense (continuous). In other words, even if the boundary bit position is further changed in the lower bit direction, it means that efficient run-length encoding can be expected. Therefore, when NZ (B ′) <Th3, the boundary bit selection unit 1003 supplies B′−1 to the coefficient encoding unit 117 as the final boundary bit position B.

  When the relationship Th3 ≦ NZ (B ′) ≦ Th2 is satisfied, the boundary bit selection unit 1003 supplies the provisional boundary bit position B ′ to the coefficient encoding unit 117 as the final boundary bit position B.

  As described above, according to the third embodiment, the run-length code is obtained by determining the distribution status of zero and non-zero coefficients in the upper bit part at the boundary bit candidate position and selecting the boundary bit. Can be made to function more efficiently.

<Modification of Third Embodiment>
The processing of the third embodiment can also be realized by a computer program as in the processing of the first and second embodiments. The apparatus configuration may be the same as that shown in FIG. 13 as the modification of the first embodiment. The processing flow is basically the same as that of the modification of the first embodiment shown in FIG. The only difference is the boundary bit determination in step S204 and the internal processing of encoding block MB (i) in step S205. That is, as described above, in step S204, processing corresponding to the boundary bit position determination unit 1004 is performed, and in step S205, encoding processing corresponding to the coefficient encoding unit 909 described in the second embodiment is performed. Is called.

  Therefore, it will be apparent that the present modification can also achieve the same operational effects as the third embodiment. That is, run length coding can be efficiently functioned by determining the distribution of the zero and non-zero coefficients in the upper bit part at the temporary boundary bit position and adjusting the temporary boundary bit position.

[Other Embodiments]
In each of the above embodiments, an example in which a method similar to JPEG Baseline is used for encoding the upper bit part has been described. However, it is easy to understand that various modifications are possible as long as run-length coding is used to transmit zero and non-zero information. In the above-described embodiment, the boundary bit position is determined using 8 × 8 pixels as a block. However, a minimum coding unit is configured by several groups of 8 × 8 blocks, such as MCU in JPEG, and each of which has a boundary bit. May be set. Alternatively, the image may be divided into tiles in advance, and the boundary bit position may be determined for each tile.

  In the embodiments, encoding of monochrome image data has been described as an example. However, it is apparent that the color space of an image can be applied to various types of image data such as RGB, CMYK, Lab, and YCrCb. The present invention is not limited by the number of color components and the type of color space.

  Further, the computer program is usually stored in a computer-readable storage medium such as a CD-ROM, and can be executed by setting it in a computer reader (CD-ROM drive) and copying or installing it in the system. Become. Therefore, it is obvious that such a computer-readable storage medium falls within the scope of the present invention.

It is a block block diagram of the image coding apparatus which concerns on 1st Embodiment. It is a flowchart which shows the encoding process procedure of the modification in 1st Embodiment. It is a flowchart which shows the process sequence of boundary bit position determination of the modification in 1st Embodiment. It is a figure which shows the example of a frequency table. It is a figure which shows the example of a cumulative frequency table. It is a figure which shows the outline of the bit separation of a coefficient. It is a figure which shows the example of low-order bit encoding data. It is a figure which shows the data structure of the encoding data file produced | generated in 1st Embodiment. It is a block block diagram of the image coding apparatus which concerns on 2nd Embodiment. It is a block block diagram of the image coding apparatus which concerns on 3rd Embodiment. 5 is a diagram showing an outline of a counter held in a non-zero run counter 1002. FIG. It is a figure which shows the example of the coefficient Cn and the coefficient Cn-1 immediately before. It is a block block diagram of the information processing apparatus which concerns on the modification of 1st Embodiment.

Claims (7)

An image encoding device that performs frequency conversion and quantization processing in units of pixel blocks from multivalued image data, and encodes each multivalued coefficient obtained by the quantization processing,
Counting means for detecting the number of effective bits from the bit position that first becomes “1” from the most significant bit to the least significant bit to the least significant bit for each coefficient and counting the number of occurrences of each effective bit number; ,
The number of occurrences of the number of effective bits B is defined as N (B), the maximum number of effective bits with the number of occurrences of 1 or more is defined as bmax, and the summation function of the following equation for the variable b = 0, 1, 2,.
S (bmax−b) = ΣN (bmax−i) (i = 0, 1,..., B)
In relation to the preset threshold value Th,
S (bmax−b)> Th
Boundary bit position determination means for determining a boundary bit position based on the maximum integer b;
Separating means for separating the values of the respective coefficients into upper bit parts and lower bit parts with the boundary bit position calculated by the boundary bit position determining means as a boundary;
Upper bit encoding means for encoding the upper bit portion of each coefficient separated by the separation means;
Low-order bit encoding means for encoding the low-order bit part of each coefficient separated by the separation means;
An image encoding device comprising: output means for generating and outputting encoded data of a pixel block of interest from encoded data obtained by the upper bit encoding means and the lower bit encoding means, respectively. . The upper bit encoding means is a run-length encoding means for encoding a combination of a continuous number of zeros and a non-zero value,
The image coding according to claim 1, wherein the lower bit encoding means is means for converting and outputting bit information at the same bit position of the lower bit part of each coefficient to a concatenated bit plane. apparatus. The separating means includes a first upper bit part higher than the boundary bit position calculated by the boundary bit position determining means, a second upper bit part higher than the boundary bit position-1, and the boundary bit position below Separated from the lower bit part of
The upper bit encoding means encodes the first upper bit part and the second upper bit part,
The output means includes
The code amount of the first upper bit part is Ca, the code amount of the second upper bit part is Cb, the code amount of the lower bit part is Cc, and the encoded data of the lower bit part is used as the boundary. When the code amount of the encoded data excluding the encoded data of the bit plane at the bit position is defined as Cd,
When Ca + Cc ≦ Cb + Cd, the encoded data of the first higher-order bit part obtained by the higher-order bit encoding means and the encoded data obtained by the lower-order bit encoding means are encoded data of the pixel block of interest. Output as
In the case of Ca + Cc> Cb + Cd, the encoded data obtained by excluding the encoded data of the bit plane at the boundary bit position from the encoded data obtained by the lower bit encoding means, and the above obtained by the upper bit encoding means The image encoding device according to claim 2, wherein the encoded data of the second upper bit part is output as encoded data of the pixel block of interest. And counting means for counting the number of non-zero runs in the upper bit part of each coefficient when each bit position is a boundary bit position based on each coefficient in the block of interest;
The number of non-zero runs of the boundary bit position calculated by the boundary bit position determining means is compared with a preset threshold value, and based on the comparison result, the boundary bit position calculated by the boundary bit position determining means The image encoding apparatus according to claim 1, further comprising: an adjusting unit that adjusts. A control method for an image encoding device that performs frequency conversion and quantization processing in units of pixel blocks from multi-value image data, and encodes each multi-value coefficient obtained by the quantization processing,
A counting step of detecting the number of effective bits from the bit position that first becomes “1” from the most significant bit to the least significant bit to the least significant bit for each coefficient, and counting the number of occurrences of each effective bit number; ,
The number of occurrences of the number of effective bits B is defined as N (B), the maximum number of effective bits with the number of occurrences of 1 or more is defined as bmax, and the summation function of the following equation for the variable b = 0, 1, 2,.
S (bmax−b) = ΣN (bmax−i) (i = 0, 1,..., B)
In relation to the preset threshold value Th,
S (bmax−b)> Th
A boundary bit position determination step for determining a boundary bit position based on the maximum integer b;
A separation step of separating the value of each coefficient into an upper bit part and a lower bit part with the boundary bit position calculated in the boundary bit position determination step as a boundary;
An upper bit encoding step for encoding the upper bit portion of each coefficient separated in the separation step;
A lower bit encoding step for encoding the lower bit portion of each coefficient separated in the separation step;
The upper bit encoding step, wherein the lower bit encoding step the coded data obtained for each to generate encoded data of the pixel of interest block, the image coding apparatus and an outputting step of outputting Control method.   A computer program that causes a computer to function as the image encoding device according to claim 1 by being read and executed by a computer.   A computer-readable storage medium storing the computer program according to claim 6.

Images