JP4928789B2 - Liquid crystal display - Google Patents

Description

  In the present invention, for example, gradation display corresponding to a video signal and non-gradation display corresponding to black or a specific halftone not corresponding to the video signal are performed for each frame period, and these gradation display and non-gradation display are respectively supported. The present invention relates to a liquid crystal display device that blinks a backlight.

  A flat display device typified by a liquid crystal display device is widely used to display an image in a computer, a car navigation system, a television receiver, or the like. A liquid crystal display device generally includes a liquid crystal display panel including a matrix array of a plurality of liquid crystal pixels, a backlight that illuminates the liquid crystal display panel, and a display control circuit that controls the display panel and the backlight. The liquid crystal display panel has a structure in which a liquid crystal layer is sandwiched between an array substrate and a counter substrate.

  The array substrate has a plurality of pixel electrodes arranged in a substantially matrix, a plurality of gate lines arranged along a row of the plurality of pixel electrodes, a plurality of source lines arranged along a column of the plurality of pixel electrodes, and a plurality of And a plurality of switching elements arranged in the vicinity of the intersection position of the plurality of gate lines and the plurality of source lines. Each switching element is made of, for example, a thin film transistor (TFT), and conducts when one gate line is driven to apply the potential of one source line to one pixel electrode. A common electrode is provided on the counter substrate so as to face the plurality of pixel electrodes arranged on the array substrate. The pair of pixel electrodes and the common electrode constitute a pixel together with a pixel region which is a part of the liquid crystal layer located between these electrodes, and the liquid crystal molecule arrangement is controlled by an electric field between the pixel electrode and the common electrode in the pixel region. The display control circuit includes a gate driver that drives a plurality of gate lines, a source driver that drives a plurality of source lines, and a controller circuit that controls these gate drivers, source drivers, and backlights.

  In the case where the liquid crystal display device is mainly used for a television receiver that displays a moving image, use of an OCB mode liquid crystal display panel in which liquid crystal molecules exhibit good response has been studied (see Patent Document 1). In this liquid crystal display panel, the liquid crystal is in a splay alignment in which the liquid crystal is almost asleep before power-on by an alignment film rubbed in parallel with each other on the pixel electrode and the common electrode. The liquid crystal display panel performs a display operation after the liquid crystal is changed from the splay alignment to the bend alignment by a relatively strong electric field applied in the initialization process when the power is turned on.

  The reason why the liquid crystal is in the splay alignment before the power is turned on is that the splay alignment is energetically more stable than the bend alignment when no liquid crystal driving voltage is applied. Once such a liquid crystal transitions to bend alignment, it reversely transitions back to splay alignment when a voltage application state below the level at which splay alignment energy and bend alignment energy antagonize or when no voltage is applied for a long period of time. It has the property of end up. In the splay alignment, the viewing angle characteristics are significantly different from the bend alignment, resulting in abnormal display.

Conventionally, in order to prevent reverse transition from bend alignment to splay alignment, for example, a driving method in which a large liquid crystal driving voltage is applied to the liquid crystal in a part of a frame period for displaying an image of one frame is employed. In a normally white liquid crystal display panel, this liquid crystal drive voltage corresponds to a black display voltage, and is therefore referred to as black insertion drive.
JP 2002-202491 A

  By the way, since the liquid crystal display panel is a hold type display device that holds the display state until the image data is updated, it is difficult to smoothly show the movement of the object due to the influence of the retinal afterimage generated in the observer's vision in moving image display. The above-described black insertion drive is effective in improving the visibility of the moving image, which is deteriorated by the observer's vision, because the retinal afterimage is cleared by changing the pixel luminance to a pseudo discrete impulse response waveform. In order to prevent the reverse transition described above, the black insertion rate is normally set to about 25% as a ratio of the black insertion period (non-gradation display period) in one frame period, but this black insertion rate is increased to about 50%. As a result, it is possible to obtain a moving image visibility that is comparable to a CRT and has no sense of incongruity.

  The backlight may be blinking driven to turn on during the gradation display period and turn off during the black insertion period. In the case of performing the blinking drive, if the black insertion rate is increased, the ratio of the liquid crystal response period to the backlight lighting time is increased. For this reason, there is a problem in that the color purity of red, green, and blue is deteriorated and the color reproduction range is narrowed. Also, the contrast is lowered for the same reason.

  Conventionally, the backlight is controlled to be turned off at the start timing of the black insertion period and turned on at the end timing of the black insertion period. This control is the same even when the black insertion rate is switched from 25% shown in FIG. 8 to 50% shown in FIG. For this reason, when the black insertion rate is 50%, the component ratio of the liquid crystal response portion (the portion where the modulation factor waveform is inclined immediately after the start and the end of the black insertion period) is larger than when the black insertion rate is 25%. As a result, color reproducibility and contrast are lowered.

  An object of the present invention is to provide a liquid crystal display device capable of improving the color reproducibility and the decrease in contrast accompanying the improvement of the moving image visibility.

According to the present invention, a liquid crystal display unit that performs non-gradation display that does not correspond to the gradation display and the video signal corresponding to a video signal periodically, illuminated corresponds to non-gradation display corresponding to the gray scale display An illumination light source that is turned off , and a light source control unit that controls a lighting time of the illumination light source that occupies a liquid crystal response period of the liquid crystal display unit required for transition between gradation display and non-gradation display , the relative increase in the non-gradation display insertion rate of the liquid crystal display unit LCD device you reduce the lighting time of the illumination light source occupying a liquid crystal response period is provided.

  In this liquid crystal display device, the light source control unit controls the lighting time of the illumination light source in the liquid crystal response period of the liquid crystal display unit required for transition between gradation display and non-gradation display. This control shortens the lighting time of the illumination light source in the liquid crystal response period of the liquid crystal display unit or increases the lighting time of the illumination light source in the liquid crystal response period of the liquid crystal display unit with respect to an increase in the insertion rate of non-gradation display. It can be lost. Therefore, even if the non-gradation display insertion rate is increased, the color reproducibility range and the contrast stability can be ensured. That is, it is possible to improve the color reproducibility and the decrease in contrast accompanying the improvement of the moving image visibility.

  Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 schematically shows a circuit configuration of the liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel DP, a backlight BL that illuminates the display panel DP, and a display control circuit CNT that controls the display panel DP and the backlight BL. The liquid crystal display panel DP has a structure in which a liquid crystal layer 3 is sandwiched between an array substrate 1 and a counter substrate 2 which are a pair of electrode substrates. The liquid crystal layer 3 is a liquid crystal in which, for example, a normally white display operation is previously transitioned from a splay alignment to a bend alignment, and a reverse transition from the bend alignment to the splay alignment is periodically applied and blocked by a voltage that causes black display. As a liquid crystal material. The display control circuit CNT controls the transmittance of the liquid crystal display panel DP by the liquid crystal driving voltage applied from the array substrate 1 and the counter substrate 2 to the liquid crystal layer 3. The transition from the splay alignment to the bend alignment can be obtained by applying a relatively large electric field to the liquid crystal by a predetermined initialization process performed by the display control circuit CNT when the power is turned on.

  FIG. 2 shows the cross-sectional structure of the liquid crystal display panel DP in detail. The array substrate 1 includes a transparent insulating substrate GL made of a glass plate or the like, a plurality of pixel electrodes PE formed on the transparent insulating substrate GL, and an alignment film AL formed on the pixel electrodes PE. The counter substrate 2 is a transparent insulating substrate GL made of a glass plate or the like, a color filter layer CF formed on the transparent insulating substrate GL, a common electrode CE formed on the color filter layer CF, and on the common electrode CE. It includes an alignment film AL to be formed. The liquid crystal layer 3 is obtained by filling the gap between the counter substrate 2 and the array substrate 1 with liquid crystal. The color filter layer CF includes a red coloring layer for red pixels, a green coloring layer for green pixels, a blue coloring layer for blue pixels, and a black coloring (light-shielding) layer for black matrix. In FIG. 2, the liquid crystal molecules are in a splay alignment state. The liquid crystal display panel DP includes a pair of retardation plates RT arranged outside the array substrate 1 and the counter substrate 2, a pair of polarizing plates PL arranged outside the retardation plates RT, and the array substrate 1 side. A light source backlight BL is provided outside the polarizing plate PL. The alignment film AL on the array substrate 1 side and the alignment film AL on the counter substrate 2 side are rubbed in parallel with each other. Thereby, the pretilt angle of the liquid crystal molecules is set to about 10 °.

  In the array substrate 1, a plurality of pixel electrodes PE are arranged in a substantially matrix shape on the transparent insulating substrate GL. In addition, a plurality of gate lines Y (Y1 to Ym) are arranged along the rows of the plurality of pixel electrodes PE, and a plurality of source lines X (X1 to Xn) are arranged along the columns of the plurality of pixel electrodes PE. . A plurality of pixel switching elements W are arranged in the vicinity of the intersection position of the gate line Y and the source line X. Each pixel switching element W is formed of a thin film transistor in which a gate is connected to the gate line Y and a source-drain path is connected between the source line X and the pixel electrode PE, and corresponds to when driven through the corresponding gate line Y. Conduction is established between the source line X and the corresponding pixel electrode PE.

 Each pixel electrode PE and common electrode CE is made of a transparent electrode material such as ITO, for example, and is covered with an alignment film AL and controlled to a liquid crystal molecular arrangement corresponding to the electric field from the pixel electrode PE and common electrode CE. A liquid crystal pixel PX is configured together with a pixel region that is a part of the pixel area.

  Each of the plurality of liquid crystal pixels PX has a liquid crystal capacitance CLC between the pixel electrode PE and the common electrode CE. The plurality of auxiliary capacitance lines C1 to Cm are each capacitively coupled to the pixel electrode PE of the liquid crystal pixel PX in the corresponding row to form an auxiliary capacitance Cs. The auxiliary capacitor Cs has a sufficiently large capacitance value with respect to the parasitic capacitance of the pixel switching element W.

  The display control circuit CNT includes a gate driver YD that sequentially drives the plurality of gate lines Y1 to Ym so that the plurality of switching elements W are conducted in units of rows, and a period in which the switching elements W in each row are conducted by driving the corresponding gate lines Y. , A source driver XD for outputting the pixel voltage Vs to the plurality of source lines X1 to Xn, a backlight driver LD for driving the backlight BL, a driving voltage generating circuit 4 for generating a driving voltage for the display panel DP, and A controller circuit 5 that controls the gate driver YD, the source driver XD, and the backlight driver (inverter) LD is provided.

  The driving voltage generation circuit 4 generates a compensation voltage generation circuit 6 that generates a compensation voltage Ve applied to the auxiliary capacitance line C through the gate driver YD, and a predetermined number of gradation reference voltages VREF used by the source driver XD. And a common voltage generating circuit 8 for generating a common voltage Vcom applied to the counter electrode CT. The controller circuit 5 includes a vertical timing control circuit 11 for generating a control signal CTY for the gate driver YD based on a synchronization signal SYNC (VSYNC, DE) and a black insertion rate setting signal BKS input from the external signal source SS, an external signal source The horizontal timing control circuit 12 that generates the control signal CTX for the source driver XD based on the synchronization signal SYNC (VSYNC, DE) input from the SS, and the image data input from the external signal source SS to the plurality of pixels PX For example, a backlight drive unit (inverter) based on the image data conversion circuit 13 that performs black insertion double speed conversion, the control signal CTX output from the vertical timing control circuit 11, and the black insertion rate setting signal BKS from the external signal source SS. Includes inverter control circuit 14 for controlling LDThe image data includes a plurality of pixel data DI for a plurality of liquid crystal pixels PX, and is updated every frame period (vertical scanning period V). The control signal CTY is supplied to the gate driver YD, and the control signal CTX is supplied to the source driver XD together with the pixel data DO obtained as a conversion result from the image data conversion circuit 13. The control signal CTY is used to cause the gate driver YD to sequentially drive the plurality of gate lines Y as described above, and the control signal CTX is the liquid crystal pixel PX for one row as the conversion result of the image data conversion circuit 13. The pixel data DO obtained in units and output in series are assigned to a plurality of source lines X and used to cause the source driver XD to perform an operation of designating output polarity.

  The gate driver YD and the source driver XD are configured using, for example, a shift register circuit in order to select the plurality of gate lines Y and the plurality of source lines X, respectively. In this case, the control signal CTY includes a first start signal (gradation display start signal) STHA for controlling the gradation display start timing, a second start signal (black insertion start signal) STHB for controlling the black insertion start timing, and a shift register. A clock signal for shifting the start signals STHA and STHB in the circuit, and a drive signal to the gate lines Y1 to Ym that are sequentially or together selected by the shift register circuit corresponding to the holding positions of the start signals STHA and STHB Including an output enable signal for controlling the output of. On the other hand, the control signal CTX is generated by the shift register circuit corresponding to the start signal for controlling the start timing of taking in the pixel data for one row, the clock signal for shifting the start signal in the shift register circuit, and the holding position of the start signal. A load signal for controlling the parallel output timing of one row of pixel data DO taken in for each of the source lines X1 to Xn selected one by one, and a polarity signal for controlling the signal polarity of the pixel voltage Vs corresponding to the pixel data Etc.

  The gate driver YD sequentially selects a plurality of gate lines Y1 to Ym for black insertion and gradation display in one frame period under the control of the control signal CTY, and turns on voltage as a drive signal for conducting the pixel switching elements W in each row. The selected gate line Y is supplied. When the image data conversion circuit 13 performs black insertion double speed conversion, one row of black insertion fixed pixel data B and one row of input pixel data DI corresponding to one row become output pixel data DO every 1H. It is converted to variable display pixel data S for tone display. The gradation display variable pixel data S has the same gradation value as the pixel data DI, and the black insertion fixed pixel data B has a gradation value of black display or specific halftone display close to black display. The black insertion fixed pixel data B for one row and the gradation display variable pixel data S for one row are respectively output in series from the image data conversion circuit 13 in the H / 2 period. The source driver XD refers to a predetermined number of gradation reference voltages VREF supplied from the gradation reference voltage generation circuit 7 to convert the pixel data B and S into pixel voltages Vs, respectively. Output to Xn in parallel.

  The pixel voltage Vs is a voltage applied to the pixel electrode PE on the basis of the common voltage Vcom of the common electrode CE, and the polarity is inverted with respect to the common voltage Vcom so as to perform, for example, frame inversion driving and line inversion driving. When black insertion driving is performed at the double vertical scanning speed, the polarity is inverted with respect to the common voltage Vcom so as to perform, for example, line inversion driving and frame inversion driving (1H1V inversion driving). The compensation voltage Ve is applied via the gate driver YD to the auxiliary capacitance line C corresponding to the gate line Y connected to the switching elements W when the switching elements W for one row are turned off. This is used to compensate for variations in the pixel voltage Vs generated in the pixels PX for one row due to the parasitic capacitance of the element W.

  When the gate driver YD drives, for example, the gate line Y1 with the on-voltage to make all the pixel switching elements W connected to the gate line Y1 conductive, the pixel voltage Vs on the source lines X1 to Xn is changed to these pixel switching elements W. To the corresponding pixel electrode PE and one end of the auxiliary capacitor Cs. The gate driver YD outputs the compensation voltage Ve from the compensation voltage generation circuit 6 to the auxiliary capacitance line C1 corresponding to the gate line Y1, and immediately after the conduction period of all the pixel switching elements W connected to the gate line Y1. In addition, an off voltage that makes these pixel switching elements W non-conductive is output to the gate line Y1. The compensation voltage Ve reduces the electric charge drawn from the pixel electrode PE by these parasitic capacitances when these pixel switching elements W become non-conductive, and substantially cancels the fluctuation of the pixel voltage Vs, that is, the punch-through voltage ΔVp.

  For example, the operation of the liquid crystal display device will be described in the case where black insertion driving is performed at a double vertical scanning speed. Here, both the first start signal STHA and the second start signal STHB are pulses input to the gate driver YD with a pulse width corresponding to the H / 2 period. The first start signal STHA is input first, and the second start signal STHB is input later than the first start signal STHA according to the black insertion rate. The black insertion rate is a holding period of a fixed pixel voltage for black insertion (that is, a black insertion period, in other words, a non-gradation display period) with respect to a holding period of a variable pixel voltage for gradation display (that is, a gradation display period) The ratio of the black insertion period in one frame period (1V: vertical scanning period).

  The gate driver YD shifts the first start signal STHA to select one of the plurality of gate lines Y1 to Ym per horizontal scanning period H and drive signals to the gate lines Y1, Y2, Y3,... In the second half of the 1H period. Is output. On the other hand, the source driver XD converts each of the gradation display variable pixel data S, S, S,... Into the pixel voltage Vs in the second half of the corresponding 1H period, and converts them to the source line with the polarity inverted every 1H. Output in parallel to X1 to Xn. These pixel voltages Vs are supplied to the liquid crystal pixels PX in the first row, the second row, the third row, the fourth row, etc. while each of the gate lines Y1 to Ym is driven in the second half of the corresponding 1H period.

  Further, the gate driver YD shifts the second start signal STHB to select a plurality of gate lines Y1 to Ym one by one per horizontal scanning period H, and to the gate lines Y1, Y2, Y3,... In the first half of the 1H period. A drive signal is output. On the other hand, the source driver XD converts each of the black-inserted fixed pixel data B, B, B,... Into the pixel voltage Vs in the first half of the corresponding 1H period, and converts them to the source line X1 with the polarity inverted every 1H. Output in parallel to ~ Xn. These pixel voltages Vs are supplied to the first, second, third,... Liquid crystal pixels PX while each of the gate lines Y1 to Ym is driven in the first half of the corresponding 1H period.

  FIG. 3 shows the relationship between the backlight BL and the display panel DP shown in FIG. The display screen DS shown in FIG. 4 includes a plurality of liquid crystal pixels PX arranged in a matrix. The backlight BL is composed of, for example, k backlight light sources LP arranged at a predetermined pitch in parallel with the rows of the plurality of liquid crystal pixels PX on the back surface of the display panel DP. These backlight light sources LP mainly illuminate each of a plurality of display areas in which the screen DS is equally divided in the vertical direction. Each of these backlight light sources LP is composed of one cold cathode tube. In the actual display panel DP, the screen DS is divided into, for example, 24 display areas, and each display area is set to include liquid crystal pixels PX for approximately 25 rows (lines). In this case, each of the 24 cold-cathode tubes illuminates about 25 rows of liquid crystal pixels PX as an illumination target. Each backlight light source LP can be composed of a plurality of cold cathode tubes.

  When the black insertion rate = 25% is set by the black insertion rate setting signal BKS, the inverter control circuit 14 performs control for blinking the corresponding backlight light source LP as shown in FIG. When the black insertion rate = 50% is set by the black insertion rate setting signal BKS, control is performed to cause the corresponding backlight light source LP to blink as shown in FIG. That is, when the black insertion rate is 25%, the backlight light source LP is turned off (OFF) at the start timing of the black insertion period and turned on (ON) at the end timing of the black insertion period. When the black insertion rate is 50%, the backlight source LP is turned off at the start timing of the black insertion period, and is turned on after the end timing of the black insertion period. The lighting delay time of the backlight light source LP is a liquid crystal response period in a display area required for transition from black display (non-gradation display) to gradation display. As a specific example, when an OCB liquid crystal pixel PX having a cell gap between the pixel electrode PE and the common electrode CE = 4.5 μm and a pretilt angle = 10 ° is driven at 60 Hz, this lighting delay time is the end of the black insertion period. 3 msec for the timing.

  In the present embodiment, the control of the inverter control circuit 14 shortens the lighting time of the backlight light source LP that occupies the liquid crystal response period in the display area with respect to the increase in the black insertion rate. As a result, a color reproduction range of 72% similar to the case where the black insertion rate = 25% can be obtained, and the contrast can be maintained at 600: 1.

  In addition, this invention is not limited to the above-mentioned embodiment, It can deform | transform variously in the range which does not deviate from the summary.

  In the above-described embodiment, the black insertion rate is changed between two values of 25% and 50%. However, the black insertion rate is set to, for example, 25%, 30%, 35%, 40%, 50% by the setting signal BKS. It may be set as 60%. In this case, the color reproduction range and contrast stability can be obtained by delaying the lighting timing of the backlight source LP with respect to the end timing of the black insertion period as the black insertion rate increases.

  In the above-described embodiment, the backlight light source LP is turned off at the start timing of the black insertion period regardless of whether the black insertion rate is 25% or 50%, but the black insertion rate is as low as 25%. In this case, the timing of turning off the backlight light source LP is delayed from the start timing of the black insertion period so that it falls within the liquid crystal response period of the display area required for transition from gradation display to black display (non-gradation display). The same effect can be obtained by controlling the extinguishing timing to approach the start timing of the black insertion period as the insertion rate increases.

  Since the color reproducibility and contrast decrease become prominent when the black insertion rate is increased to 40% or more, the above-described control is extremely effective.

  Further, when the black insertion rate = 25% is set by the black insertion rate setting signal BKS, the inverter control circuit 14 causes the corresponding backlight light source LP to blink as shown in FIG. 6 for the black insertion driving of each display area. When the black insertion rate = 50% is set by the black insertion rate setting signal BKS, the corresponding backlight light source LP is controlled to blink as shown in FIG. May be. That is, regardless of whether the black insertion rate is 25% or 50%, the backlight light source LP is turned off (OFF) at the start timing of the black insertion period and is turned on after the end timing of the black insertion period. The lighting delay time of the backlight light source LP is a liquid crystal response period in the display area required for sure transition from black display (non-gradation display) to gradation display. As a specific example, when an OCB liquid crystal pixel PX having a cell gap between the pixel electrode PE and the common electrode CE = 4.5 μm and a pretilt angle = 10 ° is driven at 60 Hz, this lighting delay time is the end of the black insertion period. The timing is 4 msec, which is longer than 3 msec in the above-described embodiment. In this modification, the backlight light source LP has a liquid crystal response period of a display area required for transition from gradation display to black display (non-gradation display) and from black display (non-gradation display) to gradation display. In most cases, the light is kept off. If the backlight light source LP is turned off in the liquid crystal response period of the display area in this way, the light from the backlight light source LP is blocked for the liquid crystal response part with poor color reproducibility, and the color reproducibility ( Color purity) can be maintained. Actually, even if the black insertion rate was varied in the range of 10% to 50%, a color reproducibility range of approximately 72% could be obtained.

  Since the color reproducibility and the decrease in contrast become significant when the black insertion rate is increased to 40% or more as described above, the control of this modification is also extremely effective.

  Incidentally, in the above-described embodiment, the plurality of backlight light sources LP are provided as the backlight BL. However, the fixed pixel voltage for black insertion is sequentially held in the liquid crystal pixels PX in all rows, and this is used for the subsequent gray scale display. When the black insertion driving for sequentially holding the variable pixel voltages in all the rows of liquid crystal pixels PX is performed for each frame period, a single backlight light source for illuminating the entire display screen DP is provided as the backlight BL, It is also possible to perform the above-described control for this backlight light source.

It is a figure which shows schematically the circuit structure of the liquid crystal display device which concerns on one Embodiment of this invention. It is a figure which shows the cross-section of the liquid crystal display panel shown in FIG. It is a figure which shows the relationship between the backlight shown in FIG. 1, and a display panel. It is a figure which shows the blink timing of the backlight light source with respect to the black insertion drive performed with the black insertion rate = 25% in the liquid crystal display device shown in FIG. It is a figure which shows the blink timing of the backlight light source with respect to the black insertion drive performed with the black insertion rate = 50% in the liquid crystal display device shown in FIG. It is a figure which shows the blink timing of the backlight light source with respect to the black insertion drive performed by the black insertion rate = 25% in the modification of the liquid crystal display device shown in FIG. It is a figure which shows the blink timing of the backlight light source with respect to the black insertion drive performed by the black insertion rate = 50% in the modification of the liquid crystal display device shown in FIG. It is a figure which shows the blink timing of the backlight with respect to the black insertion drive performed with the black insertion rate = 25% in the conventional liquid crystal display device. It is a figure which shows the blink timing of the backlight with respect to the black insertion drive performed with the black insertion rate = 50% in the conventional liquid crystal display device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Array substrate, 2 ... Opposite substrate, 3 ... Liquid crystal layer, 4 ... Drive voltage generation circuit, 5 ... Controller circuit, 6 ... Compensation voltage generation circuit, 7 ... Tone reference voltage generation circuit, 8 ... Common voltage generation circuit , 11 ... Vertical timing control circuit, 12 ... Horizontal timing control circuit, 13 ... Image data conversion circuit, 14 ... Inverter control circuit, BL ... Back light, LP ... Back light source, DP ... Liquid crystal display panel, PE ... Pixel electrode, CE ... Common electrode, CLC ... Liquid crystal capacitor, Cs ... Auxiliary capacitor, PX ... Liquid crystal pixel, W ... Switching element, Y ... Gate line, X ... Source line, CNT ... Display control circuit, LD ... Backlight drive unit, YD ... Gate driver, XD ... Source driver.

Claims (5)

A liquid crystal display unit that periodically performs gradation display corresponding to a video signal and non-gradation display not corresponding to the video signal;
An illumination light source that is turned on in response to the gradation display and turned off in response to the non-gradation display;
A light source control unit that controls a lighting time of the illumination light source in a liquid crystal response period of the liquid crystal display unit required for transition between the gradation display and the non-gradation display,
To the light source control unit may increase the non-gradation display insertion rate of the you, characterized in that it is configured to reduce the lighting time of the illumination light source occupying a liquid crystal response period of the liquid crystal display unit liquid Crystal display device. The lighting time of the illumination source, a liquid crystal display device according to claim 1, characterized in that said non-gradation display insertion rate is reduced when it is increased to more than 40%. The lighting time of the illumination source, a liquid crystal display device according to claim 1, characterized in that it is eliminated if the non-gradation display insertion rate was increased to 40% or more.   The liquid crystal display unit includes a plurality of liquid crystal pixels that are bend-aligned for display operation, and that reverse transition from the bend alignment to the splay alignment is prevented by a driving voltage applied for the non-gradation display. The liquid crystal display device according to claim 1.   2. The liquid crystal according to claim 1, wherein the light source control unit turns off the illumination light source at a start timing of the non-gradation display and turns on the illumination light source based on an insertion rate of the non-gradation display. Display device.

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