JP4911510B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to reduction of the number of CBR refresh operations.

  The storage capacity of DRAMs is increasing year by year, and 1G capacity DRAMs are also being prototyped. On the other hand, the technology for reducing the leakage current of DRAM memory cells has been remarkably advanced by efforts to improve the process. However, in reality, the leakage current reduction technology strongly depends on the manufacturing technology level. For example, the first DRAM may only have a hold time of 200 ms, while a second DRAM having the same specifications as the first DRAM may have a hold time of 800 ms.

  However, the specification of the DRAM hold time is set to 64 ms, which can be achieved by any product. Therefore, in a device equipped with a DRAM, a CBR (column address strobe before row address strobe) refresh command for the DRAM address space is issued within 64 ms. In this case, although the second DRAM has a hold time four times that of the first DRAM, the current consumption associated with the CBR refresh operation is equal to that of the first DRAM.

  In connection with the above description, a dynamic semiconductor memory device is described in Japanese Patent Laid-Open No. 7-93971. This conventional dynamic semiconductor memory device has a refresh address generating circuit for generating a refresh address at a constant cycle. The storage unit classifies and stores the refresh address into two or more types by matching the pause time in the refresh address with the shortest bit. On the basis of the stored information, unnecessary period refreshes are omitted for refresh addresses belonging to a category whose pause time is at least twice as long as the refresh address having the shortest pause time. In this way, unnecessary short cycle refresh operation for each address is omitted, and refresh power consumption is reduced.

  A semiconductor memory device is described in JP-A-11-39862. In this conventional example, a row is selected at a cycle shorter than the change cycle of the external signal. The test oscillation circuit generates an internal row address strobe signal by oscillating at a shorter cycle than the refresh oscillation circuit for designating the self-refresh cycle. When the special operation mode is selected, the test oscillation circuit is activated according to the external row address strobe signal (/ RAS), and applies the internal row address strobe signal to the row related control circuit via the selector. In this manner, the internal row address strobe signal is generated with a cycle shorter than the cycle of the row address strobe signal / RAS, and a row is selected.

  A semiconductor memory device is described in JP-A-11-120772. In this conventional example, the bias voltage generator has a self-refresh function that automatically refreshes the data in the memory cells. The bias voltage generator is activated by the activation signal only intermittently during the operation period of the refresh function. After being activated, the activation signal periodically performs a self-refresh operation twice or more. In this way, the bias circuit can operate intermittently in the self-refresh mode, the waiting time ratio is reduced, and a reduction in current is also realized.

  A self-refresh circuit is described in Japanese Patent Laid-Open No. 2000-315385. In this conventional example, the self-refresh circuit includes a binary counter circuit, a selector circuit, and a set / reset signal generation circuit. The selector circuit receives the external address signal and the output signal of the binary counter circuit, and outputs the external address signal as an internal address signal during the read / write cycle period. The selector circuit outputs the output signal of the binary counter circuit as an internal address signal during the self-refresh period. The set / reset signal generation circuit generates a set / reset signal based on the external address signal. The binary counter circuit outputs an output signal sequentially indicating addresses consecutive to the address indicated by the external address signal based on the set / reset signal during the self-refresh period.

  A self-refresh control circuit is described in Japanese Patent Laid-Open No. 2001-6356. In this conventional example, all word intensive refresh after self-refreshing can be eliminated, and extra current consumption is reduced. The timer circuit instructs a predetermined operation timing. The internal binary counter operates at a timing indicated by the timer circuit and determines a ROW address to be used for self-refresh. The counter comparison unit compares the value of the internal binary counter at the start of self-refreshing with the value of the internal binary counter during execution of self-refreshing. When the internal binary counter value at the start of self-refreshing and the currently executed internal binary counter value become the same value, a predetermined potential is output to the external I / O terminal, meaning that centralized refresh is not required.

A semiconductor memory circuit is described in JP-A-2001-283586. In this conventional system, a sufficient restore level is achieved even when using self-refreshing that requires low current consumption. The delay amount switching circuit block switches the delay amount of the RTO signal so as to delay the RTO signal that defines the deactivation of the word line during self-refresh. The signal path B is selected during CBR refresh and the signal path A is selected during self-refresh by the path selection circuit of the delay amount switching circuit block. At the time of self refresh, the RTO signal is delayed by a predetermined time by the signal path A. As a result, the active period of the RASB signal is extended, and the word line selection period is extended. During CBR refresh, signal path B is selected and the RTO signal is not delayed. Therefore, the waveform of the RASB signal is adjusted according to the length of the refresh operation cycle, and an appropriate restore level is achieved.
JP-A-7-93971 JP-A-11-39862 JP-A-11-120772 JP 2000-315385 A JP 2001-6356 A JP 2001-283586 A

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of reducing the number of CBR refresh operations.
Another object of the present invention is to provide a semiconductor memory device capable of achieving a reduction in CBR refresh operation current.
Another object of the present invention is to provide a semiconductor memory device capable of reducing the number of CBR refresh operations to 1 / m (m is an integer of 2 or more) based on the hold characteristic of the memory cell.

  The means for solving the problem will be described below using the numbers and symbols used in the [Embodiments of the Invention]. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and the description of the embodiments of the invention, but are described in [Claims]. It should not be used to interpret the technical scope of the invention.

  In the first aspect of the present invention, a semiconductor memory device includes a memory cell array (127) having a plurality of memory cells and m (m is an integer of 2 or more) times of a CBR (column address strobe before row address strobe) refresh command. The CBR refresh unit (112, 114, 116, 119, 120, 109, 121, 122, 411, 412, 409, 423, 416, which performs a refresh operation on the memory cell array once in response to reception of 418, 422, 424, 428).

  The CBR refresh unit (112, 114, 116, 119, 120, 109, 121, 122) includes a refresh unit (112, 119, 120, 109, 121, 122) for executing a refresh operation and a refresh instruction unit (116). ) And a CBR refresh control unit (114). The CBR refresh control unit (114) sets the refresh instruction unit (116) to the valid state once for m (m is an integer of 2 or more) reception of the CBR refresh command. The refresh instruction unit (116) ignores the CBR refresh command when in the invalid state and responds to the CBR refresh command when in the valid state to the refresh unit (112, 119, 120, 109, 121, 122). Is output. The refresh units (112, 119, 120, 109, 121, 122) perform a refresh operation on the memory cell array in response to a refresh instruction signal.

  Here, the CBR refresh control unit (114) performs the refresh once in response to m times reception of the CBR refresh command based on the data holding circuit (113) that holds control data and the control data. A skip unit (115) for setting the instruction unit (116) to the valid state.

  The skip unit (115) always sets the refresh instruction unit (116) to the valid state when the control data is not held in the data holding circuit (113). The skip unit (115) counts the CBR refresh command when the control data is held in the data holding circuit (113), and counts the refresh instruction once when the CBR refresh command is counted m times. The unit (116) is set to the valid state.

  According to a second aspect of the present invention, a semiconductor memory device includes a memory cell array (426) having a plurality of memory cells, and a CBR (column address strobe before row) for each of the plurality of memory cells in the memory cell array. address strobe) A CBR refresh unit (411, 412, 409, 423, 416, 418, 422, 424, 428) that performs a refresh operation once in response to receiving m (m is an integer of 2 or more) refresh commands. ).

  Here, the CBR refresh unit (411, 412, 409, 423, 416, 418, 422, 424, 428) includes an instruction signal generation unit (416) and a refresh unit (412, 418, 422, 424, 428). And a CBR refresh control unit (114). In this case, the CBR refresh control unit (114) sets the refresh unit to the valid state for each memory cell once for the reception of the CBR refresh command m (m is an integer of 2 or more) times. The instruction signal generator (416) outputs the refresh instruction signal for each memory cell in response to the CBR refresh command. The refresh units (412, 418, 422, 424, 428) perform a refresh operation on the memory cell array in response to the refresh instruction signal in the valid state.

  The CBR refresh control unit (414) includes a data holding circuit (413) that holds control data, and the refresh unit (412) once in response to m times reception of the CBR refresh command based on the control data. , 418, 422, 424, 428) may be included in the valid state.

  The skip unit (115) may always set the refresh units (412, 418, 422, 424, 428) to the valid state when the control data is not held in the data holding circuit (113). good. Alternatively, the skip unit (115) counts the CBR refresh command when the control data is held in the data holding circuit (113), and counts the CBR refresh command once when the CBR refresh command is counted m times. The refresh unit (412, 418, 422, 424, 428) may be set to the valid state.

  In a third aspect of the present invention, a semiconductor memory device includes a memory cell array (327) having a plurality of memory cells, and the memory cell array includes m (m is an integer of 2 or more) array units, and m (m CBR refresh units (112, 114, 316, 119, 120,...) That perform a refresh operation on each of the m array units once in response to receiving the CBR refresh command. 309, 331, 321, 322, 333, 337).

  The CBR refresh unit (112, 114, 316, 119, 120, 309, 331, 321, 322, 333, 337) includes m refresh units (112, 119, 120, 309, 331, 321, 322, 333). 337), a refresh instruction section (116), and a CBR refresh control section (114). In response to receiving the CBR refresh command, the CBR refresh control unit (114) is one of the m refresh units (112, 119, 120, 309, 331, 321, 322, 333, 337). Is set to the valid state. In response to the CBR refresh command, the refresh instructing unit (116) sets the m refresh units (112, 119, 120, 309, 331, 321, 322, 333, 337) in the valid state. The refresh instruction signal is output. Each of the m refresh units (112, 119, 120, 309, 331, 321, 322, 333, 337) refreshes the corresponding one of the m array units in response to a refresh instruction signal. Perform the action.

  The CBR refresh control unit (114) includes a data holding circuit (113) that holds control data, and the m refresh units (112, 119, 120, 309, 331, 321, 322) based on the control data. , 333, 337) includes a skip unit (315) for setting one of the effective states.

  The skip unit (315) includes the m refresh units (112, 119, 120, 309, 331, 321, 322, 333, and 337) when the control data is not held in the data holding circuit (113). ) Are always set to the valid state. The skip unit (315) counts the CBR refresh command when the control data is held in the data holding circuit (113), and the m refresh units (112, 119, 120, 309). , 331, 321, 322, 333, 337) are sequentially set to the valid state.

  Here, the data holding circuit (113) may include a fuse, and the fuse may be cut to hold the control data. At this time, the fuse is preferably cut based on the data retention time of the memory cell.

  Here, the data holding circuit (113) may include a nonvolatile memory, and the control data may be written to the nonvolatile memory. The control data is preferably written in the nonvolatile memory based on the data retention time of the memory cell.

  In the fourth aspect of the present invention, in the semiconductor memory device, execution of a CBR (column address strobe before row address strobe) refresh command is controlled based on the data holding time of each of the plurality of memory cells.

  As described above, the present invention relates to a CBR refresh operation in which a memory refresh operation is executed by a command outside the memory, which is distinguished from a self-refresh operation. One out of m CBR refresh commands from the outside is enabled, particularly one out of two CBR refresh commands.

  Further, it is possible to program whether or not to set the operation to 1/2 times. Therefore, the data setting time of the memory cell is poor, and the operation setting of 1/2 times is not performed for the DRAM which is judged from the result of the holding time test that the operation setting of 1/2 times may cause malfunction. It is possible.

  Conversely, if the initial setting of the memory is set to the prior art in which one internal CBR refresh operation is performed for one CBR refresh command, the result of the hold time test result is that the hold time is longer than a certain reference value. It is possible to perform the operation setting 1/2 times for the DRAM. The CBR refresh operation current can be halved by invalidating the CBR refresh command input from outside every other time.

  INDUSTRIAL APPLICABILITY The present invention is effective for a memory incorporated in a portable device and a memory incorporated in a device in which reducing current consumption of a large-scale server or the like is a technical problem.

  As described above, according to the semiconductor memory device of the present invention, the current consumption can be reduced to about half. The current consumed by the CBR refresh command operation is mainly when the word line is activated, a minute signal on the bit line is amplified, the bit line is charged or discharged to a desired level, and then the word line is reset. Is consumed. For this reason, halving the number of operations makes it possible to reduce the current consumption by about half. Needless to say, a reduction in current consumption leads to an improvement in the characteristics of a device equipped with a semiconductor memory device, and is always an important matter that is required.

  Further, halving the current consumption also means halving the heat generation of the semiconductor memory device, alleviating the temperature rise inside the semiconductor memory device, increasing the hold time of the memory cell, and further, the semiconductor memory device In addition to the inside, it is possible to reduce the rise in the internal temperature of the device in which the semiconductor memory device is mounted, and to prevent malfunction of the mounted device.

  Hereinafter, a semiconductor recording device of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a circuit configuration of the semiconductor memory device according to the first embodiment of the present invention. The semiconductor memory device according to the first embodiment includes a receiver 101-104, an internal clock generation circuit 105, a latch circuit 106-108, a RAS (row address strobe) control circuit group 109, and a CBR (Column before row) refresh control unit 114. Have The semiconductor memory device according to the first embodiment further includes a command decoder 110, a self-refresh determination circuit 111, an internal X address generation circuit 112, an X address counter circuit 119, a refresh signal generation circuit 116, a self timer 117, and an address predecoder circuit. 120, a word line driver group 121, a sense amplifier group 122, and a memory cell 127. The CBR refresh control unit 114 includes a program control circuit 113 and a skip control circuit 115. The program control circuit 113 incorporates a fuse element. The semiconductor memory device includes a memory cell array including a plurality of memory cells 127, and a refresh operation is performed on these memory cells.

  The receiver 101 receives the external clock signal CLK and outputs it to the internal clock generation circuit 105. Internal clock generation circuit 105 generates internal clock signal ICLK in response to signal CLK and outputs it to latch circuits 106-108, command decoder 110, and self-refresh determination circuit 111.

  The receiver 102 receives the row address strobe bar signal RASB, the column address strobe bar signal CASB, the write enable bar signal WEB, and the chip select bar signal CSB, and latches these signals themselves or the logical operation result of those signals. Output to the circuit 106. The latch circuit 106 latches the output from the receiver 102 in response to the internal clock signal ICLK and outputs it to the command decoder 110.

  The receiver 103 receives the clock enable signal CKE and outputs it to the latch circuit 107. The latch circuit 107 latches the output from the receiver 103 in response to the internal clock signal ICLK, and outputs it to the self-refresh determination circuit 111. The receiver 104 receives the external address signal ADD and outputs it to the latch circuit 108. The latch circuit 108 latches the output from the receiver 103 in response to the internal clock signal ICLK and outputs it to the internal X address generation circuit 112.

  Command decoder 110 decodes the output of latch circuit 106 and generates refresh signal RF and address control signal EXAL. The signal EXAL is not output for the CBR refresh command but is output for the self-refresh command. The refresh signal RF is supplied to the self-refresh determination circuit 111, the refresh signal generation circuit 116, and the skip control circuit 115. The address control signal EXAL is supplied to the internal X address generation circuit 112 and the RAS control circuit group 109.

  The skip control circuit 115 generates a refresh skip signal RFSKIP based on the flag signal FG from the program circuit 113 in response to the refresh signal RF. Refresh skip signal RFSKIP is output to refresh signal generation circuit 116. The self-refresh determination circuit 111 determines whether the external command is a CBR refresh command or a self-refresh command based on the clock enable signal CKE and the refresh signal RF. When it is determined as a self-refresh command, the command decoder 110 is notified of the determination result. In addition, a timer start signal is generated in response to the internal clock ICLK and output to the self-timer 117. The self-timer 117 measures time in response to the timer activation signal, and generates an interrupt signal when the time is up. The interrupt signal is output to the refresh signal generation circuit 116.

  The refresh signal generation circuit 116 generates a refresh instruction signal YRF and an address control signal ACBR based on the refresh signal RF, the interrupt signal from the self timer 117, and the refresh skip signal RFSKIP from the skip control circuit 115. The refresh instruction signal YRF is supplied to the RAS control circuit group 109, and the address control signal ABCR is supplied to the internal X address generation circuit 112.

  The X address counter circuit 119 updates the internal address based on an instruction from the internal X address generation circuit 112 and outputs the updated internal address to the internal X address generation circuit 112. The internal X address generation circuit 112 receives the signal EXAL from the command decoder 110 or the address control signal ACBR from the refresh signal generation circuit 116, the external address signal from the latch circuit 108, and the updated address from the X address counter circuit 119. Based on this, an internal address signal INTADD is generated. The internal address signal INTADD is supplied to the address predecoder circuit 120. Address predecoder circuit 120 internal address signal INTADD is predecoded and supplied to word line driver group 121.

  The RAS control circuit group 109 generates a drive signal in response to the signal EXAL or the refresh instruction signal YRF from the command decoder 110, and drives the word line driver group 121 and the sense amplifier group 122. The word line driver group 121 drives the word line 128 based on the address from the address predecoder circuit 120. Further, the bit line 126 is driven, and the memory cell 127 in the memory cell array is accessed. The signal of the memory cell 127 is amplified by the sense amplifier group 122 and written to the memory cell 127 again. Thus, a refresh operation is performed. In the CBR refresh operation, the activated state of the word line driver group 121 and the sense amplifier group 122 is released at the timing when the refresh operation to the memory cell is completed.

  Next, the CBR refresh control unit 114 of FIG. 1 will be described with reference to FIG. 2A shows a circuit configuration of the program control circuit 113, and FIG. 2B shows a circuit configuration of the skip control circuit 115.

  First, referring to FIG. 2A, the program control circuit 113 includes a fuse (FUSE) 502, a NAND circuit G1, a transistor Tr1, and inverters IN1 and IN2. In the present state, the level of the flag signal FG is determined depending on whether or not the fuse (FUSE) is cut. When the fuse is not cut, the flag signal FG is at a low level, and when the fuse is cut, the flag signal FG is at a high level.

  The flag signal FG when the fuse 502 is cut will be described with reference to FIGS. 3 (a), (b), and (c). When the fuse 502 is cut, the voltage VDD gradually increases when the power is turned on. At this time, since the voltage of the ground side terminal of the fuse 502 is low, the output of the NAND circuit G1 becomes high level. For this reason, the flag signal FG increases as the power supply voltage increases. When the power supply voltage VDD exceeds a certain voltage, the signal PONV becomes high level. For this reason, the transistor Tr1 is turned on, and the voltage at the ground side terminal of the fuse 502 is further lowered, so that the output of the NAND circuit G1 becomes high level. This high level output is output as the flag signal FG via the inverters IN1 and IN2.

  Next, the flag signal FG when the fuse 502 is not cut will be described with reference to FIGS. 3 (d), 3 (e), and 3 (f). When the power is turned on, the voltage VDD gradually increases. Since the fuse 502 is not cut, at this time, the terminal voltage on the fuse 502 side of the NAND circuit G1 rises, but since the signal PONV is at a low level, the output of the NAND circuit G1 is at a high level. For this reason, the flag signal FG increases as the power supply voltage increases. When the power supply voltage VDD exceeds a certain voltage, the signal PONV becomes high level. For this reason, the output of the NAND circuit G1 becomes a low level. This low level output is output as the flag signal FG via the inverters IN1 and IN2.

  Next, FIG. 2B shows a circuit configuration of the skip control circuit 115. Referring to FIG. 2B, the skip control circuit 115 includes NAND circuits G2 and G3, transfer gates T1 and T2, latches IN5 and IN6, In7 and In8, and inverters In3, In4, and In9. A circuit including transfer gates T1 and T2, latches IN5 and IN6, In7 and In8, and an inverter In4 functions as a counter.

  When the flag signal FG is at a low level, that is, when the fuse is not cut, the output of the NAND circuit G3 is always at a high level, and the signal RFSKIP is at a low level.

  On the other hand, when the flag signal FG is at a high level, that is, when the fuse is cut, the level of the signal RFSKIP depends on the output of the latch composed of the inverters IN7 and IN8. If the output of the latch composed of the inverters IN7 and IN8 is at a high level, the output of the inverter IN4 is at a low level. In this case, the output of the latch composed of the inverters IN5 and IN6 is at a low level. Since the flag signal FG is at a high level, when the signal RF is at a high level, the output of the NAND circuit G2 is at a low level. Therefore, the transfer gate T1 is turned on by the outputs of the NAND circuit G2 and the inverter IN3, and the transfer gate T2 is turned off. As a result, the low level output of the inverter IN4 is latched in the latch composed of the inverters IN5 and IN6. Next, when the signal RF changes from the high level to the low level, the transfer gate T1 is turned off and the transfer gate t2 is turned on. As a result, the output of the latch composed of the inverters IN5 and IN6 becomes high level because of the low level output of the inverter IN4. Since the transfer gate T2 is on, the output of the latch composed of the inverters IN7 and IN8 becomes low level. Thus, every time the signal RF is input, the output of the signal RFSKIP alternately changes between the high level and the low level.

  That is, in the example shown in FIG. 2B, the circuit including the latch composed of the inverters IN5 and IN6 and the latch composed of the inverters IN7 and IN8 functions as a toggle switch or a counter, and one of the two CBR refresh commands. Times are enabled. However, if the number of latch stages is increased, the counter functions as an arbitrary counter, and it is possible to validate one out of m (m is an integer of 2 or more) CBR refresh commands.

  Next, the operation of the semiconductor memory device according to the first embodiment of the present invention will be described. FIG. 4 shows waveforms at various parts of the semiconductor memory device. In this example, the fuse 502 is cut, and the signal FG remains at the high level as shown in FIG.

  In the case of a synchronous memory, as shown in FIG. 4B, an external clock signal CLK is input to the receiver 101 from the outside in the semiconductor memory device. Internal clock generation circuit 105 generates internal clock signal ICLK from external clock signal CLK. Further, as shown in FIG. 4C, a high level clock enable signal CKE is supplied to the receiver 103. The latch circuit 107 latches the signal CKE in response to the internal clock signal ICLK and outputs it to the self-refresh determination circuit 111. As shown in FIG. 4E, a command signal CMD (RASB, CASB, WEB) for giving an operation instruction of the semiconductor memory device is supplied to the receiver 102 in synchronization with the clock signal CLK. The latch circuit 106 latches the command signal CMD at the timing when the internal clock signal ICLK transitions from the low level to the high level, and outputs the command signal CMD to the command decoder 110. At this time, since the command signal CMD is commonly given to a plurality of semiconductor memory devices, it is necessary to distinguish which semiconductor memory device the command signal CMD is issued to. Therefore, as shown in FIG. 4D, the chip select bar signal CSB is input for each semiconductor memory device. When the chip select bar signal CSB is at the low level, the semiconductor memory device takes in the command signal CMD internally at the above timing. The command decoder 110 generates a refresh signal RF and a signal EXAL based on the command signal CMD. The refresh signal RF is supplied to the skip control circuit 115, the refresh signal generation circuit 116, and the self-refresh determination circuit 111 of the CBR refresh control unit 114.

  Here, it is assumed that a refresh command is input. However, there are two types of refresh commands: a CBR refresh command and a self-refresh command related to the present invention. The command signal CMD is the same for both CBR refresh and self refresh, but is distinguished by the state of the clock enable signal CKE. That is, a refresh command input when the clock enable signal CKE is at a high level is determined as a CBR refresh command, and a refresh command input when the clock enable signal CKE is at a low level is determined as a self-refresh command. FIG. 4E shows a CBR refresh command.

  The self-refresh determination circuit 111 receives the clock enable bar signal CKE from the latch circuit 107, and determines that the refresh signal RF is a CBR refresh command when the signal CKE is at a high level, as shown in FIG. 4C. To do. At this time, the timer start signal is not output to the self-timer 117. If it is determined that the refresh signal RF is a self-refresh command, a timer start signal is output to the self-timer 117. The self-timer 117 measures time in response to the timer activation signal, and generates an interrupt signal when the time is up. The interrupt signal is output to the refresh signal generation circuit 116. In the case of a self-refresh command, the refresh signal generation circuit 116 is controlled by the output from the self-timer 117.

  On the other hand, in the case of the CBR refresh command related to the present invention, the refresh signal generation circuit 116 is driven by the refresh signal RF that is output every time the CBR refresh command is input, and controls the signals YRF and ACBR. Here, as described with reference to FIG. 2, the CBR refresh control unit 114 of the present invention outputs a refresh skip signal RFSKIP that is inverted every time the refresh signal RF is input. As shown in FIGS. 4F and 4G, the level of the refresh skip signal RFSKIP changes every time the refresh signal RF transitions from high to low. Thus, the refresh signal generation circuit 116 is switched between the valid state and the invalid state. In the invalid state, the refresh signal generation circuit 116 ignores the refresh signal RF from the command decoder 110 and operates based on the refresh signal RF when in the valid state. However, the skip control circuit 115 executes this operation only when the signal FG input to the skip control circuit 115 at the output of the program circuit 113 is at a high level. In the case of self refresh, the signal RFSKIP is masked (disabled) by a signal from the self timer 117.

  The refresh signal generation circuit 116 uses the signal YRF necessary for executing refresh inside the semiconductor memory device and the signal ACBR necessary for changing the internal X address as refresh instruction signals, as shown in FIGS. As shown in (i), output is made when the RFSKIP is at a low level.

  There is an active command, which is a command for activating a memory cell at a desired address before a read (read command) or write (write command) is performed in the semiconductor memory device. In FIG. 1, a signal EXAL is output from the command decoder 110 to the internal X address generation circuit 112 and the RAS control circuit group 109 in response to an active command. The signal EXAL is not output for the CBR refresh command.

  The signal ACBR generated from the refresh signal generation circuit 116 at the time of the CBR refresh command is supplied to the internal X address generation circuit 112. The internal X address generation circuit 112 increments the X address (INTADD) in response to the signal ACBR and outputs it. The increment operation is processed in the X address counter circuit 119, and the incremented internal address INTADD is transmitted from the internal X address generation circuit 112 to the address predecoder circuit 120. The address predecode circuit 120 decodes the internal address INTADD and outputs it to the word line driver group 121.

  In response to signal YRF output from refresh signal generation circuit 116, RAS control circuit group 109 activates word line driver group 121 and sense amplifier group 122. However, only the word line driver group 121 selected by the predecoded address is activated. The refresh operation is performed when the signal of the memory cell 127 connected to the activated word line is amplified by the sense amplifier group 122 and stored in the memory cell 127 again. In the CBR refresh operation, the activated state of the word line driver group 121 and the sense amplifier group 122 is released at the timing when the refresh operation to the memory cell is completed, but the description is omitted because it is not directly related to the description of the present invention. .

  In the semiconductor memory device according to the first embodiment of the present invention, the current consumed by the CBR refresh command operation mainly activates the word line, amplifies a minute signal on the bit line, and selects the desired bit line. It is consumed when it is charged or discharged to the level of and then resets the word line. Therefore, the current consumption can be reduced by halving the number of operations. Needless to say, a reduction in current consumption leads to an improvement in the characteristics of a device equipped with a semiconductor memory device, and is always an important matter that is required.

  In addition, the fact that the current consumption is halved also means that the heat generation of the semiconductor memory device is halved, the rise in temperature inside the semiconductor memory device is alleviated, the hold time of the memory cell is lengthened, and further the semiconductor memory device The effect of alleviating not only the inside of the device but also the internal temperature of the device in which the semiconductor memory device is mounted can be prevented and the malfunction of the mounted device can be prevented.

  Next explained is a semiconductor memory device according to the second embodiment of the invention.

  The basic structure of the semiconductor memory device according to the second embodiment of the present invention is the same as that of the semiconductor memory device according to the first embodiment. The difference is that the RAS control circuit group shown in FIG. 1 is divided into two, and word line driver groups 321 and 333 and sense amplifier groups 322 and 337 are provided respectively. The command decoder 110 generates signals EXALA and EXALC in addition to the refresh signal RF and signal EXAL shown in FIG. 1 and supplies them to the RAS control circuit groups 318 and 319. The skip control circuit 329 of the CBR refresh control unit 114 outputs two signals SELA and SELC alternately. The refresh signal generation circuit 316 generates signals YRFA and YRFC and supplies them to the RAS control circuit groups 318 and 319. In the semiconductor memory device according to the second embodiment, other circuit configurations are the same as those in the first embodiment.

  The circuit configuration of the skip control circuit 329 is the same as the circuit shown in FIG. 2B, but an inverter IN10 and a NOR circuit NOR are added. The signal FG is inverted by the inverter IN10 and supplied to one input terminal of the NOR circuit. The output of the latch composed of the inverters IN7 and IN8 is supplied to the other input terminal. A signal SELA is output from the inverter IN9, and a signal SELC is output from the NOR circuit. When the signal FG is at the low level, the signals SELA and SELC are both fixed at the low level. The signal ACBR is output once every time the signal RF is input to the refresh signal generation circuit 316 twice. This means that all the address spaces divided into two areas are refreshed.

  Next, operations of the semiconductor memory device according to the second embodiment will be described with reference to FIGS. FIG. 4 shows waveforms at various parts of the semiconductor memory device. In this example, the fuse is cut, and the signal FG remains at the high level as shown in FIG.

  In the case of a synchronous memory, as shown in FIG. 7B, an external clock signal CLK is input to the receiver 101 from the outside in the semiconductor memory device. Internal clock generation circuit 105 generates internal clock signal ICLK from external clock signal CLK. Further, as shown in FIG. 7C, a high level clock enable signal CKE is supplied to the receiver 103. The latch circuit 107 latches the signal CKE in response to the internal clock signal ICLK and outputs it to the self-refresh determination circuit 111. Further, as shown in FIG. 7E, a command signal CMD (RASB, CASB, WEB) for giving an operation instruction of the semiconductor memory device is supplied to the receiver 102 in synchronization with the clock signal CLK. The latch circuit 106 latches the command signal CMD at the timing when the internal clock signal ICLK transitions from the low level to the high level, and outputs the command signal CMD to the command decoder 110. At this time, since the command signal CMD is commonly given to a plurality of semiconductor memory devices, it is necessary to distinguish which semiconductor memory device the command signal CMD is issued to. Therefore, as shown in FIG. 7D, a chip select bar signal CSB is input for each semiconductor memory device. When the chip select bar signal CSB is at the low level, the semiconductor memory device takes in the command signal CMD internally at the above timing.

  The command decoder 110 generates a refresh signal RF and a signal EXAL based on the command signal CMD. The refresh signal RF is supplied to the skip control circuit 115, the refresh signal generation circuit 116, and the self-refresh determination circuit 111 of the CBR refresh control unit 114.

  Here, it is assumed that a refresh command is input. However, there are two types of refresh commands: a CBR refresh command and a self-refresh command related to the present invention. The command signal CMD is the same for both CBR refresh and self refresh, but is distinguished by the state of the clock enable signal CKE. That is, a refresh command input when the clock enable signal CKE is at a high level is determined as a CBR refresh command, and a refresh command input when the clock enable signal CKE is at a low level is determined as a self-refresh command. FIG. 7E shows a CBR refresh command.

  The self-refresh determination circuit 111 receives the clock enable bar signal CKE from the latch circuit 107, and determines that the refresh signal RF is a CBR refresh command when the signal CKE is at a high level as shown in FIG. 7C. To do. At this time, the timer start signal is not output to the self-timer 117. If it is determined that the refresh signal RF is a self-refresh command, a timer start signal is output to the self-timer 117. The self-timer 117 measures time in response to the timer activation signal, and generates an interrupt signal when the time is up. The interrupt signal is output to the refresh signal generation circuit 116. In the case of a self-refresh command, the refresh signal generation circuit 116 is controlled by the output from the self-timer 117.

  On the other hand, in the case of the CBR refresh command related to the present invention, the refresh signal generation circuit 316 is driven by the refresh signal RF that is output every time the CBR refresh command is input, and the signals YRFA and YRFC and the address control signal ACBR are output. To do. Here, in the CBR refresh control unit 114 of the present invention, as shown in FIGS. 7H and 7I, every time the refresh signal RF is input, the signals SELA and SELC are alternately used as the refresh skip signal. Output. Further, as shown in FIG. 7 (k), the signal ACBR is output once every time the refresh signal RF is input twice. Thus, each of the outputs YRFA and YRFC of the refresh signal generation circuit 116 is switched between the valid state and the invalid state. In the invalid state, the refresh signal generation circuit 116 ignores the refresh signal RF from the command decoder 110 and operates based on the refresh signal RF when in the valid state. However, the skip control circuit 115 executes this operation only when the signal FG input to the skip control circuit 115 at the output of the program circuit 113 is at a high level. In the case of self refresh, the signal RFSKIP is masked (disabled) by a signal from the self timer 117.

  The refresh signal generation circuit 116 uses the signals YBRA and YRFC necessary for executing the refresh inside the semiconductor memory device and the signal ACBR necessary for changing the internal X address as refresh instruction signals, as shown in FIGS. ) And (k), the RFSKIP is output when it is at a low level.

  There is an active command, which is a command for activating a memory cell at a desired address before a read (read command) or write (write command) is performed in the semiconductor memory device. In the semiconductor memory device shown in FIG. 5, the signal EXAL is output from the command decoder 110 to the internal X address generation circuit 112 and the RAS control circuit group 109 in response to an active command. The signal EXAL is not output for the CBR refresh command.

  The signal ACBR generated from the refresh signal generation circuit 116 at the time of the CBR refresh command is supplied to the internal X address generation circuit 112. The internal X address generation circuit 112 increments the X address (INTADD) in response to the signal ACBR and outputs it. The increment operation is processed in the X address counter circuit 119, and the incremented internal address INTADD is transmitted from the internal X address generation circuit 112 to the address predecoder circuit 120. The address predecode circuit 120 decodes the internal address INTADD and outputs it to the word line driver group 121.

  In response to the signals YRFA and YRFC output from the refresh signal generation circuit 116, the RAS control circuit groups 318 and 319 activate the word line driver groups 321 and 333 and the sense amplifier groups 322 and 337. However, only the word line driver groups 321 and 333 selected by the predecoded address are activated. The refresh operation corresponds to the signal of the memory cells 327 and 335 connected to the activated word line being amplified by the sense amplifier groups 322 and 337 and stored in the memory cells 327 and 335 again. In the CBR refresh operation, the activation states of the word line driver groups 321 and 333 and the sense amplifier groups 322 and 337 are released at the timing when the refresh operation to the memory cells 327 and 335 is completed, which is directly related to the description of the present invention. The explanation is omitted.

  In the semiconductor memory device of the second embodiment of the present invention, an internal refresh operation is always performed in response to an external CBR refresh command, but the memory cell refreshed by the output from the skip control circuit 315 The number is half that of FIG. As described above, since most of the current consumption of the CBR refresh operation is used for the refresh operation of the memory cell, the current consumption during the CBR refresh is reduced to about half as in the case of FIG. .

  The current consumed by the CBR refresh command operation mainly activates the word line, amplifies a minute signal on the bit line, charges or discharges the bit line to a desired level, and then resets the word line. When it is consumed. Therefore, the current consumption can be reduced by halving the number of operations. Needless to say, a reduction in current consumption leads to an improvement in the characteristics of a device equipped with a semiconductor memory device, and is always an important matter that is required.

  In addition, the fact that the current consumption is halved also means that the heat generation of the semiconductor memory device is halved, the rise in temperature inside the semiconductor memory device is alleviated, the hold time of the memory cell is lengthened, and further the semiconductor memory device The effect of alleviating not only the inside of the device but also the internal temperature of the device in which the semiconductor memory device is mounted can be prevented and the malfunction of the mounted device can be prevented.

  Next, a semiconductor memory device according to a third embodiment of the present invention will be described. The semiconductor memory device according to the third embodiment includes a receiver 401, 402, 403, 404, an internal clock generation circuit 405, a latch circuit 406, 407, 408, a command decoder 410, a self-refresh determination circuit 411, an internal X address generation circuit 412. RAS control circuit group 409, refresh signal generation circuit 416, self-timer 417, X address counter circuit 418, address predecoder circuits 422 and 414 CBR refresh control unit, word line driver 424 and sense amplifier 428. The semiconductor memory device includes a memory cell array having a plurality of memory cells 426, and a refresh operation is performed on these memory cells.

  In the third embodiment, the reference numbers in the first embodiment are changed, but the semiconductor memory device according to the third embodiment is basically the same as the semiconductor memory device according to the first embodiment. Since the circuit or unit having the same name as that of the first embodiment performs the same operation as that of the first embodiment, detailed description thereof is omitted.

  The difference is that the CBR refresh control unit 414 is provided between the RAS control circuit group 409, the word line driver group 424, and the sense amplifier group 428 in the third embodiment. The CBR refresh control unit 414 includes a plurality of program control circuits 413 and a plurality of skip control circuits 415 corresponding thereto. The RAS control circuit group 409 generates a selection signal based on the signal EXAL or the signal YRF, and outputs the selection signal to the plurality of skip control circuits 415 of the CBR refresh control unit 414. Each of the plurality of skip control circuits 415 receives the selection signal from the RAS control circuit group 409 in the same manner as the refresh signal RF in the first embodiment, and receives the refresh skip signal as the word line driver group 424 and the sense amplifier group 428. Output to the corresponding one. Thus, the memory cell 426 is accessed as in the first embodiment.

  In the semiconductor memory device of the present invention described above, the signal RFSKIP is output once for the input of the signal RF twice by the skip control circuit. However, it would be easy for those skilled in the art to change the apparatus so that the signal RFSKIP is output once for m times (m is an integer of 2 or more) times of input of the signal RF. For example, it will be apparent that the latch circuit configuration in the skip control circuit may be changed to a counter circuit. In this way, the area of the memory cell array can be easily divided into an arbitrary number in the second embodiment.

  Furthermore, it is easy to replace the program control circuit shown in FIG. For example, the fuse 502 may be formed of a type that is electrically blown from a type that is cut by a laser, or a type that is that electrically destroys a capacitive element. Alternatively, the fuse 502 may be formed of a non-volatile memory element. In this case, it can be rewritten by the host device not only at the time of manufacture but also when the semiconductor memory device is used.

FIG. 1 is a block diagram showing a circuit configuration of the semiconductor memory device according to the first embodiment of the present invention. 2A and 2B are block diagrams showing circuit configurations of a program control circuit and a skip control circuit in the semiconductor memory device according to the first embodiment of the present invention. FIGS. 3A to 3F are waveform diagrams showing states of the flag signal FG when the fuse is cut and when the fuse is not cut in the semiconductor memory device according to the first embodiment of the present invention. 4A to 4J are time charts showing the operation of each part when the fuse is cut in the semiconductor memory device according to the first embodiment of the present invention. FIG. 5 is a block diagram showing a circuit configuration of the semiconductor memory device according to the second embodiment of the present invention. FIG. 6 is a block diagram showing a circuit configuration of the skip control circuit in the semiconductor memory device according to the second embodiment of the present invention. 7A to 7L are time charts showing the operation of each part when the fuse is cut in the semiconductor memory device according to the second embodiment of the present invention. FIG. 8 is a block diagram showing a circuit configuration of the skip control circuit in the semiconductor memory device according to the third embodiment of the present invention.

Explanation of symbols

101, 102, 103, 104, 401, 402, 403, 404: receiver 105, 405: internal clock generation circuit 106, 107, 108, 406, 407, 408: latch circuit 109, 309, 331, 409: RAS control circuit Group 110, 410: Command decoder 111, 411: Self-refresh determination circuit 112, 412: Internal X address generation circuit 113, 413: Program control circuit 114, 414: CBR refresh control unit 115, 315, 415: Skip control circuit 116, 316, 416: Refresh signal generation circuits 117, 417: Self-timers 119, 418: Internal X address counter circuits 120, 422: Address predecoders 121, 321, 333, 424: Word line driver groups 122, 322, 337 428: sense amplifier group IN1～IN10: Inverter G1 to G3: NAND circuit Tr1: transistors T1, T2: the transfer gate NR: NOR circuit

Claims (6)

a memory cell array having m array units (m is an integer of 2 or more);
M refresh units provided corresponding to the m array units, respectively receiving m refresh instruction signals and performing refresh operations on the m array units,
A control data holding circuit,
When the control data is held in the control data holding circuit, each of the m refresh units receives the m refresh instruction signal in a time division manner and performs a refresh operation on the m array units. When the division is performed and the control data is not held, the m refresh units simultaneously receive the m refresh instruction signals and simultaneously perform refresh operations on the m array units. Storage device. The semiconductor memory device according to claim 1 ,
A refresh instruction unit for receiving a CBR refresh command;
A CBR refresh control unit connected to the control data holding circuit and controlling the CBR refresh instruction unit;
When the control data is held in the control data holding circuit, the CBR refresh control unit sends the refresh instruction signal to the m refresh units in turn every time the refresh instruction unit receives the CBR refresh command. When the control data is not held, the refresh instruction unit is controlled to output the refresh instruction signal to all of the m refresh units every time the CBR refresh command is received. Semiconductor memory device. The semiconductor memory device according to claim 1 or 2 ,
The control data holding circuit includes a fuse, and the fuse is cut in order to hold the control data. The semiconductor memory device according to claim 3 .
The fuse is cut based on a data retention time of the memory cell. The semiconductor memory device according to claim 1 or 2 ,
The control data holding circuit includes a nonvolatile memory, and the control data is written in the nonvolatile memory. The semiconductor memory device according to claim 5 .
The control data is written into the nonvolatile memory based on the data retention time of the memory cell.

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