JP4877317B2 - Information processing apparatus and interrupt control method - Google Patents

Description

  The present invention relates to an information processing apparatus and an interrupt control method, and more particularly to an information processing apparatus and an interrupt control method for controlling an interrupt between operating systems in a hardware sharing environment.

  A system in which a plurality of operating systems (hereinafter referred to as OSs) are provided on one computer and the plurality of OSs share hardware resources has been developed. For example, a real-time OS and a general-purpose OS are mixed on one computer, and among the hardware resources, a central processing unit (hereinafter referred to as a CPU) and a memory are statically divided to each of them. There is a system that each OS occupies and uses. Here, in such a system, as for other hardware resources such as an input / output device (hereinafter referred to as an IO device), all the OSs share and use them, and each OS occupies and uses them. There is something to do.

  As a related technique, for example, there is an information processing apparatus described in Patent Document 1. The information processing apparatus described in Patent Document 1 is a system in which a main OS and a sub OS operate, and the main OS receives all interrupt requests, and issues necessary interrupts when the sub OS is in an interruptible and executable state. to deliver. Such a system is intended to control the sub-OS according to the judgment of the main OS. For example, when the main OS and the sub-OS that operate independently share some hardware resources, for example. In addition, it is difficult to apply to control for reducing the load on the main OS.

  Furthermore, as another related technique, for example, there is an information transmission apparatus described in Patent Document 2. The information transmission apparatus described in Patent Document 2 monitors the number of interrupts that occur within a certain period of time, detects a channel abnormality based on the number of interruptions, and stops the interrupt source channel for a certain period of time. Such an information transmission apparatus is not intended for a system in which a plurality of OSs are mixed.

As another related technique, there is a computer system described in Patent Document 3, for example. The computer system described in Patent Document 3 shares an IO device.
JP 2006-099331 A Japanese Patent Laid-Open No. 01-258162 JP 2007-148621 A

  When a plurality of OSs share and use hardware resources such as IO devices, an interrupt generated from the shared IO device is first notified to the real-time OS. This is because a real-time OS having a higher priority than a general-purpose OS requires real-time performance in processing related to an IO device and needs to receive an interrupt preferentially. The real-time OS that has received the interrupt determines which OS the received interrupt is for, and if the interrupt is for the general-purpose OS, transfers the received interrupt to the general-purpose OS. The general-purpose OS that has received the interrupt executes an IO process that generates the interrupt.

  Here, when the interrupt is notified to the general-purpose OS via the real-time OS, the real-time OS can be processed by the processing on the general-purpose OS, even though such an interrupt is not related to the processing on the real-time OS. It will be affected. That is, when a large number of interrupts are generated by the general-purpose OS having a low priority, a large number of interrupts to the real-time OS having a high priority are notified. The load increases and the performance is reduced. For example, when a large amount of IO processing that generates interrupts is performed by the general-purpose OS, a large amount of interrupts are notified to the real-time OS, and as a result, there is a problem that processing on the real-time OS is hindered.

  Accordingly, an object of the present invention is to provide an information processing apparatus and interrupt control capable of reducing the load of an OS with a high priority regarding interrupt processing when an OS with a high priority and an OS with a low priority share hardware resources. It is to provide a method.

  An information processing apparatus according to a first aspect of the present invention includes a first OS with a high priority, and a second OS with a low priority that shares hardware resources with the first OS. When the first OS receives an interrupt notification from a resource, the information processing apparatus executes an interrupt notification transfer process to the second OS when the interrupt is not processed by the first OS, A load control unit that detects a load associated with the transfer process of the first OS and determines a load state associated with the transfer process; and an interrupt by the hardware resource when the load control unit determines that the load is large And delay control means for delaying the processing of the second OS for generating the processing.

  The interrupt control method according to the second aspect of the present invention shares a hardware resource with a second OS having a low priority, and sends an interrupt notification from the hardware resource to the first OS having a high priority. An interrupt control method for executing an interrupt notification transfer process for the second OS when the interrupt is not processed by the first OS when received, and a load associated with the transfer process of the first OS And a load state determination step for determining a load state associated with the transfer process, and a process of the second OS that generates an interrupt process by the hardware resource when the load is determined to be large. And a delay control step for delaying.

  According to the present invention, there is provided an information processing apparatus and an interrupt control method capable of reducing the load of an OS having a high priority regarding interrupt processing when an OS having a high priority and an OS having a low priority share hardware resources. Can be provided.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals, and description thereof is omitted.

Embodiment 1 FIG.
FIG. 1 is a diagram showing an overall configuration of the information processing apparatus according to the first embodiment. As shown in FIG. 1, the information processing apparatus 1 includes a plurality of OSs (OS (1) 11 and OS (2) 12), a disk 13, an Ethernet (registered trademark) 14, and a bus controller (Bus Controller) 15. And a plurality of CPUs (CPU (1) 16, CPU (2) 17, CPU (3) 18, CPU (4) 19).

  Of the hardware resources, the OS (1) 11 and the OS (2) 12 use the CPUs 16 to 19 and the memory (not shown) in a statically divided manner. That is, OS (1) 11 uses CPU (1) 16 and CPU (2) 17, and OS (2) 12 uses CPU (3) 18 and CPU (4) 19. The memory (not shown) is divided into a plurality of areas, and the OS (1) 11 and the OS (2) 12 use corresponding areas. As for other hardware resources other than the CPU and the memory, the OS (1) 11 and the OS (2) 12 are used exclusively by one of the OSs or are shared and used by the two OSs. By configuring the system with the minimum necessary hardware resources in this way and sharing and using the hardware resources, it is not necessary to prepare hardware resources for each OS, and costs can be reduced. In the following description, it is assumed that the disk 13 and the Ethernet (registered trademark) 14 are shared hardware resources.

  In this embodiment, priorities are set for the OS (1) 11 and the OS (2) 12. On an OS having a high priority, a program that should be prioritized as a system is executed so that high real-time performance is required. In the following description, it is assumed that the OS (2) 12 is a general-purpose OS, and the OS (1) 11 is a real-time OS having a higher priority than the general-purpose OS.

  The bus controller 15 manages an interrupt of a shared hardware resource, and when an interrupt occurs, notifies the interrupt to the OS (1) 11 having a higher priority. This is because the system does not know which OS has caused an operation to generate an interrupt, so the system first notifies the interrupt to the OS (1) 11 having a higher priority via the bus controller 15. Because. Then, the OS (1) 11 that has received the interrupt checks whether or not the interrupt is an interrupt to be processed by itself, and if it is not an interrupt to be processed by itself, the OS (2) having a lower priority order. Transfer the interrupt to 12.

  When the OS (2) 12 generates an interrupt by operating a hardware resource, the interrupt is first notified to the OS (1) 11 via the bus controller 15. A process in the OS (1) 11 occurs along with the operation of the OS (2) 12. Even if the load applied to the OS (1) 11 during this process falls within the estimated range at the time of system design. There is no problem. However, when the number of interrupts generated by the OS (2) 12 greatly exceeds the estimated range, the processing load on the OS (1) 11 increases, and the original processing of the OS (1) 11 is not performed. There is a problem of being obstructed. Here, since it is unclear to which OS the interrupt to be notified is, the OS (1) 11 cannot stop interrupt processing and transfer execution. Therefore, the information processing apparatus 1 according to the first embodiment has the OS (1) so that the interrupt generated by the OS (2) 12 with the lower priority does not disturb the operation of the OS (1) 11 with the higher priority. ) 11 and OS (2) 12 cooperate, and when the load due to the interrupt of OS (1) 11 increases, the load information is notified to OS (2) 12 and the interrupt of OS (2) 12 By controlling the frequency of processing that is a cause of occurrence, the influence of the interruption by the OS (2) 12 on the OS (1) 11 is suppressed.

  Next, the configuration of the information processing apparatus 1 according to the first embodiment will be described in more detail with reference to FIG. As illustrated, the information processing apparatus 1 includes an OS (1) 11, an OS (2) 12, and a device 60.

  The OS (2) 12 includes a thread 31, a driver 40, and a delay time management unit 50. The driver 40 includes an entrance processing unit 41, a delay processing unit 42, an IO issue processing unit 43, and an exit processing unit 44. The delay time management unit 50 holds delay time data 51.

  The delay time management unit 50 receives the load notification from the load control unit 70 of the OS (1) 11, and sets the delay time data 51. The driver 40 executes delay processing by the delay processing unit 42 prior to processing by the IO issue processing unit 43. The delay processing unit 42 refers to the delay time data 51 set in the delay time management unit 50 to determine whether a delay is necessary, and executes a delay process if a delay is necessary. On the other hand, when the delay ends or when it is determined that the delay is not necessary, the delay processing is ended. When the delay processing by the delay processing unit 42 is completed, the IO issue processing unit 43 operates the device 60 by issuing an IO. The device 60 executes the instructed process, and when the process is completed, notifies the OS (1) 11 of an interrupt.

  The OS (1) 11 includes a load control unit 70. The load control unit 70 holds average interrupt frequency data 71 and average task waiting time data 72. The OS (1) 11 determines whether or not the interrupt is addressed to itself. If the interrupt is not addressed to itself, the OS (1) 11 transfers the interrupt to the OS (2) 12 and calculates the load statistics due to the interrupt. Information is acquired by the load control unit 70. Here, average interrupt frequency data 70 and average task wait time data 72 are acquired as the load statistical information. The load control unit 70 compares the acquired load statistical information with a predetermined threshold value, and if the load control unit 70 determines that the load due to the interrupt is high, notifies the OS (2) 12 of the load. The OS (2) 12 that has received the load notification updates the delay time data 51 by the delay time management unit 50 after processing the interrupt. In this example, the load state is determined using both the average interrupt frequency data 71 and the average task waiting time data 72, but may be determined using any one of the data.

  Next, the operation process of the information processing apparatus 1 will be described in detail with reference to the flowcharts shown in FIGS. Here, in the information processing apparatus 1 illustrated in FIG. 2, an operation process when the thread 31 that is a program execution unit calls the driver 40 to operate the device 60 will be described.

  As shown in FIG. 3, the driver 40 called from the thread 31 executes delay processing by the delay processing unit 42 prior to IO issue processing by the IO issue processing unit 43 when delay processing is necessary. That is, as shown in FIG. 3, the delay processing unit 42 refers to the delay time data 51 of the delay time management unit 50 and determines whether or not to execute the delay process (step S101). In the example shown in FIG. 3, when the delay time is greater than 0, the delay process is executed, and when the delay time is 0, the delay process is terminated without executing the delay process. When executing the delay process, the delay processing unit 42 waits for the process for the delay time to execute the delay process (step S102). When the delay processing by the delay processing unit 42 is executed, the IO issue processing unit 43 performs the IO issue processing subsequent to the delay processing, and when the delay processing is not executed, the determination processing in step S101. Subsequently, the IO issue process is executed. That is, the IO issue processing unit 43 performs IO issue processing and accesses the device 60. Then, when the commanded processing is completed, the device 60 newly generates an interrupt and notifies the OS (1) 11 of the generated interrupt.

  The OS (1) 11 notified of the interrupt from the device 60 confirms to whom the generated interrupt is addressed, and if the interrupt is an interrupt addressed to the OS (2) 12, the OS (1) 11 2) Transfer to 12. Further, the OS (1) 11 executes a load control process by the load control unit 70 shown in FIG. That is, as shown in FIG. 4, the load control unit 70 first updates the average interrupt frequency as the statistical information of the load due to the interrupt, and the waiting time of the task taken for this interrupt (step S201). Then, the load control unit 70 determines whether or not the average interrupt frequency exceeds a predetermined threshold (step S202). If the average interrupt frequency does not exceed the threshold, the load control unit 70 further determines whether or not the average task waiting time has exceeded a predetermined threshold (step S203). If the average interrupt frequency exceeds the threshold as a result of the determination in step S202, or if the average task waiting time exceeds the threshold as a result of the determination in step S203, the load control unit 70 sets the OS (2) 12 In response to this, the OS (1) 11 issues a load notification indicating that the interrupt load has increased, and ends the load control process. On the other hand, if the average task waiting time does not exceed the threshold as a result of the determination in step S203, the load control unit 70 ends the load control process.

  The OS (2) 12 notified of the interrupt from the OS (1) 11 executes processing related to the device 60 that has generated the interrupt. Further, the OS (2) 12 executes a delay time management process by the delay time management unit 50 shown in FIG. That is, as shown in FIG. 5, the delay time management unit 50 first checks whether the load value specified by the load notification notified from the OS1 (1) 11 is higher or lower than a predetermined threshold value. (Step S301).

  If the load value is higher than the threshold value as a result of the determination in S301, the delay time management unit 50 further determines a predetermined upper limit value (hereinafter, MAX value) specified by the delay time data 51. Or less) (step S302). When the delay time management unit 50 determines that the delay time is not smaller than the MAX value, that is, the delay time is already equal to the MAX value, the delay time cannot be further increased. finish. On the other hand, when the delay time is smaller than the MAX value, that is, there is room for increasing the delay time, the delay time management unit 50 increases the value of the delay time (step S303).

  If the load notification is lower than the threshold as a result of the determination in S301, the delay time management unit 50 further determines whether or not the current delay time specified by the delay time data 51 is greater than a predetermined lower limit value. Is determined (S304). In the example shown in FIG. 3, the lower limit value is 0. When the delay time is larger than 0, the delay time management unit 50 can further reduce the delay time, and therefore decreases the value of the delay time (step S305). On the other hand, when the delay time is 0, since the delay time cannot be further reduced, the delay time management unit 50 ends the delay time management process.

  Hereinafter, regarding each operation processing shown in FIGS. 3 to 5, the OS (1) 11 is a real-time OS, the OS (2) 12 is a general-purpose OS, and these two OSs are the Ethernet (registered trademark) 14 as the device 60. The case of sharing will be specifically described.

  First, as shown in FIG. 2, the thread 31 on the general-purpose OS uses the Ethernet (registered trademark) 14 by giving an instruction to the driver 40. Upon receiving the instruction, the driver 40 refers to the delay time data 51 of the delay time management unit 50 by the delay processing unit 42 and determines whether or not it is necessary to execute the delay processing. When it is necessary to execute the delay process, the delay processing unit 42 executes the delay process. The IO issue processing unit 43 of the driver 40 issues an IO command to the Ethernet (registered trademark) 14. The Ethernet (registered trademark) 14 that has received the IO issue command performs processing. When the processing is completed, an interrupt is generated from the Ethernet (registered trademark) 14. The generated interrupt is notified to the real-time OS.

  Next, the real-time OS notified of the interrupt checks the cause of the notified interrupt and determines whether or not the interrupt is addressed to itself. When determining that the interrupt is not addressed to itself, the real-time OS transfers the interrupt to the general-purpose OS. Further, as shown in FIG. 3, the load control unit 70 of the real-time OS measures statistical information such as the average frequency of interrupts and the waiting time of a task that is caused by the interrupts, and is not overloaded. Is determined using a predetermined threshold value. If the result of determination is that the load is high, a load notification is sent to the general-purpose OS. The general-purpose OS to which the interrupt is transferred from the real-time OS processes the transferred interrupt.

  Here, when the Ethernet (registered trademark) 14 is used in large quantities by the general-purpose OS, the real-time OS determines that the load is applied, and the delay time management unit 50 on the general-purpose OS The load control unit 70 notifies the load. As illustrated in FIG. 5, the general-purpose OS increases the delay time data 51 when receiving a load notification indicating a high load.

  When the thread 31 gives an instruction to the driver 40 to operate the Ethernet (registered trademark) 14, as shown in FIG. 4, the driver 40 causes the delay processing unit 50 to execute the delay time management unit 50. With reference to the delay time data 51, it is determined whether or not it is necessary to execute delay processing. When it is necessary to execute the delay process, the delay processing unit 42 executes the delay process. The IO issue processing unit 43 of the driver 40 issues an IO command to the Ethernet (registered trademark) 14 to operate the Ethernet (registered trademark) 14.

  As a result, the IO issue processing by the IO issue processing unit 43 is delayed by the delay time by the delay processing unit 42, so the frequency of interrupts notified to the real-time OS is reduced, and the load that has been generated for that is also reduced. Will be reduced. Then, when the frequency of interrupts notified to the real-time OS is sufficiently reduced, the real-time OS notifies the delay time management unit 50 of the general-purpose OS that the interrupt load has been reduced. Upon receiving this load notification, the general-purpose OS reduces the delay time value by the delay time management unit 50.

  As described above, in the real-time OS having a high priority, the statistical information of the load applied to the process of transferring the interrupt to the general-purpose OS having the lower priority is acquired, and the acquired statistical information exceeds a predetermined threshold. In this case, the real-time OS notifies the general-purpose OS so as to reduce interrupts. Then, in the general-purpose OS that has received the notification, the execution of the IO issuing process that generates the interrupt is delayed, and the number of IO issuing processes per unit time is reduced, thereby affecting the real-time OS by the interrupt generated by the general-purpose OS. Can be suppressed.

Embodiment 2. FIG.
Subsequently, an information processing apparatus according to Embodiment 2 of the present invention will be described. The information processing apparatus according to the second embodiment executes a delay process for a thread that executes an IO issue process prior to a process that connects the thread to a dispatch queue.

  FIG. 6 is a diagram showing a configuration of the information processing apparatus 1 according to the second embodiment. As illustrated, the information processing apparatus 1 includes an OS (1) 11, an OS (2) 12, and a device 60. The OS (2) 12 includes a scheduler 80 and a delay time management unit 50. The scheduler 80 includes a processing unit 81 (hereinafter referred to as a dispatch queue connection processing unit 81) that performs processing for connecting an executable thread to a dispatch queue, a delay processing unit 82, and an execution processing unit 83. . The delay time management unit 50 includes delay time data 51. The OS (1) 11 includes a load control unit 70. The load control unit 70 holds average interrupt frequency data 71 and average task waiting time data 72.

  FIG. 7 is a flowchart showing operation processing by the dispatch queue connection processing unit 81. As shown in FIG. 7, the dispatch queue connection processing unit 81 refers to the delay time data 51 of the delay time management unit 50 and determines whether or not to execute the delay process (step S401). In the example shown in FIG. 7, when the delay time is larger than 0, the dispatch queue connection processing unit 81 further checks whether or not the thread is executing the IO issue processing (step S402). If the delay time is 0 as a result of the determination in step S401, or if the thread is not executing the IO issuing process as a result of the investigation in step S402, the dispatch queue connection processing unit 81 executes the executable thread. For connecting to the dispatch queue (step S403). On the other hand, as a result of the investigation in step S402, when the thread is executing the IO issue processing, the dispatch queue connection processing unit 81 sets the delay time data 51 of the delay time management unit 50 as a timer and sets it. After the delay time elapses, processing for connecting an executable thread to the dispatch queue is performed (step S404).

  As described above, the information processing apparatus 1 according to the second embodiment checks whether or not the thread is a thread that executes the IO issuing process before the process of connecting the executable thread to the dispatch queue. If the thread is a thread that executes the IO issue process, the delay time management unit 50 is accessed to check whether the delay process is necessary. If the delay process is necessary, the thread is placed in the dispatch queue. Prior to the process to be connected, wait for the set delay time and then connect the thread to the dispatch queue. Thereby, it is possible to suppress the influence on the real-time OS due to the interrupt generated by the general-purpose OS.

Embodiment 3 FIG.
Subsequently, an information processing apparatus according to Embodiment 3 of the present invention will be described. In the information processing apparatus according to the third embodiment, the general-purpose OS requests permission of execution of interrupt processing from the real-time OS, and executes the interrupt processing when permitted by the real-time OS.

  FIG. 8 is a diagram showing a configuration of the information processing apparatus 1 according to the third embodiment. As illustrated, the information processing apparatus 1 includes an OS (1) 11, an OS (2) 12, and a device 60. The OS (2) 12 includes a thread 31, a driver 40, and an interrupt control unit 50. The driver 40 includes an entrance processing unit 41, an interrupt confirmation call processing unit 48, an IO issue processing unit 43, and an exit processing unit 44. The interrupt control unit 50 includes an interrupt confirmation processing unit 52. The OS (1) 11 includes a load control unit 70. The load control unit 70 holds average interrupt frequency data 71 and average task waiting time data 72.

  Next, processing of the information processing apparatus 1 according to the third embodiment will be described. Since the third embodiment has a feature in the process for determining whether or not to perform interrupt delay, the process will be mainly described.

  The interrupt confirmation call processing unit 48 uses the interrupt control for the interrupt confirmation processing unit 52 of the interrupt control unit 50 before performing an operation that generates an interrupt in the driver 40, and the load control unit of the OS1 (11). 70 is requested for permission to determine whether or not the processing for generating an interrupt may be performed.

  In response to such a request, the interrupt confirmation processing unit 52 of the interrupt control unit 50 issues an interrupt notification to the load control unit 70 of the OS (1) 11 to thereby load the load control unit 70 of the OS (1) 11. Asks for permission to perform processing that generates an interrupt. Based on data such as average interrupt frequency data 71 and average task waiting time data 72, the load control unit 70 measures statistical information such as the average frequency of interrupts and the waiting time of tasks taken for this interrupt, It is determined whether a load is excessively applied using a predetermined threshold value.

  When the load control unit 70 determines that the load is low as a result of the determination, the load control unit 70 notifies the interrupt control unit 50 (interrupt confirmation processing unit 52) of the OS (2) 12 of permission to permit an interrupt. If the load control unit 70 determines that the load is high as a result of the determination, the load control unit 70 notifies the interrupt control unit 50 (interrupt confirmation processing unit 52) of the OS (2) 12 that the interrupt is not permitted. I do.

  When receiving the permission notification from the load control unit 70, the interrupt confirmation processing unit 52 of the OS (2) 12 outputs a permission notification indicating interrupt permission to the interrupt confirmation calling processing unit 48. Then, the interrupt confirmation call processing unit 48 of the driver 40 executes interrupt processing in accordance with the permission notification.

  Further, when receiving the non-permission notification from the load control unit 70, the interrupt confirmation processing unit 52 outputs a non-permission notification indicating interrupt non-permission to the interrupt confirmation calling processing unit 48. Then, the interrupt confirmation call processing unit 48 of the driver 40 performs standby processing for a predetermined time in response to the non-permission notification. Thereafter, the interrupt confirmation call processing unit 48 uses the interrupt control for the interrupt confirmation processing unit 52 of the interrupt control unit 50 again after a predetermined time elapses, and loads the load control unit 70 of the OS1 (11). Is requested for permission to determine whether or not the processing for generating an interrupt may be performed. Thereafter, the same processing is performed, and the interrupt confirmation call processing unit 48 does not perform the interrupt processing until the permission of the load control unit 70 is acquired, and executes the interrupt processing only after acquiring the permission of the load control unit 70.

  As described above, in the information processing apparatus according to the third embodiment, the interrupt process is delayed until the real-time OS permission is obtained, so that the general-purpose OS is generated in the same manner as the information processing apparatus according to the first embodiment of the invention. The influence on the real-time OS due to the interrupt can be suppressed.

Embodiment 4 FIG.
Subsequently, an information processing apparatus according to Embodiment 4 of the present invention will be described. In the information processing apparatus according to the fourth embodiment, a shared memory is prepared, the real-time OS writes a flag indicating whether or not the interrupt generation processing of the general-purpose OS is permitted to the shared memory, and the general-purpose OS refers to the shared memory. This is to determine whether permission has been granted. Other configurations are the same as those of the third embodiment.

  FIG. 9 is a diagram showing a configuration of the information processing apparatus 1 according to the fourth embodiment. As illustrated, the information processing apparatus 1 includes an OS (1) 11, an OS (2) 12, a device 60, and a shared memory 90. The OS (2) 12 includes a thread 31, a driver 40, and an interrupt control unit 50. The driver 40 includes an entrance processing unit 41, an interrupt confirmation call processing unit 48, an IO issue processing unit 43, and an exit processing unit 44. The interrupt control unit 50 includes an interrupt confirmation processing unit 53. The OS (1) 11 includes a load control unit 70. The load control unit 70 holds average interrupt frequency data 71 and average task waiting time data 72. The shared memory 90 holds an interrupt permission flag 91.

  Next, processing of the information processing apparatus 1 according to the fourth embodiment will be described. Since the fourth embodiment has a feature in the process for determining whether or not to perform interrupt delay, this process will be mainly described.

  The interrupt confirmation call processing unit 48 requests the interrupt confirmation processing from the interrupt confirmation processing unit 53 of the interrupt control unit 50 before performing an operation that generates an interrupt in the driver 40.

  The interrupt confirmation processing unit 53 of the interrupt control unit 50 refers to the interrupt permission flag 91 of the shared memory 90 in response to the request. Here, the interrupt permission flag 91 of the shared memory 90 is set by the load control unit 70 of the OS (1) 11. Specifically, the load control unit 70, based on data such as the average interrupt frequency data 71 and the average task wait time data 72, provides statistics such as the average interrupt frequency and the task wait time taken for this interrupt. Information is measured, and it is determined using a predetermined threshold whether or not an excessive load is applied. If the load control unit 70 determines that the load is low as a result of the determination, the load control unit 70 sets an interrupt permission flag 91 indicating interrupt permission in the shared memory 90. Further, if the load control unit 70 determines that the load is high as a result of the determination, the load control unit 70 does not set the interrupt permission flag 91 in the shared memory 90.

  When the interrupt permission flag 91 is set as a result of referring to the interrupt permission flag of the shared memory 90, the interrupt confirmation processing unit 53 of the OS (2) 12 instructs the interrupt confirmation calling processing unit 48 to interrupt permission. The permission notice indicating is output. Then, the interrupt confirmation call processing unit 48 of the driver 40 executes interrupt processing in accordance with the permission notification.

  Further, as a result of referring to the interrupt permission flag 91 of the shared memory 90 as a result of the interrupt confirmation processing unit 53, if the interrupt permission flag 91 is not set, the interrupt confirmation processing unit 53 does not permit the interrupt confirmation call processing unit 48 to interrupt. The disapproval notice is output. Then, the interrupt confirmation call processing unit 48 of the driver 40 performs standby processing for a predetermined time in response to the non-permission notification. Thereafter, the interrupt confirmation call processing unit 48 requests the interrupt confirmation processing again from the interrupt confirmation processing unit 53 of the interrupt control unit 50 after a predetermined time has elapsed. Thereafter, the same processing is performed. The interrupt confirmation call processing unit 48 does not perform the interrupt processing until the interrupt permission flag 91 is set in the shared memory 90 according to the permission of the load control unit 70, and the permission by the load control unit 70 is dropped and the shared memory 90 is Interrupt processing is executed only after the interrupt permission flag 91 is set.

  As described above, in the information processing apparatus according to the fourth embodiment, the interrupt process is delayed until the real-time OS permission is obtained. Therefore, as in the information processing apparatus according to the first embodiment, the general-purpose OS is generated. The influence on the real-time OS due to the interrupt can be suppressed.

Embodiment 5 FIG.
Subsequently, an information processing apparatus according to Embodiment 5 of the present invention will be described. The information processing apparatus according to Embodiment 5 includes one OS with a relatively high priority and two OSs with a relatively low priority.

  FIG. 10 is a diagram showing a configuration of the information processing apparatus 1 according to the fifth embodiment. As illustrated, the information processing apparatus 1 includes an OS (1) 11, an OS (2) 12, an OS (3) 21, and a device 60. The OS (2) 12 and the OS (3) 21 each include a thread, a driver, and a delay time management unit, and the configuration and function thereof are the same as those of the first embodiment. The OS (1) 11 includes a load control unit 70. The load control unit 70 holds average interrupt frequency data of the OS (2) 12, average interrupt frequency data of the OS (3) 21, and average task waiting time data.

  Next, processing of the information processing apparatus 1 according to the fifth embodiment will be described. When the OS (1) 11 receives the interrupt notification from the device 60, the OS (1) 11 investigates which OS handles the notified interrupt as in the first embodiment of the invention. If the OS that should process the interrupt is OS (2) 12 or OS (3) 21, OS (1) 11 transfers the interrupt to that OS. During the transfer process, the OS (1) 11 measures the waiting time of the task generated due to the interrupt to be transferred and the frequency of occurrence of the interrupt to each OS. The acquired information is recorded for each OS, and it is confirmed whether or not the load of each OS exceeds the threshold. If it exceeds, the load information is notified for each OS. For the delay processing method, any one of the first to fourth embodiments described above is used.

  As described above, also in the information processing apparatus according to the fifth embodiment, similarly to the information processing apparatus according to the first embodiment of the invention, it is possible to suppress the influence on the real-time OS due to the interrupt generated by the general-purpose OS.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  In the present invention, for example, in an environment in which two or more different OSs share hardware on one computer and an interrupt is notified to one OS, the interrupt is not generated by an IO process by the OS that is not notified of the interrupt directly. When the load of the OS notified directly becomes high, it can be applied to a use for reducing the load caused by the interrupt.

1 is a block diagram showing a schematic configuration of an information processing apparatus according to a first embodiment of the invention. It is a block diagram which shows the structure of the information processing apparatus concerning Embodiment 1 of invention. It is a flowchart which shows the process of the information processing apparatus concerning Embodiment 1 of invention. It is a flowchart which shows the process of the information processing apparatus concerning Embodiment 1 of invention. It is a flowchart which shows the process of the information processing apparatus concerning Embodiment 1 of invention. It is a block diagram which shows the structure of the information processing apparatus concerning Embodiment 2 of invention. It is a flowchart which shows the process of the information processing apparatus concerning Embodiment 2 of invention. It is a block diagram which shows the structure of the information processing apparatus concerning Embodiment 3 of invention. It is a block diagram which shows the structure of the information processing apparatus concerning Embodiment 4 of invention. It is a block diagram which shows the structure of the information processing apparatus concerning Embodiment 5 of invention.

Explanation of symbols

1 information processing apparatus, 11 OS (1), 12 OS (2), 13 disks,
14 Ethernet (registered trademark), 15 bus controller, 16-19 CPU,
21 OS (3), 31 threads, 40 drivers, 50 delay time management unit,
60 devices, 70 load control unit, 80 scheduler, 90 shared memory

Claims (17)

A first OS having a higher priority and a second OS having a lower priority sharing hardware resources with the first OS, and the first OS receives an interrupt notification from the hardware resources An information processing apparatus that executes interrupt notification transfer processing to the second OS when the interrupt is not processed by the first OS,
Load control means for detecting a load associated with the transfer process of the first OS and determining a load state associated with the transfer process;
An information processing apparatus comprising: delay control means for delaying processing of the second OS, which generates interrupt processing by the hardware resource when the load control means determines that the load is large.   The load control means determines the state of the load based on the average interrupt frequency related to the interrupt processing by the second OS, the average task waiting time required for the interrupt processing, or both the average interrupt frequency and the average task time. The information processing apparatus according to claim 1, further comprising:   The information processing apparatus according to claim 2, wherein the load control unit determines that the load is high when the average interrupt frequency or the average task time exceeds a threshold value.   When the load control unit determines that the load is high, the delay control unit updates the delay time value so that the delay time value is increased. When the load control unit determines that the load is low, the delay control unit The information processing apparatus according to any one of claims 1 to 3, wherein the information is updated so that the value becomes smaller.   5. The information processing apparatus according to claim 1, wherein the delay control unit executes delay control for a process of connecting an execution thread to a dispatch queue.   The information processing apparatus according to claim 1, wherein the load control unit is provided in the first OS, and the delay control unit is provided in the second OS. When the load control means is provided in the first OS and the delay control means is provided in the second OS,
The delay control unit performs an interrupt notification to the load control unit provided in the first OS when performing an interrupt process to the hardware resource,
The load control means detects the load associated with the transfer process of the first OS in response to the interrupt notification, determines the state of the load associated with the transfer process, and notifies the permission notification when the load is low. When it is high, send a notice of disapproval to the delay control means
The delay control unit executes the interrupt process when receiving a permission notification, and executes the interrupt notification to the load control unit again after waiting for a predetermined time when receiving a non-permission notification. The information processing apparatus according to any one of claims 1 to 5. When the load control unit is provided in the first OS and the delay control unit is provided in the second OS,
The load control means sets an interrupt permission flag indicating the determined load state in the shared memory,
The delay control means refers to an interrupt permission flag set in the shared memory when performing an interrupt process to the hardware resource, and executes the interrupt process when an interrupt is permitted, 6. The information processing apparatus according to claim 1, wherein if the permission is not permitted, the interrupt permission flag is referred again after waiting for a predetermined time.   When the information processing apparatus has a plurality of OSs with low priorities, the load control means notifies the delay control means provided for each of the OSs with low priorities according to individual load conditions. The information processing apparatus according to claim 1, wherein: It is not an interrupt that is processed by the first OS when it shares hardware resources with the second OS with a lower priority and receives an interrupt notification from the hardware resource for the first OS with a higher priority. An interrupt control method for executing interrupt notification transfer processing to the second OS sometimes,
A load state determination step of detecting a load associated with the transfer process of the first OS and determining a load state associated with the transfer process;
An interrupt control method comprising: a delay control step of delaying the processing of the second OS, which generates an interrupt processing by the hardware resource when it is determined that the load is large.   In the load state determination step, based on the average interrupt frequency related to the interrupt processing by the second OS, the average task waiting time required for the interrupt processing, or both the average interrupt frequency and the average task time, The interrupt control method according to claim 10, wherein a state is determined.   12. The interrupt control method according to claim 11, wherein, in the load state determination step, it is determined that the load is high when the average interrupt frequency or the average task time exceeds a threshold value.   In the delay control step, when it is determined that the load is high in the load state determination step, the delay time value is updated to be large, and when the load control unit determines that the load is low, the delay time is The interrupt control method according to claim 10, wherein the interrupt control method is updated so that the value becomes smaller.   The interrupt control method according to any one of claims 10 to 13, wherein, in the delay control step, delay control is executed for a process of connecting an execution thread to a dispatch queue.   The interrupt control method according to any one of claims 10 to 14, wherein the first OS executes the load state determination step, and the second OS executes the delay control step. It is not an interrupt that is processed by the first OS when it shares hardware resources with the second OS with a lower priority and receives an interrupt notification from the hardware resource for the first OS with a higher priority. An interrupt control method for executing interrupt notification transfer processing to the second OS sometimes,
The second OS executing an interrupt notification to the first OS when performing an interrupt process on the hardware resource;
The first OS detects the load associated with the transfer process of the first OS in response to the interrupt notification, determines the load state associated with the transfer process, and sends a permission notice when the load is low. Sending a disapproval notice to the second OS when the
The second OS executes the interrupt process when receiving the permission notification, and executes the interrupt notification again with respect to the first OS after waiting for a predetermined time when receiving the non-permission notification. And an interrupt control method. It is not an interrupt that is processed by the first OS when it shares hardware resources with the second OS with a lower priority and receives an interrupt notification from the hardware resource for the first OS with a higher priority. An interrupt control method for executing interrupt notification transfer processing to the second OS sometimes,
The first OS sets an interrupt permission flag indicating a load state associated with the transfer processing of the first OS;
When the second OS performs an interrupt process to the hardware resource, the second OS refers to the interrupt permission flag, executes the interrupt process when the interrupt is permitted, and the interrupt is not permitted. And a step of referring to the interrupt permission flag again after waiting for a predetermined time.

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