JP4876553B2 - Output circuit - Google Patents

Description

  The present invention relates to an output circuit mounted on a semiconductor integrated circuit device.

(Output circuit of the first conventional example)
FIG. 10 is a circuit diagram showing an output circuit of the first conventional example. In FIG. 10, 1 is a semiconductor integrated circuit device, 2 is a first conventional output circuit mounted on the semiconductor integrated circuit device 1, 3 is an output terminal of the semiconductor integrated circuit device 1, 4 is an external signal wiring, and 5 is a termination. A resistor 6 is a termination voltage line for supplying a termination voltage VTT.

  The output circuit 2 of the first conventional example has a pre-buffer 7 and an output buffer 8. The pre-buffer 7 receives an internal output signal SA 1 output from a predetermined circuit (not shown) in the semiconductor integrated circuit device 1 and outputs a control signal SB 1, and has an inverter 9.

  In the inverter 9, 10 is a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) constituting a pull-up circuit, and 11 is an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) constituting a pull-down circuit.

  The PMOS transistor 10 has a source connected to a VDD power supply line 12 that is a first power supply line for supplying a power supply voltage VDD, and a gate connected to an input node of the prebuffer 7 (an input node of the output circuit 2 of the first conventional example) 13. The drain is connected to the output node 14 of the prebuffer 7. The NMOS transistor 11 has a drain connected to the output node 14 of the prebuffer 7, a gate connected to the input node 13 of the prebuffer 7, and a source connected to a ground line which is a second power supply line.

  The output buffer 8 receives the control signal SB1 output from the prebuffer 7 and outputs an external output signal SC1, and has an NMOS transistor 15. The NMOS transistor 15 has a drain connected to the output terminal 3, a gate connected to the output node 14 of the prebuffer 7, a source connected to the ground line, and an N-channel open drain output circuit.

  FIG. 11 is an operation waveform diagram of the output circuit 2 of the first conventional example, showing an internal output signal SA1, a control signal SB1, and an external output signal SC1. That is, in the output circuit 2 of the first conventional example, when the potential of the internal output signal SA1 is at VDD, the PMOS transistor 10 = off state, the NMOS transistor 11 = on state, and the potential of the control signal SB1 = 0V. . As a result, the NMOS transistor 15 = off state and the potential of the external output signal SC1 = VTT.

  From this state, when the internal output signal SA1 falls to 0V, the PMOS transistor 10 = on state and the NMOS transistor 11 = off state, and the control signal SB1 rises from 0V to VDD. As a result, the NMOS transistor 15 is turned on, and the external output signal SC1 falls from VTT to about 0V.

  Thereafter, when the internal output signal SA1 rises from 0V to VDD, the PMOS transistor 10 = off state and the NMOS transistor 11 = on state, and the control signal SB1 falls from VDD to 0V. As a result, the NMOS transistor 15 is turned off, and the external output signal SC1 rises from about 0V to VTT.

(Output circuit of the second conventional example)
FIG. 12 is a circuit diagram showing an output circuit of a second conventional example. In FIG. 12, 17 is a semiconductor integrated circuit device, 18 is a second conventional output circuit mounted on the semiconductor integrated circuit device 17, 19 is an output terminal of the semiconductor integrated circuit device 17, 20 is an external signal wiring, and 21 is a termination. Resistance.

  The output circuit 18 of the second conventional example has a pre-buffer 22 and an output buffer 23. The pre-buffer 22 receives an internal output signal SA 2 output from a predetermined circuit (not shown) in the semiconductor integrated circuit device 17 and outputs a control signal SB 2, and has an inverter 24.

  In the inverter 24, 25 is a PMOS transistor constituting a pull-up circuit, and 26 is an NMOS transistor constituting a pull-down circuit. The PMOS transistor 25 has a source connected to the VDD power supply line 27, a gate connected to the input node 28 of the prebuffer 22 (an input node of the output circuit 18 of the second conventional example) 28, and a source connected to the output node 29 of the prebuffer 22. Connected to. The NMOS transistor 26 has a drain connected to the output node 29 of the prebuffer 22, a gate connected to the input node 28 of the prebuffer 22, and a source connected to the ground line.

  The output buffer 23 receives the control signal SB2 output from the pre-buffer 22 and outputs an external output signal SC2, and has a PMOS transistor 30. The PMOS transistor 30 has a source connected to the VDD power supply line 27, a gate connected to the output node 29 of the prebuffer 22, and a drain connected to the output terminal 19 to constitute a P-channel open drain output circuit.

  FIG. 13 is an operation waveform diagram of the output circuit 18 of the second conventional example, showing the internal output signal SA2, the control signal SB2, and the external output signal SC2. That is, in the output circuit 18 of the second conventional example, when the potential of the internal output signal SA2 is 0V, the PMOS transistor 25 = on state, the NMOS transistor 26 = off state, and the potential of the control signal SB2 = VDD. . As a result, the PMOS transistor 30 = off state and the potential of the external output signal SC2 = 0V.

  When the internal output signal SA2 rises to VDD from this state, the PMOS transistor 25 = off state and the NMOS transistor 26 = on state, and the control signal SB2 falls from VDD to 0V. As a result, the PMOS transistor 30 is turned on, and the external output signal SC2 rises from 0V to about VDD.

  Thereafter, when the internal output signal SA2 falls from VDD to 0V, the PMOS transistor 25 = on state and the NMOS transistor 26 = off state, and the control signal SB2 rises from 0V to VDD. As a result, the PMOS transistor 30 is turned off, and the external output signal SC2 falls from about VDD to 0V.

(Output circuit of third conventional example)
FIG. 14 is a circuit diagram showing an output circuit of a third conventional example. In FIG. 14, 32 is a semiconductor integrated circuit device, 33 is a third conventional output circuit mounted on the semiconductor integrated circuit device 32, 34 is an output terminal of the semiconductor integrated circuit device 32, and 35 is an external signal wiring.

  The output circuit 33 of the third conventional example has a pre-buffer 36 and an output buffer 37. The pre-buffer 36 receives an internal output signal SA3 output from a predetermined circuit (not shown) in the semiconductor integrated circuit device 32 and receives a control signal SBP3 as a first control signal and a control as a second control signal. The signal SBN3 is output, and inverters 38 and 39 are provided.

  The inverter 38 receives the internal output signal SA3 and outputs the control signal SBP3, and has a PMOS transistor 40 that constitutes a pull-up circuit and an NMOS transistor 41 that constitutes a pull-down circuit.

  The PMOS transistor 40 has a source connected to the VDD power supply line 42, a gate connected to the input node 43 of the prebuffer 36 (an input node of the output circuit 33 of the third conventional example) 43, and a drain connected to the first buffer of the prebuffer 36. The output node 44 is connected. The NMOS transistor 41 has a drain connected to the first output node 44 of the prebuffer 36, a gate connected to the input node 43 of the prebuffer 36, and a source connected to the ground line.

  The inverter 39 receives the internal output signal SA3 and outputs the control signal SBN3, and has a PMOS transistor 45 that constitutes a pull-up circuit and an NMOS transistor 46 that constitutes a pull-down circuit.

  The PMOS transistor 45 has a source connected to the VDD power supply line 42, a gate connected to the input node 43 of the prebuffer 36, and a drain connected to the second output node 47 of the prebuffer 36. The NMOS transistor 46 has a drain connected to the second output node 47 of the prebuffer 36, a gate connected to the input node 43 of the prebuffer 36, and a source connected to the ground line.

  The output buffer 37 receives the control signals SBP3 and SBN3 output from the prebuffer 36 and outputs an external output signal SC3. The output buffer 37 includes a PMOS transistor 48 constituting a pull-up circuit and an NMOS transistor 49 constituting a pull-down circuit. Have.

  The PMOS transistor 48 has a source connected to the VDD power supply line 42, a gate connected to the first output node 44 of the prebuffer 36, and a drain connected to the output node 50 of the output buffer 37. The NMOS transistor 49 has a drain connected to the output node 50 of the output buffer 37, a gate connected to the second output node 47 of the prebuffer 36, and a source connected to the ground line.

  FIG. 15 is an operation waveform diagram of the output circuit 33 of the third conventional example, showing the internal output signal SA3, the control signals SBP3 and SBN3, and the external output signal SC3. That is, in the output circuit 33 of the third conventional example, when the potential of the internal output signal SA3 is at VDD, the PMOS transistor 40 = off state, the NMOS transistor 41 = on state, and the potential of the control signal SBP3 = 0V. . Further, the PMOS transistor 45 = off state, the NMOS transistor 46 = on state, and the potential of the control signal SBN3 = 0V. As a result, the PMOS transistor 48 is turned on, the NMOS transistor 49 is turned off, and the potential of the external output signal SC3 is VDD.

  From this state, when the internal output signal SA3 falls to 0V, the PMOS transistor 40 = on state and the NMOS transistor 41 = off state, and the control signal SBP3 rises from 0V to VDD. Further, the PMOS transistor 45 is turned on and the NMOS transistor 46 is turned off, so that the control signal SBN3 rises from 0V to VDD. As a result, the PMOS transistor 48 is turned off, the NMOS transistor 49 is turned on, and the external output signal SC3 falls from VDD to 0V.

Thereafter, when the internal output signal SA3 rises from 0V to VDD, the PMOS transistor 40 = off state and the NMOS transistor 41 = on state, and the control signal SBP3 falls from VDD to 0V. Further, the PMOS transistor 45 is turned off and the NMOS transistor 46 is turned on, and the control signal SBN3 falls from VDD to 0V. As a result, the PMOS transistor 48 is turned on and the NMOS transistor 49 is turned off, and the external output signal SC3 rises from 0V to VDD.
JP-A-8-63267 JP-A-9-311743 JP-A-9-325177

(Problems of the output circuit of the first conventional example)
In the output circuit 2 of the first conventional example shown in FIG. 10, when the threshold voltage VthN of the NMOS transistor varies due to manufacturing variations of the semiconductor integrated circuit device 1, an external output signal is generated according to the drive capability of the NMOS transistor 15 of the output buffer 8. The slew rate of SC1 will vary.

  For example, when the threshold voltage VthN of the NMOS transistor varies to the low voltage side and the internal output signal SA1 falls from VDD to 0V, the NMOS transistor 15 of the output buffer 8 is shown by a broken line W2 in FIG. As shown in FIG. 8, the external output signal SC1 acts in the direction of sharply falling, and the slew rate at the fall of the external output signal SC1 varies in the direction of increasing.

(Problems of the output circuit of the second conventional example)
In the output circuit 18 of the second conventional example shown in FIG. 12, when the threshold voltage VthP of the PMOS transistor varies due to manufacturing variations of the semiconductor integrated circuit device 17, an external output signal is generated according to the driving capability of the PMOS transistor 30 of the output buffer 23. The slew rate of SC2 will vary.

  For example, in the case where the threshold voltage VthP of the PMOS transistor varies to the high voltage side (the side where | VthP | becomes smaller), when the internal output signal SA2 rises from 0 V to VDD, the PMOS transistor 30 of the output buffer 23 As shown by the broken line W4 in FIG. 13C, the external output signal SC2 acts in a direction to rise more steeply, and the slew rate at the rise of the external output signal SC2 varies in the direction of increasing.

(Problems of the output circuit of the third conventional example)
In the output circuit 33 of the third conventional example shown in FIG. 14, when the threshold voltage VthN of the NMOS transistor varies due to manufacturing variations of the semiconductor integrated circuit device 32, an external output signal is generated according to the driving capability of the NMOS transistor 49 of the output buffer 37. The slew rate at the fall of SC3 will vary. Further, if the threshold voltage VthP of the PMOS transistor varies, the slew rate at the rising edge of the external output signal SC3 varies depending on the drive capability of the PMOS transistor 48 of the output buffer 37.

  For example, when the threshold voltage VthN of the NMOS transistor varies to the low voltage side and the internal output signal SA3 falls from VDD to 0V, the NMOS transistor 49 of the output buffer 37 is shown by a broken line W6 in FIG. Thus, the external output signal SC3 acts in a direction that falls more steeply, and the slew rate at the fall of the external output signal SC3 varies in a direction that increases.

  Further, when the threshold voltage VthP of the PMOS transistor varies on the high voltage side (where | VthP | becomes smaller), when the internal output signal SA3 rises from 0 V to VDD, the PMOS transistor 48 of the output buffer 37 As shown by the broken line W8 in FIG. 15C, the external output signal SC3 acts more steeply and the slew rate when the external output signal SC3 rises varies in the direction of increasing.

  In view of this point, an object of the present invention is to provide an output circuit that can suppress variations in the slew rate of an external output signal due to variations in the threshold voltage of transistors in an output buffer.

  The output circuit of the present invention includes a prebuffer that inputs an internal output signal and outputs a control signal, and an output buffer that inputs the control signal and outputs an external output signal, and the prebuffer includes the output buffer. And a means for adjusting a voltage change of the control signal so as to suppress a variation in slew rate of the external output signal due to a variation in threshold voltage of the transistors.

  According to the present invention, the prebuffer has means for adjusting the voltage change of the control signal so as to suppress the variation of the slew rate of the external output signal due to the variation of the threshold voltage of the transistor of the output buffer. The variation in the slew rate of the external output signal due to the variation in the threshold voltage can be suppressed.

(First embodiment)
FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the present invention. In FIG. 1, 52 is a semiconductor integrated circuit device, 53 is an output circuit of the first embodiment of the present invention mounted on the semiconductor integrated circuit device 52, 54 is an output terminal of the semiconductor integrated circuit device 52, 55 is an external signal wiring, 56 is a termination resistor, and 57 is a termination voltage line for supplying a termination voltage VTT.

  The output circuit 53 of the first embodiment of the present invention includes a prebuffer 58 having a circuit configuration different from that of the prebuffer 7 included in the output circuit 2 of the first conventional example shown in FIG. 10, and the drain of the NMOS transistor 15 is connected to the output terminal. The other components are connected in the same manner as the output circuit 2 of the first conventional example shown in FIG.

  The prebuffer 58 has a control signal voltage change adjustment circuit 59 connected between the drain of the PMOS transistor 10 and the internal output node 14 (the output node 14 of the prebuffer 7 shown in FIG. 10). The configuration is similar to the conventional prebuffer 7 shown. The control signal voltage change adjustment circuit 59 adjusts the voltage change at the rising edge of the control signal SB1, and constitutes a pull-up circuit that pulls up the control signal SB1 together with the PMOS transistor 10.

  The control signal voltage change adjustment circuit 59 includes an NMOS transistor 60, a current source 61, and a PMOS transistor 62 that forms a variable resistance element. The NMOS transistor 60 has a drain and a gate connected to the VDD power supply line 12, a source connected to the upstream end of the current source 61, and the current source 61 connected to the ground line at the downstream end. The PMOS transistor 62 has a source connected to the drain of the PMOS transistor 10, a gate connected to the source of the NMOS transistor 60, and a drain connected to the internal output node 14.

  Since the NMOS transistor 60 is diode-connected, when the threshold voltage of the NMOS transistor is VthN, the source voltage of the NMOS transistor 60 is VDD−VthN, and VDD−VthN is supplied to the gate of the PMOS transistor 62. As a result, when the PMOS transistor 10 is turned on, the source-gate voltage of the PMOS transistor 62 becomes VthN. In this example, the circuit constant is set so that the PMOS transistor 62 is turned on in this state.

  In the case of this example, the on-resistance value of the PMOS transistor 62 depends on the threshold voltage VthN of the NMOS transistor 60. When the threshold voltage VthN of the NMOS transistor 60 is high, the voltage between the source and gate of the PMOS transistor 62 increases. The on-resistance value of the transistor 62 becomes small. On the other hand, when the threshold voltage VthN of the NMOS transistor 60 is low, the source-gate voltage of the PMOS transistor 62 decreases and the on-resistance value of the PMOS transistor 62 increases.

  In the output circuit 53 of the first embodiment of the present invention configured as described above, when the potential of the internal output signal SA1 is at VDD, the PMOS transistor 10 = off state, the NMOS transistor 11 = on state, and the control signal SB1. The potential is 0V. As a result, the NMOS transistor 15 = off state and the potential of the external output signal SC1 = VTT.

  From this state, when the internal output signal SA1 falls to 0V, the PMOS transistors 10, 62 = on and the NMOS transistor 11 = off, and the control signal SB1 rises from 0V to VDD. As a result, the NMOS transistor 15 is turned on, and the external output signal SC1 falls from VTT to about 0V.

  Thereafter, when the internal output signal SA1 rises from 0V to VDD, the PMOS transistor 10 = off state and the NMOS transistor 11 = on state, and the control signal SB1 falls from VDD to 0V. As a result, the NMOS transistor 15 is turned off, and the external output signal SC1 rises from about 0V to VTT.

  As described above, in the output circuit 53 according to the first embodiment of the present invention, when the internal output signal SA1 falls from VDD to 0V, the PMOS transistors 10 and 62 are turned on, and the NMOS transistor 11 is turned off. The signal SB1 rises from 0V to VDD. As a result, the NMOS transistor 15 is turned on, and the NMOS transistor 15 falls the external output signal SC1 from VTT to about 0V. As a result, when the threshold voltage VthN of the NMOS transistor varies, the driving capability of the NMOS transistor 15 varies.

  However, if the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 52 varies to the high voltage side and the threshold voltage VthN of the NMOS transistor 60 is high, the voltage between the source and gate of the PMOS transistor 62 increases, and the PMOS transistor The on-resistance value of 62 becomes small. Therefore, the pull-up circuit including the PMOS transistor 10 and the control signal voltage change adjustment circuit 59 has a high driving capability.

  As a result, when the internal output signal SA1 falls from VDD to 0V, the rise of the control signal SB1 becomes steeper, and the NMOS transistor 15 has its threshold voltage VthN varied to the high voltage side, and its driving capability is lowered. In spite of this, it acts so that the fall of the external output signal SC1 does not become slower.

  On the other hand, when the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 52 varies toward the low voltage side and the threshold voltage VthN of the NMOS transistor 60 is low, the voltage between the source and gate of the PMOS transistor 62 becomes small. The on-resistance value of the PMOS transistor 62 increases. Accordingly, the pull-up circuit composed of the PMOS transistor 10 and the control signal voltage change adjustment circuit 59 has a low driving capability.

  As a result, when the internal output signal SA1 falls from VDD to 0V, the rise of the control signal SB1 becomes slower, and the threshold voltage VthN of the NMOS transistor 15 varies toward the low voltage side, and its driving capability increases. In spite of this, it acts so that the falling edge of the external output signal SC1 does not become steeper.

  Therefore, according to the output circuit 53 of the first embodiment of the present invention, variations in the slew rate of the external output signal SC1 due to variations in the threshold voltage VthN of the NMOS transistor 15 of the output buffer 8 can be suppressed.

(Second Embodiment)
FIG. 2 is a circuit diagram showing an output circuit according to a second embodiment of the present invention. In FIG. 2, 64 is a semiconductor integrated circuit device, 65 is an output circuit of the second embodiment of the present invention mounted on the semiconductor integrated circuit device 64, 66 is an output terminal of the semiconductor integrated circuit device 64, 67 is an external signal wiring, 68 is a termination resistor, and 69 is a termination voltage line for supplying a termination voltage VTT.

  The output circuit 65 according to the second embodiment of the present invention includes a prebuffer 70 having a circuit configuration different from that of the prebuffer 7 included in the output circuit 2 of the first conventional example shown in FIG. 10, and the drain of the NMOS transistor 15 is connected to the output terminal. The other components are the same as those of the output circuit 2 of the first conventional example shown in FIG.

  The prebuffer 70 has a control signal voltage change adjusting circuit 71 connected between the drain of the PMOS transistor 10 and the internal output node 14 (the output node 14 of the prebuffer 7 shown in FIG. 10). The configuration is similar to the conventional prebuffer 7 shown. The control signal voltage change adjustment circuit 71 adjusts the voltage change at the rise of the control signal SB1, and constitutes a pull-up circuit that pulls up the control signal SB1 together with the PMOS transistor 10.

  The control signal voltage change adjustment circuit 71 includes an NMOS transistor 72, a current source 73, and a PMOS transistor 74 that forms a variable resistance element. The NMOS transistor 72 has a drain and a gate connected to the drain of the PMOS transistor 10, a source connected to the upstream end of the current source 73, and the current source 73 connected a downstream end to the ground line. The PMOS transistor 74 has a source connected to the drain of the PMOS transistor 10, a gate connected to the source of the NMOS transistor 72, and a drain connected to the internal output node 14.

  Since the NMOS transistor 72 is diode-connected, when the threshold voltage of the NMOS transistor 72 is VthN, when the PMOS transistor 10 is turned on, the source voltage of the NMOS transistor 72 is VDD−VthN, and the gate of the PMOS transistor 74 is VDD-VthN is supplied. As a result, the source-gate voltage of the PMOS transistor 74 becomes VthN. In this example, circuit constants are set so that the PMOS transistor 74 is turned on in this state.

  In the case of this example, the on-resistance value of the PMOS transistor 74 depends on the threshold voltage VthN of the NMOS transistor 72. When the threshold voltage VthN of the NMOS transistor 72 is high, the voltage between the source and gate of the PMOS transistor 74 increases. The on-resistance value of the transistor 74 is reduced. On the other hand, when the threshold voltage VthN of the NMOS transistor 72 is low, the source-gate voltage of the PMOS transistor 74 decreases, and the on-resistance value of the PMOS transistor 74 increases.

  In the output circuit 65 of the second embodiment of the present invention configured as described above, when the potential of the internal output signal SA1 is at VDD, the PMOS transistor 10 = off state, the NMOS transistor 11 = on state, and the control signal SB1. The potential is 0V. As a result, the NMOS transistor 15 = off state and the potential of the external output signal SC1 = VTT.

  From this state, when the internal output signal SA1 falls to 0V, the PMOS transistors 10, 74 = on and the NMOS transistor 11 = off, and the control signal SB1 rises from 0V to VDD. As a result, the NMOS transistor 15 is turned on, and the external output signal SC1 falls from VTT to about 0V.

  Thereafter, when the internal output signal SA1 rises from 0V to VDD, the PMOS transistor 10 = off state and the NMOS transistor 11 = on state, and the control signal SB1 falls from VDD to 0V. As a result, the NMOS transistor 15 is turned off, and the external output signal SC1 rises from about 0V to VTT.

  As described above, in the output circuit 65 according to the second embodiment of the present invention, when the internal output signal SA1 falls from VDD to 0V, the PMOS transistors 10 and 74 are turned on, and the NMOS transistor 11 is turned off. The signal SB1 rises from 0V to VDD. As a result, the NMOS transistor 15 is turned on, and the NMOS transistor 15 falls the external output signal SC1 from VTT to about 0V. As a result, when the threshold voltage VthN of the NMOS transistor varies, the driving capability of the NMOS transistor 15 varies.

  However, if the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 64 varies to the high voltage side and the threshold voltage VthN of the NMOS transistor 72 is high, the voltage between the source and gate of the PMOS transistor 74 increases, and the PMOS transistor The on-resistance value of 74 becomes small. Therefore, the pull-up circuit composed of the PMOS transistor 10 and the control signal voltage change adjusting circuit 71 has a high driving capability.

  As a result, when the internal output signal SA1 falls from VDD to 0V, the rise of the control signal SB1 becomes steeper, and the NMOS transistor 15 has its threshold voltage VthN varied to the high voltage side, and its driving capability is lowered. In spite of this, it acts so that the fall of the external output signal SC1 does not become slower.

  On the other hand, when the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 64 varies toward the low voltage side and the threshold voltage VthN of the NMOS transistor 72 is low, the voltage between the source and gate of the PMOS transistor 74 becomes small. The on-resistance value of the PMOS transistor 74 increases. Accordingly, the pull-up circuit composed of the PMOS transistor 10 and the control signal voltage change adjusting circuit 71 has a small driving capability.

  As a result, when the internal output signal SA1 falls from VDD to 0V, the rise of the control signal SB1 becomes slower, and the threshold voltage VthN of the NMOS transistor 15 varies toward the low voltage side, and its driving capability increases. In spite of this, it acts so that the falling edge of the external output signal SC1 does not become steeper.

  Therefore, according to the output circuit 65 of the second embodiment of the present invention, variations in the slew rate of the external output signal SC1 due to variations in the threshold voltage VthN of the NMOS transistor 15 in the output buffer 8 can be suppressed.

(Third embodiment)
FIG. 3 is a circuit diagram showing an output circuit according to a third embodiment of the present invention. In FIG. 3, 76 is a semiconductor integrated circuit device, 77 is an output circuit of the third embodiment of the present invention mounted on the semiconductor integrated circuit device 76, 78 is an output terminal of the semiconductor integrated circuit device 76, 79 is an external signal wiring, 80 is a termination resistor, and 81 is a termination voltage line for supplying a termination voltage VTT.

  The output circuit 77 according to the third embodiment of the present invention includes a pre-buffer 7 having a circuit configuration different from that of the pre-buffer 7 included in the output circuit 2 of the first conventional example shown in FIG. 10, and the drain of the NMOS transistor 15 is connected to the output terminal. The other components are connected in the same manner as the output circuit 2 of the first conventional example shown in FIG.

  The prebuffer 82 is configured by connecting the control voltage output node of the control signal voltage change adjusting circuit 83 to the substrate (back gate) of the PMOS transistor 10 and is otherwise configured in the same manner as the prebuffer 7 shown in FIG. . The control signal voltage change adjusting circuit 83 adjusts the voltage change at the rising edge of the control signal SB1, and constitutes a pull-up circuit that pulls up the control signal SB1 together with the PMOS transistor 10.

  The control signal voltage change adjustment circuit 83 includes an NMOS transistor 84 and a current source 85. The NMOS transistor 84 has a drain and a gate connected to the VDD power supply line 12, a source connected to the upstream end of the current source 85 and the substrate (back gate) of the PMOS transistor 10, and the current source 85 connected a downstream end to the ground line. is doing.

  Since the NMOS transistor 84 is diode-connected, when the threshold voltage of the NMOS transistor 84 is VthN, the source voltage of the NMOS transistor 84 becomes VDD−VthN, and VDD−VthN is supplied to the substrate (back gate) of the PMOS transistor 10. Is done.

  In the case of this example, the threshold voltage VthP of the PMOS transistor 10 depends on the threshold voltage VthN of the NMOS transistor 84. When the threshold voltage VthN of the NMOS transistor 84 is high, the source-substrate voltage (source-back gate) of the PMOS transistor 10 is increased. And the threshold voltage VthP of the PMOS transistor 10 is increased (| VthP | is decreased). On the other hand, when the threshold voltage VthN of the NMOS transistor 84 is low, the source-substrate voltage of the PMOS transistor 10 decreases and the threshold voltage VthP of the PMOS transistor 10 decreases (| VthP | increases).

  In the output circuit 77 of the third embodiment of the present invention configured as described above, when the potential of the internal output signal SA1 is at VDD, the PMOS transistor 10 = off state, the NMOS transistor 11 = on state, and the control signal SB1. The potential is 0V. As a result, the NMOS transistor 15 = off state and the potential of the external output signal SC1 = VTT.

  From this state, when the internal output signal SA1 falls to 0V, the PMOS transistor 10 = on state and the NMOS transistor 11 = off state, and the control signal SB1 rises from 0V to VDD. As a result, the NMOS transistor 15 is turned on, and the external output signal SC1 falls from VTT to about 0V.

  Thereafter, when the internal output signal SA1 rises from 0V to VDD, the PMOS transistor 10 = off state and the NMOS transistor 11 = on state, and the control signal SB1 rises from 0 to VDD. As a result, the NMOS transistor 15 is turned off, and the external output signal SC1 rises from about 0V to VTT.

  As described above, in the output circuit 77 of the third embodiment of the present invention, when the internal output signal SA1 falls from VDD to 0V, the PMOS transistor 10 = on state and the NMOS transistor 11 = off state, and the control signal SB1. Rises from 0V to VDD. As a result, the NMOS transistor 15 is turned on, and the NMOS transistor 15 falls the external output signal SC1 from VTT to about 0V. When the threshold voltage VthN of the transistor varies, the driving capability of the NMOS transistor 15 varies.

  However, if the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 76 varies to the high voltage side and the threshold voltage VthN of the NMOS transistor 84 is high, the source-substrate voltage (source-back gate) of the PMOS transistor 10 is increased. Voltage) increases, and the threshold voltage VthP of the PMOS transistor 10 increases (| VthP | decreases). Therefore, the driving capability of the PMOS transistor 10 is increased.

  As a result, when the internal output signal SA1 falls from VDD to 0V, the rise of the control signal SB1 becomes steeper, and the NMOS transistor 15 has its threshold voltage VthN varied to the high voltage side, and its driving capability is lowered. In spite of this, it acts so that the fall of the external output signal SC1 does not become slower.

  On the other hand, when the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 76 varies toward the low voltage side and the threshold voltage VthN of the NMOS transistor 84 is low, the voltage between the source and substrate of the PMOS transistor 10 (source The voltage between the back gates) decreases, and the threshold voltage VthP of the PMOS transistor 10 decreases (| VthP | increases). Therefore, the driving capability of the PMOS transistor 10 is reduced.

  As a result, when the internal output signal SA1 falls from VDD to 0V, the rise of the control signal SB1 becomes slower, and the threshold voltage VthN of the NMOS transistor 15 varies toward the low voltage side, and its driving capability increases. In spite of this, it acts so that the falling edge of the external output signal SC1 does not become steeper.

  Therefore, according to the output circuit 77 of the third embodiment of the present invention, variations in the slew rate of the external output signal SC1 due to variations in the threshold voltage VthN of the NMOS transistor 15 of the output buffer 8 can be suppressed.

(Fourth embodiment)
FIG. 4 is a circuit diagram showing an output circuit according to a fourth embodiment of the present invention. In FIG. 4, 87 is a semiconductor integrated circuit device, 88 is an output circuit of the fourth embodiment of the present invention mounted on the semiconductor integrated circuit device 87, 89 is an output terminal of the semiconductor integrated circuit device 87, 90 is an external signal wiring, 91 is a terminal resistor.

  An output circuit 88 according to the fourth embodiment of the present invention includes a prebuffer 92 having a circuit configuration different from that of the prebuffer 22 included in the output circuit 18 of the second conventional example shown in FIG. 12, and the drain of the PMOS transistor 30 is connected to the output terminal. The other components are connected in the same manner as the output circuit 18 of the second conventional example shown in FIG.

  The pre-buffer 92 has a control signal voltage change adjustment circuit 93 connected between the internal output node 29 (the output node 29 of the pre-buffer 22 shown in FIG. 12) and the drain of the NMOS transistor 26, and the others are shown in FIG. The same configuration as the pre-buffer 22 shown in FIG. The control signal voltage change adjustment circuit 93 adjusts the voltage change at the fall of the control signal SB2, and constitutes a pull-down circuit that pulls down the control signal SB2 together with the NMOS transistor 26.

  The control signal voltage change adjustment circuit 93 includes a current source 94, a PMOS transistor 95, and an NMOS transistor 96 that forms a variable resistance element. The current source 94 has an upstream end connected to the VDD power supply line 27, and the PMOS transistor 95 has a source connected to the downstream end of the current source 94, and a gate and a drain connected to the ground line. The NMOS transistor 96 has a drain connected to the internal output node 29, a gate connected to the source of the PMOS transistor 95, and a source connected to the drain of the NMOS transistor 26.

  Since the PMOS transistor 95 is diode-connected, if the threshold voltage of the PMOS transistor 95 is VthP, the source voltage of the PMOS transistor 95 is | VthP |, and | VthP | is supplied to the gate of the NMOS transistor 96. As a result, when the NMOS transistor 26 is turned on, the gate-source voltage of the NMOS transistor 96 becomes | VthP |. In this example, the circuit constant is set so that the NMOS transistor 96 is turned on in this state.

  In the case of this example, the on-resistance value of the NMOS transistor 96 depends on the threshold voltage VthP of the PMOS transistor 95. When the threshold voltage VthP of the PMOS transistor 95 is low (| VthP | is large), The voltage between the transistors increases, and the on-resistance value of the NMOS transistor 96 decreases. On the other hand, when the threshold voltage VthP of the PMOS transistor 95 is high (| VthP | is small), the gate-source voltage of the NMOS transistor 96 becomes small and the on-resistance value of the NMOS transistor 96 becomes large.

  In the output circuit 88 of the fourth embodiment of the present invention configured as described above, when the potential of the internal output signal SA2 is 0V, the PMOS transistor 25 = on state, the NMOS transistor 26 = off state, and the control signal SB2 The potential is VDD. As a result, the PMOS transistor 30 = off state and the potential of the external output signal SC2 = 0V.

  From this state, when the internal output signal SA2 falls to VDD, the PMOS transistor 25 = off state and the NMOS transistors 26, 96 = on state, and the control signal SB2 falls from VDD to 0V. As a result, the PMOS transistor 30 is turned on, and the external output signal SC2 rises from 0V to about VDD.

  Thereafter, when the internal output signal SA2 falls to 0V, the PMOS transistor 25 = on state and the NMOS transistor 26 = off state, and the control signal SB2 rises from 0V to VDD. As a result, the PMOS transistor 30 is turned off, and the external output signal SC2 falls from about VDD to 0V.

  As described above, in the output circuit 88 of the fourth embodiment of the present invention, when the internal output signal SA2 rises from 0V to VDD, the PMOS transistor 25 = off state and the NMOS transistors 26, 96 = on state, and the control signal SB2 falls from VDD to 0V. As a result, the PMOS transistor 30 is turned on, and the PMOS transistor 30 raises the external output signal SC2 from 0V to about VDD. However, manufacturing variations of the semiconductor integrated circuit device 87 occur. As a result, when the threshold voltage VthP of the PMOS transistor varies, the driving capability of the PMOS transistor 30 varies.

  However, when the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 87 varies to the low voltage side and the threshold voltage VthP of the PMOS transistor 95 is low (| VthP | is large), the gate of the NMOS transistor 96 -The source-to-source voltage increases and the on-resistance value of the NMOS transistor 96 decreases. Therefore, the pull-down circuit composed of the NMOS transistor 26 and the control signal voltage change adjusting circuit 93 has a high driving capability.

  As a result, when the internal output signal SA2 rises from 0V to VDD, the fall of the control signal SB2 becomes steeper, and the threshold voltage VthP of the PMOS transistor 30 varies toward the low voltage side, and its driving capability is lowered. In spite of this, it acts so that the rising edge of the external output signal SC2 does not become slower.

  On the other hand, when the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 87 varies to the high voltage side, and the threshold voltage VthP of the PMOS transistor 95 is high (| VthP | is small), the NMOS transistor The gate-source voltage of 96 decreases, and the on-resistance value of the NMOS transistor 96 increases. Therefore, the pull-down circuit composed of the NMOS transistor 26 and the control signal voltage change adjusting circuit 93 has a low driving capability.

  As a result, when the internal output signal SA2 rises from 0V to VDD, the fall of the control signal SB2 becomes slower, and the PMOS transistor 30 has its threshold voltage VthP varied to the high voltage side and its driving capability is increased. Nevertheless, the rise of the external output signal SC2 is prevented from becoming steeper.

  Therefore, according to the output circuit 88 of the fourth embodiment of the present invention, variation in the slew rate of the external output signal SC2 due to variation in the threshold voltage VthP of the PMOS transistor 30 of the output buffer 23 can be suppressed.

(Fifth embodiment)
FIG. 5 is a circuit diagram showing an output circuit according to a fifth embodiment of the present invention. In FIG. 5, 98 is a semiconductor integrated circuit device, 99 is an output circuit of the fifth embodiment of the present invention mounted on the semiconductor integrated circuit device 98, 100 is an output terminal of the semiconductor integrated circuit device 98, 101 is an external signal wiring, Reference numeral 102 denotes a termination resistor.

  The output circuit 99 of the fifth embodiment of the present invention includes a pre-buffer 103 having a circuit configuration different from that of the pre-buffer 22 included in the output circuit 18 of the second conventional example shown in FIG. 12, and the drain of the PMOS transistor 30 is connected to the output terminal. The other components are connected in the same manner as the output circuit 18 of the second conventional example shown in FIG.

  The pre-buffer 103 has a control signal voltage change adjusting circuit 104 connected between the internal output node 29 (the output node 29 of the pre-buffer 22 shown in FIG. 12) and the drain of the NMOS transistor 26. The same configuration as the pre-buffer 22 shown in FIG. The control signal voltage change adjustment circuit 104 adjusts the voltage change at the fall of the control signal SB2, and constitutes a pull-down circuit that pulls down the control signal SB2 together with the NMOS transistor 26.

  The control signal voltage change adjustment circuit 104 includes a current source 105, a PMOS transistor 106, and an NMOS transistor 107 that forms a variable resistance element. The current source 105 has an upstream end connected to the VDD power supply line 27, and the PMOS transistor 106 has a source connected to the downstream end of the current source 105, and a gate and drain connected to the drain of the NMOS transistor 26. The NMOS transistor 107 has a drain connected to the internal output node 29, a gate connected to the source of the PMOS transistor 106, and a source connected to the drain of the NMOS transistor 26.

  Since the PMOS transistor 106 is diode-connected, when the threshold voltage of the PMOS transistor 106 is VthP, when the NMOS transistor 26 is in the on state, the source voltage of the PMOS transistor 106 is | VthP | | VthP | is supplied. As a result, when the NMOS transistor 26 is turned on, the gate-source voltage of the NMOS transistor 107 becomes | VthP |. In this example, the circuit constant is set so that the NMOS transistor 107 is turned on in this state.

  In this example, the on-resistance value of the NMOS transistor 107 depends on the threshold voltage VthP of the PMOS transistor 106. When the threshold voltage VthP of the PMOS transistor 106 is low (| VthP | is large), the gate-source of the NMOS transistor 107 The voltage between the transistors increases, and the on-resistance value of the NMOS transistor 107 decreases. On the other hand, when the threshold voltage VthP of the PMOS transistor 106 is high (| VthP | is small), the gate-source voltage of the NMOS transistor 107 decreases, and the on-resistance value of the NMOS transistor 107 increases.

  In the output circuit 99 of the fifth embodiment of the present invention configured as described above, when the potential of the internal output signal SA2 is 0V, the PMOS transistor 25 = on state, the NMOS transistor 26 = off state, and the control signal SB2 The potential is VDD. As a result, the PMOS transistor 30 = off state and the potential of the external output signal SC2 = 0V.

  When the internal output signal SA2 rises to VDD from this state, the PMOS transistor 25 = off state and the NMOS transistors 26 and 107 = on state, and the control signal SB2 falls from VDD to 0V. As a result, the PMOS transistor 30 is turned on, and the external output signal SC2 rises from 0V to about VDD.

  Thereafter, when the internal output signal SA2 falls to 0V, the PMOS transistor 25 = on state and the NMOS transistor 26 = off state, and the control signal SB2 rises from 0V to VDD. As a result, the PMOS transistor 30 is turned off, and the external output signal SC2 falls from about VDD to 0V.

  As described above, in the output circuit 99 according to the fifth embodiment of the present invention, when the internal output signal SA2 rises from 0V to VDD, the PMOS transistor 25 = off state and the NMOS transistors 26, 107 = on state, and the control signal SB2 falls from VDD to 0V. As a result, the PMOS transistor 30 is turned on, and the PMOS transistor 30 raises the external output signal SC2 from 0V to about VDD. However, manufacturing variations of the semiconductor integrated circuit device 98 occur. As a result, when the threshold voltage VthP of the PMOS transistor varies, the driving capability of the PMOS transistor 30 varies.

  However, if the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 98 varies toward the low voltage side and the threshold voltage VthP of the PMOS transistor 106 is low (| VthP | is large), the gate of the NMOS transistor 107 -The source-to-source voltage increases and the on-resistance value of the NMOS transistor 107 decreases. Therefore, the pull-down circuit composed of the NMOS transistor 26 and the control signal voltage change adjusting circuit 104 has a high driving capability.

  As a result, when the internal output signal SA2 rises from 0V to VDD, the fall of the control signal SB2 becomes steeper, and the threshold voltage VthP of the PMOS transistor 30 varies toward the low voltage side, and its driving capability is lowered. In spite of this, it acts so that the rising edge of the external output signal SC2 does not become slower.

  On the other hand, when the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 98 varies toward the high voltage side and the threshold voltage VthP of the PMOS transistor 106 is high (| VthP | is small), the NMOS transistor The source-gate voltage of 107 decreases, and the on-resistance value of the NMOS transistor 107 increases. Therefore, the pull-down circuit composed of the NMOS transistor 26 and the control signal voltage change adjusting circuit 104 has a small driving capability.

  As a result, when the internal output signal SA2 rises from 0V to VDD, the fall of the control signal SB2 becomes slower, and the PMOS transistor 30 has its threshold voltage VthP varied to the high voltage side and its driving capability is increased. Nevertheless, the rise of the external output signal SC2 is prevented from becoming steeper.

  Therefore, according to the output circuit 99 of the fifth embodiment of the present invention, variations in the slew rate of the external output signal SC2 due to variations in the threshold voltage VthP of the PMOS transistor 30 of the output buffer 23 can be suppressed.

(Sixth embodiment)
FIG. 6 is a circuit diagram showing an output circuit according to a sixth embodiment of the present invention. In FIG. 6, 109 is a semiconductor integrated circuit device, 110 is an output circuit of the sixth embodiment of the present invention mounted on the semiconductor integrated circuit device 109, 111 is an output terminal of the semiconductor integrated circuit device 109, 112 is an external signal wiring, Reference numeral 113 denotes a termination resistor.

  The output circuit 110 according to the sixth embodiment of the present invention includes a prebuffer 114 having a circuit configuration different from that of the prebuffer 22 included in the output circuit 18 of the second conventional example shown in FIG. 12, and the drain of the PMOS transistor 30 is connected to the output terminal. The other components are connected in the same manner as the output circuit 18 of the second conventional example shown in FIG.

  The pre-buffer 114 is configured by connecting the control voltage output node of the control signal voltage change adjustment circuit 115 to the substrate (back gate) of the NMOS transistor 26, and the others are configured in the same manner as the pre-buffer 22 shown in FIG. . The control signal voltage change adjustment circuit 115 adjusts the voltage change at the fall of the control signal SB2, and constitutes a pull-down circuit that pulls down the control signal SB2 together with the NMOS transistor 26.

  The control signal voltage change adjustment circuit 115 includes a current source 116 and a PMOS transistor 117. The current source 116 has an upstream end connected to the VDD power supply line 27, and the PMOS transistor 117 has a source connected to the downstream end of the current source 116 and the substrate (back gate) of the NMOS transistor 26, and a gate and a drain connected to the ground line. is doing.

  Since the PMOS transistor 117 is diode-connected, if the threshold voltage of the PMOS transistor 117 is VthP, the source voltage of the PMOS transistor 117 is | VthP |, and | VthP | is supplied to the substrate (back gate) of the NMOS transistor 26. Is done.

  In this example, the on-resistance value of the NMOS transistor 26 depends on the threshold voltage VthP of the PMOS transistor 117. When the threshold voltage VthP of the PMOS transistor 117 is low (| VthP | is large), the substrate / source of the NMOS transistor 26 The inter-voltage (back gate-source voltage) increases, and the threshold voltage VthN of the NMOS transistor 26 decreases. On the other hand, when the threshold voltage VthP of the PMOS transistor 117 is high (| VthP | is small), the substrate-source voltage of the NMOS transistor 26 is small, and the threshold voltage VthN of the NMOS transistor 26 is high.

  In the output circuit 110 of the sixth embodiment of the present invention configured as described above, when the potential of the internal output signal SA2 is 0V, the PMOS transistor 25 = on state, the NMOS transistor 26 = off state, and the control signal SB2 The potential is VDD. As a result, the PMOS transistor 30 = off state and the potential of the external output signal SC2 = 0V.

  When the internal output signal SA2 rises to VDD from this state, the PMOS transistor 25 = off state and the NMOS transistor 26 = on state, and the control signal SB2 falls from VDD to 0V. As a result, the PMOS transistor 30 is turned on, and the external output signal SC2 rises from 0V to about VDD.

  Thereafter, when the internal output signal SA2 falls to 0V, the PMOS transistor 25 = on state and the NMOS transistor 26 = off state, and the control signal SB2 rises from 0V to VDD. As a result, the PMOS transistor 30 is turned off, and the external output signal SC2 falls from about VDD to 0V.

  As described above, in the output circuit 110 according to the sixth embodiment of the present invention, when the internal output signal SA2 rises from 0V to VDD, the PMOS transistor 25 = off state and the NMOS transistor 26 = on state, and the control signal SB2 is As a result, the voltage drops from VDD to 0V. As a result, the PMOS transistor 30 is turned on, and the PMOS transistor 30 raises the external output signal SC2 from 0V to about VDD. When the threshold voltage VthP of the transistor varies, the driving capability of the PMOS transistor 30 varies.

  However, if the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 109 varies toward the low voltage side and the threshold voltage VthP of the PMOS transistor 117 is low (| VthP | is large), the substrate of the NMOS transistor 26 The source voltage (back gate-source voltage) increases, and the threshold voltage VthN of the NMOS transistor 26 decreases. Therefore, the driving capability of the NMOS transistor 26 is increased.

  As a result, when the internal output signal SA2 rises from 0V to VDD, the fall of the control signal SB2 becomes steeper, and the threshold voltage VthP of the PMOS transistor 30 varies toward the low voltage side, and its driving capability is lowered. In spite of this, it acts so that the rising edge of the external output signal SC2 does not become slower.

  On the other hand, when the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 109 varies toward the high voltage side and the threshold voltage VthP of the PMOS transistor 117 is high (| VthP | is small), the NMOS transistor The substrate-source voltage (back gate-source voltage) 26 of the NMOS transistor 26 decreases, and the threshold voltage VthN of the NMOS transistor 26 increases. Therefore, the driving capability of the NMOS transistor 26 is lowered.

  As a result, when the internal output signal SA2 rises from 0V to VDD, the fall of the control signal SB2 becomes slower, and the PMOS transistor 30 has its threshold voltage VthP varied to the high voltage side and its driving capability is increased. Nevertheless, the rise of the external output signal SC2 is prevented from becoming steeper.

  Therefore, according to the output circuit 110 of the sixth embodiment of the present invention, variations in the slew rate of the external output signal SC2 due to variations in the threshold voltage VthP of the PMOS transistor 30 of the output buffer 23 can be suppressed.

(Seventh embodiment)
FIG. 7 is a circuit diagram showing an output circuit according to a seventh embodiment of the present invention. In FIG. 7, 119 is a semiconductor integrated circuit device, 120 is an output circuit of the seventh embodiment of the present invention mounted on the semiconductor integrated circuit device 119, 121 is an output terminal of the semiconductor integrated circuit device 119, and 122 is an external signal wiring. is there.

  The output circuit 120 of the seventh embodiment of the present invention includes a prebuffer 123 having a circuit configuration different from that of the prebuffer 36 included in the output circuit 33 of the third conventional example shown in FIG. 14, and an output node 50 of the output buffer 37. The other components are connected in the same manner as the output circuit 33 of the third conventional example shown in FIG.

  The pre-buffer 123 has an inverter 124 that forms a first pre-buffer and an inverter 125 that forms a second pre-buffer. The inverter 124 connects the control signal voltage change adjustment circuit 126 between the internal output node 44 (the first output node 44 of the prebuffer 36 shown in FIG. 14) and the drain of the NMOS transistor 41. 14 is configured similarly to the inverter 38 shown in FIG.

  The control signal voltage change adjustment circuit 126 adjusts the voltage change at the fall of the control signal SBP3, and constitutes a pull-down circuit that pulls down the control signal SBP3 together with the NMOS transistor 41.

  The control signal voltage change adjustment circuit 126 includes a current source 127, a PMOS transistor 128, and an NMOS transistor 129 that forms a variable resistance element. The current source 127 has an upstream end connected to the VDD power supply line 42, and the PMOS transistor 128 has a source connected to the downstream end of the current source 127, and a gate and a drain connected to the ground line. The NMOS transistor 129 has a drain connected to the internal output node 44, a gate connected to the source of the PMOS transistor 128, and a source connected to the drain of the NMOS transistor 41.

  Since the PMOS transistor 128 is diode-connected, if the threshold voltage of the PMOS transistor 128 is VthP, the source voltage of the PMOS transistor 128 is | VthP |, and | VthP | is supplied to the gate of the NMOS transistor 129. As a result, when the NMOS transistor 41 is turned on, the gate-source voltage of the NMOS transistor 129 becomes | VthP |. In this example, the circuit constant is set so that the NMOS transistor 129 is turned on in this state.

  In this example, the on-resistance value of the NMOS transistor 129 depends on the threshold voltage VthP of the PMOS transistor 128. When the threshold voltage VthP of the PMOS transistor 128 is low (| VthP | is large), the gate-source of the NMOS transistor 129 The voltage between the transistors increases, and the on-resistance value of the NMOS transistor 129 decreases. On the other hand, when the threshold voltage VthP of the PMOS transistor 128 is high (| VthP | is small), the gate-source voltage of the NMOS transistor 129 decreases, and the on-resistance value of the NMOS transistor 129 increases.

  The inverter 125 connects the control signal voltage change adjustment circuit 130 between the drain of the PMOS transistor 45 and the internal output node 47 (second output node 47 of the prebuffer 36 shown in FIG. 14). 14 is configured similarly to the inverter 39 shown in FIG. The control signal voltage change adjustment circuit 130 adjusts the voltage change at the rise of the control signal SBN3, and constitutes a pull-up circuit that pulls up the control signal SBN3 together with the PMOS transistor 45.

  The control signal voltage change adjustment circuit 130 includes an NMOS transistor 131, a current source 132, and a PMOS transistor 133 serving as a variable resistance element. The NMOS transistor 131 has a drain and a gate connected to the VDD power supply line 42, a source connected to the upstream end of the current source 132, and the current source 132 connected to the ground line at the downstream end. The PMOS transistor 133 has a source connected to the drain of the PMOS transistor 45, a gate connected to the source of the NMOS transistor 131, and a drain connected to the internal output node 47.

  Since the NMOS transistor 131 is diode-connected, when the threshold voltage of the NMOS transistor 131 is VthN, the source voltage of the NMOS transistor 131 is VDD−VthN, and VDD−VthN is supplied to the gate of the PMOS transistor 133. As a result, when the PMOS transistor 45 is turned on, the source-gate voltage of the PMOS transistor 133 becomes VthN. In this example, the circuit constant is set so that the PMOS transistor 133 is turned on in this state.

  In the case of this example, the on-resistance value of the PMOS transistor 133 depends on the threshold voltage VthN of the NMOS transistor 131. When the threshold voltage VthN of the NMOS transistor 131 is high, the voltage between the source and gate of the PMOS transistor 133 increases. The on-resistance value of 133 becomes small. On the other hand, when the threshold voltage VthN of the NMOS transistor 131 is low, the source-gate voltage of the PMOS transistor 133 decreases and the on-resistance value of the PMOS transistor 133 increases.

  In the output circuit 120 of the seventh embodiment of the present invention configured as above, when the potential of the internal output signal SA3 is at VDD, the PMOS transistor 40 = off state, the NMOS transistors 41, 129 = on state, the control signal The potential of SBP3 is 0V. Further, the PMOS transistor 45 = off state, the NMOS transistor 46 = on state, and the potential of the control signal SBN3 = 0V. As a result, the PMOS transistor 48 is turned on, the NMOS transistor 49 is turned off, and the potential of the external output signal SC3 is VDD.

  From this state, when the potential of the internal output signal SA3 falls to 0V, the PMOS transistor 40 = on state and the NMOS transistor 41 = off state, and the control signal SBP3 rises from 0V to VDD. Further, the PMOS transistors 45 and 133 are turned on, the NMOS transistor 46 is turned off, and the control signal SBN3 rises from 0V to VDD. As a result, the PMOS transistor 48 is turned off, the NMOS transistor 49 is turned on, and the external output signal SC3 falls from VDD to 0V.

  Thereafter, when the potential of the internal output signal SA3 rises to VDD, the PMOS transistor 40 = off state and the NMOS transistors 41, 129 = on state, and the control signal SBP3 falls from VDD to 0V. Further, the PMOS transistor 45 is turned off and the NMOS transistor 46 is turned on, and the control signal SBN3 falls from VDD to 0V. As a result, the PMOS transistor 48 is turned on and the NMOS transistor 49 is turned off, and the external output signal SC3 rises from 0V to VDD.

  As described above, in the output circuit 120 of the seventh embodiment of the present invention, when the internal output signal SA3 rises from 0V to VDD, the PMOS transistor 40 = off state and the NMOS transistors 41, 129 = on state, and the control signal SBP3 falls from VDD to 0V, and the PMOS transistor 48 is turned on. Further, the PMOS transistor 45 is turned off, the NMOS transistor 46 is turned on, the control signal SBN3 falls from VDD to 0 V, and the NMOS transistor 49 is turned off.

  As a result, the PMOS transistor 48 raises the external output signal SC3 from 0V to VDD. However, if the threshold voltage VthP of the PMOS transistor varies due to manufacturing variations of the semiconductor integrated circuit device 119, the driving capability of the PMOS transistor 48 is reduced. It will vary.

  However, when the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 119 varies to the low voltage side and the threshold voltage VthP of the PMOS transistor 128 is low (| VthP | is large), the gate of the NMOS transistor 129 -The source-to-source voltage increases and the on-resistance value of the NMOS transistor 129 decreases. Therefore, the pull-down circuit composed of the NMOS transistor 41 and the control signal voltage change adjustment circuit 126 has a high driving capability.

  As a result, when the internal output signal SA3 rises from 0V to VDD, the fall of the control signal SBP3 becomes steeper, and the PMOS transistor 48 has its threshold voltage VthP on the low voltage side, and its driving capability is lowered. Despite this, the rise of the external output signal SC3 acts so as not to become slower.

  On the other hand, when the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 119 varies toward the high voltage side and the threshold voltage VthP of the PMOS transistor 128 is high (| VthP | is small), the NMOS transistor The gate-source voltage of 129 decreases, and the on-resistance value of the NMOS transistor 129 increases. Accordingly, the pull-down circuit composed of the NMOS transistor 41 and the control signal voltage change adjustment circuit 126 has a small driving capability.

  As a result, when the internal output signal SA3 rises from 0V to VDD, the fall of the control signal SBP3 becomes more gradual, and the PMOS transistor 48 has its threshold voltage VthP varied to the high voltage side, and its driving capability is increased. Nevertheless, the rise of the external output signal SC3 is prevented from becoming steeper.

  Therefore, according to the output circuit 120 of the seventh embodiment of the present invention, variations in the slew rate of the external output signal SC3 due to variations in the threshold voltage VthP of the PMOS transistor 48 of the output buffer 37 can be suppressed.

  In the output circuit 120 according to the seventh embodiment of the present invention, when the internal output signal SA3 falls from VDD to 0V, the PMOS transistor 40 = on state and the NMOS transistor 41 = off state, and the control signal SBP3 starts from 0V. The voltage rises to VDD, and the PMOS transistor 48 is turned off. Further, the PMOS transistors 45 and 133 are turned on, the NMOS transistor 46 is turned off, the control signal SBN3 rises from 0 V to VDD, and the NMOS transistor 49 is turned on.

  As a result, the NMOS transistor 49 causes the external output signal SC3 to fall from VDD to 0V. However, if the threshold voltage VthN of the NMOS transistor varies due to manufacturing variations of the semiconductor integrated circuit device 119, the driving capability of the NMOS transistor 49 is reduced. It will vary.

  However, if the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 119 varies to the high voltage side and the threshold voltage VthN of the NMOS transistor 131 is high, the voltage between the source and gate of the PMOS transistor 133 increases, and the PMOS transistor The on-resistance value of 133 becomes small. Therefore, the pull-up circuit composed of the PMOS transistor 45 and the control signal voltage change adjustment circuit 130 has a high driving capability.

  As a result, when the internal output signal SA3 falls from VDD to 0V, the rise of the control signal SBN3 becomes steeper, and the NMOS transistor 49 has its threshold voltage VthN varied to the high voltage side and its driving capability is lowered. In spite of this, it acts so that the falling of the external output signal SC3 does not become slower.

  On the other hand, when the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 119 varies to the low voltage side and the threshold voltage VthN of the NMOS transistor 131 is low, the voltage between the source and gate of the PMOS transistor 133 becomes small. The on-resistance value of the PMOS transistor 133 increases, and the pull-up circuit composed of the PMOS transistor 45 and the control signal voltage change adjustment circuit 130 increases the driving capability.

  As a result, when the internal output signal SA3 falls from VDD to 0V, the rise of the control signal SBN3 becomes slower and the NMOS transistor 49 has its threshold voltage VthN fluctuated on the low voltage side, and its driving capability is increased. In spite of this, it acts so that the falling edge of the external output signal SC3 does not become steeper.

  Therefore, according to the output circuit 120 of the seventh embodiment of the present invention, variations in the slew rate of the external output signal SC3 due to variations in the threshold voltage VthN of the NMOS transistor 49 of the output buffer 37 can be suppressed.

(Eighth embodiment)
FIG. 8 is a circuit diagram showing an output circuit according to an eighth embodiment of the present invention. In FIG. 8, 135 is a semiconductor integrated circuit device, 136 is an output circuit of the eighth embodiment of the present invention mounted on the semiconductor integrated circuit device 135, 137 is an output terminal of the semiconductor integrated circuit device 135, and 138 is an external signal wiring. is there.

  The output circuit 136 according to the eighth embodiment of the present invention includes a prebuffer 139 having a circuit configuration different from that of the prebuffer 36 included in the output circuit 33 of the third conventional example shown in FIG. 14, and an output node 50 of the output buffer 37. The other components are connected in the same manner as the output circuit 33 of the third conventional example shown in FIG.

  The pre-buffer 139 includes an inverter 140 that forms a first pre-buffer and an inverter 141 that forms a second pre-buffer. The inverter 140 connects a control signal voltage change adjustment circuit 142 between the internal output node 44 (first output node 44 of the prebuffer 36 shown in FIG. 14) and the drain of the NMOS transistor 41. 14 is configured similarly to the inverter 38 shown in FIG.

  The control signal voltage change adjusting circuit 142 adjusts the voltage change at the fall of the control signal SBP3, and constitutes a pull-down circuit that pulls down the control signal SBP3 together with the NMOS transistor 41.

  The control signal voltage change adjustment circuit 142 includes a current source 143, a PMOS transistor 144, and an NMOS transistor 145 that forms a variable resistance element. The current source 143 has an upstream end connected to the VDD power supply line 42, and the PMOS transistor 144 has a source connected to the downstream end of the current source 143 and a gate and drain connected to the drain of the NMOS transistor 41. The NMOS transistor 145 has a drain connected to the internal output node 44, a gate connected to the source of the PMOS transistor 144, and a source connected to the drain of the NMOS transistor 41.

  Since the PMOS transistor 144 is diode-connected, when the threshold voltage of the PMOS transistor 144 is VthP, the source voltage of the PMOS transistor 144 is | VthP |, and | VthP | is supplied to the gate of the NMOS transistor 145. As a result, when the NMOS transistor 41 is turned on, the gate-source voltage of the NMOS transistor 145 becomes | VthP |. In this example, the circuit constant is set so that the NMOS transistor 145 is turned on in this state.

  In this example, the on-resistance value of the NMOS transistor 145 depends on the threshold voltage VthP of the PMOS transistor 144. When the threshold voltage VthP of the PMOS transistor 144 is low (| VthP | is large), the gate-source of the NMOS transistor 145 The voltage between the transistors increases, and the on-resistance value of the NMOS transistor 145 decreases. On the other hand, when the threshold voltage VthP of the PMOS transistor 144 is high (| VthP | is small), the gate-source voltage of the NMOS transistor 145 decreases and the on-resistance value of the NMOS transistor 145 increases.

  The inverter 141 connects the control signal voltage change adjusting circuit 146 between the drain of the PMOS transistor 45 and the internal output node 47 (the second output node 47 of the prebuffer 36 shown in FIG. 14). 14 is configured similarly to the inverter 39 shown in FIG. The control signal voltage change adjustment circuit 146 adjusts the voltage change at the rise of the control signal SBN3, and constitutes a pull-up circuit that pulls up the control signal SBN3 together with the PMOS transistor 45.

  The control signal voltage change adjustment circuit 146 includes an NMOS transistor 147, a current source 148, and a PMOS transistor 149 that forms a variable resistance element. The NMOS transistor 147 has a gate and drain connected to the drain of the PMOS transistor 45, a source connected to the upstream end of the current source 148, and the current source 148 connected to the ground line at the downstream end. The PMOS transistor 149 has a source connected to the drain of the PMOS transistor 45, a gate connected to the source of the NMOS transistor 147, and a drain connected to the internal output node 47.

  Since the NMOS transistor 147 is diode-connected, when the threshold voltage of the NMOS transistor 147 is VthN, the source voltage of the NMOS transistor 147 is VDD−VthN, and VDD−VthN is supplied to the gate of the PMOS transistor 149. As a result, when the PMOS transistor 45 is turned on, the source-gate voltage of the PMOS transistor 149 becomes VthN. In this example, the circuit constant is set so that the PMOS transistor 149 is turned on in this state.

  In the case of this example, the on-resistance value of the PMOS transistor 149 depends on the threshold voltage VthN of the NMOS transistor 147. When the threshold voltage VthN of the NMOS transistor 147 is high, the voltage between the source and gate of the PMOS transistor 149 increases. The on-resistance value of the transistor 149 is small. On the other hand, when the threshold voltage VthN of the NMOS transistor 147 is low, the source-gate voltage of the PMOS transistor 149 decreases and the on-resistance value of the PMOS transistor 149 increases.

  In the output circuit 136 of the eighth embodiment of the present invention configured as above, when the potential of the internal output signal SA3 is at VDD, the PMOS transistor 40 = off state, the NMOS transistors 41, 145 = on state, the control signal The potential of SBP3 is 0V. Further, the PMOS transistor 45 = off state, the NMOS transistor 46 = on state, and the potential of the control signal SBN3 = 0V. As a result, the PMOS transistor 48 is turned on, the NMOS transistor 49 is turned off, and the potential of the external output signal SC3 is VDD.

  From this state, when the potential of the internal output signal SA3 falls to 0V, the PMOS transistor 40 = on state and the NMOS transistor 41 = off state, and the control signal SBP3 rises from 0V to VDD. Further, the PMOS transistors 45 and 149 are turned on and the NMOS transistor 46 is turned off, and the control signal SBN3 rises from 0V to VDD. As a result, the PMOS transistor 48 is turned off, the NMOS transistor 49 is turned on, and the external output signal SC3 falls from VDD to 0V.

  Thereafter, when the internal output signal SA3 rises to VDD, the PMOS transistor 40 = off state, the NMOS transistors 41, 145 = on state, and the control signal SBP3 falls from VDD to 0V. Further, the PMOS transistor 45 is turned off and the NMOS transistor 46 is turned on, and the control signal SBN3 falls from VDD to 0V. As a result, the PMOS transistor 48 is turned on and the NMOS transistor 49 is turned off, and the external output signal SC3 rises from 0V to VDD.

  As described above, in the output circuit 136 according to the eighth embodiment of the present invention, when the internal output signal SA3 rises from 0V to VDD, the PMOS transistor 40 = off state and the NMOS transistors 41, 145 = on state. SBP3 falls from VDD to 0V, and the PMOS transistor 48 is turned on. Further, the PMOS transistor 45 is turned off, the NMOS transistor 46 is turned on, the control signal SBN3 falls from VDD to 0 V, and the NMOS transistor 49 is turned off.

  As a result, the PMOS transistor 48 raises the external output signal SC3 from 0V to VDD. However, if the threshold voltage VthP of the PMOS transistor varies due to manufacturing variations of the semiconductor integrated circuit device 135, the driving capability of the PMOS transistor 48 is reduced. It will vary.

  However, if the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 135 varies toward the low voltage side and the threshold voltage VthP of the PMOS transistor 144 is low (| VthP | is large), the gate of the NMOS transistor 145 -The source voltage increases and the on-resistance value of the NMOS transistor 145 decreases. Therefore, the pull-down circuit composed of the NMOS transistor 41 and the control signal voltage change adjustment circuit 142 has a high driving capability.

  As a result, when the internal output signal SA3 rises from 0V to VDD, the fall of the control signal SBP3 becomes steeper, and the PMOS transistor 48 has its threshold voltage VthP on the low voltage side, and its driving capability is lowered. Despite this, the rise of the external output signal SC3 acts so as not to become slower.

  On the other hand, when the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 135 varies toward the high voltage side and the threshold voltage VthP of the PMOS transistor 144 is high (| VthP | is small), the NMOS transistor The gate-source voltage of 145 decreases, and the on-resistance value of the NMOS transistor 145 increases. Therefore, the pull-down circuit composed of the NMOS transistor 41 and the control signal voltage change adjusting circuit 142 has a low driving capability.

  As a result, when the internal output signal SA3 rises from 0V to VDD, the fall of the control signal SBP3 becomes more gradual, and the PMOS transistor 48 has its threshold voltage VthP varied to the high voltage side, and its driving capability is increased. Nevertheless, the rise of the external output signal SC3 is prevented from becoming steeper.

  Therefore, according to the output circuit 136 of the eighth embodiment of the present invention, variations in the slew rate of the external output signal SC3 due to variations in the threshold voltage VthP of the PMOS transistor 48 of the output buffer 37 can be suppressed.

  In the output circuit 136 according to the eighth embodiment of the present invention, when the internal output signal SA3 falls from VDD to 0V, the PMOS transistor 40 = on state and the NMOS transistor 41 = off state, and the control signal SBP3 starts from 0V. The voltage rises to VDD, and the PMOS transistor 48 is turned off. Further, the PMOS transistors 45 and 149 are turned on, the NMOS transistor 46 is turned off, the control signal SBN3 rises from 0V to VDD, and the NMOS transistor 49 is turned on.

  As a result, the NMOS transistor 49 causes the external output signal SC3 to fall from VDD to 0V. However, if the threshold voltage VthN of the NMOS transistor varies due to manufacturing variations of the semiconductor integrated circuit device 135, the driving capability of the NMOS transistor 49 is reduced. It will vary.

  However, if the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 135 varies to the high voltage side and the threshold voltage VthN of the NMOS transistor 147 is high, the voltage between the source and gate of the PMOS transistor 149 increases, and the PMOS transistor The on-resistance value of 149 becomes small. Therefore, the pull-up circuit composed of the PMOS transistor 45 and the control signal voltage change adjusting circuit 146 has a high driving capability.

  As a result, when the internal output signal SA3 falls from VDD to 0V, the rise of the control signal SBN3 becomes steeper, and the NMOS transistor 49 has its threshold voltage VthN varied to the high voltage side and its driving capability is lowered. In spite of this, it acts so that the falling of the external output signal SC3 does not become slower.

  On the other hand, when the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 135 varies toward the low voltage side and the threshold voltage VthN of the NMOS transistor 147 is low, the voltage between the source and gate of the PMOS transistor 149 becomes small. The on-resistance value of the PMOS transistor 149 increases. Accordingly, the pull-up circuit composed of the PMOS transistor 45 and the control signal voltage change adjusting circuit 146 has a low driving capability.

As a result, when the internal output signal SA3 falls from VDD to 0V, the rise of the control signal SBN3 becomes slower and the NMOS transistor 49 has its threshold voltage VthN fluctuated on the low voltage side, and its driving capability is increased. In spite of this, it acts so that the falling edge of the external output signal SC3 does not become steeper.

  Therefore, according to the output circuit 136 of the eighth embodiment of the present invention, variations in the slew rate of the external output signal SC3 due to variations in the threshold voltage VthN of the NMOS transistor 49 of the output buffer 37 can be suppressed.

(Ninth embodiment)
FIG. 9 is a circuit diagram showing an output circuit according to the ninth embodiment of the present invention. In FIG. 9, 151 is a semiconductor integrated circuit device, 152 is an output circuit according to the ninth embodiment of the present invention mounted on the semiconductor integrated circuit device 151, 153 is an output terminal of the semiconductor integrated circuit device 151, and 154 is an external signal wiring. is there.

  The output circuit 152 of the ninth embodiment of the present invention includes a prebuffer 155 having a circuit configuration different from that of the prebuffer 36 included in the output circuit 33 of the third conventional example shown in FIG. The other connection is made to the output terminal 153, and the others are configured in the same manner as the output circuit 33 of the third conventional example shown in FIG.

  The pre-buffer 155 includes an inverter 156 that forms a first pre-buffer and an inverter 157 that forms a second pre-buffer. The inverter 156 is configured by connecting the control voltage output node of the control signal voltage change adjustment circuit 158 to the substrate (back gate) of the NMOS transistor 41, and is otherwise configured in the same manner as the inverter 38 shown in FIG. The control signal voltage change adjustment circuit 158 adjusts the voltage change at the fall of the control signal SBP3, and constitutes a pull-down circuit that pulls down the control signal SBP3 together with the NMOS transistor 41.

  The control signal voltage change adjustment circuit 158 includes a current source 159 and a PMOS transistor 160. The current source 159 has an upstream end connected to the VDD power supply line 42, and the PMOS transistor 160 has a source connected to the downstream end of the power supply line 159 and the substrate (back gate) of the NMOS transistor 41, and a gate and drain connected to the ground line. is doing.

  Since the PMOS transistor 160 is diode-connected, if the threshold voltage of the PMOS transistor 160 is VthP, the source voltage of the PMOS transistor 160 is | VthP |, and | VthP | is supplied to the substrate (back gate) of the NMOS transistor 41. Is done.

  In the case of this example, the threshold voltage VthN of the NMOS transistor 41 depends on the threshold voltage VthP of the PMOS transistor 160. When the threshold voltage VthP of the PMOS transistor 160 is low (| VthP | is large), the substrate / source of the NMOS transistor 41 The inter-voltage (back gate-source voltage) increases, and the threshold voltage VthN of the NMOS transistor 41 decreases. On the other hand, when the threshold voltage VthP of the PMOS transistor 160 is high (| VthP | is small), the substrate-source voltage of the NMOS transistor 41 becomes small and the threshold voltage VthN of the NMOS transistor 41 becomes high.

  The inverter 157 is configured by connecting the control voltage output node of the control signal voltage change adjustment circuit 161 to the substrate (back gate) of the PMOS transistor 45, and is otherwise configured in the same manner as the inverter 39 shown in FIG. The control signal voltage change adjustment circuit 161 adjusts the voltage change at the rise of the control signal SBN3, and constitutes a pull-up circuit that pulls up the control signal SBN3 together with the PMOS transistor 45.

  The control signal voltage change adjustment circuit 161 includes an NMOS transistor 162 and a current source 163. The NMOS transistor 162 has a gate and drain connected to the VDD power line 42, a source connected to the upstream end of the current source 163 and the substrate (back gate) of the PMOS transistor 45, and the current source 163 connected to the ground line at the downstream end. is doing.

  Since the NMOS transistor 162 is diode-connected, when the threshold voltage of the NMOS transistor 162 is VthN, the source voltage of the NMOS transistor 162 is VDD−VthN, and VDD−VthN is supplied to the substrate (back gate) of the PMOS transistor 45. Is done.

  In this example, the threshold voltage VthP of the PMOS transistor 45 depends on the threshold voltage VthN of the NMOS transistor 162. When the threshold voltage VthN of the NMOS transistor 162 is high, the source-substrate voltage (source-back gate) of the PMOS transistor 45 is increased. And the threshold voltage VthP of the PMOS transistor 45 increases. On the other hand, when the threshold voltage VthN of the NMOS transistor 162 is low, the source-substrate voltage of the PMOS transistor 45 becomes small, and the threshold voltage VthP of the PMOS transistor 45 becomes low.

  In the output circuit 152 of the ninth embodiment of the present invention configured as above, when the potential of the internal output signal SA3 is at VDD, the PMOS transistor 40 = off state, the NMOS transistor 41 = on state, and the control signal SBP3. The potential is 0V. Further, the PMOS transistor 45 = off state, the NMOS transistor 46 = on state, and the potential of the control signal SBN3 = 0V. As a result, the PMOS transistor 48 is turned on, the NMOS transistor 49 is turned off, and the potential of the external output signal SC3 is VDD.

  From this state, when the internal output signal SA3 falls to 0V, the PMOS transistor 40 = on state and the NMOS transistor 41 = off state, and the control signal SBP3 rises from 0V to VDD. Further, the PMOS transistor 45 is turned on and the NMOS transistor 46 is turned off, so that the control signal SBN3 rises from 0V to VDD. As a result, the PMOS transistor 48 is turned off, the NMOS transistor 49 is turned on, and the external output signal SC3 falls from VDD to 0V.

  Thereafter, when the internal output signal SA3 rises to VDD, the PMOS transistor 40 = off state and the NMOS transistor 41 = on state, and the control signal SBP3 falls from VDD to 0V. Further, the PMOS transistor 45 is turned off and the NMOS transistor 46 is turned on, and the control signal SBN3 falls from VDD to 0V. As a result, the PMOS transistor 48 is turned on and the NMOS transistor 49 is turned off, and the external output signal SC3 rises from 0V to VDD.

  As described above, in the output circuit 152 of the ninth embodiment of the present invention, when the internal output signal SA3 rises from 0V to VDD, the PMOS transistor 40 = off state and the NMOS transistor 41 = on state, and the control signal SBP3 is The voltage falls from VDD to 0 V, and the PMOS transistor 48 is turned on. Further, the PMOS transistor 45 is turned off, the NMOS transistor 46 is turned on, the control signal SBN3 falls from VDD to 0 V, and the NMOS transistor 49 is turned off.

  As a result, the PMOS transistor 48 raises the external output signal SC3 from 0V to VDD. However, if the threshold voltage VthP of the PMOS transistor varies due to manufacturing variations of the semiconductor integrated circuit device 151, the driving capability of the PMOS transistor 48 is reduced. It will vary.

  However, when the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 151 varies toward the low voltage side and the threshold voltage VthP of the PMOS transistor 160 is low (| VthP | is large), the substrate of the NMOS transistor 41 The source voltage (back gate-source voltage) increases, and the threshold voltage VthN of the NMOS transistor 41 decreases. Therefore, the driving capability of the NMOS transistor 41 is increased.

  As a result, when the internal output signal SA3 rises from 0V to VDD, the fall of the control signal SBP3 becomes steeper, and the PMOS transistor 48 has its threshold voltage VthP on the low voltage side, and its driving capability is lowered. In spite of this, it acts so that the falling of the external output signal SC3 does not become slower.

  On the other hand, when the threshold voltage VthP of the PMOS transistor of the semiconductor integrated circuit device 151 varies toward the high voltage side and the threshold voltage VthP of the PMOS transistor 160 is high (| VthP | is small), the NMOS transistor 41, the substrate-source voltage (back gate-source voltage) decreases, and the threshold voltage VthN of the NMOS transistor 41 increases. Therefore, the driving capability of the NMOS transistor 41 is lowered.

  As a result, when the internal output signal SA3 rises from 0V to VDD, the fall of the control signal SBP3 becomes more gradual, and the PMOS transistor 48 has its threshold voltage VthP varied to the high voltage side, and its driving capability is increased. In spite of this, it acts so that the falling edge of the external output signal SC3 does not become steeper.

  Therefore, according to the output circuit 152 of the ninth embodiment of the present invention, variations in the slew rate of the external output signal SC3 due to variations in the threshold voltage VthP of the PMOS transistor 48 of the output buffer 37 can be suppressed.

  In the output circuit 152 of the ninth embodiment of the present invention, when the internal output signal SA3 falls from VDD to 0V, the PMOS transistor 40 is turned on and the NMOS transistor 41 is turned off, and the control signal SBP3 is changed from 0V. The voltage rises to VDD, and the PMOS transistor 48 is turned off. Further, the PMOS transistor 45 is turned on, the NMOS transistor 46 is turned off, the control signal SBN3 rises from 0 V to VDD, and the NMOS transistor 49 is turned on.

  As a result, the NMOS transistor 49 causes the external output signal SC3 to fall from VDD to 0V. However, if the threshold voltage VthN of the NMOS transistor varies due to manufacturing variations of the semiconductor integrated circuit device 151, the driving capability of the NMOS transistor 49 is reduced. It will vary.

  However, if the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 151 varies toward the high voltage side and the threshold voltage VthN of the NMOS transistor 162 is high, the source-substrate voltage (source-back gate) of the PMOS transistor 45 is increased. Voltage) increases, and the threshold voltage VthP of the PMOS transistor 45 increases. Therefore, the driving capability of the PMOS transistor 45 is increased.

  As a result, when the internal output signal SA3 falls from VDD to 0V, the rise of the control signal SBN3 becomes steeper, and the NMOS transistor 49 has its threshold voltage VthN varied to the high voltage side and its driving capability is lowered. In spite of this, it acts so that the falling of the external output signal SC3 does not become slower.

  On the other hand, when the threshold voltage VthN of the NMOS transistor of the semiconductor integrated circuit device 151 varies toward the low voltage side and the threshold voltage VthN of the NMOS transistor 162 is low, the voltage between the source and substrate of the PMOS transistor 45 (source The voltage between the back gates) decreases, and the threshold voltage VthP of the PMOS transistor 45 decreases. Therefore, the driving capability of the PMOS transistor 45 is lowered.

  As a result, when the internal output signal SA3 falls from VDD to 0V, the rise of the control signal SBN3 becomes slower and the NMOS transistor 49 has its threshold voltage VthN fluctuated on the low voltage side, and its driving capability is increased. In spite of this, it acts so that the falling edge of the external output signal SC3 does not become steeper.

  Therefore, according to the output circuit 152 of the ninth embodiment of the present invention, variations in the slew rate of the external output signal SC3 due to variations in the threshold voltage VthN of the NMOS transistor 49 of the output buffer 37 can be suppressed.

  Here, when the output circuit of the present invention is arranged, the output circuit of the present invention includes at least the following output circuits.

  (Additional remark 1) It has the prebuffer which inputs an internal output signal and outputs a control signal, and the output buffer which inputs the said control signal and outputs an external output signal, The said prebuffer is a transistor of the said output buffer. An output circuit comprising: means for adjusting a voltage change of the control signal so as to suppress a variation in a slew rate of the external output signal due to a variation in a threshold voltage.

  (Supplementary Note 2) The output buffer includes a first first terminal having a drain connected to the output terminal for the external output signal, a gate connected to the output node of the prebuffer, and a source connected to a second power supply line. The pre-buffer is connected between a first power supply line and an output node of the pre-buffer, and receives the internal input signal to receive a threshold of the first first polarity transistor. A pull-up circuit that pulls up the control signal so as to suppress variations in the slew rate of the external output signal due to voltage variations, and is connected between the output node of the prebuffer and the second power supply line; The output circuit according to claim 1, further comprising a pull-down circuit for inputting the internal input signal and pulling down the control signal.

  (Supplementary Note 3) The pull-up circuit includes a first second polarity transistor having a source connected to the first power supply line and a gate connected to an input node of the prebuffer, and one end connected to the first first power supply line. Connected to the drain of a bipolar transistor and connected to the output node of the prebuffer to suppress variation in the slew rate of the external output signal due to variation in the threshold voltage of the first first polarity transistor. And a control signal voltage change adjustment circuit for adjusting the voltage change of the control signal as described above, wherein the pull-down circuit connects the drain to the output node of the prebuffer, and connects the gate to the input node of the prebuffer, The output circuit according to claim 2, further comprising a second first polarity transistor having a source connected to the second power supply line.

  (Supplementary Note 4) The control signal voltage change adjusting circuit includes a third first polarity type transistor having a gate and a drain connected to the first power supply line, and an upstream end serving as a source of the third first polarity type transistor. A current source having the other end connected to the second power supply line, a source connected to the drain of the first second polarity transistor, and a gate connected to the source of the third polarity transistor. The output circuit according to claim 3, further comprising a second second polarity type transistor having a drain connected to the drain and a drain connected to the output node of the prebuffer.

  (Supplementary Note 5) The control signal voltage change adjusting circuit includes a third first polarity type transistor having a gate and a drain connected to a drain of the first second polarity type transistor, and an upstream end of the third first polarity type transistor. A current source connected to the source of the polar transistor, the other end connected to the second power supply line, a source connected to the drain of the first second polarity transistor, and a gate connected to the third first transistor 4. The output circuit according to claim 3, further comprising a second second polarity transistor having a drain connected to a source of the polarity transistor and a drain connected to an output node of the prebuffer.

  (Supplementary Note 6) The pull-up circuit includes a first second terminal having a source connected to the first power supply line, a gate connected to the input node of the prebuffer, and a drain connected to the output node of the prebuffer. A polarity type transistor and a control voltage output node are connected to a substrate of the first second polarity type transistor, and variation in slew rate of the external output signal due to variation in threshold voltage of the first first polarity type transistor is detected. A control signal voltage change adjustment circuit for adjusting a voltage change of the control signal to suppress, the pull-down circuit connects a drain to the output node of the prebuffer and a gate to an input node of the prebuffer The output according to claim 2, further comprising a second first polarity transistor having a source connected to the second power supply line. Road.

  (Supplementary note 7) The control signal voltage change adjusting circuit has a third first polarity type circuit in which a gate and a drain are connected to the first power supply line and a source is connected to a substrate of the first second polarity type transistor. The output circuit according to claim 6, wherein a transistor and an upstream end are connected to a source of the third first polarity transistor, and a downstream end is connected to the second power supply line.

  (Supplementary note 8) The output buffer includes a first second source having a source connected to the first power supply line, a gate connected to the output node of the prebuffer, and a drain connected to the output terminal for the external output signal. A pull-up circuit having a polarity transistor, wherein the pre-buffer is connected between the first power supply line and an output node of the pre-buffer, and inputs the internal input signal to pull up the control signal Are connected between the output node of the prebuffer and the second power supply line, the internal output signal is input, and the external output signal due to the variation in the threshold voltage of the first second polarity transistor is input. The output circuit according to claim 1, further comprising a pull-down circuit that pulls down the control signal so as to suppress variations in slew rate.

  (Supplementary Note 9) The pull-up circuit includes a second second terminal having a source connected to the first power supply line, a gate connected to an input node of the prebuffer, and a drain connected to an output node of the prebuffer. The pull-down circuit has one end connected to the output node of the prebuffer, and suppresses variation in the slew rate of the external output signal due to variation in the threshold voltage of the first second polarity transistor. A control signal voltage change adjusting circuit for adjusting the voltage change of the control signal, a drain connected to the other end of the control signal voltage change adjusting circuit, a gate connected to the input node of the prebuffer, and a source connected The output circuit according to claim 8, further comprising a first first polarity transistor connected to the second power supply line.

  (Supplementary Note 10) The control signal voltage change adjustment circuit includes a current source having an upstream end connected to the first power supply line, a source connected to a downstream end of the current source, and a gate and a drain connected to the second power supply. A third second polarity transistor connected to the line; a drain connected to the output node of the prebuffer; a gate connected to a source of the third second polarity transistor; and a source connected to the first first transistor. The output circuit according to claim 9, further comprising a second first polarity type transistor connected to a drain of the one polarity type transistor.

  (Supplementary Note 11) The control signal voltage change adjustment circuit includes a current source having an upstream end connected to the first power supply line, a source connected to a downstream end of the current source, and a gate and a drain connected to the first first power line. A third second polarity transistor connected to the drain of the unipolar transistor; a drain connected to the output node of the prebuffer; a gate connected to the source of the third second polarity transistor; The output circuit according to claim 9, further comprising a second first polarity type transistor connected to a drain of the first first polarity type transistor.

  (Supplementary Note 12) The pull-up circuit includes a second second terminal having a source connected to the first power supply line, a gate connected to the input node of the prebuffer, and a drain connected to the output node of the prebuffer. A first transistor having a drain connected to an output node of the prebuffer, a gate connected to an input node of the prebuffer, and a source connected to the second power supply line; A first polarity type transistor and a control voltage output node are connected to the substrate of the first first polarity type transistor, and the slew rate of the external output signal due to a variation in the threshold voltage of the first second polarity type transistor. The control signal voltage change adjusting circuit for adjusting a voltage change of the control signal so as to suppress variation is provided. Circuit.

  (Supplementary Note 13) The control signal voltage change adjusting circuit includes a current source having an upstream end connected to the first power supply line, and a source connected to the downstream end of the current source and the substrate of the first first polarity transistor. 13. The output circuit according to appendix 12, wherein the output circuit has a third second polarity transistor connected thereto.

  (Supplementary note 14) The output buffer has a source connected to the first power supply line, a gate connected to the first output node of the prebuffer, and a drain connected to the output terminal for the external output signal. A first polarity transistor having a drain connected to the output terminal for the external output signal, a gate connected to a second output node of the prebuffer, and a source connected to a second power supply line. A first polarity type transistor, wherein the prebuffer receives the internal input signal and outputs a first control signal to a first output node of the prebuffer; and the internal input A second prebuffer for inputting a signal and outputting a second control signal to a second output node of the prebuffer, wherein the first prebuffer includes the first power line and the prebuffer. The first of A first pull-up circuit connected to an output node and configured to input the internal input signal to pull up the first control signal; a first output node of the pre-buffer; and the second power supply The first control so as to suppress variation in the slew rate of the external output signal due to variation in the threshold voltage of the first second polarity transistor by inputting the internal output signal. A first pull-down circuit for pulling down a signal, wherein the second pre-buffer is connected between the first power supply line and a second output node of the pre-buffer, and receives the internal output signal And pulling the second control signal so as to suppress variation in the slew rate of the external output signal due to variation in the threshold voltage of the first first polarity transistor. A second pull-up circuit to be connected, and a second output node of the second pre-buffer and the second power supply line, and the second control circuit receives the internal output signal and inputs the second control signal. The output circuit according to claim 1, further comprising a second pull-down circuit for pulling down the signal.

(Supplementary Note 15) The first pull-up circuit has a source connected to the first power supply line, a gate connected to the input node of the prebuffer, and a drain connected to the first output node of the prebuffer. And the first pull-down circuit includes:
One end is connected to the first output node of the pre-buffer, and the first control signal is configured to suppress variation in the slew rate of the external output signal due to variation in the threshold voltage of the first second polarity transistor. And a drain connected to the other end of the first control signal voltage change adjusting circuit, a gate connected to the input node of the prebuffer, and a source connected The second pull-up circuit has a source connected to the first power supply line and a gate connected to the input node of the prebuffer. A third second polarity type transistor connected to the first end, and one end connected to the drain of the third second polarity type transistor and the other end connected to the second output node of the prebuffer. The second control signal voltage change adjustment for adjusting the voltage change of the second control signal so as to suppress the variation of the slew rate of the external output signal due to the variation of the threshold voltage of the first first polarity transistor. The second pull-down circuit has a drain connected to the second output node of the prebuffer, a gate connected to the input node of the prebuffer, and a source connected to the second power supply line The output circuit according to appendix 2, wherein the output circuit has a third first polarity transistor.

  (Supplementary Note 16) The first control signal voltage change adjustment circuit includes a first current source having an upstream end connected to the first power supply line, and a source connected to a downstream end of the first current source. A fourth polarity transistor having a gate and a drain connected to the second power supply line; a drain connected to the first output node of the prebuffer; and a gate having the fourth polarity transistor The second control signal voltage change adjusting circuit has a gate and a drain connected to the source of the second control signal voltage, and the source is connected to the drain of the second first polarity transistor. A fifth first polarity type transistor connected to the first power supply line, and an upstream end connected to the source of the fifth first polarity type transistor and the other end connected to the second power supply line. 2 current source and source in front A fifth second transistor having a drain connected to the drain of the third second polarity transistor, a gate connected to a source of the fifth first transistor, and a drain connected to the second output node of the prebuffer. The output circuit according to appendix 15, wherein the output circuit has a polar transistor.

  (Supplementary Note 17) The first control signal voltage change adjusting circuit includes a first current source having an upstream end connected to the first power supply line, and a source connected to a downstream end of the first current source. , A fourth second polarity transistor having a gate and a drain connected to the drain of the second first polarity transistor, a drain connected to the first output node of the prebuffer, and a gate connected to the fourth output transistor The second control signal voltage change adjustment circuit has a fourth first polarity type transistor connected to the source of the second polarity type transistor and having the source connected to the drain of the second first polarity type transistor. A fifth first polarity transistor having a gate and a drain connected to the drain of the third second polarity transistor; an upstream end connected to the source of the fifth first polarity transistor; and the other end A second current source connected to the second power supply line; a source connected to a drain of the third second polarity transistor; a gate connected to a source of the fifth first polarity transistor; 16. The output circuit according to claim 15, further comprising a fifth second polarity type transistor having a drain connected to a second output node of the prebuffer.

(Supplementary Note 18) The first pull-up circuit has a source connected to the first power supply line, a gate connected to the input node of the prebuffer, and a drain connected to the first output node of the prebuffer. And the first pull-down circuit includes:
A second first polarity transistor having a drain connected to the first output node of the prebuffer, a gate connected to the input node of the prebuffer, and a source connected to the second power supply line; and a control voltage An output node is connected to the substrate of the second first polarity type transistor, and the first output polarity is controlled so as to suppress variations in the slew rate of the external output signal due to variations in the threshold voltage of the first second polarity type transistor. A first control signal voltage change adjusting circuit for adjusting a voltage change of the control signal, wherein the second pull-up circuit has a source connected to the first power supply line and a gate input to the prebuffer. A third second polarity transistor having a drain connected to the second output node of the prebuffer and a control voltage output node to the third second polarity. The second control signal is connected to the transistor substrate and adjusts the voltage change of the second control signal so as to suppress the variation of the slew rate of the external output signal due to the variation of the threshold voltage of the first first polarity transistor. The second pull-down circuit has a drain connected to the second output node of the prebuffer, a gate connected to the input node of the prebuffer, and a source connected to the second buffer node. 15. The output circuit according to appendix 14, further comprising a third first polarity transistor connected to two power supply lines.

  (Supplementary Note 19) The first control signal voltage change adjustment circuit includes a current source having an upstream end connected to the first power supply line, a source connected to the downstream end of the first current source, and the second first A second polarity type transistor having a gate and a drain connected to the second power line, the second control signal voltage change adjusting circuit having a gate and a drain connected to the substrate of the polarity type transistor; A fourth first polarity type transistor connected to the first power supply line and having a source connected to a substrate of the third second polarity type transistor; and an upstream end of the source of the fourth first polarity type transistor. The output circuit according to claim 18, further comprising a second current source connected to the second power source and having a downstream end connected to the second power supply line.

1 is a circuit diagram showing an output circuit of a first embodiment of the present invention. It is a circuit diagram which shows the output circuit of 2nd Embodiment of this invention. It is a circuit diagram which shows the output circuit of 3rd Embodiment of this invention. It is a circuit diagram which shows the output circuit of 4th Embodiment of this invention. It is a circuit diagram which shows the output circuit of 5th Embodiment of this invention. It is a circuit diagram which shows the output circuit of 6th Embodiment of this invention. It is a circuit diagram which shows the output circuit of 7th Embodiment of this invention. It is a circuit diagram which shows the output circuit of 8th Embodiment of this invention. It is a circuit diagram which shows the output circuit of 9th Embodiment of this invention. It is a circuit diagram which shows the output circuit of a 1st prior art example. FIG. 11 is an operation waveform diagram of the output circuit of the first conventional example shown in FIG. 10. It is a circuit diagram which shows the output circuit of a 2nd prior art example. FIG. 13 is an operation waveform diagram of the output circuit of the second conventional example shown in FIG. 12. It is a circuit diagram which shows the output circuit of a 3rd prior art example. FIG. 15 is an operation waveform diagram of the output circuit of the third conventional example shown in FIG. 14.

Explanation of symbols

DESCRIPTION OF SYMBOLS 2 ... Output circuit of 1st prior art example 7 ... Pre buffer 8 ... Output buffer 18 ... Output circuit of 2nd prior art example 22 ... Pre buffer 23 ... Output buffer 33 ... Output circuit of 3rd prior art example 36 ... Pre buffer 37 ... Output Buffer 53 ... Output circuit of the first embodiment of the present invention 58 ... Pre-buffer 59 ... Control signal voltage change adjusting circuit 65 ... Output circuit of the second embodiment of the present invention 70 ... Pre-buffer 71 ... Control signal voltage change adjusting circuit 77 ... Output circuit 82 according to the third embodiment of the present invention 82 ... Prebuffer 83 ... Control signal voltage change adjusting circuit 88 ... Output circuit according to the fourth embodiment of the present invention 92 ... Prebuffer 93 ... Control signal voltage change adjusting circuit 99 ... Book Output circuit 103 of the fifth embodiment of the invention ... Pre-buffer 104 ... Control signal voltage change adjusting circuit 110 ... Output circuit of the sixth embodiment of the invention 114 ... Pre-buffer 115... Control signal voltage change adjustment circuit 120... Output circuit of seventh embodiment of the present invention 123... Pre-buffer 124... Inverter (first pre-buffer)
125 ... inverter (second pre-buffer)
126, 130: Control signal voltage change adjusting circuit 136: Output circuit according to the eighth embodiment of the present invention 139: Pre-buffer 140: Inverter (first pre-buffer)
141. Inverter (second pre-buffer)
142, 146 ... control signal voltage change adjusting circuit 152 ... output circuit of the ninth embodiment of the present invention 155 ... pre-buffer 156 ... inverter (first pre-buffer)
157 ... Inverter (second pre-buffer)
158, 161 ... Control signal voltage change adjustment circuit

Claims (5)

A pre-buffer that inputs an internal output signal and outputs a control signal;
An output buffer for inputting the control signal and outputting an external output signal ;
Before Symbol output buffer,
A first first polarity transistor having a drain connected to the output terminal for the external output signal, a gate connected to the output node of the prebuffer, and a source connected to a second power supply line;
The pre-buffer is
A pull-up circuit connected between said output node and the first power supply line, to pull up the control signals enter the internal output signal,
Which is connected between the output node and the second power supply line, have a pull-down circuit for pulling down the control signal to input said internal output signal,
The pull-up circuit is
A first second polarity type transistor having a source connected to the first power supply line and a gate connected to an input node of the prebuffer;
One end connected to the drain of the first second polarity type transistor, to connect the other end to said output node, and a control signal voltage change adjustment circuit for adjusting the voltage change before Symbol control signal,
The pull-down circuit has a drain connected to said output node, a gate connected to said input node, have a second of the first polarity type transistor having a source connected to said second power supply line,
The control signal voltage change adjusting circuit is
A second second polarity transistor having a source connected to the drain of the first second polarity transistor and a drain connected to the output node;
A third first polarity transistor having a drain and a gate connected to the first power supply line or the drain of the first second polarity transistor, and a source connected to the gate of the second second polarity transistor When,
An upstream end connected to the third source of the first polarity type transistor, the output circuit you further comprising a current source connected to the downstream end to said second power supply line. A pre-buffer that inputs an internal output signal and outputs a control signal;
An output buffer for inputting the control signal and outputting an external output signal;
The output buffer is
A first first polarity transistor having a drain connected to the output terminal for the external output signal, a gate connected to the output node of the prebuffer, and a source connected to a second power supply line;
The pre-buffer is
A pull-up circuit connected between a first power supply line and the output node, for pulling up the control signal by inputting the internal output signal;
A pull-down circuit which is connected between the output node and the second power supply line and inputs the internal output signal to pull down the control signal;
The pull-up circuit is
A second polarity type transistor having a source connected to the first power line, a gate connected to an input node of the prebuffer, and a drain connected to the output node;
A control signal voltage change adjusting circuit for connecting a control voltage output node to the substrate of the second polarity type transistor and adjusting a voltage change of the control signal;
The pull-down circuit is
A second first polarity transistor having a drain connected to the output node, a gate connected to the input node, and a source connected to the second power supply line;
The control signal voltage change adjusting circuit is
A third first polarity transistor having a drain and a gate connected to the first power supply line and a source connected to the control voltage output node;
A current source having an upstream end connected to the control voltage output node and a downstream end connected to the second power supply line;
An output circuit characterized by. A pre-buffer that inputs an internal output signal and outputs a control signal;
An output buffer for inputting the control signal and outputting an external output signal ;
Before Symbol output buffer,
A source connected to the first power supply line, a gate connected to an output node of said pre-buffer has a first second polarity type transistor drain connected to the output terminal for the external output signal,
The pre-buffer is
A pull-up circuit wherein the first power supply line is connected between the output node, to pull up the control signals enter the internal output signal,
Connected between said output node and a second power supply line, enter the internal output signal have a pull-down circuit for pulling down the control signal,
The pull-up circuit is
A second second polarity transistor having a source connected to the first power supply line, a gate connected to the input node of the prebuffer, and a drain connected to the output node;
The pull-down circuit is
A first first polarity transistor having a source connected to the second power supply line and a gate connected to the input node;
One end connected to the drain of the first first polarity transistor, the other end connected to the output node, and a control signal voltage change adjusting circuit for adjusting a voltage change of the control signal;
The control signal voltage change adjusting circuit is
A second first polarity transistor having a source connected to the drain of the first first polarity transistor and a drain connected to the output node;
A third second polarity transistor having a drain and a gate connected to the second power supply line or the drain of the first first polarity transistor, and a source connected to the gate of the second first polarity transistor. When,
An upstream end connected to said first power supply line, the output circuit you further comprising a current source connected to the downstream end to a source of said third second polarity type transistor. A pre-buffer that inputs an internal output signal and outputs a control signal;
An output buffer for inputting the control signal and outputting an external output signal;
The output buffer is
A source connected to the first power supply line, a gate connected to an output node of said pre-buffer has a first second polarity type transistor drain connected to the output terminal for the external output signal,
The pre-buffer is
A pull-up circuit wherein the first power supply line is connected between the output node, to pull up the control signals enter the internal output signal,
Connected between said output node and a second power supply line, enter the internal output signal have a pull-down circuit for pulling down the control signal,
The pull-up circuit is
A second second polarity transistor having a source connected to the first power line, a gate connected to the input node of the prebuffer, and a drain connected to the output node;
The pull-down circuit is
A first polarity transistor having a drain connected to the output node, a gate connected to the input node, and a source connected to the second power supply line;
A control signal voltage change adjusting circuit for connecting a control voltage output node to the substrate of the first polarity type transistor and adjusting a voltage change of the control signal;
The control signal voltage change adjusting circuit is
A third second polarity transistor having a drain and a gate connected to the second power supply line and a source connected to the control voltage output node;
An upstream end connected to said first power supply line, the output circuit you further comprising a current source connected to the downstream end to the control voltage output node. A pre-buffer that inputs an internal output signal and outputs a control signal;
An output buffer for inputting the control signal and outputting an external output signal ;
Before Symbol output buffer,
A source connected to the first power supply line, a first connected to the output node, the first second polarity type transistor drain connected to the output terminal for the external output signal of the pre-buffer gate,
A drain connected to the output terminal for the external output signal, a gate connected to a second output node of said pre-buffer has a first first polarity type transistor having a source connected to the second power supply line ,
The pre-buffer is
A first pre-buffer for outputting a first control signal to input said internal output signal on said first output node,
A second pre-buffer that outputs a second control signal to said second output node by entering the internal output signal,
The first pre-buffer is
Connected between said first output node and the first power supply line, a first pull-up circuit for pulling up the first control signal to input said internal output signal,
Connected between the second power supply line and the first output node, and enter the internal output signal having a first pull-down circuit for pulling down the first control signal,
The second pre-buffer is
A second pull-up circuit is connected to pull up the second control signal to input said internal output signal between the second output node and the first power supply line,
Connected between the second power supply line and the second output node, and enter the internal output signal have a second pull-down circuit for pulling down the second control signal,
The first pull-up circuit includes:
A second second polarity transistor having a source connected to the first power line, a gate connected to the input node of the prebuffer, and a drain connected to the first output node;
The first pull-down circuit includes
A second first polarity transistor having a source connected to the second power supply line and a gate connected to the input node;
A first control signal voltage change adjustment that adjusts a voltage change of the first control signal by connecting one end to the drain of the second first polarity type transistor and connecting the other end to the first output node. Have a circuit,
The second pull-up circuit is
A third second polarity transistor having a source connected to the first power supply line and a gate connected to the input node;
One end is connected to the drain of the third second polarity transistor, and the other end is connected to the second output node, and a second control signal voltage change adjustment for adjusting a voltage change of the second control signal. Have a circuit,
The second pull-down circuit includes
A third polarity transistor having a drain connected to the second output node, a gate connected to the input node, and a source connected to the second power supply line;
The first control signal voltage change adjustment circuit includes:
A fourth first polarity transistor having a source connected to the drain of the second first polarity transistor and a drain connected to the first output node;
A fourth second polarity transistor having a drain and a gate connected to the second power supply line or the drain of the second first polarity transistor, and a source connected to the gate of the fourth first polarity transistor When,
A first current source having an upstream end connected to the first power supply line and a downstream end connected to a source of the fourth second polarity transistor;
The second control signal voltage change adjustment circuit includes:
A fifth second polarity transistor having a source connected to the drain of the third second polarity transistor and a drain connected to the second output node;
A fifth first polarity transistor having a drain and a gate connected to the first power supply line or the drain of the third second polarity transistor, and a source connected to the gate of the fifth second polarity transistor When,
An upstream end connected to the fifth first source polarity type transistor, the output circuit you further comprising a second current source connected to the downstream end to said second power supply line.

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