JP4868248B2 - Data transmission system - Google Patents

Description

  The present invention relates to a data transmission system in which a plurality of IC chips are daisy chain connected to perform data transmission between IC chips by serial communication of a plurality of lanes, and more particularly to a data transmission system capable of reducing power consumption.

  Prior art documents related to a data transmission system in which a plurality of conventional IC chips are daisy chain connected to perform data transmission between the IC chips by serial communication of a plurality of lanes are as follows.

JP 11-175127 A JP 2000-244516 A JP 2002-297460 A JP 2003-196230 A JP 2005-117134 A

  FIG. 7 is a configuration block diagram showing an example of a conventional data transmission system in which a plurality of IC chips are daisy chain connected to perform data transmission between IC chips by serial communication of a plurality of lanes.

  In FIG. 7, 1 is a master IC chip that generates data to be transmitted and transmits the data by serial communication of a plurality of lanes, and 2, 3 and 4 receive data addressed to the self among the data transmitted from the master IC chip. And a slave IC chip for data processing.

  Three serial communication paths from the master IC chip 1 indicated by “SC01” in FIG. 7 are connected to the slave IC chip 2.

  Then, the three serial communication paths from the slave IC chip 2 indicated by “SC02” in FIG. 7 are connected to the slave IC chip 3, and the three serial communications from the slave IC chip 3 indicated by “SC03” in FIG. The path is connected to the slave IC chip 4, and the three serial communication paths indicated by "SC04" in FIG. 7 are connected from the slave IC chip 4 to the subsequent slave IC chip (not shown).

  Here, the operation of the conventional example shown in FIG. 7 will be described with reference to FIGS. 8, 9, 10, 11 and 12. FIG. 8 is a block diagram illustrating a specific example of the master IC chip, FIG. 9 is a flowchart illustrating the operation of the master IC chip, FIG. 10 is an explanatory diagram illustrating an example of transmitted data, and FIG. 11 is a diagram of the slave IC chip. FIG. 12 is a flowchart for explaining the operation of the slave IC chip.

  8, 5 is a data generation circuit that generates transmission data, 6 is an address generation circuit that generates an address and adds it to the transmission data, and 7 is a lane that divides transmission data into three serial communication paths (three lanes). The dividing circuits 8, 9, and 10 are serial transmission circuits that perform parallel / serial conversion on the divided transmission data and transmit it to the serial communication path. 5, 6, 7, 8, 9 and 10 constitute a master IC chip 50.

  The output terminal of the data generation circuit 5 is connected to the input terminal of the address generation circuit 6, and the output terminal of the address generation circuit 6 is connected to the input terminal of the lane division circuit 7.

  Further, the three output terminals of the lane division circuit 7 are connected to the input terminals of the serial transmission circuits 8, 9 and 10, respectively, and the output terminals of the serial transmission circuits 8, 9 and 10 are "SL11" and "SL12" in FIG. And the serial communication path indicated by “SL13”.

  In “S001” in FIG. 9, the master IC chip 50 generates transmission data by the data generation circuit 5. In “S002” in FIG. 9, the master IC chip 50 generates an address of the transmission destination by the address generation circuit 6. The master IC chip 50 divides the transmission data into three serial communication paths by the lane division circuit 7 in “S003” in FIG.

  For example, as indicated by “SD21”, “SD22”, and “SD23” in FIG. 10, the master IC chip 50 has a 30-bit wide transmission destination at the head of the transmission data generated by the address generation circuit 6 with a 30-bit width. The lane dividing circuit 7 divides the 30-bit address and transmission data into three with a 10-bit width.

  Then, in “S004” in FIG. 9, the master IC chip 50 performs parallel / serial conversion of the divided transmission data (including the address) for each lane by the serial transmission circuits 8, 9 and 10 in FIG. The data is transmitted to serial communication paths indicated by SL11 "," SL12 ", and" SL13 ".

  On the other hand, in FIG. 11, 11, 12 and 13 are serial receiving circuits that receive data from the serial communication path and perform serial / parallel conversion, 14 is an inter-lane synchronization circuit that performs synchronization between lanes (between serial communication paths), Reference numeral 15 is an address decoding circuit, 16 is a data processing circuit, and 17, 18 and 19 are serial transmission circuits for parallel / serial conversion of transmission data and transmitting it to a serial communication path.

  Further, 11, 12, 13, 14, 15, 16, 17, 18, and 19 constitute a slave IC chip 51.

  In FIG. 11, the serial communication paths indicated by “SL31”, “SL32” and “SL33” are connected to the input terminals of the serial receiving circuits 11, 12 and 13, respectively, and the parallel output terminals of the serial receiving circuits 11, 12 and 13 are lanes. The three synchronization terminals 14 are connected to the three input terminals, respectively.

  The output terminal of the inter-lane synchronization circuit 14 is connected to the input terminal of the address decoding circuit 15, and the output terminal of the address decoding circuit 15 is connected to the input terminal of the data processing circuit 16. The serial output terminals of the serial receiving circuits 11, 12, and 13 are connected to the input terminals of the serial transmitting circuits 19, 18, and 17, respectively.

  In “S101” in FIG. 12, the slave IC chip 51 determines whether data is received by the serial receiving circuits 11, 12, and 13, and if it is determined that data has been received, In “S102”, the slave IC chip 51 performs serial / parallel conversion of the received data by the serial reception circuits 11, 12, and 13.

  However, as indicated by “RD21”, “RD22”, and “RD23” in FIG. 10, the reception times of the received data are not the same depending on the status of each serial communication path.

  For example, the reception data indicated by “RD21” in FIG. 10 is delayed by the time indicated by “DT21” in FIG. 10 with respect to the transmission time, whereas the reception data indicated by “RD22” in FIG. The data is delayed by the time indicated by “DT22” in FIG. 10 from the received data indicated by “RD21” in FIG.

  Similarly, for example, the received data indicated by “RD23” in FIG. 10 is further delayed by the time indicated by “DT23” in FIG. 10 than the received data indicated by “RD22” in FIG.

  That is, unless the variation in the reception time of the reception data between the serial communication paths (lanes) is corrected, the transmission data transmitted correctly cannot be restored.

  Therefore, in “S103” in FIG. 12, the slave IC chip 51 corrects the variation in the reception time of the reception data between the serial communication paths (lanes) by the inter-lane synchronization circuit 14 and restores the address and the transmission data. . Incidentally, an existing method is used as a method for correcting variations in reception time of received data between serial communication paths (lanes).

  For example, an address and transmission data divided by 10-bit width are taken out and restored to 30-bit width address and transmission data.

  In “S104” in FIG. 12, the slave IC chip 51 extracts the added address from the data restored by the address decoding circuit 15, and the address extracted in “S105” in FIG. Determine whether or not.

  If it is determined in “S105” in FIG. 12 that the address is addressed to itself, in “S106” in FIG. 12, the slave IC chip 51 processes the received and restored data by the data processing circuit 16. .

  On the other hand, if it is determined in “S105” in FIG. 12 that the address is not addressed to itself, in “S107” in FIG. 12, the slave IC chip 51 discards the received and restored data and the serial transmission circuit. Data received by the serial reception circuits 11, 12, and 13 (serial data) by 19, 18, and 17 through the serial communication paths indicated by "SL41", "SL42", and "SL43" in FIG. Forward to.

  As a result, the master IC chip adds an address to the transmission data and divides the data into a plurality of serial communication paths (lanes) and transmits the data. The slave IC chip restores the received data and determines whether the data is addressed to itself. If the data is addressed to itself, the data processing is performed. In other cases, the received data is transferred to another slave IC chip. Communication enables data transmission between IC chips.

  However, in the conventional example shown in FIG. 6, it is determined whether or not the received data is addressed to itself until the data received by the inter-lane synchronization circuit 14 is restored and the address contents are evaluated by the address decoding circuit 15. There is a problem that all data received by the inter-lane synchronization circuit 14 must be restored because it cannot be determined.

In particular, since the inter-lane synchronization circuit 14 is generally composed of a FIFO (First In First Out) buffer having a large circuit scale, the inter-lane synchronization circuit for restoring received data that is not addressed to itself is often used. There is a problem that the power consumption increases due to the operation of 14.
Therefore, the problem to be solved by the present invention is to realize a data transmission system capable of reducing power consumption.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a data transmission system in which a plurality of IC chips are daisy chained and data transmission between IC chips is performed by serial communication of a plurality of lanes.
A data generation circuit for generating transmission data having a predetermined bit width; an address generation circuit for generating an address of a transmission destination of the transmission data and adding the transmission data to the transmission data; the transmission data output from the address generation circuit; Generates a lane division circuit that divides an address corresponding to the plurality of lanes, and a flag that specifies a destination slave IC chip corresponding to the address, and generates a plurality of flags that are respectively added to the divided transmission data A master IC chip having a circuit and a plurality of first serial transmission circuits that respectively convert the outputs of the plurality of flag generation circuits into parallel / serial and transmit to the plurality of serial communication paths; A plurality of serial receiving circuits that receive data and perform serial / parallel conversion, and a plurality of these serial receiving circuits. The flag is extracted from the data output from the receiver circuit, and a plurality of flag decoding circuits for determining whether or not the flag is addressed to the slave IC chip, and operates only when the flag is addressed to the slave IC chip. The inter-lane synchronization circuit that corrects variations in the reception time of the reception data between the serial communication paths and restores the address and the transmission data after removing the flag, and processing of the output of the inter-lane synchronization circuit And a second serial transmission circuit that transfers the received data to another slave IC chip via a plurality of serial communication paths when the flag is not addressed to the slave IC chip . By providing a slave IC chip, the inter-lane synchronization circuit operates only when data addressed to itself is received. Runode, it is possible to reduce power consumption.

The invention according to claim 2
In the data transmission system according to claim 1 ,
The flag is
By assigning a code that increments by 1 to the slave IC chip of the transmission destination, the inter-lane synchronization circuit operates only when data addressed to itself is received, so it is possible to reduce power consumption Become.

The invention described in claim 3
In the data transmission system according to claim 1 ,
The flag is
Since one bit of the flag is assigned to each slave IC chip of the transmission destination, the inter-lane synchronization circuit operates only when data addressed to itself is received, so that power consumption can be reduced. In addition, data addressed to a plurality of slave IC chips can be transmitted simultaneously (multicast).

The invention according to claim 4
In the data transmission system according to claim 1 ,
By including the flag in the address, the inter-lane synchronization circuit operates only when data addressed to itself is received, so that power consumption can be reduced.

The present invention has the following effects.
According to the first, second, third, fourth, fifth and sixth inventions, the master IC chip adds an address to the transmission data to divide it into a plurality of serial communication paths (lanes) and adds a flag respectively. The data of the slave IC chip is extracted and the flag of one serial communication channel (lane) is extracted to determine whether the data is addressed to itself. If the data is addressed to itself, the data is restored. In other cases, the received data is transferred to other slave IC chips, so that the inter-lane synchronization circuit operates only when data addressed to itself is received, thereby reducing power consumption. It becomes possible.

  According to the invention of claim 5, by assigning one bit of the flag to each slave IC chip as a transmission destination, data addressed to a plurality of slave IC chips can be transmitted simultaneously (multicast).

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a data transmission system according to the present invention.

  In FIG. 1, 20 is a master IC chip that generates data to be transmitted and transmits the data by serial communication of a plurality of lanes, and 21, 22 and 23 receive data addressed to themselves within the data transmitted from the master IC chip. And a slave IC chip for data processing.

  Three serial communication paths from the master IC chip 20 indicated by “SC 51” in FIG. 1 are connected to the slave IC chip 21.

  The three serial communication paths from the slave IC chip 21 indicated by “SC52” in FIG. 1 are connected to the slave IC chip 22, and the three serial communications from the slave IC chip 22 indicated by “SC53” in FIG. The path is connected to the slave IC chip 23, and the three serial communication paths indicated by “SC54” in FIG. 1 are connected from the slave IC chip 23 to the subsequent slave IC chip (not shown).

  Here, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG. 2, FIG. 3, FIG. 4, FIG. 2 is a block diagram illustrating a specific example of the master IC chip, FIG. 3 is a flowchart illustrating the operation of the master IC chip, FIG. 4 is an explanatory diagram illustrating an example of transmitted data, and FIG. 5 is a diagram of the slave IC chip. FIG. 6 is a flowchart for explaining the operation of the slave IC chip.

  In FIG. 2, 24 is a data generation circuit that generates transmission data, 25 is an address generation circuit that generates an address and adds it to the transmission data, and 26 is a lane that divides the transmission data into three serial communication paths (three lanes). Division circuits 27, 28 and 29 generate a flag for designating a transmission destination for each lane and add it to transmission data, and 30, 31 and 32 perform serial / serial conversion on the divided transmission data. It is a serial transmission circuit that transmits to a communication path.

  Reference numerals 24, 25, 26, 27, 28, 29, 30, 31 and 32 constitute a master IC chip 52.

  The output terminal of the data generation circuit 24 is connected to the input terminal of the address generation circuit 25, and the output terminal of the address generation circuit 25 is connected to the input terminal of the lane division circuit 26 and the input terminals of the flag generation circuits 27, 28 and 29, respectively. Is done.

  The three output terminals of the lane division circuit 26 are connected to the input terminals of the serial transmission circuits 30, 31 and 32 via flag generation circuits 27, 28 and 29, respectively, and the output terminals of the serial transmission circuits 30, 31 and 32 are connected. Are connected to serial communication paths indicated by “SL61”, “SL62” and “SL63” in FIG.

  In “S201” in FIG. 3, the master IC chip 52 generates transmission data by the data generation circuit 24. In “S202” in FIG. 3, the master IC chip 52 generates an address of the transmission destination by the address generation circuit 25. Then, in “S203” in FIG. 3, the master IC chip 52 divides the transmission data into three serial communication paths by the lane division circuit 26.

  Further, in “S204” in FIG. 3, the master IC chip 52 generates a flag for designating the transmission destination based on the address generated by the address generation circuit 25 by the flag generation means 27, 28, and 29, and divides it into three. Each flag is added to the transmitted data.

  For example, as indicated by “SD71”, “SD72”, and “SD73” in FIG. 4, the master IC chip 52 has a 30-bit width transmission destination at the head of the transmission data generated by the address generation circuit 25 with a 30-bit width. The lane dividing circuit 26 divides the 30-bit address and transmission data into three with a 10-bit width, and adds 10-bit width flags with the flag generation circuits 27, 28, and 29.

  Here, the 10-bit width flag added to the transmission data divided into three is identifiable for each lane (serial communication path), and is different for each lane (serial communication path). Or a common flag.

  For example, when the slave IC chip 21 is the transmission destination, “0000000001 (10-bit binary value)”, when the slave IC chip 22 is the transmission destination, “0000000010 (10-bit binary value)”, the slave IC chip 23 transmits. In the case of the destination, “0000000011 (10-bit binary value)” is assumed, which is common to each lane (serial communication path).

  Then, in “S205” in FIG. 3, the master IC chip 52 performs parallel / serial conversion of the divided transmission data (including the flag and address) for each lane by the serial transmission circuits 30, 31, and 32. The data is transmitted to the serial communication paths indicated by “SL61”, “SL62”, and “SL63”.

  On the other hand, in FIG. 5, 33, 34, and 35 are serial receiving circuits that receive data from the serial communication path and perform serial / parallel conversion, and 36, 37, and 38 are flags added to each lane (serial communication path). Decoding flag decoding circuit, 39 is an inter-lane synchronizing circuit for synchronizing lanes (between serial communication paths), 40 is an address decoding circuit, 41 is a data processing circuit, 42, 43 and 44 are parallel / serial conversion of transmission data And a serial transmission circuit for transmitting to the serial communication path.

  33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43 and 44 constitute a slave IC chip 53.

  The serial communication paths indicated by “SL81”, “SL82” and “SL83” in FIG. 5 are connected to the input terminals of the serial receiving circuits 33, 34 and 35, respectively, and the parallel output terminals of the serial receiving circuits 33, 34 and 35 are flags. The signals are connected to the three input terminals of the inter-lane synchronization circuit 39 via the decode circuits 36, 37 and 38, respectively.

  The output terminal of the inter-lane synchronization circuit 39 is connected to the input terminal of the address decoding circuit 40, and the output terminal of the address decoding circuit 40 is connected to the input terminal of the data processing circuit 41. The serial output terminals of the serial reception circuits 33, 34, and 35 are connected to input terminals of the serial transmission circuits 44, 43, and 42 via flag decoding circuits 36, 37, and 38, respectively.

  In “S301” in FIG. 6, the slave IC chip 53 determines whether or not the serial receiving circuits 33, 34, and 35 have received data. If it is determined that the data has been received, In “S302”, the slave IC chip 53 performs serial / parallel conversion of the reception data by the serial reception circuits 33, 34 and 35.

  Further, in “S303” in FIG. 6, the slave IC chip 53 extracts one of the lane (serial communication path) flags by the flag decode circuits 36, 37, and 38, and in “S304” in FIG. The IC chip 53 determines whether or not the extracted flag is addressed to itself by the flag decoding circuit 36, 37 or 38.

  That is, since data indicated by “RD71” in FIG. 4 is received first, a flag is extracted from the received data, and it is determined whether or not the extracted flag is addressed to itself.

  For example, if the slave IC chip 53 corresponds to the slave IC chip 22 in FIG. 1 and the extracted flag is “0000000010 (10-bit binary value)”, the extracted flag is addressed to itself. Judge that there is.

  However, as indicated by “RD71”, “RD72”, and “RD73” in FIG. 4, the reception times of the received data are not the same depending on the status of each serial communication path.

  For example, the reception data indicated by “RD71” in FIG. 4 is delayed by the time indicated by “DT71” in FIG. 4 with respect to the transmission time, whereas the reception data indicated by “RD72” in FIG. The data is delayed by the time indicated by “DT72” in FIG. 4 from the received data indicated by “RD71” in FIG.

  Similarly, for example, the reception data indicated by “RD73” in FIG. 4 is further delayed by the time indicated by “DT73” in FIG. 4 from the reception data indicated by “RD72” in FIG.

  That is, unless the variation in the reception time of the reception data between the serial communication paths (lanes) is corrected, the transmission data transmitted correctly cannot be restored.

  If it is determined in “S304” in FIG. 6 that the address is addressed to itself, in “S305” in FIG. 6, the slave IC chip 53 receives data between serial communication paths (lanes) by the inter-lane synchronization circuit 39. In addition to correcting variations in data reception time, the address and transmission data are restored after removing the flag. Incidentally, an existing method is used as a method for correcting variations in reception time of received data between serial communication paths (lanes).

  For example, while removing the flag, the address and transmission data divided by 10-bit width are taken out and restored to the 30-bit width address and transmission data.

  Then, in “S306” in FIG. 6, the slave IC chip 51 uses the data processing circuit 41 to process the received and restored data. In addition, the address decoding circuit 40 may determine the data addressed to itself based on the added address as in the conventional example.

  On the other hand, if it is determined in “S304” in FIG. 6 that the address is not addressed to itself, the slave IC chip 51 performs serial transmission in “S307” in FIG. 6 without operating the inter-lane synchronization circuit 39. The data (serial data) received by the serial receiving circuits 33, 34 and 35 by the circuits 44, 43 and 42 are connected to other slave ICs via the serial communication paths indicated by “SL91”, “SL92” and “SL93” in FIG. Transfer to chip.

  For example, if the slave IC chip 53 corresponds to the slave IC chip 22 in FIG. 1 and the extracted flag is “0000000011 (10-bit binary value)”, the extracted flag is not addressed to itself. Therefore, the received data (serial data) is transferred to another slave IC chip without operating the inter-lane synchronization circuit 39.

  As a result, the master IC chip adds an address to the transmission data and divides the data into a plurality of serial communication paths (lanes), adds a flag to each of the transmission data, and transmits one serial communication path among the data received by the slave IC chip. (Lane) flag is extracted to determine whether the data is addressed to you. If the data is addressed to you, restore the data and perform data processing. Otherwise, receive the received data By transferring the data to the slave IC chip, the inter-lane synchronization circuit operates only when data addressed to itself is received, so that it is possible to reduce power consumption.

  In the description of the embodiment shown in FIG. 1 and the like, as a flag to be added, for example, “0000000001 (10-bit binary value)” when the slave IC chip 21 is the transmission destination, the slave IC chip 22 is the transmission destination. Is assigned a code that increments by one, such as “0000000010 (10-bit binary value)” and “0000000011 (10-bit binary value)” when the slave IC chip 23 is the transmission destination. Of course, the present invention is not limited to this.

  For example, by assigning one bit of a flag to each slave IC chip as a transmission destination, data addressed to a plurality of slave IC chips can be transmitted simultaneously (multicast).

  For example, when the slave IC chip 21 is the transmission destination, “0000000001 (10-bit binary value)”, when the slave IC chip 22 is the transmission destination, “0000000010 (10-bit binary value)”, the slave IC chip 23 transmits. If the destination is “0000000100 (10-bit binary value)”, a flag capable of simultaneous transmission (multicast) is generated by calculating the logical sum of these values.

  That is, when data is transmitted to the slave IC chips 22 and 23, “0000000110 (10 bits), which is the logical sum of“ 0000000010 (10-bit binary value) ”and“ 0000000100 (10-bit binary value) ”. Binary value) ”is the flag.

  When data is transmitted to the slave IC chips 21 to 23, “0000000001 (10-bit binary value)”, “0000000010 (10-bit binary value)”, and “0000000100 (10-bit binary value)” are used. "0000000111 (10-bit binary value)" that is a logical sum of "and" becomes a flag.

  On the other hand, on the slave IC chip side, whether or not the data is addressed to itself is easily determined based on whether or not “1” is set in the bit allocated to itself among the extracted flags.

  That is, for example, in the slave IC chip 21, it is only necessary to detect whether or not “1” is set in the least significant bit (LSB (Least Significant Bit)) of the 10-bit width flag.

  Further, in the description of the embodiment shown in FIG. 1 and the like, it is described that a flag is added separately from the address. However, when there is a vacancy in the bit width of the address, the flag is added to the vacant area in the address. The information may be included.

  In the description of the embodiment shown in FIG. 1 and the like, the number of serial communication paths, which is the number of lanes, is illustrated for the sake of simplicity, but of course, the number is not limited to this number. As long as the number of lanes (serial communication paths) is plural, it does not matter.

  In the description of the embodiment shown in FIG. 1 and the like, three slave IC chips are illustrated for simplicity of explanation, but of course, the number of slave IC chips is not limited to this number. It does not matter as long as there are multiple items.

  In the description of the embodiment shown in FIG. 1 and the like, the address decoding circuit is described in the slave IC chip, but whether or not the data is addressed to itself is determined in advance based on the added flag. The decoding circuit is not an essential component.

1 is a block diagram showing a configuration of an embodiment of a data transmission system according to the present invention. It is a block diagram showing a specific example of a master IC chip. It is a flowchart explaining operation | movement of a master IC chip. It is explanatory drawing which shows an example of the data transmitted. It is a block diagram showing a specific example of a slave IC chip. It is a flowchart explaining operation | movement of a slave IC chip. It is a configuration block diagram showing an example of a conventional data transmission system. It is a block diagram showing a specific example of a master IC chip. It is a flowchart explaining operation | movement of a master IC chip. It is explanatory drawing which shows an example of the data transmitted. It is a block diagram showing a specific example of a slave IC chip. It is a flowchart explaining operation | movement of a slave IC chip.

Explanation of symbols

1, 20, 50, 52 Master IC chip 2,3,4,21,22,23,51,53 Slave IC chip 5,24 Data generation circuit 6,25 Address generation circuit 7,26 Lane division circuit 8,9, 10, 17, 18, 19, 30, 31, 32, 42, 43, 44 Serial transmission circuit 11, 12, 13, 33, 34, 35 Serial reception circuit 14, 39 Inter-lane synchronization circuit 15, 40 Address decoding circuit 16 , 41 Data processing circuit 27, 28, 29 Flag generation circuit 36, 37, 38 Flag decoding circuit

Claims (4)

In a data transmission system in which a plurality of IC chips are daisy chained and data transmission between IC chips is performed by serial communication of a plurality of lanes.
A data generation circuit for generating transmission data having a predetermined bit width;
An address generation circuit that generates an address of a transmission destination of the transmission data and adds the address to the transmission data;
A lane division circuit that divides the transmission data and the address output from the address generation circuit corresponding to the plurality of lanes;
A plurality of flag generation circuits for generating a flag for designating a slave IC chip of a transmission destination corresponding to the address and adding the flag to the divided transmission data;
A plurality of first serial transmission circuits for parallel / serial converting the outputs of the plurality of flag generation circuits and transmitting them to a plurality of serial communication paths;
A master IC chip having
A plurality of serial receiving circuits that receive data from a plurality of serial communication paths and perform serial / parallel conversion;
A plurality of flag decoding circuits for extracting a flag from data output from the plurality of serial receiving circuits and determining whether the flag is addressed to the slave IC chip;
It operates only when the flag is addressed to the slave IC chip, corrects the variation in the reception time of the reception data between the serial communication paths, and restores the address and the transmission data after removing the flag. Inter-lane synchronization circuit,
A data processing circuit for processing the output of the inter-lane synchronization circuit;
A second serial transmission circuit for transferring the received data to other slave IC chips via a plurality of serial communication paths when the flag is not addressed to the slave IC chip;
A data transmission system comprising a plurality of slave IC chips. The flag is
The data transmission system according to claim 1, wherein a code whose code is incremented by 1 is assigned to a slave IC chip as a transmission destination. The flag is
2. The data transmission system according to claim 1, wherein one bit of a flag is assigned to each slave IC chip as a transmission destination. Data transmission system according to claim 1, characterized in that was included with the flag in the address.

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