JP4853845B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The invention disclosed in this specification relates to a semiconductor device provided with an active circuit using a thin film transistor (hereinafter referred to as TFT) using a crystalline semiconductor film and a manufacturing method thereof. In particular, the present invention can be suitably used for an electro-optical device typified by a liquid crystal display device in which an image display region and a drive circuit thereof are provided on the same substrate, and an electronic apparatus equipped with the electro-optical device. Note that the semiconductor device in this specification refers to all devices that function by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic apparatus in which the electro-optical device is mounted.
[0002]
[Prior art]
Conventionally, TFTs using thin-film semiconductors are known. Thin film semiconductors are roughly classified into two types: those made of an amorphous semiconductor and those made of a crystalline semiconductor.
[0003]
Amorphous semiconductors are most commonly used because they have a low fabrication temperature, can be fabricated relatively easily by a vapor phase method, and are mass-productive. They are mainly used in active matrix liquid crystal display devices. It is used to construct a circuit. However, since TFTs using an amorphous silicon film have a low operating speed, there is a problem that P-channel TFTs cannot be put into practical use. For this reason, establishment of a manufacturing method of a TFT made of a crystalline semiconductor, which is superior in physical properties such as conductivity to an amorphous semiconductor, is strongly demanded.
[0004]
Known crystalline semiconductors include polycrystalline semiconductors and microcrystalline semiconductors. As a method for obtaining these crystalline semiconductors,
(1) A film having crystallinity is directly formed at the time of film formation.
(2) An amorphous semiconductor film is formed, and crystallinity is imparted by irradiating laser light.
(3) An amorphous semiconductor film is formed and crystallinity is imparted by heat treatment.
Such a method is known.
[0005]
However, the method (1) has a problem that it is difficult to uniformly form a film having good semiconductor properties and the film forming temperature is as high as 600 ° C. or higher, so that an inexpensive glass substrate cannot be used. .
[0006]
In the method (2), it is known that a high-quality crystalline semiconductor can be obtained even at a temperature of 400 ° C. or lower. Generally, a method by excimer laser light irradiation is performed. However, since the irradiation area of the laser beam is small and the stability of the laser oscillation device is not sufficient, an inexpensive glass substrate with low heat resistance can be used, but throughput is required to process amorphous silicon on a large area substrate. And have problems with uniformity.
[0007]
Although the method (3) has the advantage of being able to cope with a large area, since the solid-phase crystallization phenomenon is used, the variation in crystal grain size is large, and heat treatment for several tens of hours is required at a high temperature of 600 to 900 ° C. or higher. It is. For this reason, in addition to the problem of throughput, there is a problem that an inexpensive glass substrate cannot be used as in (1).
[0008]
As one means for solving such a problem, there is a method (JP-A-8-78329) for promoting crystallization using a predetermined metal element which is the invention of the present applicant. This is a method in which a metal element typified by Ni is added to an amorphous semiconductor film, and then a crystalline semiconductor film is obtained by heat treatment. According to this method, since a crystalline semiconductor film can be obtained at 600 ° C. or less and in a short time, an inexpensive glass substrate can be used. However, since Ni element remains in the crystalline semiconductor film, TFTs manufactured thereby have problems such as variation in characteristics and deterioration in reliability.
[0009]
Regarding removal of residual Ni element, the present applicant has disclosed a method by a gettering process (Japanese Patent Laid-Open No. 10-214786). However, a mask forming process for selectively adding Ni element, and gettering are disclosed. The mask formation process for selectively adding the elements is required, and the heat treatment needs to be performed twice in the crystallization process and the gettering process. It was getting worse.
[0010]
Further, a method by a gettering process (Japanese Patent Laid-Open No. 11-97352) has been disclosed by the present applicant, but a mask forming step for selectively adding Ni element and a gettering element are selectively added. And a mask forming process for this purpose. In addition, an inorganic film having high heat resistance is used as a mask.
[0011]
[Problems to be solved by the invention]
In the present invention, in a TFT manufactured using a crystalline semiconductor obtained by using a metal element that promotes crystallization of silicon, an increase in the number of processes is suppressed as much as possible, and the TFT element has an adverse effect on the TFT characteristics. It is an object of the present invention to provide a technique for suppressing the problem.
[0012]
[Means for Solving the Problems]
One of the inventions disclosed in this specification is characterized in that crystallization is performed using a metal element that promotes crystallization, and gettering of the metal element is performed in a region adjacent to the crystallized region. A method for manufacturing a semiconductor device.
[0013]
In another aspect of the invention, crystallization is performed by a metal element that promotes crystallization, gettering of the metal element is performed in a region adjacent to the crystallized region, and crystallization and gettering are performed in the same heat treatment. A method for manufacturing a semiconductor device, which is performed in a process.
[0014]
In still another aspect of the invention, crystallization is performed by a metal element that promotes crystallization, and gettering of the metal element is performed in a region adjacent to the crystallized region, and the gettering element is an amorphous semiconductor. In the semiconductor device, the metal element that is selectively added to and promotes crystallization is added to the entire amorphous semiconductor including a region to which a gettering element is added (hereinafter referred to as a gettering region). This is a manufacturing method.
[0015]
In the structures of the three inventions described above, it is most preferable to use Ni as the metal element that promotes crystallization. In general, as the metal element, one or more kinds selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, Ge, Pb, and In can be used.
[0016]
In the configurations of the three inventions described above, it was most preferable to use P (phosphorus) as the gettering element. Examples of the gettering element include P, As, Sb, and N. In this sense, the gettering element may be selected from group 15 elements in the long-period periodic table. The invention disclosed in this specification can obtain the highest effect when nickel (Ni) is selected as the metal element and phosphorus (P) is selected as the gettering element.
[0017]
Metal element addition and gettering element addition methods for promoting crystallization are ion implantation, diffusion using a solution, diffusion using a solid, diffusion from a film formed by sputtering or CVD. A method such as a plasma treatment method, a gas adsorption method or the like can be used. A combination of these methods can also be used.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described in detail in the following embodiments, taking an active matrix liquid crystal display device as an example.
[0019]
[Embodiment 1]
The embodiment of the present invention will be described with reference to FIGS. Here, a method for manufacturing a pixel TFT in the display area and a TFT in a driver circuit provided around the display area on the same substrate will be described in detail according to the process. However, in order to simplify the description, a CMOS circuit that is a basic circuit such as a shift register circuit and a buffer circuit is shown in the control circuit, and an n-channel TFT that forms a sampling circuit.
[0020]
FIG. 1 shows a manufacturing process of this embodiment. First, an amorphous silicon film 102 is formed to a thickness of 20 to 150 nm (preferably 30 to 80 nm) on a Corning 1737 glass substrate 101 (strain point 667 ° C.).
[0021]
In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by plasma CVD as an amorphous semiconductor film. However, in addition to an amorphous silicon semiconductor, a compound semiconductor film such as an amorphous silicon germanium film is also used. Can be used.
[0022]
An insulating film may be interposed between the glass substrate and the amorphous semiconductor film when the amorphous semiconductor film is formed. In particular, the insulating film and the amorphous semiconductor film are continuously formed without being exposed to the atmosphere, so that the surface can be prevented from being contaminated. Voltage fluctuation can be reduced.
[0023]
As a method for forming the amorphous semiconductor film, a known method such as a low pressure CVD method or a sputtering method can be used in addition to the plasma CVD method.
[0024]
In this embodiment, Corning 1737 glass is used as the substrate 101, but it goes without saying that other substrate materials can be used according to the final purpose and application. (Fig. 1 (A))
[0025]
After the amorphous silicon film is formed, a resist mask 103 is formed with a photoresist as a mask for selectively adding a gettering element, and a gettering element is selectively added to obtain a gettering region. Form. The mask material may be any material that can block the addition of the gettering element, such as a silicon oxide film, but in this embodiment, a photoresist is used to simplify the process.
[0026]
Examples of the gettering element include phosphorus (P), arsenic (As), antimony (Sb), and nitrogen (N). In this sense, the gettering element may be selected from elements of Group 15 of the long-period periodic table. In this embodiment, phosphorus is used as the gettering element. Specifically, phosphine (PH _Three ) Was added by plasma-excited ion doping without mass separation. Of course, an ion implantation method for performing mass separation may be used.
[0027]
In the region of the amorphous silicon film 102 not protected by the resist mask, 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three Phosphorus (P) was added at a concentration of 5 to obtain phosphorus element added regions 104a to 104b. Since phosphorus is not added to the region protected by the resist mask, the phosphorus element added regions (gettering regions) 104a to 104b can be selectively formed. After the addition of phosphorus element, the resist mask 103 was removed. (Fig. 1 (B))
[0028]
Thereafter, a solution containing Ni as a catalyst element for promoting crystallization of the amorphous silicon film 102 was applied by a spin coating method to form a Ni-containing layer 105. Ni is one of the metal element catalytic elements for promoting the crystallization of the amorphous silicon film 102. In addition to Ni, the metal elements include Fe, Co, Ru, Rh, Pd, Os, and Ir. , Pt, Cu, Au, Ge, Pb, or In can be used.
[0029]
In the present invention, the spin coating method is used when the Ni-containing layer 105 is formed. However, a means for forming a thin film containing a catalytic element using a vapor phase method such as a sputtering method or a vapor deposition method may be used. (Figure 1 (C))
[0030]
Next, heat treatment (500 ° C. to 700 ° C., 2 to 24 hours, preferably 550 ° C. to 600 ° C., 4 hours to 12 hours) is performed. Here, heat treatment was performed at 550 ° C. for 12 hours. In this heat treatment step, first, a region to which phosphorus is not added is crystallized by the catalytic action of Ni to obtain crystalline silicon 107a to 107c. Bound with phosphorus and immobilized.
[0031]
Phosphorus hardly diffuses below 800 ° C., and the bond between phosphorus and Ni is strong, so that the Ni finally existing in the Ni-containing region layer 107 is almost entirely in the phosphorus element-added regions 104a to 104b. Fixed.
[0032]
The heat treatment in this embodiment is performed in a heating furnace provided with a resistance heater, but may be a heat treatment by irradiation with infrared light, for example.
[0033]
As described above, crystallization by the catalytic action of Ni and gettering of Ni after the completion of crystallization could be performed by one heat treatment. (Figure 1 (D))
[0034]
In addition, crystal growth different from normal crystal growth is observed in this heat treatment. (FIGS. 15A and 15B)
[0035]
Although Ni is retained on the entire surface of the amorphous silicon film, the needle-like crystal grows in the direction parallel to the substrate surface from the end of the phosphorus element addition region due to the presence of the phosphorus element addition region. Can be observed in FIG. 15 (A) and FIG. 15 (B). The crystal of the region formed in this way is very large, and it is useful to arrange this region so as to become the source region or drain region of the TFT, since it can reduce the resistance and facilitate activation.
[0036]
FIG. 15A is an optical micrograph after FPM treatment for 60 minutes after annealing at 575 ° C. for 12 hours. FIG. 15B is an optical micrograph after annealing at 550 ° C. for 12 hours and then FPM treatment for 60 minutes.
[0037]
Further, although the amorphous silicon film depends on the amount of hydrogen contained, it is preferable to perform heat treatment at 400 to 500 ° C. for about 1 hour to crystallize after sufficiently desorbing hydrogen. In that case, the hydrogen content is preferably 5 atom% or less.
[0038]
Then, the crystalline silicon 107a to 107c is patterned into an island shape to form island-shaped semiconductor layers 108 to 111. (Figure 1 (C))
[0039]
Thereafter, a mask layer 112 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by plasma CVD or sputtering. (Fig. 2 (A))
[0040]
Then, a resist mask 113 is provided and 1 × 10 6 for the purpose of controlling the threshold voltage over the entire surface of the island-shaped semiconductor layers 109 to 111 for forming the n-channel TFT. ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three Boron (B) was added as an impurity element imparting p-type at a moderate concentration. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film.
[0041]
The boron (B) addition here is not necessarily required, but the semiconductor layers 114 to 116 to which boron (B) is added in this step (referred to as channel doping step) have the threshold voltage of the n-channel TFT within a predetermined range. It was preferable to form to fit in. Note that in this specification, the semiconductor layers 114 to 116 containing a p-type impurity element in the above concentration range are referred to as channel-doped semiconductor layers. (Fig. 2 (B))
[0042]
In order to form the LDD region of the n-channel TFT of the driver circuit, an impurity element imparting n-type conductivity is selectively added to the island-like semiconductor layers 114 and 116. Therefore, resist masks 117a to 117d are formed in advance. As the impurity element imparting n-type conductivity, phosphorus (P) or arsenic (As) may be used. Here, phosphine (PH) is added to add phosphorus (P). _Three ) Was applied. The formed impurity regions 117 and 118 have a phosphorus (P) concentration of 2 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three It may be in the range. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 118 to 120 formed here is defined as (n ^- ). The impurity region 120 is a semiconductor layer for forming a storage capacitor of the pixel matrix circuit, and phosphorus (P) is added to this region at the same concentration. (Fig. 2 (C))
[0043]
Next, the mask layer 112 is removed with hydrofluoric acid or the like, and a step of activating the impurity element added in FIGS. 2B and 2C is performed. The activation can be performed by a heat treatment at 500 to 600 ° C. for 1 to 4 hours or a laser activation method in a nitrogen atmosphere. Moreover, you may carry out using both together. In this embodiment, a laser activation method is used, a KrF excimer laser beam (wavelength 248 nm) is used to form a linear beam, an oscillation frequency of 5 to 50 Hz, and an energy density of 100 to 500 mJ / cm. ² As a result, the entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed by scanning the linear beam with an overlap ratio of 80 to 98%. Note that there are no particular limitations on the irradiation conditions of the laser beam, and the practitioner may make an appropriate decision. (Fig. 2 (D))
[0044]
Then, the gate insulating film 121 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm using a plasma CVD method or a sputtering method. As the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. The nitrided oxide film is an insulating film containing silicon, nitrogen, and oxygen in predetermined amounts, and is an insulating film represented by SiOxNy. The nitrided oxide film is SiH _Four , N ₂ O and NH _Three Can be produced as a raw material gas, and the concentration of nitrogen contained is preferably 25 atomic% or more and less than 50 atomic%. In this embodiment, the silicon nitride oxide film is formed with a thickness of 120 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure.
[0045]
Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, but may have a laminated structure such as two layers or three layers as necessary. In this embodiment, the conductive layer (A) 122 made of a conductive nitride metal film and the conductive layer (B) 123 made of a metal film are laminated. The conductive layer (B) 123 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy film in which the elements are combined. (Typically, the conductive layer (A) 122 may be formed of tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, nitride). It is made of molybdenum (MoN). Alternatively, tungsten silicide, titanium silicide, or molybdenum silicide may be applied to the conductive layer (A) 122 as an alternative material. In the conductive layer (B), the concentration of impurities contained in the conductive layer (B) should be reduced in order to reduce the resistance. For example, tungsten (W) was able to realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.
[0046]
The conductive layer (A) 122 may be 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 123 may be 200 to 400 nm (preferably 250 to 350 nm). In this embodiment, a 30 nm thick tantalum nitride film is used for the conductive layer (A) 122 and a 350 nm Ta film is used for the conductive layer (B) 123, both of which are formed by sputtering. In film formation by this sputtering method, if an appropriate amount of Xe or Kr is added to the sputtering gas Ar, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with P (phosphorus) with a thickness of about 2 to 20 nm under the conductive layer (A) 122. This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, an alkali metal element contained in a trace amount in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 120. Can be prevented. (Fig. 3 (A))
[0047]
Next, resist masks 124a to 124e are formed, and the conductive layer (A) 122 and the conductive layer (B) 123 are etched together to form gate electrodes 125 to 128 and a capacitor wiring 129. The gate electrodes 125 to 128 and the capacitor wiring 129 are integrally formed of 125a to 128a made of a conductive layer (A) and 125b to 128b made of a conductive layer (B). At this time, the gate electrodes 126 and 127 formed in the driver circuit are formed so as to overlap with part of the impurity regions 118 and 119 with the gate insulating film 121 interposed therebetween. (Fig. 3 (B))
[0048]
Next, in order to form a source region and a drain region of the p-channel TFT of the driver circuit, a step of adding an impurity element imparting p-type is performed. Here, impurity regions are formed in a self-aligning manner using the gate electrode 125 as a mask. At this time, a region where the n-channel TFT is formed is covered with a resist mask 130. And diborane (B ₂ H ₆ The impurity region 131 was formed by an ion doping method using). The boron (B) concentration in this region is 3 × 10 ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three To be. In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 131 formed here is defined as (p ⁺⁺ ). (Fig. 3 (C))
[0049]
Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 132a to 132c were formed, and an impurity element imparting n-type conductivity was added to form impurity regions 133 to 137. This is the phosphine (PH _Three ), And the phosphorus (P) concentration in this region is 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three It was. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 133 to 137 formed here is defined as (n ⁺ ). (Fig. 3 (D))
[0050]
The impurity regions 133 to 137 already contain phosphorus (P) or boron (B) added in the previous step, but P (phosphorus) is added at a sufficiently higher concentration than that. The influence of phosphorus (P) or boron (B) added in the previous step may not be considered. Further, since the phosphorus (P) concentration added to the impurity region 138 is 1/2 to 1/3 of the boron (B) concentration added in FIG. 3C, p-type conductivity is ensured, and TFT characteristics are obtained. It had no effect on.
[0051]
Then, an impurity adding step for imparting n-type for forming the LDD region of the n-channel TFT of the pixel matrix circuit was performed. Here, an impurity element imparting n-type in a self-aligning manner is added by ion doping using the gate electrode 128 as a mask. The concentration of phosphorus (P) to be added is 1 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three By adding the impurity element at a concentration lower than that of the impurity element added in FIGS. 2C, 3C, and 3D, substantially only the impurity regions 138 and 139 are formed. The In this specification, the concentration of an impurity element imparting n-type contained in the impurity regions 138 and 139 is set to (n ^- ). (Fig. 4 (A))
[0052]
Thereafter, a heat treatment process is performed to activate the impurity element imparting n-type or p-type added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation process was performed by furnace annealing. The heat treatment is performed in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, at 400 to 800 ° C., typically 500 to 600 ° C. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours. went. Further, in the case where a substrate 101 having heat resistance such as a quartz substrate is used, heat treatment may be performed at 800 ° C. for 1 hour, and activation of the impurity element, impurity region to which the impurity element is added, and A good junction with the channel formation region could be formed.
[0053]
In this heat treatment, the conductive layers (C) 125c to 129c are formed with a thickness of 5 to 80 nm from the surface of the metal films 125b to 129b forming the gate electrodes 125 to 128 and the capacitor wiring 129. For example, when the conductive layers (B) 125b to 129b are tungsten (W), tungsten nitride (WN) can be formed, and when tantalum (Ta) is used, tantalum nitride (TaN) can be formed. The conductive layers (C) 125c to 129c can be formed in the same manner even when the gate electrodes 125 to 128 and the capacitor wiring 129 are exposed to a plasma atmosphere containing nitrogen using nitrogen or ammonia. Further, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. (Fig. 4 (B))
[0054]
FIGS. 6A and 7A are top views of the TFT in the steps up to here, and the AA ′ section and the CC ′ section are taken along the lines AA ′ and CC of FIG. 4B. It corresponds to '. Further, the BB ′ cross section and the DD ′ cross section correspond to the cross sectional views of FIGS. 8A and 9A. Although the gate insulating film is omitted in the top views of FIGS. 6 and 7, the gate electrodes 125 to 128 and the capacitor wiring 129 are formed on at least the island-like semiconductor layers 108 to 111 as shown in the drawings through the steps so far. Has been.
[0055]
When the activation and hydrogenation steps are completed, a second conductive film is formed as a gate wiring. This second conductive film includes a conductive layer (D) mainly composed of aluminum (Al) or copper (Cu), which is a low resistance material, and titanium (Ti), tantalum (Ta), tungsten (W), molybdenum. It is good to form with the conductive layer (E) which consists of (Mo). In this embodiment, an aluminum (Al) film containing 0.1 to 2 wt% of titanium (Ti) is formed as the conductive layer (D) 140, and a titanium (Ti) film is formed as the conductive layer (E) 141. The conductive layer (D) 140 may have a thickness of 200 to 400 nm (preferably 250 to 350 nm), and the conductive layer (E) 141 may have a thickness of 50 to 200 (preferably 100 to 150 nm). (Fig. 4 (C))
[0056]
Then, in order to form a gate wiring connected to the gate electrode, the conductive layer (E) 141 and the conductive layer (D) 140 were etched to form gate wirings 142 and 143 and a capacitor wiring 144. The etching process starts with SiCl _Four And Cl ₂ And BCl _Three The conductive layer (E) is removed from the surface of the conductive layer (E) to the middle of the conductive layer (D) by a dry etching method using a mixed gas with, and then the conductive layer (D) is removed by wet etching with a phosphoric acid-based etching solution. The gate wiring could be formed while maintaining the selective processability with the base.
[0057]
6B and 7B are top views of this state, and the AA ′ and CC ′ cross sections correspond to AA ′ and CC ′ in FIG. 4D. ing. Further, the BB ′ section and the DD ′ section correspond to BB ′ and DD ′ in FIGS. 8B and 9B. 6B and 7B, part of the gate wirings 142 and 143 overlaps with part of the gate electrodes 125, 126, and 128 and is in electrical contact. This state is also apparent from the cross-sectional structure diagrams of FIGS. 8B and 9B corresponding to the BB ′ cross section and the DD ′ cross section, and the conductive layer (C) forming the first conductive layer. And the conductive layer (D) forming the second conductive layer are in electrical contact.
[0058]
The first interlayer insulating film 145 is formed of a silicon oxide film or a silicon oxynitride film with a thickness of 500 to 1500 nm, and then a contact hole reaching the source region or the drain region formed in each island-like semiconductor layer is formed. Then, source wirings 146 to 149 and drain wirings 150 to 153 are formed. Although not shown, in this embodiment, the electrode is a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film is 150 nm continuously formed by sputtering.
[0059]
Next, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed as the passivation film 154 with a thickness of 50 to 500 nm (typically 100 to 300 nm). When the hydrogenation treatment was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Here, an opening may be formed in the passivation film 154 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later. (Fig. 5 (A))
[0060]
6C and 7C show top views of this state, and the AA ′ and CC ′ sections correspond to AA ′ and CC ′ in FIG. 5A. is doing. The BB ′ cross section and the DD ′ cross section correspond to BB ′ and DD ′ in FIGS. 8C and 9C. Although the first interlayer insulating film is omitted in FIGS. 6C and 7C, source wirings 146, 147, and non-illustrated source and drain regions of the island-shaped semiconductor layers 108, 109, and 111 are illustrated. 149 and drain wirings 150, 151, and 153 are connected through a contact hole formed in the first interlayer insulating film.
[0061]
Thereafter, a second interlayer insulating film 155 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate. Then, a contact hole reaching the drain wiring 153 is formed in the second interlayer insulating film 155, and pixel electrodes 156 and 157 are formed. The pixel electrode may be a transparent conductive film in the case of a transmissive liquid crystal display device, and may be a metal film in the case of a reflective liquid crystal display device. In this embodiment, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by sputtering in order to obtain a transmissive liquid crystal display device. (Fig. 5 (B))
[0062]
In this way, a substrate having the TFTs of the driving circuit and the pixel TFTs of the display area on the same substrate could be completed. A p-channel TFT 201, a first n-channel TFT 202, and a second n-channel TFT 203 are formed in the driver circuit, and a pixel TFT 204 and a storage capacitor 205 are formed in the display region. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0063]
The p-channel TFT 201 of the driver circuit includes a channel formation region 206, source regions 207a and 207b, and drain regions 208a and 208b in the island-shaped semiconductor layer 108. The first n-channel TFT 202 includes an LDD region 210 that overlaps the island-shaped semiconductor layer 109 with a channel formation region 209 and a gate electrode 126 (hereinafter, such an LDD region is referred to as Lov), a source region 211, and a drain region 212. have. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. The second n-channel TFT 203 has a channel formation region 213, LDD regions 214 and 215, a source region 216, and a drain region 217 in the island-shaped semiconductor layer 110. This LDD region is formed with an LDD region that does not overlap with the Lov region and the gate electrode 127 (hereinafter, such LDD region is referred to as Loff), and the length of the Loff region in the channel length direction is 0.3-2. It is 0 μm, preferably 0.5 to 1.5 μm. The pixel TFT 204 includes channel formation regions 218 and 219, Loff regions 220 to 223, and source or drain regions 224 to 226 in the island-shaped semiconductor layer 111. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm, preferably 1.5 to 2.5 μm. Further, the storage capacitor 205 includes a capacitor wiring 129, 144, an insulating film made of the same material as the gate insulating film, and a semiconductor layer 227 connected to the drain region 226 of the pixel TFT 204 and doped with an impurity element imparting n-type conductivity. Is formed. Although the pixel TFT 204 has a double gate structure in FIG. 5B, it may have a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided.
[0064]
In the present embodiment, an example in which the top gate type is used as the TFT type has been described. However, the present invention can also be used for a bottom-gate TFT in which the gate electrode is on the lower side (substrate side) of the active layer. Furthermore, the LDD region, the source region, and the drain region can be easily activated by forming the gate electrode from a heat-resistant conductive material, and the wiring resistance can be sufficiently reduced by forming the gate electrode from a low-resistance material. Therefore, the display area (screen size) can be applied to a display device of 4 inch class or more.
[0065]
[Embodiment 2]
This embodiment is an example in which the crystallization and gettering heat treatments in the first embodiment are performed in two stages in the same heat treatment step. Note that the drawings and reference numerals are also used in the first embodiment.
[0066]
First, as in the first embodiment, an amorphous silicon film 102 was formed to a thickness of 55 nm on the substrate 101.
[0067]
Next, a resist mask 103 was formed, and phosphorus (P) was selectively added as a gettering element. As in the first embodiment, the phosphine (PH _Three 1 × 10 by ion doping with plasma excitation without mass separation ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three Was added at a concentration of
[0068]
After removing the resist mask 103, a solution containing Ni as a catalytic element for promoting crystallization of the amorphous silicon film 102 was applied by a spin coating method to form a Ni-containing layer 105.
[0069]
Next, heat treatment was performed at 550 ° C. for 4 hours in a heating furnace, and the amorphous silicon film 102 was crystallized by the catalytic action of Ni to obtain crystalline silicon 107a to 107c. Thereafter, heat treatment was performed at 600 ° C. for 4 hours without taking out from the electric furnace, and Ni gettering treatment was performed.
[0070]
In general, the heat treatment temperature is lower than the strain point of the substrate material, and it is known that the substrate is deformed as the treatment temperature approaches the strain point. In this embodiment, a Corning 1737 glass substrate (strain point 667 ° C.) was used. However, if the processing temperature is about the same as that of the present embodiment, the processing time can be shortened with almost no deformation of the substrate. .
[0071]
As described above, the crystallization and gettering treatment temperatures are changed stepwise, so that substantially two heat treatments are performed. It was possible to carry out in less time than 1.
[0072]
In changing the processing temperature stepwise, it may be changed a plurality of times, or may be changed continuously instead of stepwise.
[0073]
Subsequent steps are to produce TFTs according to the first embodiment and other known methods.
[0074]
[Embodiment 3]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 10, an alignment film 601 is formed on the active matrix substrate in the state of FIG. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A light shielding film 603, a transparent conductive film 604, and an alignment film 605 were formed on the counter substrate 602 on the counter side. After the alignment film was formed, rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, the pixel matrix circuit, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), or the like by a known cell assembling process. Thereafter, a liquid crystal material 606 was injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix liquid crystal display device shown in FIG. 10 was completed.
[0075]
Next, the configuration of the active matrix liquid crystal display device will be described with reference to the perspective view of FIG. 11 and the top view of FIG. 11 and 12 use the same reference numerals in order to correspond to the cross-sectional structure diagrams of FIGS. 1 to 5 and FIG. A cross-sectional structure taken along line EE ′ shown in FIG. 12 corresponds to the cross-sectional view of the pixel matrix circuit shown in FIG.
[0076]
In FIG. 11, the active matrix substrate includes a display region 306, a scanning signal driving circuit 304, and an image signal driving circuit 305 formed on the glass substrate 101. A pixel TFT 204 is provided in the display area, and a driving circuit provided in the periphery is configured based on a CMOS circuit. The scanning signal driving circuit 304 and the image signal driving circuit 305 are connected to the pixel TFT 204 by a gate wiring 128 and a source wiring 149, respectively. Further, the FPC 731 is connected to the external input terminal 734 and is connected to the respective drive circuits by the input wirings 302 and 303.
[0077]
FIG. 12 is a top view showing almost one pixel in the display area 306. The gate wiring 143 intersects the semiconductor layer 111 thereunder through a gate insulating film (not shown). Although not shown, the semiconductor layer includes a source region, a drain region, and n ^- A Loff region formed of a region is formed. Reference numeral 161 denotes a contact portion between the source wiring 149 and the source region 224, 162 denotes a contact portion between the drain wiring 153 and the drain region 226, and 163 denotes a contact portion between the drain wiring 153 and the pixel electrode 156. The storage capacitor 205 is formed in a region where the capacitor wirings 129 and 144 overlap with the semiconductor layer 227 extending from the drain region 226 of the pixel TFT 204 and the gate insulating film.
[0078]
Note that although the active matrix liquid crystal display device of this embodiment has been described with reference to the structure described in Embodiment 1, an active matrix liquid crystal display device can be manufactured by freely combining with the structure of Embodiment 2. it can.
[0079]
[Embodiment 4]
An active matrix substrate, a liquid crystal display device, and an EL display device manufactured by implementing the present invention can be used in various electro-optical devices. The present invention can be applied to all electronic devices in which such an electro-optical device is incorporated as a display device. Examples of electronic devices include personal computers, digital cameras, video cameras, portable information terminals (mobile computers, mobile phones, electronic books, etc.), navigation systems, and the like.
[0080]
FIG. 13A illustrates a personal computer, which includes a main body 2001 including a microprocessor and a memory, an image input portion 2002, a display device 2003, and a keyboard 2004. The present invention can form the display device 2003 and other signal processing circuits.
[0081]
FIG. 13B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102 and other signal control circuits.
[0082]
FIG. 13C illustrates an electronic game device such as a video game or a video game, which is incorporated in a main body 2301, a controller 2305, a display device 2303, and a main body 2301 on which an electronic circuit 2308 such as a CPU and a recording medium 2304 are mounted. A display device 2302 is included. The display device 2303 and the display device 2302 incorporated in the main body 2301 may display the same information, or display the information on the recording medium 2304 using the former as a main display device and the latter as a sub display device. The operation state can be displayed, or a touch sensor function can be added to provide an operation panel. In addition, the main body 2301, the controller 2305, and the display device 2303 may be wired communication in order to transmit signals to each other, or may be wireless communication or optical communication by providing sensor units 2306 and 2307. The present invention can be applied to the display devices 2302 and 2303. The display device 2303 can also use a conventional CRT.
[0083]
FIG. 13D shows a player using a recording medium (hereinafter referred to as a recording medium) in which a program is recorded. The player includes a main body 2401, a display device 2402, a speaker unit 2403, a recording medium 2404, and operation switches 2405. A recording medium such as a DVD (Digital Versatile Disc) or a compact disc (CD) can be used to play music programs, display images, display video games (or video games), and display information via the Internet. . The present invention can be suitably used for the display device 2402 and other signal control circuits.
[0084]
FIG. 13E illustrates a digital camera which includes a main body 2501, a display device 2502, an eyepiece unit 2503, an operation switch 2504, and an image receiving unit (not illustrated). The present invention can be applied to the display device 2502 and other signal control circuits.
[0085]
FIG. 14A illustrates a front projector, which includes a light source optical system, a display device 2601, and a screen 2602. The present invention can be applied to display devices and other signal control circuits. FIG. 14B shows a rear projector, which includes a main body 2701, a light source optical system and display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to display devices and other signal control circuits.
[0086]
Note that FIG. 14C illustrates an example of the structure of the light source optical system and the display devices 2601 and 2702 in FIGS. 14A and 14B. The light source optical system and the display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2804 to 2806, a dichroic mirror 2803, a beam splitter 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. The projection optical system 2810 includes a plurality of optical lenses. Although FIG. 14C illustrates a three-plate type example using three liquid crystal display devices 2808, the invention is not limited to such a method, and a single-plate optical system may be used. In addition, an optical path, a film having a polarizing function, a film for adjusting a phase, an IR film, or the like may be provided in the optical path indicated by an arrow in FIG. FIG. 14D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. The light source optical system shown in FIG. 14D is an example and is not limited to the illustrated configuration.
[0087]
Although not shown here, the present invention can also be applied to a navigation system, a reading circuit of an image sensor, and the like. As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields.
[0088]
Thus, the applicable range of the present invention is extremely wide and can be applied to electronic devices in all fields. Further, the electronic device of the present embodiment can be realized by using a configuration composed of any combination of the first to third embodiments.
【The invention's effect】
In the invention disclosed in this specification,
(1) A gettering region is selectively formed in an amorphous semiconductor film.
(2) A metal element for promoting crystallization is added to the entire amorphous semiconductor film including the gettering region.
(3) Crystallization of the amorphous semiconductor with the metal element and gettering of the metal element are performed in the same heat treatment step.
(3) The gettering region is removed, and a region crystallized with the metal element is used as an active layer.
The structure is basically adopted.
[0089]
In this way, in a TFT manufactured using a crystalline semiconductor film obtained by using a metal element that promotes crystallization of the semiconductor film, the adverse effect of the metal element on the characteristics can be suppressed. it can.
[0090]
Further, the invention disclosed in this specification has a feature that the above effect can be obtained in a simplified manufacturing process.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT;
FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT;
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT;
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT;
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT;
FIG. 6 is a top view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT;
7 is a top view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a driver circuit TFT; FIG.
FIG. 8 is a top view illustrating a manufacturing process of a TFT of a driver circuit.
FIG. 9 is a top view illustrating a manufacturing process of a pixel TFT.
FIG. 10 is a cross-sectional view illustrating a structure of a liquid crystal display device.
FIG. 11 is a perspective view illustrating a structure of a liquid crystal display device.
FIG. 12 is a top view showing pixels in a display area.
FIG 13 illustrates an example of an electronic device.
FIG 14 illustrates an example of an electronic device.
FIG. 15 is a photograph of crystal growth by an optical microscope.
[Explanation of symbols]
101 substrate
102 Amorphous silicon film
103a to 103c resist mask
104a to 104b Phosphorus element addition region (gettering region)
105 Ni-containing layer
106 Ni movement
107a-107c crystalline silicon
108-111 Island-like semiconductor layer
112 Mask layer
113 resist mask
114 to 116 channel doped semiconductor layer
117a to 117d resist mask
118-120 n-type impurity region
121 Gate insulation film
122 Conductive layer (A)
123 Conductive layer (B)
124a-124e resist mask
125 to 128 Gate electrode
129 Capacitance wiring
125c to 129c conductive layer (C)
130 resist mask
131 P ++ impurity region
132a-132c resist mask
133-137 n + impurity region
138 to 139 n--impurity region
140 Conductive layer (D)
141 Conductive layer (E)
142-143 Gate wiring
144 Capacitance wiring
145 First interlayer insulating film
146 to 149 Source wiring
150 to 153 drain wiring
154 Passivation film
155 Second interlayer insulating film
156 to 157 Pixel electrode

Claims (5)

Forming a mask on the amorphous semiconductor film;
Next, a gettering region is formed by selectively adding a group 15 element into the amorphous semiconductor film using the mask,
Next, after removing the mask, a metal element that promotes crystallization is added to the entire surface of the amorphous semiconductor film,
Next, in the same heat treatment step, the amorphous semiconductor film is crystallized by a first heat treatment to form a crystalline semiconductor film, and then the temperature is changed higher than the temperature of the first heat treatment. A method for manufacturing a semiconductor device, wherein the metal element is gettered by a second heat treatment. Forming a mask on the amorphous semiconductor film;
Next, a gettering region is formed by selectively adding a group 15 element into the amorphous semiconductor film using the mask,
Next, after removing the mask, a metal element that promotes crystallization is added to the entire surface of the amorphous semiconductor film,
Next, in the same heat treatment step, the amorphous semiconductor film is crystallized by a first heat treatment to form a crystalline semiconductor film, and then the temperature is changed higher than the temperature of the first heat treatment. Performing gettering of the metal element by a second heat treatment;
After the gettering, patterning the crystalline semiconductor film,
Forming a gate insulating film on the patterned crystalline semiconductor film;
A method for manufacturing a semiconductor device, wherein a gate electrode is formed on the patterned crystalline semiconductor film with the gate insulating film interposed therebetween. In claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the mask is formed of a photoresist. In any one of Claims 1 thru | or 3,
One or more kinds selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, Ge, Pb, and In are used as the metal element. Manufacturing method. In any one of Claims 1 thru | or 3,
A manufacturing method of a semiconductor device, wherein Ni is used as the metal element.

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