JP4848562B2 - Multiprocessor - Google Patents

Description

  The present invention relates to a multiprocessor having a plurality of processor cores and related technology.

  In the multiprocessor of Patent Document 1, data transfer between an external memory and an internal memory is performed by DMA.

  In the multiprocessor of Patent Document 2, a memory management unit for accessing an external memory is mounted for each processor core.

  In the conventional multiprocessor, the bus for accessing the shared internal memory is generally the same as the bus for controlling the other functional units by the CPU.

JP-A-11-175398 JP 2001-51958 A

  In the multiprocessor of Patent Document 1, when performing block transfer of data between an external memory and an internal memory, high-speed data transfer is possible by DMA transfer. However, when performing random data access to discrete addresses, DMA transfer is inefficient.

  In the multiprocessor of Patent Document 2, since each of the processor cores is equipped with a memory management unit, the circuit configuration becomes complicated and the cost cannot be reduced.

  In the above conventional multiprocessor in which the bus for accessing the shared internal memory and the bus for controlling the other functional units by the CPU are the same, the access for controlling the other functional units by the CPU is the internal memory. The bus bandwidth is wasted.

  Accordingly, an object of the present invention is to provide a multiprocessor capable of efficiently accessing an external memory and a related technique.

  Another object of the present invention is to provide a multiprocessor and related technology capable of reducing the cost by simplifying the circuit configuration related to access to an external memory.

  Furthermore, another object of the present invention is to provide a multiprocessor and related technology capable of preventing waste of bus bandwidth of an internal memory due to control over a processor core.

  According to the first aspect of the present invention, the multiprocessor is a multiprocessor capable of accessing an external bus, and is shared by a plurality of processor cores each executing arithmetic processing and the plurality of processor cores. Direct direct memory access transfer between the internal memory and the external memory connected to the external bus by arbitrating direct memory access transfer requests from the internal memory and a part or all of the processor core Arbitrarily request to use the external bus from the memory access controller, part or all of the processor core and the direct memory access controller, and the external to the one of the processor core or the direct memory access controller Outside to allow access to the bus Includes a memory interface, a.

  In this configuration, part or all of the processor core has both a function of issuing an external bus use request directly to the external memory interface and a function of issuing a direct memory access transfer request to the direct memory access controller. Therefore, when random data access is performed to discrete addresses, an external bus use request is issued directly to the external memory interface, and direct memory is used when performing block transfer of data or page swap required by the virtual memory management mechanism. By issuing a direct memory access transfer request to the access controller, efficient access to the external memory becomes possible.

  In the multiprocessor, the direct access memory controller includes a plurality of buffers each storing the direct memory access transfer request from the corresponding processor core, and a plurality of the direct memory access transfers sent by the plurality of buffers. Arbitration means that arbitrates the request and outputs any one of the direct memory access transfer requests, and can hold a plurality of the direct memory access transfer requests, and has received the direct memory access transfer request output by the arbitration means A queue that sequentially outputs; and a direct memory access transfer execution unit that executes a direct memory access transfer according to the direct memory access transfer request output by the queue.

  This configuration includes a plurality of buffers and queues that hold a plurality of direct memory access transfer requests from a plurality of processor cores. Therefore, a direct memory access transfer request can be accepted even during direct memory access transfer execution. This is particularly effective when there is only one direct memory access channel.

  In the multiprocessor, the external memory interface performs arbitration according to a priority table that defines priorities of the processor core and the direct memory access controller that can make a request to use the external bus, and the priority table is A plurality are prepared, and the priorities are different from each other.

  According to this configuration, since the priority order is not fixed, even a processor core whose priority order is set low in a certain priority order table can set a high priority order in another priority order table. It is possible to prevent a request for using the external bus of the processor core from waiting for such a long time as to cause a problem for the system. The same applies to the direct memory access controller.

  In this multiprocessor, the external memory interface performs arbitration by switching the priority table when a predetermined condition is satisfied.

  According to this configuration, the priority table can be switched according to the purpose by setting a predetermined condition according to the purpose.

  The predetermined condition is that a request for using the external bus from the predetermined processor core or the direct memory access controller is waited for a predetermined time.

  According to this configuration, it is possible to prevent a request for using the external bus from a predetermined processor core or direct memory access controller from waiting for such a long time as to cause a problem in the system.

  The external bus interface includes a control register accessible by at least one of the processor cores, and the priority table is switched with an additional condition that a predetermined value is set in the control register by the at least one processor core. Can also be done.

  According to this configuration, it is possible to dynamically set whether to perform arbitration while fixing to one priority table, or to perform arbitration while switching a plurality of priority tables.

  According to a second aspect of the present invention, the multiprocessor is a multiprocessor capable of accessing an external bus, and includes a plurality of processor cores each executing arithmetic processing, and a part or all of the processor cores. An external memory interface that arbitrates use requests of the external bus and permits any one of the processor cores to access the external bus, and the external memory interface includes a plurality of different memory interfaces. An external memory connected to the external bus through the selected memory interface, the external memory being of a type corresponding to the selected memory interface. Access.

  In this configuration, the external memory interface has a mechanism for accessing the external memory. Therefore, even when different types of memory interfaces are supported, it is not necessary for each of the processor cores to include a plurality of memory interfaces. For this reason, the circuit configuration can be simplified, and the cost can be reduced.

  In the multiprocessor, the address space of the external bus is divided into a plurality of areas, and the type of the external memory can be set for each area, and the external memory interface permits access to the external bus. The memory interface corresponding to the type of the external memory set in the area including the address issued by the processor core is selected, and the external memory is accessed through the selected memory interface.

  According to this configuration, since the type of the external memory can be set for each area of the address space of the external bus, a plurality of different types of external memories can be connected.

  In this multiprocessor, the external memory interface includes a plurality of first control registers corresponding to the plurality of areas, and the plurality of first control registers are accessible by at least one processor core. When the at least one processor core sets a value in the first control register, the type of the external memory is set for the area corresponding to the first control register.

  According to this configuration, the type of the external memory can be dynamically set for each area by the processor core.

  In the multiprocessor, the address space of the external bus is divided into a plurality of areas, and the data bus width of the external bus can be set for each area. According to this configuration, a plurality of external memories having different data bus widths can be connected.

  In the multiprocessor, the external memory interface includes a plurality of second control registers corresponding to the plurality of areas, and the plurality of second control registers can be accessed by at least one processor core. When the at least one processor core sets a value in the second control register, the data bus width of the external bus is set for the area corresponding to the second control register.

  According to this configuration, the data bus width of the external bus can be dynamically set for each area by the processor core.

  In the multiprocessor, the address space of the external bus is divided into a plurality of areas, and the access timing to the external memory can be set for each of the areas. According to this configuration, a plurality of external memories having different access timings can be connected.

  In this multiprocessor, the external memory interface includes a plurality of third control registers corresponding to the plurality of areas, and the plurality of third control registers can be accessed by at least one processor core. When the at least one processor core sets a value in the third control register, an access timing to the external memory is set for the area corresponding to the third control register.

  According to this configuration, the access timing for the external memory can be dynamically set for each area by the processor core.

  In the multiprocessor, the external memory interface includes a fourth control register accessible by at least one of the processor cores, and the at least one processor core sets a value in the fourth control register. The boundary of the area is set. According to this configuration, the boundary of the region can be dynamically set by the processor core.

  According to a third aspect of the present invention, the multiprocessor includes a plurality of processor cores each executing arithmetic processing, an internal memory shared by the plurality of processor cores, and data transfer between the processor core and the internal memory. And a second data transfer path for performing data transfer for the processor core to control the other processor core.

  In this configuration, the path for accessing the shared internal memory and the path for controlling the processor core are separated from each other, so that waste of the bus bandwidth of the internal memory due to the control for the processor core can be prevented.

  In the multiprocessor, the processor core that controls the other processor core using the second data transfer path is a central processing unit that interprets and executes a program instruction. According to this configuration, each processor core can be dynamically controlled by software.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is incorporated. In the present specification and drawings, when it is necessary to indicate which bit of a signal, [a: b] or [a] is added after the signal name. [A: b] means the a-th bit to the b-th bit of the signal, and [a] means the a-th bit of the signal. “0b” means a binary number, and “0x” means a hexadecimal number.

  FIG. 1 is a block diagram showing an internal configuration of a multimedia processor 1 according to the embodiment of the present invention. As shown in FIG. 1, this multimedia processor includes an external memory interface 3, a DMAC (direct memory access controller) 4, a central processing unit (hereinafter referred to as “CPU”) 5, a CPU local RAM 7, and a rendering processing unit. (Hereinafter referred to as “RPU”) 9, color palette RAM 11, sound processing unit (hereinafter referred to as “SPU”) 13, SPU local RAM 15, geometry engine (hereinafter referred to as “GE”) 17, Y Sorting unit (hereinafter referred to as “YSU”) 19, external interface block 21, main RAM access arbiter 23, main RAM 25, I / O bus 27, video DAC (digital to analog con) Erter) 29, audio DAC block 31, and A / D converter (hereinafter, referred to as "ADC".) 33 comprises a. The external memory interface 3 includes memory interfaces (MIF) 40, 41 and 42. The CPU 5 includes an IPL (initial program loader) 35.

  Here, CPU5, RPU9, SPU9, GE17, and YSU19 may be referred to as a processor core. Further, when it is not necessary to distinguish between the main RAM 25 and the external memory 50, they are referred to as “memory MEM”.

  The external memory interface 3, which is one of the features of the present invention, is responsible for reading data from the external memory 50 and writing data to the external memory 50 via the external bus 51. The memory interface 40 is a standard asynchronous interface (hereinafter referred to as “NOR interface”), and the memory interface 41 is a standard asynchronous interface with page mode (hereinafter referred to as “NOR interface with page mode”). The memory interface 42 is a NAND flash EEPROM compatible interface (hereinafter referred to as “NAND interface”). The external memory interface 3 will be described in detail later.

  The DMAC 4 which is one of the features of the present invention performs DMA transfer between the main RAM 25 and the external memory 50 connected to the external bus 51. The DMAC 4 will be described in detail later.

  The CPU 5 executes programs stored in the memory MEM to perform various calculations and control of the entire system. Further, the CPU 5 can make a program and data transfer request to the DMAC 4, and can directly fetch the program code from the external memory 50 or directly access the data to the external memory 50 without going through the DMAC 4. . The IPL 35 loads a program to be started first from the external memory 50 when the power is turned on or reset.

  The I / O bus 27 which is one of the features of the present invention is a system control bus having the CPU 5 as a bus master, and each functional unit (external memory interface 3, RPU9, SPU13, GE17, YSU19, bus slave). And the external interface block 21) are used to access the control registers and the local RAMs 7, 11, and 15. In this way, these functional units are controlled by the CPU 5 through the I / O bus 27.

  The CPU local RAM 7 is a RAM dedicated to the CPU 5, and is used as a stack area for saving data at the time of a subroutine call or interruption, a storage area for variables handled only by the CPU 5, and the like.

  The RPU 9 generates a three-dimensional image composed of polygons and sprites in real time. Specifically, the RPU 9 reads each structure instance of the polygon structure array and each structure instance of the sprite structure array sorted by the YSU 19 from the main RAM 25, executes a predetermined process, and executes a screen ( An image is generated for each horizontal line according to the scan of the display screen. The generated image is converted into a data stream indicating a composite video signal waveform and output to the video DAC 29. Further, the RPU 9 has a function of making a DMA transfer request to the DMAC 4 for taking in texture pattern data of polygons and sprites.

  The texture pattern data is two-dimensional pixel array data that is pasted on a polygon or sprite. Each pixel data is a part of information for designating an entry in the color palette RAM 11. Hereinafter, the pixels of the texture pattern data are referred to as “texels”, and are used separately from “pixels” that indicate the pixels constituting the image displayed on the screen.

  The polygon structure array is a structure array for polygons that are polygonal graphic elements, and the sprite structure array is a structure array for sprites that are rectangular graphic elements parallel to the screen. The elements of the polygon structure array are called “polygon structure instances”, and the elements of the sprite structure array are called “sprite structure instances”. However, when it is not necessary to distinguish between the two, they may be simply referred to as “structure instances”.

  Each polygon structure instance stored in the polygon structure array includes display information for each polygon (including texture pattern data storage addresses in texture mapping mode and color data (RGB color components) in Gouraud shading mode). One polygon corresponds to one polygon structure instance. Each sprite structure instance stored in the sprite structure array is display information for each sprite (including the texture pattern data storage address), and one sprite corresponds to one sprite structure instance.

  The video DAC 29 is a digital / analog converter for generating an analog video signal. The video DAC 29 converts the data stream input from the RPU 9 into an analog composite video signal, and outputs it from a video signal output terminal (not shown) to a television monitor or the like (not shown).

  In the present embodiment, the color palette RAM 11 is composed of a color palette of 512 colors, that is, 512 entries. The RPU 9 refers to the color palette RAM 11 using the texel data included in the texture pattern data as part of an index for designating the entry of the color palette, and converts the texture pattern data into color data (RGB color components).

  The SPU 13 generates PCM (pulse code modulation) waveform data (hereinafter referred to as “wave data”), amplitude data, and main volume data. Specifically, the SPU 13 time-division multiplexes wave data for a maximum of 64 channels, time-division multiplexes envelope data for a maximum of 64 channels, and multiplies the channel volume data to generate amplitude data. Then, the SPU 13 outputs the main volume data, the time-division multiplexed wave data, and the time-division multiplexed amplitude data to the audio DAC block 31. Further, the SPU 13 has a function of making a DMA transfer request for taking in wave data and envelope data to the DMAC 4.

  The audio DAC block 31 converts the wave data, amplitude data, and main volume data input from the SPU 13 into analog signals, and multiplies the results to generate analog audio signals. This analog audio signal is output from an audio signal output terminal (not shown) to an audio input terminal (not shown) of a television monitor or the like (not shown).

  The SPU local RAM 15 stores parameters used when the SPU 13 performs wave reproduction and envelope generation (for example, storage addresses and pitch information of wave data and envelope data).

  The GE 17 executes a geometric operation for displaying a three-dimensional image. Specifically, the GE 17 performs operations such as matrix product, vector affine transformation, vector orthogonal transformation, perspective projection transformation, vertex lightness / polygon lightness calculation (vector inner product), and polygon back surface culling processing (vector outer product).

  The YSU 19 sorts each structure instance of the polygon structure array and each structure instance of the sprite structure array stored in the main RAM 25 according to the sorting rules 1 to 4. In this case, the polygon structure array and the sprite structure array are separately sorted.

  Sort rule 1 is to rearrange the polygon structure instances in ascending order of the minimum Y coordinate. The minimum Y coordinate is the smallest Y coordinate among the Y coordinates of the three vertices of the polygon. The Y coordinate is the vertical coordinate of the screen, and the downward direction is the positive direction. Sort rule 2 is to arrange the polygon structure instances in descending order of the depth value for a plurality of polygons having the same minimum Y coordinate.

  However, the YSU 19 regards a plurality of polygons having pixels displayed on the first line of the screen as being the same even if the minimum Y coordinate is different, so that the sorting rule 2 is not the sorting rule 1. According to the above, the polygon structure instances are rearranged. That is, when there are a plurality of polygons having pixels displayed on the top line of the screen, the minimum Y coordinate is regarded as the same, and they are rearranged in descending order of the depth value. This is the sort rule 3.

  Sort rules 1 to 3 are applied even in the case of interlaced scanning. However, in the sorting for displaying the odd field, the minimum Y coordinate of the polygon displayed on the odd line and / or the minimum Y coordinate of the polygon displayed on the even line immediately before the odd line are the same. As a result, the sorting by the sorting rule 2 is performed. However, the first odd line is excluded. This is because there is no previous even line. On the other hand, in the sorting for displaying the even field, the minimum Y coordinate of the polygon displayed on the even line and / or the minimum Y coordinate of the polygon displayed on the odd line immediately before the even line are the same. As a result, the sorting by the sorting rule 2 is performed. This is sort rule 4.

  Sort rules 1 to 4 for sprites are the same as sort rules 1 to 4 for polygons, respectively.

  The external interface block 21 is an interface with the peripheral device 54 and includes a 24-channel programmable digital input / output (I / O) port. Each 24 channel I / O port has 4 channels of mouse interface function, 4 channels of light gun interface function, 2 channels of general-purpose timer / counter, 1 channel of asynchronous serial interface function, 1 channel Are internally connected to one or more of the general-purpose parallel / serial conversion port functions.

  The ADC 33 is connected to 4-channel analog input ports, and converts the analog signal input from the analog input device 52 into a digital signal via these. For example, an analog input signal such as a microphone sound is sampled and converted into digital data.

  The main RAM access arbiter 23 which is one of the features of the present invention is from a functional unit (CPU 5, RPU 9, GE 17, YSU 19, DMAC 4, and external interface block 21 (asynchronous serial port or general-purpose parallel / serial conversion port)). The access to the main RAM 25 is arbitrated, and access permission is given to one of the functional units.

  The main RAM 25 is used as a work area, a variable storage area, a virtual storage management area, and the like for the CPU 5. Further, the main RAM 25 is a storage area for data that the CPU 5 delivers to other functional units, a storage area for data that the RPU 9 and SPU 13 have acquired from the external memory 50 by DMA, a storage area for input data and output data for the GE 17 and YSU 19, etc. Also used as

  The external bus 51 is a bus for accessing the external memory 50. It is accessed from the IPL 35, the CPU 5, and the DMAC 4 via the external memory interface 3. The address bus of the external bus 51 is composed of 30 bits, and an external memory 50 of 1 Gbyte (= 8 Gbit) at the maximum can be connected. The data bus of the external bus 51 is composed of 16 bits, and can connect an external memory 50 having a data bus width of 8 bits or 16 bits. External memories having different data bus widths can be connected at the same time, and a function of automatically switching the data bus width according to the external memory to be accessed is provided.

  FIG. 2 is an explanatory diagram of the address space of the external bus 51. As shown in FIG. 2, the address space of the external bus 51 is divided into two areas so that two different types of external memories can be connected, and are called a primary memory area and a secondary memory area, respectively. One of the memory interfaces 40 to 42 is set for each area. Of course, the same memory interface can be set in the two areas, or different memory interfaces can be set. Hereinafter, the external memory interface 3 will be described in detail.

  Returning to FIG. 1, the memory interface 40, that is, the NOR interface is such that each bit of address and data is connected in parallel between the external memory interface 3 and the external memory 50, and has a clock signal for synchronization between signals. There is no memory interface. Standard mask ROM, standard SRAM, NOR flash EEPROM, and the like have a NOR interface. Therefore, these memories can be used as the external memory 50.

  The memory interface 41, that is, the NOR interface with page mode is a NOR interface that supports the page mode. Therefore, a memory having a NOR interface and supporting the page mode can be used as the external memory 50. In general, the page mode is an access mode in which the access time after the second time in the page can be shortened when accesses are continued in the page set in the memory. The page size varies depending on the type of memory.

  The memory interface 42, that is, the NAND interface is a memory interface compatible with the interface of the NAND flash EEPROM. However, since the NAND interface of the multiprocessor 1 does not include hardware for error correction, the NAND flash EEPROM cannot be connected as it is, and can be connected to a NAND flash EEPROM compatible mask ROM or the like. Therefore, those memories can be used as the external memory 50.

  The external memory interface 3 arbitrates external bus access request factors (factors requesting access to the external bus 51) from the IPL 35, the CPU 5, and the DMAC 4 in accordance with an EBI priority table to be described later. Select the access request factor. Then, access to the external bus 51 is permitted for the selected external bus access request factor. These details will be described.

  FIG. 3 is a view showing an example of an EBI priority table that is referred to when arbitrating by the external memory interface 3. Referring to FIG. 3A, external bus access request factors include a block transfer request by IPL 35, a data access request by CPU 5, a DMA request by DMAC 4, and an instruction fetch request by CPU 5. The priority is highest for No. 1 and decreases as the number increases.

  The external memory interface 3 arbitrates external bus access request factors according to the EBI priority table of FIG. However, if the instruction fetch request by the CPU 5 is waited for 10 microseconds or more and the setting of the arbitration priority control register described later is “priority change enable”, the EBI priority table shown in FIG. Is used. When the instruction fetch is performed by the CPU 5 in this state, the EBI priority table shown in FIG. 3A is used again.

  Returning to FIG. 2, among the external bus access request factors, the DMA request by the DMAC 4 and the data access request by the CPU 5 can access the entire area of the address space of the external bus 51. On the other hand, in the instruction fetch request by the CPU 5 and the block transfer request by the IPL 35, the accessible area is limited.

  In the instruction fetch request by the CPU 5, the range of 0x0000000 to 0x00FFFFFF is an accessible external bus address. The IPL 35 transfers the data (startup program) stored in the external bus address 0x0000000-0x000000FF to the address 0x0000-0x00FF of the main RAM 25 when the multimedia processor 1 starts up, and starts the program execution of the CPU 5 from the address 0x0000 of the main RAM 25 Let Therefore, in the block transfer request by the IPL 35, the external bus address outside the range of 0x0000000 to 0x000000FF is not accessed.

  FIG. 4 is an explanatory diagram of a control register provided in the external memory interface 3. As shown in FIG. 4, each control register is arranged at a corresponding I / O bus address in the figure, and the CPU 5 can read and write via the I / O bus 27.

  The secondary memory start address register is a control register for setting the start address of the secondary memory area, that is, the boundary between the primary memory area and the secondary memory area. However, only the upper 10 bits of the external bus address can be set, and the lower 20 bits are all fixed to “0”. Therefore, the start address of the secondary memory area can be set in units of 1M bytes (= 8M bits) such as 0x00000000, 0x00100000, 0x00200000,.

  The primary memory type register is the type of memory interface (external memory) set in the primary memory area (memory interface 40, 41 or 42), page size (4, 8, 16, 32, 64, 128, 256 or 512 bytes). A control register for setting the data bus width (8 or 16 bits) and the address size (3 or 4 bytes) of the NAND interface.

  The primary memory access timing register is a control register for setting the access timing to the primary memory area.

  That is, the control register holds the access cycle time Tac, the page access cycle time Tapc (valid when the memory interface 41 is set), the command latch enable signal CLE and the address latch enable signal ALE with respect to the write enable signal / WE. Time Tcah (valid when the memory interface 42 is set), delay time Tcd from the start of the access cycle of the memory select signal / CS0B, delay time Trd from the start of the access cycle of the read enable signal / REB, read enable signal / REB Pulse width Trpw, delay time Twd from the start of the access cycle of the write enable signal / WEB, pulse width Twpw of the write enable signal / WEB, write enable signal / WE Write data hold time Tdh with respect to the rising edge (effective when a memory interface 40 or 41 other than the memory interface 42 is set), write data hold time Tfdh with respect to the rising edge of the write enable signal / WEB (memory interface 42 is set) And the write data setup time Tds with respect to the fall of the write enable signal / WEB is set. These will become clear from the description of FIGS.

  The secondary memory type register is the type of memory interface (external memory) set in the secondary memory area (memory interface 40, 41 or 42), page size (4, 8, 16, 32, 64, 128, 256 or 512 bytes). A control register for setting the data bus width (8 or 16 bits) and the address size (3 or 4 bytes) of the NAND interface.

  The secondary memory access timing register is a control register for setting the access timing to the secondary memory area. The specific setting contents are the same as those of the primary memory access timing register. However, delay time Tcd is a delay time from the start of the access cycle of memory select signal / CS1B.

  The arbitration priority control register is a control register for controlling the priority in arbitration between external bus access request factors. When “1” is set in this register and “priority change enable” is set, if an instruction fetch request from the CPU 5 is waited for 10 microseconds or longer, the EBI priority table shown in FIG. The priority of the instruction fetch request by the CPU 5 is raised. When the instruction fetch is performed by the CPU 5 in this state, the EBI priority table shown in FIG. 3A is used again. If “0” is set in this register, “priority change is disabled”, and the above priority change is not performed.

  The external memory interface 3 has an area (primary memory area or secondary memory area) including an external bus address issued by a functional unit (IPL 35, CPU 5, or DMAC 4) that has permitted access to the external bus 51 as a result of arbitration. The set memory interface 40, 41 or 42 is selected, and the external memory 50 is accessed through the selected memory interface.

  In this case, the selected memory interface reads / writes based on the read / write information, the data transfer byte count information, and / or the write data output by the functional unit that is permitted to access the external bus 51. Take control.

  FIG. 5 is a block diagram showing the request queue 45 of the DMAC 4 and its peripheral part. As shown in FIG. 5, the DMAC 4 includes a request buffer 105 that holds a DMA request from the CPU 5, a request buffer 109 that holds a DMA request from the RPU 9, a request buffer 113 that holds a DMA request from the SPU 13, and a DMA request arbiter 44. A request queue 45 and a DMA execution unit 46.

  When the DMA transfer request is entered in two or more request buffers among the request buffers 105, 109, and 113, the DMA request arbiter 44 sends the DMA transfer request to the tail end of the request queue 45 according to the DMA priority table described later. To send. The request queue 45 having four entries has a FIFO structure, and is sequentially sent to the DMA execution unit 46 from the DMA transfer request received first. The DMA execution unit 46 issues an access request to the external bus 51 (a DMA request as an external bus access request factor), and if access to the external bus 51 is permitted, the DMA transfer request received from the request queue 45 DMA transfer according to the above is executed.

  Since DMAC 4 has only one DMA channel, DMA transfer cannot be executed at the same time, but request buffers 105, 109, and 113 that hold DMA transfer requests from CPU 5, RPU 9, and SPU 13, and four entries Since the request queue 45 is provided, the DMA transfer request can be accepted even during the DMA transfer.

  FIG. 6 is a view showing an example of a DMA priority order table that is referred to when mediation is performed by the DMAC 4. Referring to FIG. 6, as described above, this DMA priority table is stored in DMA request arbiter 44 in a state where DMA transfer requests are entered in two or more request buffers among request buffers 105, 109, and 113. Indicates which DMA transfer request is sent to the request queue 45 with priority.

  The priority is highest for No. 1 and decreases as the number increases. Therefore, the higher priority order is the DMA transfer request by the SPU 13, the DMA transfer request by the RPU 9, and the DMA transfer request by the CPU 5. In the present embodiment, the priority is fixed by hardware and cannot be changed.

  The DMA request factors (factors requesting DMA transfer) from the SPU 13, RPU 9, and CPU 5 will be described in order.

  Referring to FIG. 6, the DMA request factors of SPU 13 include (1) transferring wave data to the wave buffer and (2) transferring envelope data to the envelope buffer. The wave buffer and envelope buffer are temporary storage areas for wave data and envelope data set on the main RAM 25, respectively. The head address of the temporary storage area is determined by a control register (not shown) in the SPU 13, and the size of the temporary storage area is determined by setting the number of playback channels. The arbitration between the two DMA request factors of the SPU 13 is performed by hardware (not shown) in the SPU 13, and the DMAC 4 is not concerned.

  As a DMA request factor of the RPU 9, there is transferring the texture pattern data to the texture buffer. The texture buffer is a temporary storage area for texture pattern data set on the main RAM 25. The head address and size of this temporary storage area are determined by a control register (not shown) in the RPU 9.

  The DMA request factors of the CPU 5 include (1) page transfer when a page miss occurs in virtual storage management, and (2) data transfer requested by an application program or the like. When a plurality of DMA transfer requests are generated simultaneously in the CPU 5, the arbitration is performed by software executed by the CPU 5, and the DMAC 4 is not concerned.

  The DMA request factor (1) by the CPU 5 will be described in a little more detail. The DMA transfer request of the CPU 5 is made according to the execution of software. In the general software structure of the multimedia processor 1, virtual memory management is performed by an OS (Operating System). When a page miss occurs in the virtual memory management and a page swap is necessary, the OS issues a DMA transfer request to the DMAC 4.

  The DMA request factor (2) by the CPU 5 will be described in a little more detail. A DMA request is issued when it is necessary to transfer data between the external memory 50 and the main RAM 25 during execution of system software such as an OS or application software.

  The DMAC 4 has a data decompression function based on the LZ77 algorithm, and can perform DMA transfer while decompressing the compressed data stored in the external memory 50 in response to an MDA transfer request from the CPU 5.

  FIG. 7 is an explanatory diagram of a control register included in the DMAC 4. As shown in FIG. 7, each control register is arranged at a corresponding I / O bus address in the figure, and the CPU 5 can read and write via the I / O bus 27. That is, these control registers are set when a DMA transfer request is made by the CPU 5.

  In the DMA transfer source address register, the transfer source address in the DMA transfer is set by the physical address of the external bus 51. In the DMA transfer destination address register, the transfer destination address in the DMA transfer is set as the physical address of the main RAM 25. The number of transfer bytes in DMA transfer is set in the DMA transfer byte number register. In data decompression DMA, the number of bytes after decompression is counted.

  The DMA control register is a register that performs various controls of the DMAC 4, and includes a DMA transfer enable bit, a DMA start bit, and an interrupt enable bit. The DMA transfer enable bit is a bit for controlling enable / disable of DMA transfer requested by the CPU 5. When “1” is set in the DMA start bit, the DMA transfer request (transfer source address, transfer destination address, and transfer byte count) written in the request buffer 105 corresponding to the CPU 5 is sent to the request queue 45. The The interrupt enable bit is a bit for controlling whether or not to make an interrupt request to the CPU 5 when the DMA transfer requested by the CPU 5 is completed.

  The DMA data expansion control register includes a data expansion enable bit. This bit is a bit that controls enabling / disabling of data expansion in the DMA transfer requested by the CPU 5. The DMA status register is a register representing various statuses of the DMAC 4 and includes a request queue busy bit, a DMA completion bit, a DMA execution bit, and a DMA incomplete field.

  The request queue busy bit indicates the state (busy / ready) of the request queue 45. If the status of the request queue 45 is “busy”, no new DMA transfer request is entered in the request queue 45. The DMA completion bit is set to “1” every time the DMA transfer requested by the CPU 5 is completed. When the interrupt enable bit is set to enable, an interrupt request to the CPU 5 is generated at the same time that the DMA completion bit is set to “1”. The DMA executing bit is a bit indicating whether or not DMA transfer is being executed. The DMA incomplete field is a field indicating the number of incomplete DMA transfers requested from the CPU 5.

  The DMA data expansion ID register stores an ID code in the data expansion DMA. When the DMA data expansion control register is set to enable, if the first two bytes of the 256-byte block match the ID code set in the DMA data expansion ID register, the DMAC 4 compresses the block. Decompress data.

  Next, access to the external memory 50 will be described with reference to the timing charts of FIGS. In the description of FIGS. 8 to 11, the period 1T represents one cycle of the system clock of the multimedia processor 1 and corresponds to about 10.2 nanoseconds.

  FIG. 8 is a timing chart showing a random access read cycle in the NOR interface. In the example of FIG. 8, Tac = 9T, Tcd = 1T, Trd = 2T, and Trpw = 7T. The meanings of the periods Tac, Tcd, Trd, and Trpw are as described in FIG. The set data bus width of the external bus 51 is 16 bits.

These periods must satisfy all of the following conditions:
Tac ≧ Trd + Trpw
Tac ≧ 2T
Tac> Tcd
Trpw> 0T
When these conditions are not satisfied, writing to the primary memory access timing register and the secondary memory access timing register of the external memory interface 3 is ignored.

  Referring to FIG. 8, memory interface 40 starts sending external bus address EA [29: 0] to external bus 51 in start cycle CY0 of access cycle period Tac. The external bus address EA is transmitted during the access cycle period Tac. Then, the memory interface 40 asserts the memory select signal / CSB0 or / CSB1 after a period Tcd from the rising edge of the system clock in the start cycle CY0. Further, the memory interface 40 asserts the read enable signal / REB after a period Trd from the rise of the system clock in the start cycle CY0. Then, the memory interface 40 takes in the data ED [15: 0] read from the external memory 50 to the external bus 51 at the rising edge of the system clock in the last cycle of the access cycle Tac. Since it is read access, the write enable signal / WEB is kept negated.

  FIG. 9 is a timing chart showing a read cycle of page mode access in the NOR interface with page mode. In the example of FIG. 9, Tac = 5T, Tapc = 3T, Tcd = 1T, Trd = 2T, Trpw = 3T. The meanings of the periods Tac, Tapc, Tcd, Trd, and Trpw are as described in FIG. However, in FIG. 9, the period Tac is a cycle time of random access. The set data bus width of the external bus 51 is 16 bits.

These periods must satisfy all of the following conditions:
Tac ≧ Trd + Trpw
Tac ≧ 2T
Tapc> 0T
Tac> Tcd
Trpw> 0T
When these conditions are not satisfied, writing to the primary memory access timing register and the secondary memory access timing register of the external memory interface 3 is ignored.

  Referring to FIG. 9, the first read cycle CYR whose length is defined by the period Tac is a random access cycle, and the following three read cycles CYP1 to CYP3 whose length is defined by the period Tapc are in page mode. It is an access cycle.

  The memory interface 41 starts sending the external bus address EA [29: 0] to the external bus 51 in the start cycle CY0 of the access cycle period Tac. The external bus address EA is transmitted during the access cycle period Tac. Then, the memory interface 41 asserts the memory select signal / CSB0 or / CSB1 after a period Tcd from the rise of the system clock in the start cycle CY0. Further, the memory interface 41 asserts the read enable signal / REB after a period Trd from the rise of the system clock in the start cycle CY0. Then, the memory interface 41 takes in the data ED [15: 0] read from the external memory 50 to the external bus 51 at the rising edge of the system clock in the final cycle of the first read cycle CYR.

  In the next read cycle CYP 1, the memory interface 41 sends the next external bus address EA to the external memory 50. Then, the memory interface 41 takes in new data ED read from the external memory 50 to the external bus 51 at the rising edge of the system clock in the final cycle of the read cycle CYP1. Such an operation is continuously performed in the subsequent read cycles CYP2 and CYP3.

  As described above, in the page mode access, only the control of the memory select signals / CSB0, / CSB1 and the read enable signal / REB is necessary only in the first read cycle CYR. In the subsequent read cycles CYP1 to CYP3, the control thereof is performed. Becomes unnecessary, and high-speed access becomes possible. Since it is read access, the write enable signal / WEB is kept negated.

  FIG. 10 is a timing chart showing a random access write cycle in the NOR interface. In the example of FIG. 10, Tac = 9T, Tcd = 1T, Twd = 2T, Twpw = 6T, Tds = 1T, and Tdh = 1T. The meanings of the periods Tac, Tcd, Twd, Twpw, Tds, and Tdh are as described in FIG. The set data bus width of the external bus 51 is 16 bits.

These periods must satisfy all of the following conditions:
Tac ≧ Twd + Twpw
Tac ≧ 2T
Tac> Tcd
Twpw> 0T
Twd ≧ Tds
When these conditions are not satisfied, writing to the primary memory access timing register and the secondary memory access timing register of the external memory interface 3 is ignored.

  Referring to FIG. 10, memory interface 40 starts sending external bus address EA [29: 0] to external memory 50 in start cycle CY0 of access cycle period Tac. The external bus address EA is transmitted during the access cycle period Tac. Then, the memory interface 40 asserts the memory select signal / CSB0 or / SCB1 after a period Tcd from the rising edge of the system clock in the start cycle CY0. Further, the memory interface 40 asserts the write enable signal / WEB after a period Twd from the rising edge of the system clock in the start cycle CY0.

  The memory interface 40 starts sending the write data ED [15: 0] to the external bus 51 before the write enable signal / WEB is asserted, that is, earlier by the time Tds. Further, after the write enable signal / WEB is negated, the memory interface 40 continues to send the write data ED to the external bus 51 for a time Tdh. Since it is a write access, the read enable signal / REB is kept negated.

  Even when the area to be accessed (see FIG. 2) is set to the page mode, page mode access is not applied in the write cycle, and all are random access.

  FIG. 11 is a timing chart showing a read cycle in the NAND interface. In the example of FIG. 11, Tcd = 1T, Tcah = 2T, Twd = 2T, Twpw = 3T, Tds = 1T, Tfdh = 2T, Trd = 2T, Trpw = 4T. The setting of these periods is as described in FIG. The set data bus width of the external bus 51 is 16 bits.

  Referring to FIG. 11, when accessing the external memory 50 of the NAND interface, the memory interface 42 first issues a read command to the external memory 50. At this time, the memory interface 42 asserts the command latch enable signal CLE. The types of commands issued by the memory interface 42 are two types of read commands, “0x00” and “0x01”. Two types of read commands are prepared because the LSB of the command indicates the eighth bit A8 of the read start address.

  Subsequently, the memory interface 42 issues a read start address to the external memory 50. At this time, the memory interface 42 asserts an address latch enable signal ALE. The read start address is issued in 8 bits divided into 3 times. However, when the capacity of the connected external memory 50 exceeds 32 Mbytes, it must be set to a mode in which the input is divided into four times of 8 bits. This setting is performed in the primary memory type register or the secondary memory type register of the external memory interface 3.

  When these commands are issued and the read start address is issued, the write enable signal / WEB is asserted.

  Here, the period Twd indicates a delay time from the start cycle of issuing a command or read start address until the write enable signal / WEB is asserted. The period Twpw indicates the length of the period during which the write enable signal / WEB is asserted. The period Tcah is the hold time of the command latch enable signal CLE and the address latch enable signal ALE with respect to the write enable signal / WE, the period Tcd is the delay time from the start of the access cycle of the memory select signal / CS0B or / CS1B, and the period Tfdh is The read command hold time with respect to the rise of the write enable signal / WEB, the period Tds, is the read command setup time with respect to the fall of the write enable signal / WEB.

  When the read start address is input, the external memory 50 enters a busy state. In the busy state, the external memory 50 sets the ready / busy signal RDY_BSYB to a low level (busy). When the memory interface 42 detects the transition of the ready / busy signal RDY_BSYB from the low level (busy) to the high level (ready), the memory interface 42 starts reading data.

  However, if the busy state is shorter than one cycle of the system clock, the memory interface 42 may not be able to detect the busy state. Therefore, since the ready / busy output of the external memory 50 has a maximum delay of 200 nanoseconds, the ready / busy signal RDY_BSYB is already at a high level (ready) 200 nanoseconds after issuing the last byte of the read start address. , It can be determined that the external memory 50 has already passed the busy state and is in the ready state. Therefore, if the ready / busy signal RDY_BSYB indicates a high level (ready) 20T after issuing the last byte of the read start address, the memory interface 42 immediately starts data reading.

  When the data read is started, the memory interface 42 reads the data from the external memory 50 by asserting the read enable signal / REB. Each time the read enable signal / REB is asserted, the external memory 50 of the NAND interface outputs memory words having consecutive addresses to the data bus ED of the external bus 51. The memory interface 42 takes in the read data from the data bus ED of the external bus 51 at the end of one read cycle, that is, at the rising edge of the system clock at which the read enable signal / REB is negated.

  As described above, in the data read from the external memory 50 of the NAND interface, the data can be continuously read from the read start address every time the read enable signal / REB is asserted. However, when the read reaches the end of the page, the ready / busy signal RDY_BSYB indicates Low level (busy) again, and the read is interrupted until it becomes High level (ready).

  Here, the period Trd indicates a delay time from the start cycle of the read cycle until the read enable signal / REB is asserted. The period Trpw indicates the length of the period during which the read enable signal / REB is asserted.

  As described above, in this embodiment, the CPU 5 has both a function for issuing an external bus access request directly to the external memory interface 3 and a function for making a DMA transfer request to the DMAC 4. Accordingly, when random access is made to discrete addresses, an external bus access request is issued directly to the external memory interface 3, and when performing block transfer of data or page swap required by the virtual memory management mechanism, the DMAC 4 By issuing a DMA transfer request to the external memory 50, efficient access to the external memory 50 becomes possible.

  In this embodiment, the IPL 35, the CPU 5, and the DMAC 4 only make an external bus access request to the external memory interface 3, and the external memory interface 3 has a mechanism for reading / writing data. ing. Therefore, even when different types of memory interfaces are supported, it is not necessary for each of the IPL 35, the CPU 5, and the DMAC 4 to include a plurality of memory interfaces. For this reason, the circuit configuration can be simplified, and the cost can be reduced.

  Even in a conventional multiprocessor, a plurality of processor cores share an external bus through an external memory interface, but each processor core has a mechanism for reading / writing data. Therefore, in order to be able to connect external memories of different types such as NOR interface and NAND interface, each of the processor cores must have a plurality of different memory interfaces. This complicates the circuit configuration and cannot reduce the cost.

  Further, in the present embodiment, the access path to the shared main RAM 25 (that is, the main RAM access arbiter 23) and the path for controlling the functional unit (that is, the I / O bus 27) are separated. Therefore, waste of the bus bandwidth of the main RAM 25 due to control on the functional unit can be prevented.

  In this case, the functional unit is controlled using the I / O bus 27 by the CPU 5 that interprets and executes the program instruction, so that the functional unit can be dynamically controlled by software.

  Further, in the present embodiment, three request buffers 105, 109 and 113 for holding three DMA transfer requests from the CPU 5, RPU 9, and SPU 13 and a four-entry request queue 45 are provided. Therefore, a DMA transfer request can be accepted even during DMA transfer execution. This is particularly effective when there is only one DMA channel.

  Further, in the present embodiment, the external memory interface 3 is configured when the instruction fetch request from the CPU 5 is waited for 10 microseconds or more and the setting of the arbitration priority control register is “priority change enable”. Refer to the EBI priority table shown in FIG. 3B instead of 3 (a). Therefore, it is possible to prevent the instruction fetch request by the CPU 5 from being kept waiting so long as to cause a problem in the system. In addition, by accessing the arbitration priority control register, the CPU 5 can dynamically set whether to perform arbitration while fixing to one priority table, or to perform arbitration while switching between two priority tables. .

  Furthermore, according to the present embodiment, since the address space of the external bus 51 is divided into a primary memory area and a secondary memory area, the type of the external memory can be set for each area. External memory can be connected. Further, since the data bus width of the external bus 51 can be set for each region, a plurality of external memories having different data bus widths can be connected. Furthermore, since the access timing to the external memory can be set for each area, a plurality of external memories having different access timings can be connected.

  Furthermore, according to the present embodiment, as shown in FIG. 4, a memory type register and an access timing register are provided for each of the primary memory area and the secondary memory area. Therefore, the CPU 5 can dynamically set the type of the external memory 50, the data bus width of the external bus 51, and the access timing to the external memory 50 for each area. In addition, since the secondary memory start address register is provided, the CPU 5 can dynamically set the boundary of the area.

  The present invention is not limited to the above-described embodiment, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

  (1) In the above description, only the IPL 35, the CPU 5, and the DMAC 4 can make an external bus access request to the external memory interface 3. However, more functional units can make an external bus access request. You can also.

  (2) In the above description, only the CPU 5, RPU 9, and SPU 13 can make a DMA transfer request to the DMAC 4, but more functional units or fewer functional units can make a DMA transfer request. You can also. In this case, the DMAC 4 is provided with the same number of request buffers as the number of functional units that can make a DMA transfer request. Further, the number of entries in the request queue 45 is not limited to four.

  (3) In the above description, the address space of the external bus 51 is divided into two areas, but it can also be divided into three or more areas. In this case, the same number of sets of memory type registers and access timing registers as the number of areas are provided.

  (4) In the above description, the three memory interfaces 40 to 42 are provided, but the number may be two or less, or four or more. Further, although the NOR interface, the NOR interface with page mode, and the NAND interface are supported as the memory interface, the type of the memory interface is not limited to these.

  (5) In the above, only the CPU 5 uses the I / O bus 27 to control other functional units, but a plurality of functional units can control other functional units by the I / O bus 27. You can also

  (6) In the above description, the EBI priority order table is fixed. However, a plurality of different EBI priority order tables can be switched and used when a predetermined condition is satisfied. In addition, although two DMA priority tables are used by switching, three or more DMA priority tables can also be used by switching.

It is a block diagram which shows the internal structure of the multimedia processor 1 by embodiment of this invention. 4 is an explanatory diagram of an address space of an external bus 51. FIG. It is an illustration figure of the EBI priority table referred in the case of mediation by the external memory interface 3. It is explanatory drawing of the control register with which the external memory interface 3 is provided. It is a block diagram which shows the request queue 45 of DMAC4, and its peripheral part. It is an illustration figure of the DMA priority order table referred in the case of arbitration by DMAC4. It is explanatory drawing of the control register with which DMAC4 is provided. It is a timing chart which shows the read cycle of random access in a NOR interface. It is a timing chart which shows the read cycle of page mode access in a NOR interface with page mode. It is a timing chart which shows the write cycle of random access in a NOR interface. 3 is a timing chart showing a read cycle in a NAND interface.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Multimedia processor, 3 ... External memory interface, 4 ... DMAC, 5 ... CPU, 9 ... RPU, 13 ... SPU, 17 ... GE, 19 ... YSU, 21 ... External interface block, 23 ... Main RAM access arbiter, 25 ... main RAM, 27 ... I / O bus, 40-42 ... memory interface (MIF), 44 ... DMA request arbiter, 45 ... request queue, 46 ... DMA execution unit, 51 ... external bus, 50 ... external memory, 105, 109, 113: Request buffer.

Claims (11)

A multiprocessor capable of accessing an external bus,
A plurality of processor cores each executing arithmetic processing;
An internal memory shared by the plurality of processor cores;
A direct memory access controller that arbitrates direct memory access transfer requests from a part or all of the processor core and performs direct memory access transfer between the internal memory and the external memory connected to the external bus; ,
Arbitration requests for the use of the external bus from part or all of the processor core and the direct memory access controller are made to access any one of the processor core or the direct memory access controller to the external bus. An external memory interface to allow ,
The at least one processor core has a function of issuing the direct memory access transfer request to the direct memory access controller and a function of issuing a request to use the external bus to the external memory interface. multiprocessor you.   The at least one processor core issues a request to use the external bus to the external memory interface when performing random data access to a discrete address, and the data block transfer or virtual memory management mechanism requests The multiprocessor according to claim 1, wherein when performing page swap, the direct memory access transfer request is issued to the direct memory access controller.   The at least one processor core issues a request to use the external bus to the external memory interface when performing random data access to discrete addresses, and directs the data when performing block transfer of data. The multiprocessor according to claim 1, wherein the direct memory access transfer request is issued to a memory access controller. The plurality of processor cores include a central processing unit, a sound processing unit, and a rendering processing unit,
The use request of the external bus that can be issued by the central processing unit is a data access request or an instruction fetch request,
The direct memory access transfer request of the sound processing unit is a wave data transfer request or an envelope data transfer request,
The direct memory access transfer request of the rendering processing unit is a texture pattern data transfer request,
4. The multiprocessor according to claim 1, wherein the direct memory access transfer request of the central processing unit is a data transfer request requested by an application program. The use request of the external bus that can be issued by the central processing unit is the data access request, the instruction fetch request, or a block transfer request including an activation program,
5. The multiprocessor according to claim 4, wherein the direct memory access transfer request of the central processing unit is the data transfer request requested by an application program or a page transfer request when a page miss occurs in virtual memory management. . Arbitration between the wave data transfer request and the envelope data transfer request of the sound processing unit is performed by the sound processing unit,
The multiprocessor according to claim 5, wherein arbitration between the data transfer request and the page transfer request of the central processing unit is performed by the central processing unit. The direct access memory controller is
A plurality of buffers each storing the direct memory access transfer request from the corresponding processor core;
Arbitration means for arbitrating a plurality of the direct memory access transfer requests sent by the plurality of buffers and outputting any one of the direct memory access transfer requests;
A queue that can hold a plurality of the direct memory access transfer requests, and outputs the direct memory access transfer requests output by the arbitration means in the order received;
The multiprocessor according to claim 1, further comprising direct memory access transfer execution means for executing direct memory access transfer in response to the direct memory access transfer request output from the queue. The external memory interface performs arbitration according to a priority table that defines priorities of the processor core and the direct memory access controller that can make a request to use the external bus,
The multiprocessor according to any one of claims 1 to 7, wherein a plurality of the priority order tables are prepared and have different priority orders. The multiprocessor according to claim 8 , wherein the external memory interface performs arbitration by switching the priority table when a predetermined condition is satisfied. The multiprocessor according to claim 9 , wherein the predetermined condition is that a request for use of the external bus from the predetermined processor core or the direct memory access controller is waited for a predetermined time. The external bus interface includes a control register accessible by at least one of the processor cores, and the priority table is switched with an additional condition that a predetermined value is set in the control register by the at least one processor core. The multiprocessor according to claim 10, wherein:

Images