JP4838756B2 - Multiple length arithmetic method, multiple length arithmetic device and program - Google Patents

Description

  The present invention relates to a technique for performing multiple length arithmetic, and more particularly to a technique for performing multiple length arithmetic on large data at high speed.

  The number of data bits that can be handled by a CPU (Central Processing Unit) register is limited to 32 bits or 64 bits. Therefore, when performing a large integer operation exceeding the number of bits that can be handled by the CPU register in a general-purpose CPU, an operation method called a multiple-length operation method is used. In general, in the multiple length arithmetic method, an operation is performed in units of the word length using an array in which a large integer is divided for each bit length (word length) that can be handled by the CPU register.

  Normally, data used for calculation on the CPU is loaded from the main memory into the CPU register, and after calculation is performed on the CPU, the calculation result is stored in the main memory. However, the time for loading data from the main memory to the CPU register is longer than the time required for simple calculation. Therefore, in a general CPU, after copying a part of the data in the main memory to a memory called a cache memory that can be accessed at high speed, the data is loaded from the cache memory to the CPU register. The speed is increased by using the data in the cache memory when the same data is loaded for the second time and thereafter.

In addition, as an approach to perform multiple-precision operations at high speed in an environment where all data exists in the cache memory, by converting an operation with a large operation cost (time required for operation) into a combination of operations with a lower operation cost A method of reducing the overall calculation cost is employed. For example, when multiplying large integers with a general CPU, the operation cost of multiplication is larger than the operation cost of summation, so product operation such as Karatsuba method (Non-patent Document 1) is used for sum operation. Generally, a method of speeding up by converting is adopted.
Takeshi Umeya, “Karatsuba method”, [online], February 14, 2001, [May 8, 2007 search], Internet <URL http://homepage1.nifty.com/~umetani/ims/2001 /20010214001/0.html>

However, in the conventional method, for an integer x _i having a large data size, R = x ₁ · r ₁ +… + x _I · r _I (I is a natural number of 2 or more, i∈ {1, ..., I} and r _i are integers), the computation may not be performed sufficiently fast.
If the data size of x _i is a very large value (for example, about 1 Mbit), each x _i read into the cache memory overflows the cache memory and the main memory is accessed each time the CPU refers to x _i. It becomes a necessary situation. In general, the cache memory is a memory that can be accessed at high speed, but its storage capacity is very small compared to the main memory. Therefore, in an environment where the access speed to the main memory becomes slower than the calculation speed, the access speed to the main memory becomes a bottleneck, not the calculation cost, and the calculation speed decreases.

The present invention has been made in view of these points, with respect to the data size is large integer x _i, fast calculation of _{R = x 1 · r 1 +} ... + x I · r I by multiple length arithmetic The purpose is to provide technology performed in

In the present invention, in order to solve the above problems, the bit dividing portion is, x _i for each (j) the bit length x _i is omega (j) [j∈ {1, ..., J} , J is 2 or more natural numbers, x _i is a bit-splitting process that divides into x _i (J), ..., x _i (1) bit combinations x _i = x _i (J) | ... | x _i (1)] The control unit substitutes 1 for j and 0 for α (1), and the product-sum operation unit obtains α (j) and x _i (j) and r _i read into the cache memory. And a product-sum operation process for calculating T (j) = α (j) + x ₁ (j) · r ₁ +… + x _I (j) · r _I , and after the product-sum operation process, shift portion, the lower omega (j) bits of T (j) and R _j, a shift process and T new bits other than R _j in (j) α (j + 1 ), after the shift process, When the calculation control unit determines whether j = J or not and j ≠ J in the determination step, the calculation control unit performs processing with j + 1 as a new j. The loop process to return to the sum operation process and the above If j = J is determined in the fixed process, the bit combination unit calculates the bit combination R = α (J) | R _J |… | R ₁ of α (J), R _J , ..., R ₁ Then, a multiple length operation of R = x ₁ · r ₁ +... + X _I · r _I is performed by a multiple length operation having a bit combination process of outputting R.

Here, product-sum operation unit handled x _i (j) is the data divided from x _i, for J is a natural number of 2 or more, the bit length of x _i (j) is the bit length of x _i Also short. Therefore, compared to the case where the product-sum operation unit handles x _i , the frequency at which data overflows from the cache memory can be reduced, and the number of accesses to the main memory can be reduced. As a result, the calculation speed can be improved as a whole.

Preferably, in the present invention, the storage capacity of the cache memory is smaller than the total value of the data amount of any one x _{i and} the data amount of all r _i , and is obtained by dividing the x _i. It is larger than the sum of the data amount of one x _i (j) and the data amount of all r _i . In this case, it is possible to reliably reduce the frequency at which data overflows from the cache memory in an environment where calculation is performed with all r _i stored in the cache memory.

Preferably, in the present invention, the product-sum operation process is a process in which the product-sum operation unit performs an operation in units of a predetermined bit length W, and ω (h) is longer than the predetermined bit length W. , Shorter than the bit length of x _i . In this case, since the product-sum operation unit needs to refer to the data of x _i (j) more than once, by reducing the frequency of x _i (j) overflowing from the cache memory according to the present invention, The number of accesses can be reliably reduced.

  In the present invention, preferably, ω (j) is constant for all j. Thereby, the product-sum operation unit can use the same carry processing for each j, and the operation content can be simplified as a whole. As an example of the effect, the program length for configuring the product-sum operation unit can be shortened.

According to another embodiment of the present invention, the product sum calculation process, the product-sum operation unit, x _i (j) a bit length W-a (W> a ≧ 0) divided x _i (j for each, p ) [P∈ {1, ..., P}, P is a natural number greater than 1, x _i (j) is a bit combination x of x _i (j, P), ..., x _i (j, 1) _i (j) = x _i (j, P) | ... | x _i (j, 1)] and r _i is divided into bit lengths W−b (W> b ≧ 0, I ≦ 2 ^{a + b} ) R _i (q) [q∈ {1, ..., Q}, Q is a natural number greater than 1, r _i is the bit combination r _i = r _i (Q), ..., r _i (1) r _i (Q) | ... | r _i (1)], and the operation is performed in units of bit length W, and x ₁ (j, p) · r ₁ (q) + ... + x _I (j, p) ・ r _I (q) is calculated, and T (j) = α (j) + x ₁ (j) ・ r ₁ +… + x _I (j) it is the process of calculating the · r _I.

Here, the bit length of the product x _i (j, p) · r _i (q) of x _i (j, p) of the bit length W−a and r _i (q) of the bit length W−b is always 2・ Below W and I ≦ 2 ^{a + b} , so the bit length of x ₁ (j, p) ・ r ₁ (q) +… + x _I (j, p) ・ r _I (q) must be 2 · W or less. In this case, carry processing with a bit length of 2 · W or more is unnecessary in the process of calculating x ₁ (j, p) · r ₁ (q) +… + x _I (j, p) · r _I (q) Become. As a result, the number of carry processing can be reduced and the calculation speed can be improved. Note that T (j) = α (j) + x ₁ (using the calculation result of x ₁ (j, p) ・ r ₁ (q) +… + x _I (j, p) ・ r _I (q) j) · r ₁ +... + x _I (j) · r _I can be calculated using, for example, a known multiple-length arithmetic method.

Preferably, in the present invention, each x _i (j) divided by the bit dividing unit is x ₁ (1), ..., x _I (1), x ₁ (2), ..., x _I (2), ..., x ₁ (J), ..., x _I (J) is stored in memory so that burst transfer is possible, and x ₁ (1), ..., x _I ( 1), x ₁ (2), ..., x _I (2), ..., x ₁ (J), ..., x _I (J) are sequentially read into the cache memory.

Here, the product-sum operation unit calculates T (j) = α (j) + x ₁ (j) · r ₁ +… + x _I (j) · r _I from j = 1 to j = J. In doing so, x ₁ (1), ..., x _I (1), x ₁ (2), ..., x _I (2), ..., x ₁ (J), ..., x Use x _i (j) in the order of _I (J). X ₁ (1), ..., x _I (1), x ₁ (2), ..., x _I (2), ..., x ₁ (J), ..., x By storing these data in memory so that burst transfer is possible in the order of _I (J), the transfer speed of x _i (j) is improved in an environment where burst transfer is more efficient than random transfer. As a result, the calculation speed is improved.

Further, when I is a natural number of 2 or more, i∈ {1,..., I}, x _i is an integer of 0 or more, and r _i is an integer, R = x ₁ · r ₁ +. + x _I · r _I is a multiple-precision arithmetic method in which H is an integer greater than or equal to 2, h∈ {1, ..., H}, and S (h) is an integer greater than or equal to 2. , S (h) ∈ {1, ..., S (h)} and i (h, s (h)) ∈ {i (h, 1), ..., i (h, S (h) )} ⊂ {1, ..., I} and {i (1,1), ..., i (1, S (1)), ..., i (H, 1), ... , i (H, S (H))} = {1, ..., I}, R (h) = x _{i (h, 1)} · r _{i (h, 1)} +… + x _{i (h , S (h))} · ri _{(h, S (h))} , J (h) is a natural number of 2 or more, and j∈ {1, ..., J (h)} a) The bit division unit converts x _{i (h, s (h))} to x _{i (h, s (h))} (j) each bit length is ω (h, j) (x _{i (h, s (h))} is the bit combination x _{i (h, s (h) )} of x _{i (h, s (h))} (J (h)), ..., x _{i (h, s (h))} (1 _{) )} = x _{i (h, s (h))} (J (h)) |… | x _{i (h, s (h))} (1)] and (b) , J is assigned 1 and α (h, 1) is assigned 0, and (c) h corresponding to r _{i (h, 1)} , ..., r _{i (h, S (} a _h)) key A cache process to load into Sshumemori, (d) product-sum operation unit, α (h, j) and read into the cache memory the _{x i (h, s (h} )) (j) and r _{i (h, s ( h))} and T (h, j) = α (h, j) + x _{i (h, 1)} (j) ・ r _{i (h, 1)} +… + x _{i (h, S (h )) A} product-sum operation process for calculating (j) · r _{i (h, S (h))} , and (e) after the product-sum operation process, the shift unit is subordinate to T (h, j) ω ( (f, j) bits are R (h, j) and T (h, j) other than R (h, j) is a new α (h, j + 1) shift process, and (f) After the shift process, the calculation control unit determines whether or not j = J (h), and (g) if j ≠ J (h) is determined in the determination process, the calculation control unit Is a loop process that returns j + 1 as a new j and returns the process to the product-sum operation process, and (h) when j = J (h) is determined in the determination process, the bit combination unit , J (h)), R (h, J (h)), ..., R (h, 1) bit combination R (h) = α (h, J (h)) | R (h, J (h)) | ... | A bit combination process for calculating R (h, 1), and sequentially for each h And rows, the addition unit, R = R (1) + ... + calculates R (H), multiple length arithmetic method comprising an adding step of outputting the R, is provided.

In this method, R = x ₁ · r ₁ +... + X _I · r _I = R (1) +... + R (H), and R is calculated by applying the present invention every R (h). This method is effective when the value of i is large and all r ₁ ,..., R _I cannot be stored in the cache memory at once.

In this case, the storage capacity of the cache memory is smaller than the total value of the data amount of any one x _{i (h, s (h)) and} the data amount of all r _i , and the x _{i ( h, s (h))} is obtained by dividing one x _{i (h, s (h))} (j) data amount and r _{i (h, 1)} , ..., It is desirable to be larger than the total value of r _{i (h, S (h)) and} the data amount. This is because r _{i (h, 1)} ,..., R _{i (h, S (h))} necessary for the product-sum operation unit to calculate R (h) can be stored in the cache memory at a time.

As described above, according to the present invention, it is possible to perform the calculation of R = x ₁ · r ₁ +... + X _I · r _I at high speed for multiple integers x _i with a large data size. .

The best mode for carrying out the present invention will be described below with reference to the drawings.
[First Embodiment]
First, a first embodiment of the present invention will be described.
<Configuration>
FIG. 1 is a block diagram showing the configuration of the multiple length arithmetic device 1 of this embodiment, and FIG. 2 is a block diagram illustrating the detailed configuration of the register file 50 and the product-sum operation unit 60 of FIG. The arrows in FIGS. 1 and 2 indicate the flow of data, but the description of the flow of data input / output to the arithmetic control unit 90 and part of the flow of data input / output to the register file 50 is omitted. is doing.

As illustrated in FIG. 1, the multiple length arithmetic device 1 of this embodiment includes a main memory 10, a bit division unit 20, a cache memory 30, a register storage unit 40, a register file 50, a product-sum operation unit 60, and a shift unit 70. The bit combination unit 80 and the operation control unit 90 are provided.
The multiple length arithmetic device 1 of this embodiment is configured such that a predetermined program is read into a known computer including a CPU, a RAM (Random Access Memory), a ROM (Compact Disc Read Only Memory), a hard disk device, a bus, and the like. It is constructed by executing the program.

  That is, the main memory 10 corresponds to, for example, a RAM or a hard disk device. The cache memory 30 is a memory that can be accessed at a higher speed than the main memory 10, and corresponds to, for example, a cache memory configured in the CPU. Further, as illustrated in FIG. 2, the register file 50 is configured in, for example, a CPU, and includes a plurality of registers 51 each having a bit length (register length) of storable data of W. Note that W is a calculation processing unit of the product-sum calculation unit 60 and corresponds to, for example, a word length. The value of W can be exemplified by 32 bits and 64 bits, but the present invention is not limited to this.

  In addition, the bit division unit 20, the product-sum operation unit 60, the shift unit 70, the bit combination unit 80, and the operation control unit 90 correspond to, for example, a CPU into which a predetermined program has been read. Here, the product-sum operation unit 60 illustrated in FIG. 2 is a block diagram in the case where multiple multiplication is performed by the Karatsuba method (see Non-Patent Document 1), and a multiplication unit 61 that performs multiplication in units of bit length W. A subtracting unit 62, an adding unit 63, and a carry unit 64 are provided.

<Multiple length calculation method>
Next, the multiple length calculation method of this embodiment will be described.
[Assumption]
In this embodiment, L (L is a natural number of 2 or more) bit-length bit data Xε {0,1} ^L is divided into I (I is a natural number of 2 or more) pieces of an integer x _{i of} 0 or more according to a predetermined procedure. (I∈ {1, ..., I}, x _i is bit data) and given integer r _i (i∈ {1, ..., I}, r _i is bit data), R = x ₁ · r ₁ + ... + x _I · r _I multiple length calculation is performed. Further, it is assumed that integer x _i and integer r _i are stored in the main memory 10 as preprocessing for that purpose.

[Multiple-length operation of R = x ₁ · r ₁ + ... + x _I · r _I ]
FIG. 4 is a flowchart for explaining the multiple length arithmetic method of this embodiment. Hereinafter, description will be made with reference to this figure.

First, the bit dividing section 20 reads the x _i from the main memory 10, by dividing the x _i x _i every (j) is the bit length omega (j), a main memory 10 each x _i (j) (Step S1 / bit division process). FIG. 3A is a conceptual diagram showing how each x _i is divided for each x _i (j). Where j∈ {1, ..., J}, J is a constant of a natural number of 2 or more, and x _i = x _i (J) |… | x _i (1) (x _i (J) | ... | x _i (1) satisfies the relationship of x _i (J), ..., bit combination of x _i (1)). Further, ω (j) is longer than the predetermined bit length W and shorter than the bit length of x _i . In addition, the storage capacity of the cache memory 30 of the present embodiment is smaller than the total value of the data amount of any one x _{i and} the data amount of all r _i , and one obtained by dividing the x _i It is assumed that it is larger than the total value of the data amount of x _i (j) and the data amount of all r _i . Further, as described above, it is desirable for ω (j) to be constant for all j in order to improve the efficiency of computation.

  After step S1, the arithmetic control unit 90 substitutes 1 for j, substitutes 0 for α (1), and stores the result in the register 51 (step S2 / initialization process). The arithmetic control unit 90 controls each process using the values of j and α (j) stored in the register 51.

Next, under the control of the arithmetic control unit 90, all r _i stored in the main memory 10 are read into the cache memory 30 (step S3).

Thereafter, the product-sum operation unit 60 reads α _i (j) from the main memory 10 into the cache memory 30 and uses α _i (j) and x _i (j) and r _i read into the cache memory 30. T (j) = α (j) + x ₁ (j) · r ₁ +… + x _I (j) · r _I is calculated by multiple length operation of word length W, and the operation result T (j) Is output (step S4 / product-sum operation process). That is, the register storage unit 40 divides x _i (j) (FIG. 3A) stored in the cache memory 30 for each bit length W, x _i (j, p) [p∈ {1,. ., P}, P ≧ 2, x _i (j) = x _i (j, P) | ... | x _i (j, 1)] (FIG. 3B) and r stored in the cache memory 30 r _i (q) [q∈ {1,..., Q}, r _i = r _i (Q) | ... | r _i (1) obtained by dividing _i (FIG. 3 (c)) for each bit length W (FIG. 3 (d)) is stored in the register 51 having the register length W, and the product-sum operation unit 60, the shift unit 70, and the bit combination unit 80 perform T (j ) = α (j) + x ₁ (j) · r ₁ +... + x _I (j) · r _I is calculated and output. Hereinafter, a specific example of the product-sum operation process (step S4) will be described.

[Specific example of product-sum operation process (step S4)]
FIG. 5 is a flowchart for explaining a specific example of the product-sum operation process (step S4) of FIG. Hereinafter, description will be made with reference to this figure. In addition, the process using Karatuba method (nonpatent literature 1) is illustrated here. However, the present invention is not limited to this, and step S4 is performed using another known multiple-length arithmetic method (such as a well-known writing algorithm or an algorithm using fast Fourier transform). May be. Further, for the sake of simplicity of explanation, here, a case where the bit length ω (j) of x _i (j) and r _i is 2 words (2 · W) or less is exemplified.

  First, the arithmetic control unit 90 substitutes 1 for i, and stores i in the register 51 (step S4a). Note that the arithmetic control unit 90 controls each process using i stored in the register 51.

Next, the arithmetic control unit 90 determines whether x _i (j) exists in the cache memory 30 (step S4b). Here, if x _i (j) is stored in the cache memory 30, the arithmetic control unit 90 moves the process to step S4d. If x _i (j) is not stored in the cache memory 30, the main memory 10 reads x _i (j) into the cache memory 30 and moves the process to step S4d.

In step S4d, x _i obtained by dividing x _i a (j) for each bit length W (j, p) _{[p∈ {1,2}, x i (} j) = x i (j, 2) | x i ( j, 1)] and r _i (q) [q∈ {1,2}, r _i = r _i (2) | r _i (1)] obtained by dividing r _i for each bit length W, s _i (j, 1) = x _i (j, 1) ・ r _i (1), s _i (j, 3) = x _i (j, 2) ・ r _i (2), s _i (j, 2 ) = {x _i (j, 2) -x _i (j, 1)} ・ (r _i (1) -r _i (2)) + s _i (j, 1) + s _i (j, 3) Calculate (step S4d). Specifically, for example, the register storage unit 40 reads x _i (j, 1) and r _i (1) from the cache memory 30 and stores them in the register 51, and the multiplication unit 61 (FIG. 2) is stored. X _i (j, 1) and r _i (1) are used to calculate s _i (j, 1) = x _i (j, 1) ・ r _i (1), and s _i (j, 1) is calculated Store in the register 51. In addition, for example, the register storage unit 40 reads x _i (j, 2) and r _i (2) from the cache memory 30 and stores them in the register 51, and the multiplication unit 61 stores the stored x _i (j, 2). ) And r _i (2), s _i (j, 3) = x _i (j, 2) · r _i (2) is calculated, and s _i (j, 3) is stored in the register 51. Further, the multiplication unit 61, the subtraction unit 62, and the addition unit 63 use the data stored in the register 51, so that s _i (j, 2) = {x _i (j, 2) −x _i (j, 1)} Calculate (r _i (1) −r _i (2)) + s _i (j, 1) + s _i (j, 3) and store s _i (j, 2) in the register 51. Note that the storage capacity of the cache memory 30 of this embodiment is larger than the total value of the data amount of one x _i (j) and the data amount of all r _i , so that other operations and temporary operations are added to the cache memory 30. If the area can be secured, s _i (j, 1) = x _i (j, 1) ・ r _i (1), s _i (j, 3) = x _i (j, 2) ・ r _i (2 ), s _i (j, 2) = {x _i (j, 2) -x _i (j, 1)} ・ (r _i (1) -r _i (2)) + s _i (j, 1) + x _i (j) and r _i necessary for the calculation of s _i (j, 3) do not overflow from the cache memory 30. In this case, it is not necessary to access the main memory 10 in step S4d (characteristic of this embodiment).

After step S4d, the arithmetic control unit 90 determines whether i stored in the register 51 is I (step S4e). If i = I is not satisfied, i + 1 is set as a new I in the register 51. After storing (step S4f), the process returns to step S4b. On the other hand, if i = I, the adder 63 uses the data in the register 51 to s (j, 1) = s ₁ (j, 1) + ... + s _I (j, 1), s ( j, 2) = s ₁ (j, 2) + ... + s _I (j, 2), s (j, 3) = s ₁ (j, 3) + ... + s _I (j, 3 ) And s (j, 1), s (j, 2), s (j, 3) are stored in the register 51 (step S4g).

  After step S4g, the adding unit 63 calculates s (j, 1) + α (j) using the data in the register 51, and the carry unit 64 calculates the lower W bits of the calculation result as T (j, 1), the other bits are set to β (j, 2), and they are stored in the register 51 (step S4h). Next, the adding unit 63 calculates s (j, 2) + β (j, 2) using the data in the register 51, and the carry unit 64 calculates the lower W bits of the calculation result as T (j, 2), the other bits are set to β (j, 3), and they are stored in the register 51 (step S4i). Next, the adder 63 calculates s (j, 3) + β (j, 3) using the data in the register 51, and stores the calculation result as T (j, 3) in the register 51 (step S4j).

After that, the bit combination unit 80 stores the bit combination T (j) = T (j, 3) | T of T (j, 3), T (j, 2), T (j, 1) stored in the register 51. (j, 2) | T (j, 1) is output (end of description of step S4k / [specific example of product-sum operation process (step S4)]).
Product-sum operation process (step S4) after the shift unit 70, T lower (j) omega (j) bits as R _j, T new bits other than R _j in (j) α (j + 1 ) These are output (step S5 / shift process).

After the shift process (step S5), the arithmetic control unit 90 refers to j stored in the register 51 and determines whether j = J (step S6 / determination process). If it is determined that j ≠ J, the arithmetic control unit 90 stores j + 1 as a new j in the register 51 and returns the process to the product-sum operation process (step S4) (step S4). S7 / loop process). On the other hand, the determination process when it is determined that j = J in (step S6), and the bit coupling portion _{80, α (J), R J} , ..., bit combination of _{R 1 R = α (J)} | R J | ... | calculates the R _1, and outputs the R (step S8 / bit binding process).

  As described above, in this embodiment, if another calculation or a temporary area can be secured in the cache memory 30, it is not necessary to access the main memory 10 in step S4d, so that the calculation speed is improved.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.
The present embodiment is a modification of the first embodiment. In the product-sum operation process (step S4), the product-sum operation unit 60 sets x _i (j) to a bit length W−a (W> a ≧ 0). X _i (j, p) [p∈ {1, ..., P}, P is a natural number greater than 1, x _i (j) is x _i (j, P), ..., x _i (j, 1) bit combination x _i (j) = x _i (j, P) | ... | x _i (j, 1)], and r _i is a bit length W−b (W> b ≧ 0, R _i (q) [q∈ {1, ..., Q}, Q is a natural number of 1 or more, r _i is r _i (Q), ..., r divided every I ≦ 2 ^{a + b} ) _i (1) bit combination r _i = r _i (Q) | ... | r _i (1)], and the operation is performed in units of bit length W, and x ₁ (j, p) ・ r ₁ (q) +… + x _I (j, p) ・ r _I (q) is calculated and T (j) = α (j) + x ₁ (j) ・Only the point of calculating r ₁ +... + x _I (j) · r _I is different from the first embodiment. Only this difference will be described below.

<Example 1>
The first embodiment of the present embodiment is an example in which P = Q = 2 and b> a (FIGS. 6A and 6B), and multiplication is performed in units of bit length W by a writing algorithm.
FIG. 7 is a flowchart for explaining the processing in step S4 in Example 1 of the second embodiment. Hereinafter, the processing in step S4 in the second embodiment will be described with reference to FIG.

Since Steps S4a to 4c of Example 1 are the same as those of the first embodiment, description thereof is omitted. In the first embodiment, after step S4b or S4c, loaded into the cache memory 30, x was divided x _i a (j) for each bit length Wa _i (j, p) [p∈ {1,2}, _{x i (j) = x i} (j, 2) | x i (j, 1) ] and, r _i (q) [q∈ {1 obtained by dividing the r _i for each bit length Wb (b> a), 2}, r _i = r _i (2) | r _i (1)] and s _i (j, 1) = x _i (j, 1) ・ r _i (1), s _i (j, 2 ) = x _i (j, 1) ・ r _i (2), s _i (j, 3) = x _i (j, 2) ・ r _i (1), s _i (j, 4) = x _i (j , 2) · r _i (2) is calculated (step S4m).

Specifically, for example, the register storage unit 40 reads x _i (j, 1) and r _i (1) from the cache memory 30 and stores them in the register 51, and the multiplication unit 61 (FIG. 2) is stored. X _i (j, 1) and r _i (1) are used to calculate s _i (j, 1) = x _i (j, 1) ・ r _i (1), and s _i (j, 1) is calculated Store in the register 51. In addition, for example, the register storage unit 40 reads x _i (j, 2) and r _i (2) from the cache memory 30 and stores them in the register 51, and the multiplication unit 61 stores the stored x _i (j, 2). ) And r _i (2), s _i (j, 3) = x _i (j, 2) · r _i (2) is calculated, and s _i (j, 3) is stored in the register 51. Further, the multiplication unit 61 uses the data stored in the register 51 to generate s _i (j, 2) = x _i (j, 1) · r _i (2) and s _i (j, 3) = x _i ( j, 2) · r _i (1) is calculated, and s _i (j, 2) and s _i (j, 3) are stored in the register 51. Since the bit length of x _i (j, p) is Wa and the bit length of r _i (q) is Wb, s _i (j, 1), s _i (j, 2), s _i ( j, 3) and s _i (j, 4) are all bit strings of 2 · W− (a + b) [= (Wa) + (Wb)] bits.

After step S4m, the arithmetic control unit 90 determines whether i stored in the register 51 is I (step S4e). If i = I is not satisfied, i + 1 is set as a new I in the register 51. After storing (step S4f), the process returns to step S4b. On the other hand, if i = I, the adder 63 uses the data in the register 51 to s (j, 1) = s ₁ (j, 1) + ... + s _I (j, 1), s ( j, 2) = s ₁ (j, 2) + ... + s _I (j, 2), s (j, 3) = s ₁ (j, 3) + ... + s _I (j, 3 ), s (j, 4) = s ₁ (j, 4) + ... + s _I (j, 4) is calculated and s (j, 1), s (j, 2), s (j, 3), s (j, 4) is stored in the register 51 (step S4n). In this embodiment, s _i (j, 1), s _i (j, 2), s _i (j, 3), and s _i (j, 4) are all 2 · W− (a + b) [= (Wa) + (Wb)] bit sequence and satisfy I ≦ 2 ^{a + b} , so s (j, 1), s (j, 2), s (j, 3), s (j, Each of 4) is a bit string of 2 · W bits or less. That is, carry processing of 2 words or more is unnecessary in the calculation of step S4n (characteristic of this embodiment).

  After step S4n, the adding unit 63 calculates s (j, 1) + α (j) using the data in the register 51, and the carry unit 64 calculates the lower Wb bit of the operation result as T (j, 1), the other bits are set to β (j, 2), and they are stored in the register 51 (step S4p). Next, the adding unit 63 calculates s (j, 2) + β (j, 2) using the data in the register 51, and the carry unit 64 uses the lower-order ba [= (Wa) − (Wb)] The bits are set to T (j, 2), and the other bits are set to β (j, 3) (step S4q). Next, the adding unit 63 calculates s (j, 3) + β (j, 3) using the data in the register 51, and the carry unit 64 calculates the lower order (Wb) [= (Wa ) + (Wb)-(Wa)] bits are set to T (j, 3), and other bits are set to β (j, 4) (step S4r). Next, the adder 63 calculates s (j, 4) + β (j, 4) using the data in the register 51, and stores the calculation result as T (j, 4) in the register 51 (step S1). S4s).

After that, the bit combination unit 80 generates a bit combination T (j) = T (j, 4), T (j, 3), T (j, 2), T (j, 1) stored in the register 51. T (j, 4) | T (j, 3) | T (j, 2) | T (j, 1) is output (step S4t).
<Example 2>
Example 2 of the present embodiment is an example in which P = Q = 2 and b = a (FIGS. 6C and 6D), and multiplication is performed in units of bit length W by the Karatsuba method (Non-patent Document 1). .
FIG. 8 is a flowchart for explaining the processing in step S4 in Example 2 of the second embodiment. Hereinafter, the processing in step S4 in the second embodiment will be described with reference to FIG. The only difference between the first embodiment and the second embodiment is that step S4d (FIG. 5) is replaced with step S4t (FIG. 8).

In step S4t of this embodiment, x _i (j, p) [pε {1,2}, x _i (j) = x _i (j, 2)) obtained by dividing x _i (j) for each bit length Wa. | x _i (j, 1) and], r _i obtained by dividing the r _i for each bit length Wb (q) _{[q∈ {1,2}, r i =} r i (2) | r i (1) ] , S _i (j, 1) = x _i (j, 1) ・ r _i (1), s _i (j, 3) = x _i (j, 2) ・ r _i (2), s _i (j, 2) = {x _i (j, 2) -x _i (j, 1)} ・ (r _i (1) -r _i (2)) + s _i (j, 1) + s _i (j , 3) is calculated (step S4t). Here, since the bit length of x _i (j, p) is Wa and the bit length of r _i (q) is Wb, s _i (j, 1), s _i (j, 2), s _i (j, 3) is a bit string of 2 · W− (a + b) [= (Wa) + (Wb)] bits. In order to satisfy I ≦ 2 ^{a + b} , s (j, 1), s (j, 2), and s (j, 3) calculated in step S4g are all 2 · W bits or less. It becomes a bit string. That is, carry processing of 2 words or more is unnecessary in the calculation of step S4g (characteristic of this embodiment).

As described above, in this embodiment, x ₁ (j, p) · r ₁ (q) + ... + x _I (j, p) · r _I (q) are all bit strings of 2 · W bits or less. . Therefore, it is not necessary to carry more than 2 words in the calculation of x ₁ (j, p) · r ₁ (q) +… + x _I (j, p) · r _I (q), reducing the operation cost. be able to.

[Third Embodiment]
This embodiment is a modification of the first and second embodiments. The difference from the first and second embodiments is that each x _i (j) divided by the bit dividing unit 20 is x ₁ (1),..., X _I (1), x ₁ (2). , ..., x _I (2), ..., x ₁ (J), ..., x _I (J) are stored in the main memory 10 so that burst transfer is possible, and x ₁ (1), ..., x _I (1), x ₁ (2), ..., x _I (2), ..., x ₁ (J), ..., x _I (J) It is a point read into the memory 30.

FIG. 9 shows x ₁ (1), ..., x _I (1), x ₁ (2), ..., x _I (2), ..., x ₁ ( It is the conceptual diagram which illustrated J), ..., x _I (J). As illustrated in FIG. 9, in this embodiment, x ₁ (1), ..., x _I (1), x ₁ (2), ..., x _I (2), ..., x ₁ Each x _i (j) is stored in the main memory 10 in the order of (J),..., X _I (J). Thus, only by specifying the head address of x ₁ (1) stored in the main memory 10, x ₁ (1), ..., x _I (1), x ₁ (2), ..., _{x I (2), ...,} x 1 (J), ..., can be burst transfer x _i a (j) sequentially into the cache memory 30 in the order of x _I (J). In step S4 of FIG. 4, x ₁ (1), ..., x _I (1), x ₁ (2), ..., x _I (2), ..., x ₁ (J) ,. .., x _I for x _i (j) is required in the order (J), each of x _i and _{(j) x 1 (1)} , ..., x I (1), x 1 (2) , ..., x _I (2), ..., x ₁ (J), ..., x _I (J) are preferably stored in the main memory 10 so as to be capable of burst transfer. .

[Fourth Embodiment]
The present embodiment is a modification of the first and second embodiments, and R = x ₁ · r ₁ + ... + x _I · r _I = R (1) + ... + R (H) and R (h) The method of the present invention is applied every time (h∈ {1,..., H}, H is an integer constant equal to or greater than 2) (feature of this embodiment). In this embodiment, the number of accesses to the main memory 10 can be reduced when the value of I is large and all r ₁ ,..., R _I cannot be stored in the cache memory 30 at the same time. That is, the storage capacity of the cache memory 30 is smaller than the total value of the data amount of any one of x _{i (h, s (h)) and} the data amount of all r _i , and the x _{i (h, s (h))} is obtained by dividing the data amount of one x _{i (h, s (h))} (j) and r _{i (h, 1)} , ..., r _{i ( This} is a particularly effective method when it is larger than the total value of the data amount of _{h, S (h))} . Where S (h) is an integer greater than or equal to 2, s (h) ∈ {1, ..., S (h)}, and i (h, s (h)) ∈ {i (h, 1 ), ..., i (h, S (h))} ⊂ {1, ..., I} and {i (1,1), ..., i (1, S (1)) , ..., i (H, 1), ..., i (H, S (H))} = {1, ..., I} and R (h) = x _{i (h, 1 )} · R _{i (h, 1)} +... + X _{i (h, S (h))} · r _{i (h, S (h))} .

Below, it demonstrates centering on difference with 1st, 2nd embodiment, and abbreviate | omits description about the matter which is common in 1st, 2nd embodiment.
<Configuration>
FIG. 10 is a block diagram showing a configuration of the multiple length arithmetic apparatus 100 of the present embodiment. The arrows in FIG. 10 indicate the flow of data, but the description of the flow of data input / output to the arithmetic control unit 90 and part of the flow of data input / output to the register file 50 is omitted. Yes.

  As illustrated in FIG. 10, the multiple length arithmetic device 100 according to this embodiment includes a main memory 10, a bit division unit 20, a cache memory 30, a register storage unit 40, a register file 50, a product-sum operation unit 60, and a shift unit 70. , A bit combination unit 80, an operation control unit 90, and an addition unit 110. 10 that have the same processing functions as those in FIG. 1 are denoted by the same reference numerals as those in FIG.

<Multiple length calculation method>
Next, the multiple length calculation method of this embodiment will be described.
[Assumption]
This is the same as described in the first embodiment.
[Multiple-length operation of R = x ₁ · r ₁ + ... + x _I · r _I ]
FIG. 11 is a flowchart for explaining the multiple length arithmetic method of this embodiment. Hereinafter, description will be made with reference to this figure.
First, the arithmetic control unit 90 substitutes 1 for h, and stores h in the register 51 of the register file 50 (step S11). The arithmetic control unit 90 controls each process using h stored in the register 51.

Next, the bit dividing unit 20 reads x _{i (h, s (h))} from the main memory 10 and sets x _{i (h, s (h))} to x with each bit length being ω (h, j). Each _{i (h, s (h))} (j) is divided and each x _{i (h, s (h))} (j) is stored in the main memory 10 (step S12 / bit division process). X _{i (h, s (h))} is the bit combination x _i of x _{i (h, s (h))} (J (h)), ..., x _{i (h, s (h))} (1) _{(h, s (h))} = x _{i (h, s (h))} (J (h)) |… | x _{i (h, s (h))} (1) where J (h) is 2 These are natural number constants, j∈ {1, ..., J (h)}.
Next, the arithmetic control unit 90 substitutes 1 for j, substitutes 0 for α (h, 1), and stores them in the register 51 of the register file 50 (step S13 / initialization process). The arithmetic control unit 90 controls each process using j and α (h, 1) stored in the register 51. Also, under the control of the arithmetic control unit 90, r _{i (h, 1)} ,..., R _{i (h, S (h)) corresponding} to _h are read into the cache memory (step S14 / cache process) ).

Thereafter, the product-sum operation unit 60 sequentially reads x _{i (h, s (h))} (j) into the cache memory 30, while α (h, j) and x _{i (h, s (h))} (j ) And r _{i (h, s (h))} and T (h, j) = α (h, j) + x _{i (h, 1)} (j) · r _{i (h, 1)} +… + x _{i (h, S (h))} (j) · r _{i (h, S (h))} is calculated and T (h, j) is output (step S15 / product-sum operation process). After the product-sum operation process (step S15), the shift unit 70 sets the lower ω (h, j) bits of T (h, j) to R (h, j) and R (h, j) of T (h, j). Bits other than j) are set as new α (h, j + 1), and R (h, j) and α (h, j + 1) are output (step S16 / shift process).

  After the shifting process (step S16), the arithmetic control unit 90 refers to j stored in the register 51 of the register file 50 and determines whether j = J (h) (step S17 / determination process). . If it is determined that j ≠ J (h), the arithmetic control unit 90 stores j in the register 51 with j + 1 as a new j, and returns the process to step S15 (step S18 / loop process). . On the other hand, if it is determined that j = J (h) in the determination process (step S17), the bit combination unit 80 determines that α (h, J (h)), R (h, J (h)),. , R (h, 1) bit combination R (h) = α (h, J (h)) | R (h, J (h)) | ... | R (h, 1) ) Is output (step S19 / bit combination process).

  Next, the arithmetic control unit 90 refers to the register 51 to determine whether h = H, and if not h = H, stores h + 1 as a new h in the register 51 (step S21). ), The process returns to step S12. On the other hand, if h = H, the adding unit 110 calculates R = R (1) +... + R (H) and outputs R (step S21 / addition process).

[Fifth Embodiment]
In this embodiment, the third embodiment is applied to the fourth embodiment. That is, in this embodiment, in the order from h = 1 to h = H, each x _{i (h, s (h))} (j) for each _h is x _{i (h, 1)} (1),. .., x _{i (h, S (h))} (1), x _{i (h, 1)} (2), ..., x _{i (h, S (h))} (2), ..., x _{i (h, 1)} (J (h)), ..., x _{i (h, S (h))} (J (h)) are stored in the main memory 10 so as to be capable of burst transfer, and x _{i (h, 1)} (1), ..., x _{i (h, S (h))} (1), x _{i (h, 1)} (2), ..., x _{i (h, S (h ))} (2), ..., x _{i (h, 1)} (J (h)), ..., x _{i (h, S (h))} (J (h)) 30 is read (feature of this embodiment).

12 (a) and 12 (b) show x _{i (h, 1)} (1), ..., x _{i (h, S (h))} (1), x _{i (h} ) stored in the main memory 10. _{, 1)} (2), ..., x _{i (h, S (h))} (2), ..., x _{i (h, 1)} (J (h)), ..., x _{i (} It is the conceptual diagram which illustrated _{h, S (h))} (J (h)).

As illustrated in FIG. 12A, each x _{i (h, s (h))} (j) is represented by x _{i (h, 1)} (1), ..., x _{i (h, S (h ))} (1), x _{i (h, 1)} (2), ..., x _{i (h, S (h))} (2), ..., x _{i (h, 1)} (J (h )), ..., x _{i (h, S (h))} (J (h)) are stored in the main memory 10 so as to be capable of burst transfer. Where x _{i (h, 1)} (1), ..., x _{i (h, S (h))} (1), x _{i (h, 1)} (2), ..., x _{i ( h, S (h))} (2), ..., x _{i (h, 1)} (J (h)), ..., x _{i (h, S (h))} (J (h)) The stored area of the main memory 10 is referred to as a block [h]. Also, the start address of block [h] is expressed as AS (h), and the end address is expressed as AE (h).

As shown in FIG. 12B, each block [h] is stored in the main memory 10 so as to be capable of burst transfer in the order of block [1], block [2],..., Block [H]. The Thus, each x _{i (h, s (h))} (j) becomes x _{i (1,1)} (1), ..., x _{i (1, S (1))} (1), x _{i (1,1)} (2), ..., x _{i (1, S (1))} (2), ..., x _{i (1,1)} (J (1)), ..., x _{i (1, S (1))} (J (1)), ..., x _{i (H, 1)} (1), ..., x _{i (H, S (H))} (1), x _{i (H, 1)} (2), ..., x _{i (H, S (H))} (2), ..., x _{i (H, 1)} (J (H)), ..., It is stored in the main memory 10 so as to be capable of burst transfer in the order of x _{i (H, S (H))} (J (H)). As a _result, x _{i (1,1)} only to specify the start address AS (h) (1), from the main memory 10 in the cache memory _{30 x i (1,1) (1} ), ..., x _{i (1, S (1))} (1), x _{i (1,1)} (2), ..., x _{i (1, S (1))} (2), ..., x _{i (1 , 1)} (J (1)), ..., x _{i (1, S (1))} (J (1)), ..., x _{i (H, 1)} (1), ..., x _{i (H, S (H))} (1), x _{i (H, 1)} (2), ..., x _{i (H, S (H))} (2), ..., x _{i (} Burst transfer is possible in the order of _{H, 1)} (J (H)), ..., xi _{(H, S (H))} (J (H)).

In step S15 of FIG. 11, x _{i (1,1)} (1), ..., x _{i (1, S (1))} (1), x _{i (1,1)} (2), ... , x _{i (1, S (1))} (2), ..., x _{i (1,1)} (J (1)), ..., x _{i (1, S (1))} (J ( 1)), ..., x _{i (H, 1)} (1), ..., x _{i (H, S (H))} (1), x _{i (H, 1)} (2), ... ., x _{i (H, S (H))} (2), ..., x _{i (H, 1)} (J (H)), ..., x _{i (H, S (H))} (J Since x _{i (h, s (h))} (j) is required in the order of (H)), the configuration of storing in the main memory 10 so that burst transfer is possible in this order is preferable for the present invention.

〔Experimental result〕
As described above, in each of the above-described embodiments, x _i that exceeds the storage capacity (cache size) of the cache memory 30 in total with other operations and the temporary area in the middle of the operation n, and a size larger than the cache size. It is possible to improve the calculation speed of the multiple length calculation of R = x ₁ · r ₁ + ... + x _I · r _I for small r _i .

  FIG. 13 shows the experimental results to show this effect. In FIG. 13, in Athlon64x2 2Ghz, the operation of “Tetsu Oda, Go Yamamoto, Kazuro Aoki,“ High-speed data verification ”, SCIS, Jan. 23-26 2007 (“ Reference 1 ”)) without applying the present invention. A comparison of the calculation speed between the case where the calculation is performed (conventional method) and the case where the calculation according to Reference 1 is performed by applying the first embodiment in Athlon64x2 2Ghz (first embodiment) is shown. As shown in FIG. 13, the computation speed in the conventional method is about 12.5 (Gbps), whereas the computation speed in the first embodiment is about 8 (Gbps).

[Modifications, etc.]
The present invention is not limited to the embodiment described above. For example, you may implement this invention combining the structure of each embodiment suitably. In addition, the various processes described above are not only executed in time series according to the description, but may be executed in parallel or individually according to the processing capability of the apparatus that executes the processes or as necessary. Needless to say, other modifications are possible without departing from the spirit of the present invention.

  Further, when the above-described configuration is realized by a computer, processing contents of functions that each device should have are described by a program. The processing functions are realized on the computer by executing the program on the computer.

  The program describing the processing contents can be recorded on a computer-readable recording medium. The computer-readable recording medium may be any medium such as a magnetic recording device, an optical disk, a magneto-optical recording medium, or a semiconductor memory. Specifically, for example, the magnetic recording device may be a hard disk device or a flexible Discs, magnetic tapes, etc. as optical disks, DVD (Digital Versatile Disc), DVD-RAM (Random Access Memory), CD-ROM (Compact Disc Read Only Memory), CD-R (Recordable) / RW (ReWritable), etc. As the magneto-optical recording medium, MO (Magneto-Optical disc) or the like can be used, and as the semiconductor memory, EEP-ROM (Electronically Erasable and Programmable-Read Only Memory) or the like can be used.

  The program is distributed by selling, transferring, or lending a portable recording medium such as a DVD or CD-ROM in which the program is recorded. Furthermore, the program may be distributed by storing the program in a storage device of the server computer and transferring the program from the server computer to another computer via a network.

  A computer that executes such a program first stores, for example, a program recorded on a portable recording medium or a program transferred from a server computer in its own storage device. When executing the process, the computer reads a program stored in its own recording medium and executes a process according to the read program. As another execution form of the program, the computer may directly read the program from a portable recording medium and execute processing according to the program, and the program is transferred from the server computer to the computer. Each time, the processing according to the received program may be executed sequentially. Also, the program is not transferred from the server computer to the computer, and the above-described processing is executed by a so-called ASP (Application Service Provider) type service that realizes the processing function only by the execution instruction and result acquisition. It is good. Note that the program in this embodiment includes information that is used for processing by an electronic computer and that conforms to the program (data that is not a direct command to the computer but has a property that defines the processing of the computer).

  In this embodiment, the present apparatus is configured by executing a predetermined program on a computer. However, at least a part of these processing contents may be realized by hardware.

   As an industrial application field of the present invention, for example, the data verification processing of Reference 1 can be exemplified.

FIG. 1 is a block diagram illustrating a configuration of a multiple length arithmetic apparatus according to the first embodiment. FIG. 2 is a block diagram illustrating a detailed configuration of the register file and the product-sum operation unit of FIG. FIG. 3 is a conceptual diagram for explaining the data structure. FIG. 4 is a flowchart for explaining the multiple length arithmetic method according to the first embodiment. FIG. 5 is a flowchart for explaining a specific example of the product-sum operation process (step S4) of FIG. FIG. 6 is a conceptual diagram for explaining the data configuration. FIG. 7 is a flowchart for explaining the processing in step S4 in Example 1 of the second embodiment. FIG. 8 is a flowchart for explaining the processing in step S4 in Example 2 of the second embodiment. FIG. 9 shows x ₁ (1), ..., x _I (1), x ₁ (2), ..., x _I (2), ..., x ₁ (J ), ..., x _I (J). FIG. 10 is a block diagram showing the configuration of the multiple length arithmetic device of the fourth embodiment. FIG. 11 is a flowchart for explaining the multiple length arithmetic method of the fourth embodiment. FIG. 12 shows x _{i (h, 1)} (1), ..., x _{i (h, S (h))} (1), x _{i (h, 1)} (2), stored in the main memory. ..., x _{i (h, S (h))} (2), ..., x _{i (h, 1)} (J (h)), ..., x _{i (h, S (h))} It is the conceptual diagram which illustrated (J (h)). FIG. 13 is a diagram showing experimental results to show the effect of this embodiment.

Explanation of symbols

1,100 multiple length arithmetic unit

Claims (10)

R = x ₁ · r ₁ +… + x where I is a natural number of 2 or more, i∈ {1, ..., I}, x _i is an integer of 0 or more, and r _i is an integer _A multiple length arithmetic method for calculating _I · r _I ,
The bit dividing unit is configured such that x _i is a natural number greater than or equal to 2 for each x _i (j) where each bit length is ω (j), and x _i is x _i ( J), ..., x _i (1) bit combination x _i = x _i (J) | ... | x _i (1)]
An initialization process in which the arithmetic control unit substitutes 1 for j and 0 for α (1),
The product-sum operation unit uses α (j) and x _i (j) and r _i read into the cache memory, and T (j) = α (j) + x ₁ (j) · r ₁ +… + a sum-of-products operation for calculating x _I (j) · r _I ;
After the product-sum operation process, a shift process of shifting part, the lower omega (j) bits of T (j) and R _j, and T new bits other than R _j in (j) α (j + 1 ) When,
After the shifting process, the calculation control unit determines whether or not j = J,
When it is determined that j ≠ J in the determination process, the calculation control unit sets a new j as j + 1 and a loop process that returns the process to the product-sum calculation process;
If it is determined that j = J above determination process, the bit coupling _{portion, α (J), R J} , ..., bit combination of _{R 1 R = α (J)} | a R ₁ | R _J | ... A bit combination process to calculate and output R;
A multiple length arithmetic method characterized by comprising: The multiple length arithmetic method according to claim 1,
The storage capacity of the cache memory is
Smaller than the sum of the amount of data amount and all r _i of any one of the x _i, data volume and all r _i of the one obtained by dividing the x _i x _i (j) Larger than the total amount of data with
A multiple length arithmetic method characterized by the above. The multiple length arithmetic method according to claim 1 or 2,
The product-sum operation process is a process in which the product-sum operation unit performs an operation in units of a predetermined bit length W.
ω (j) is longer than the predetermined bit length W and shorter than the bit length of x _i ,
A multiple length arithmetic method characterized by the above. The multiple length arithmetic method according to claim 1,
ω (j) is constant for all j,
A multiple length arithmetic method characterized by the above. The multiple length arithmetic method according to claim 1,
The product-sum operation process is
The product-sum operation unit divides x _i (j) into bit lengths W−a (W> a ≧ 0), where x _i (j, p) [p∈ {1, ..., P}, P Is a natural number greater than 1, x _i (j) is the bit combination of x _i (j, P), ..., x _i (j, 1) x _i (j) = x _i (j, P) |… | x _i (j, 1)] and r _i (q) [q∈ {1, ...] obtained by dividing r _i into bit lengths W−b (W> b ≧ 0, I ≦ 2 ^{a + b} ). , Q}, Q is a natural number of 1 or more, r _i is a bit combination of r _i (Q), ..., r _i (1) r _i = r _i (Q) |… | r _i (1)] To calculate x ₁ (j, p) · r ₁ (q) +… + x _I (j, p) · r _I (q) for one or more sets of p and q Is a process of calculating T (j) = α (j) + x ₁ (j) · r ₁ + ... + x _I (j) · r _I using the calculation result,
A multiple length arithmetic method characterized by the above. The multiple length arithmetic method according to claim 1,
Each x _i (j) divided by the bit dividing unit is
x ₁ (1), ..., x _I (1), x ₁ (2), ..., x _I (2), ..., x ₁ (J), ..., x _I (J ) Stored in memory so that burst transfer is possible in the order of x ₁ (1), ..., x _I (1), x ₁ (2), ..., x _I (2), ..., x ₁ (J), ..., x _I Read sequentially into cache memory in the order of (J).
A multiple length arithmetic method characterized by the above. R = x ₁ · r ₁ +… + x where I is a natural number of 2 or more, i∈ {1, ..., I}, x _i is an integer of 0 or more, and r _i is an integer _A multiple length arithmetic method for calculating _I · r _I ,
Let H be an integer greater than or equal to 2, h∈ {1, ..., H}, S (h) be an integer greater than or equal to 2, and s (h) ∈ {1, ..., S (h)} , I (h, s (h)) ∈ {i (h, 1), ..., i (h, S (h))} ⊂ {1, ..., I} and {i (1, 1), ..., i (1, S (1)), ..., i (H, 1), ..., i (H, S (H))} = {1, ..., I} and R (h) = x _{i (h, 1)} · r _{i (h, 1)} +… + x _{i (h, S (h))} · r _{i (h, S (h))} When J (h) is a natural number of 2 or more and j∈ {1, ..., J (h)},
(a) The bit division unit converts x _{i (h, s (h))} to each x _{i (h, s (h))} (j) whose bit length is ω (h, j) (x _{i (h , s (h))} is x _{i (h, s (h))} (J (h)), ..., x _{i (h, s (h))} (1) bit combination x _{i (h, s (h ))} = x _{i (h, s (h))} (J (h)) |… | x _{i (h, s (h))} (1)]
(b) an initialization process in which the arithmetic control unit substitutes 1 for j and 0 for α (h, 1);
(c) a cache process for reading r _{i (h, 1)} , ..., r _{i (h, S (h)) corresponding} to _h into cache memory;
(d) The product-sum operation unit uses α (h, j) and x _{i (h, s (h))} (j) and r _{i (h, s (h))} read into the cache memory, T (h, j) = α (h, j) + x _{i (h, 1)} (j) ・ r _{i (h, 1)} +… + x _{i (h, S (h))} (j) ・ r a product-sum operation process for calculating _{i (h, S (h))} ;
(e) After the above product-sum operation process, the shift unit sets R (h, j) as the lower ω (h, j) bits of T (h, j) and R (h, j) of T (h, j) ) And a shift process that sets bits other than) as a new α (h, j + 1),
(f) After the shifting process, the calculation control unit determines whether j = J (h),
(g) When it is determined that j ≠ J (h) in the determination process, the calculation control unit sets a new j to j + 1 and returns the process to the product-sum calculation process.
(h) If it is determined that j = J (h) in the above determination process, the bit combination part is α (h, J (h)), R (h, J (h)), ..., R ( bit combination process of calculating bit combination R (h) = α (h, J (h)) | R (h, J (h)) | ... | R (h, 1) of h, 1);
Sequentially for each h,
An adding unit calculates R = R (1) +... + R (H) and outputs R; and
A multiple length arithmetic method characterized by comprising: The multiple length arithmetic method according to claim 7,
The storage capacity of the cache memory is
It is smaller than the sum of the data amount of any one x _{i (h, s (h)) and} the data amount of all r _i , and is obtained by dividing x _{i (h, s (h)).} A single x _{i (h, s (h))} (j) data amount and r _{i (h, 1)} , ..., r _{i (h, S (h))} data amount corresponding to _h Greater than the sum of
A multiple length arithmetic method characterized by the above. R = x ₁ · r ₁ +… + x where I is a natural number of 2 or more, i∈ {1, ..., I}, x _i is an integer of 0 or more, and r _i is an integer _A multiple length arithmetic unit that performs the operation of _I · r _I ,
x _i for each (j) the bit length x _i is omega (j) [j∈ {1, ..., J} , J is a natural number of 2 or more, x _i is x _i (J), ..., x _i (1) bit combination x _i = x _i (J) | ... | x _i (1)],
Using α (j) and x _i (j) and r _i read into the cache memory, T (j) = α (j) + x ₁ (j) · r ₁ +… + x _I (j) · a sum-of-products operation unit that performs r _I operation;
Lower omega (j) bits of T (j) and R _j, a shift unit for a T new bits other than R _j in (j) α (j + 1 ),
An arithmetic control unit that executes processing of the product-sum operation unit and the shift unit up to j = J while increasing j by 1 from j = 1 and j = 0 as initial values,
Bit combination R of α (J), R _J , ..., R ₁ R = α (J) | R _J | ... | R ₁ and a bit combination unit for outputting R;
A multiple length arithmetic device characterized by comprising:   The program for making a computer perform each process of the multiple length arithmetic method in any one of Claim 1 to 8.

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