JP4831873B2 - Self-luminous device and manufacturing method thereof - Google Patents

Description

【００６３】
【化２】

【００６４】
また、特開平１０−９２５７６号公報に記載された分子式のポリフェニルビニルを用いることもできる。分子式は以下のようになる。
【００６５】
【化３】

【００６６】
【化４】

【００６７】
また、ＰＶＫ系有機ＥＬ材料としては以下のような分子式がある。
【００６８】
【化５】

【００６９】
高分子系有機ＥＬ材料はポリマーの状態で溶媒に溶かして塗布することもできるし、モノマーの状態で溶媒に溶かして塗布した後に重合することもできる。モノマーの状態で塗布した場合、まずポリマー前駆体が形成され、真空中で加熱することにより重合してポリマーになる。
【００７０】
具体的なＥＬ層としては、赤色に発光するＥＬ層にはシアノポリフェニレンビニレン、緑色に発光するＥＬ層にはポリフェニレンビニレン、青色に発光するＥＬ層にはポリフェニレンビニレン若しくはポリアルキルフェニレンを用いれば良い。膜厚は３０〜１５０ｎｍ（好ましくは４０〜１００ｎｍ）とすれば良い。
【００７１】
但し、以上の例は本発明のＥＬ層として用いることのできる有機ＥＬ材料の一例であって、これに限定する必要はない。
【００７２】
また、有機ＥＬ材料を溶解させる代表的な溶媒としてはトルエン、キシレン、クロロベンゼン、ジクロロベンゼン、アニソール、クロロフォルム、ジクロロメタン、γブチルラクトン、ブチルセルソルブ、シクロヘキサン、ＮＭＰ（Ｎ−メチル−２−ピロリドン）、シクロヘキサノン、ジオキサンまたは、ＴＨＦ（テトラヒドロフラン）といった溶媒が挙げられる。
【００７３】
さらに、ＥＬ層４２を形成する際、ＥＬ層は水分や酸素の存在によって容易に劣化してしまうため、処理雰囲気は水分や酸素の少ない雰囲気とし、窒素やアルゴンといった不活性ガス中で行うことが望ましい。さらに処理雰囲気としては、ＥＬ材料を溶解させた溶媒の蒸発速度を制御できることから、用いた溶媒雰囲気にするのも良い。なお、これらを実施するためには、図１の薄膜形成装置を、不活性ガスを充填したクリーンブースに設置し、その雰囲気中で発光層の成膜工程を行うことが望ましい。
【００７４】
また、ＥＬ層を形成する方法として、ここで示した、スピンコーティング法の他にインクジェット法等を用いても良い。
【００７５】
また、低分子系有機ＥＬ材料を用いてＥＬ層を形成する場合には、蒸着法などを用いることも可能である。なお、低分子系有機ＥＬ材料としては、公知の材料を用いることができる。
【００７６】
以上のようにしてＥＬ層４２を形成したら、次に遮光性導電膜からなる陰極４３、保護電極４４及び第２パッシベーション膜４５が形成される。本実施形態では陰極４３として、ＭｇＡｇからなる導電膜を用い、保護電極４４としてアルミニウムからなる導電膜を用いる。また、第２パッシベーション膜４５としては、１０ｎｍ〜１μm（好ましくは２００〜５００ｎｍ）の厚さの窒化珪素膜を用いる。
【００７７】
なお、上述のようにＥＬ層は熱に弱いので、陰極４３及び第２パッシベーション膜４５はなるべく低温（好ましくは室温から１２０℃までの温度範囲）で成膜するのが望ましい。従って、プラズマＣＶＤ法、真空蒸着法又は溶液塗布法（スピンコート法）が望ましい成膜方法と言える。
【００７８】
ここまで完成したものをアクティブマトリクス基板とよび、アクティブマトリクス基板に対向して、対向基板（図示せず）が設けられる。本実施形態では対向基板としてガラス基板を用いる。なお、対向基板としては、プラスチックやセラミックスからなる基板を用いても良い。
【００７９】
また、アクティブマトリクス基板と対向基板はシール剤（図示せず）によって接着され、密閉空間（図示せず）が形成される。本実施形態では、密閉空間をアルゴンガスで充填している。勿論、この密閉空間内に酸化バリウムといった乾燥剤を配置したり、酸化防止剤を配置することも可能である。
【００８０】
さらに、対向基板のアクティブマトリクス基板側の面に、仕事関数が低く、酸化されやすい金属や、吸湿性の金属を成膜しておくと酸素を捕捉する機能や吸湿機能を設けることができる。なお、対向基板上に感光性アクリル樹脂のような有機樹脂で凹凸を付けた後にこれらの金属を成膜すると、表面積を大きくすることができるので、より効果的である。
【００８１】
【実施例】
〔実施例１〕
本発明の実施例における画素部とその周辺に設けられる駆動回路部のＴＦＴを同時に作製する方法について図６〜図８を用いて説明する。但し、説明を簡単にするために、駆動回路に関しては基本回路であるＣＭＯＳ回路を図示することとする。
【００８２】
まず、図６（Ａ）に示すように、ガラス基板３００上に下地膜３０１を３００ｎｍの厚さに形成する。本実施例では下地膜３０１として１００ｎｍ厚の窒化酸化珪素膜と２００ｎｍの窒化酸化珪素膜とを積層して用いる。この時、ガラス基板３００に接する方の窒素濃度を１０〜２５ｗｔ％としておくと良い。もちろん下地膜を設けずに石英基板上に直接素子を形成しても良い。
【００８３】
次に下地膜３０１の上に５０ｎｍの厚さの非晶質珪素膜（図示せず））を公知の成膜法で形成する。なお、非晶質珪素膜に限定する必要はなく、非晶質構造を含む半導体膜（微結晶半導体膜を含む）であれば良い。さらに非晶質シリコンゲルマニウム膜などの非晶質構造を含む化合物半導体膜でも良い。また、膜厚は２０〜１００ｎｍの厚さであれば良い。
【００８４】
そして、公知の技術により非晶質珪素膜を結晶化し、結晶質珪素膜（多結晶シリコン膜若しくはポリシリコン膜ともいう）３０２を形成する。公知の結晶化方法としては、電熱炉を使用した熱結晶化方法、レーザー光を用いたレーザーアニール結晶化法、赤外光を用いたランプアニール結晶化法がある。本実施例では、ＸｅＣｌガスを用いたエキシマレーザー光を用いて結晶化する。
【００８５】
なお、本実施例では線状に加工したパルス発振型のエキシマレーザー光を用いるが、矩形であっても良いし、連続発振型のアルゴンレーザー光や連続発振型のエキシマレーザー光を用いることもできる。
【００８６】
本実施例では結晶質珪素膜をＴＦＴの活性層として用いるが、非晶質珪素膜を用いることも可能である。また、オフ電流を低減する必要のあるスイッチング用ＴＦＴの活性層を非晶質珪素膜で形成し、電流制御用ＴＦＴの活性層を結晶質珪素膜で形成することも可能である。非晶質珪素膜はキャリア移動度が低いため電流を流しにくくオフ電流が流れにくい。即ち、電流を流しにくい非晶質珪素膜と電流を流しやすい結晶質珪素膜の両者の利点を生かすことができる。
【００８７】
次に、図６（Ｂ）に示すように、結晶質珪素膜３０２上に酸化珪素膜からなる保護膜３０３を１３０ｎｍの厚さに形成する。この厚さは１００〜２００ｎｍ（好ましくは１３０〜１７０ｎｍ）の範囲で選べば良い。また、珪素を含む絶縁膜であれば他の膜でも良い。この保護膜３０３は不純物を添加する際に結晶質珪素膜が直接プラズマに曝されないようにするためと、微妙な濃度制御を可能にするために設ける。
【００８８】
そして、その上にレジストマスク３０４a、３０４bを形成し、保護膜３０３を介してｎ型を付与する不純物元素（以下、ｎ型不純物元素という）を添加する。なお、ｎ型不純物元素としては、代表的には１５族に属する元素、典型的にはリン又は砒素を用いることができる。なお、本実施例ではホスフィン（ＰＨ₃）を質量分離しないでプラズマ励起したプラズマ（イオン）ドーピング法を用い、リンを１×１０¹⁸atoms/cm³の濃度で添加する。勿論、質量分離を行うイオンインプランテーション法を用いても良い。
【００８９】
この工程により形成されるｎ型不純物領域３０５には、ｎ型不純物元素が２×１０¹⁶〜５×１０¹⁹atoms/cm³（代表的には５×１０¹⁷〜５×１０¹⁸atoms/cm³）の濃度で含まれるようにドーズ量を調節する。
【００９０】
次に、図６（Ｃ）に示すように、保護膜３０３およびレジスト３０４ａ、３０４ｂを除去し、添加した１５族に属する元素の活性化を行う。活性化手段は公知の技術を用いれば良いが、本実施例ではエキシマレーザー光の照射により活性化する。勿論、パルス発振型でも連続発振型でも良いし、エキシマレーザー光に限定する必要はない。但し、添加された不純物元素の活性化が目的であるので、結晶質珪素膜が溶融しない程度のエネルギーで照射することが好ましい。なお、保護膜３０３をつけたままレーザー光を照射しても良い。
【００９１】
なお、このレーザー光による不純物元素の活性化に際して、熱処理による活性化を併用しても構わない。熱処理による活性化を行う場合は、基板の耐熱性を考慮して４５０〜５５０℃程度の熱処理を行えば良い。
【００９２】
この工程によりｎ型不純物領域３０５の端部、即ち、ｎ型不純物領域３０５、の周囲に存在するｎ型不純物元素を添加していない領域との境界部（接合部）が明確になる。このことは、後にＴＦＴが完成した時点において、ＬＤＤ領域とチャネル形成領域とが非常に良好な接合部を形成しうることを意味する。
【００９３】
次に、図６（Ｄ）に示すように、結晶質珪素膜の不要な部分を除去して、島状の半導体膜（以下、活性層という）３０６〜３０９を形成する。
【００９４】
次に、図６（Ｅ）に示すように、活性層３０６〜３０９を覆ってゲート絶縁膜３１０を形成する。ゲート絶縁膜３１０としては、１０〜２００ｎｍ、好ましくは５０〜１５０ｎｍの厚さの珪素を含む絶縁膜を用いれば良い。これは単層構造でも積層構造でも良い。本実施例では１１０ｎｍ厚の窒化酸化珪素膜を用いる。
【００９５】
次に、２００〜４００ｎｍ厚の導電膜を形成し、パターニングしてゲート電極３１１〜３１５を形成する。このゲート電極３１１〜３１５の端部をテーパー状にすることもできる。なお、本実施例ではゲート電極と、ゲート電極に電気的に接続された引き回しのための配線（以下、ゲート配線という）とを別の材料で形成する。具体的にはゲート電極よりも低抵抗な材料をゲート配線として用いる。これは、ゲート電極としては微細加工が可能な材料を用い、ゲート配線には微細加工はできなくとも配線抵抗が小さい材料を用いるためである。勿論、ゲート電極とゲート配線とを同一材料で形成しても構わない。
【００９６】
また、ゲート電極は単層の導電膜で形成しても良いが、必要に応じて二層、三層といった積層膜とすることが好ましい。ゲート電極の材料としては公知のあらゆる導電膜を用いることができる。ただし、上述のように微細加工が可能、具体的には２μm以下の線幅にパターニング可能な材料が好ましい。
【００９７】
代表的には、タンタル（Ｔａ）、チタン（Ｔｉ）、モリブデン（Ｍｏ）、タングステン（Ｗ）、クロム（Ｃｒ）、シリコン（Ｓｉ）から選ばれた元素からなる膜、または前記元素の窒化物膜（代表的には窒化タンタル膜、窒化タングステン膜、窒化チタン膜）、または前記元素を組み合わせた合金膜（代表的にはＭｏ−Ｗ合金、Ｍｏ−Ｔａ合金）、または前記元素のシリサイド膜（代表的にはタングステンシリサイド膜、チタンシリサイド膜）を用いることができる。勿論、単層で用いても積層して用いても良い。
【００９８】
本実施例では、５０ｎｍ厚の窒化タンタル（ＴａＮ）膜と、３５０ｎｍ厚のタンタル（Ｔａ）膜とからなる積層膜を用いる。これはスパッタ法で形成すれば良い。また、スパッタガスとしてＸｅ、Ｎｅ等の不活性ガスを添加すると応力による膜はがれを防止することができる。
【００９９】
またこの時、ゲート電極３１２はｎ型不純物領域３０５の一部とゲート絶縁膜３１０を挟んで重なるように形成する。この重なった部分が後にゲート電極と重なったＬＤＤ領域となる。なお、ゲート電極３１３，３１４は、断面では、二つに見えるが実際には電気的に接続されている。
【０１００】
次に、図７（Ａ）に示すように、ゲート電極３１１〜３１５をマスクとして自己整合的にｎ型不純物元素（本実施例ではリン）を添加する。こうして形成される不純物領域３１６〜３２３にはｎ型不純物領域３０５の１／２〜１／１０（代表的には１／３〜１／４）の濃度でリンが添加されるように調節する。具体的には、１×１０¹⁶〜５×１０¹⁸atoms/cm³（典型的には３×１０¹⁷〜３×１０¹⁸atoms/cm³）の濃度が好ましい。
【０１０１】
次に、図７（Ｂ）に示すように、ゲート電極等を覆う形でレジストマスク３２４a〜３２４ｄを形成し、ｎ型不純物元素（本実施例ではリン）を添加して高濃度にリンを含む不純物領域３２５〜３２９を形成する。ここでもホスフィン（ＰＨ₃）を用いたイオンドープ法で行い、この領域のリンの濃度は１×１０²⁰〜１×１０²¹atoms/cm³（代表的には２×１０²⁰〜５×１０²¹atoms/cm³）となるように調節する。
【０１０２】
この工程によってｎチャネル型ＴＦＴのソース領域及びドレイン領域が形成されるが、スイッチング用ＴＦＴでは、図７（Ａ）の工程で形成したｎ型不純物領域３１９〜３２１の一部を残す。この残された領域が、図２におけるスイッチング用ＴＦＴ２０１のＬＤＤ領域１５a〜１５dに対応する。
【０１０３】
次に、図７（Ｃ）に示すように、レジストマスク３２４a〜３２４ｄを除去し、新たにレジストマスク３３２を形成する。そして、ｐ型不純物元素（本実施例ではボロン）を添加し、高濃度にボロンを含む不純物領域３３３〜３３６を形成する。ここではジボラン（Ｂ₂Ｈ₆）を用いたイオンドープ法により３×１０²⁰〜３×１０²¹atoms/cm³（代表的には５×１０²⁰〜１×１０²¹atoms/cm³ノ）濃度となるようにボロンを添加する。
【０１０４】
なお、不純物領域３３３〜３３６には既に１×１０²⁰〜１×１０²¹atoms/cm³の濃度でリンが添加されているが、ここで添加されるボロンはその少なくとも３倍以上の濃度で添加される。そのため、予め形成されていたｎ型の不純物領域は完全にｐ型に反転し、ｐ型の不純物領域として機能する。
【０１０５】
次に、レジストマスク３３２を除去した後、それぞれの濃度で添加されたｎ型またはｐ型不純物元素を活性化する。活性化手段としては、ファーネスアニール法、レーザーアニール法、及びランプアニール法で行うことができる。本実施例では電熱炉において窒素雰囲気中、５５０℃、４時間の熱処理を行う。
【０１０６】
このとき雰囲気中の酸素を極力排除することが重要である。なぜならば酸素が少しでも存在していると露呈したゲート電極の表面が酸化され、抵抗の増加を招くと共に後にオーミックコンタクトを取りにくくなるからである。従って、上記活性化工程における処理雰囲気中の酸素濃度は１ｐｐｍ以下、好ましくは０．１ｐｐｍ以下とすることが望ましい。
【０１０７】
次に、活性化工程が終了したら図７（Ｄ）に示すように３００ｎｍ厚のゲート配線３３７を形成する。ゲート配線３３７の材料としては、アルミニウム（Ａｌ）又は銅（Ｃｕ）を主成分（組成として５０〜１００％を占める。）とする金属を用いれば良い。配置としては図３のようにゲート配線２１１とスイッチング用ＴＦＴのゲート電極１９a、１９b（図６（Ｅ）の３１３、３１４）が電気的に接続するように形成する。
【０１０８】
このような構造とすることでゲート配線の配線抵抗を非常に小さくすることができるため、面積の大きい画像表示領域（画素部）を形成することができる。即ち、画面の大きさが対角１０インチ以上（さらには３０インチ以上）のＥＬ表示装置を実現する上で、本実施例の画素構造は極めて有効である。
【０１０９】
次に、図８（Ａ）に示すように、第１層間絶縁膜３３８を形成する。第１層間絶縁膜３３８としては、珪素を含む絶縁膜を単層で用いるか、２種類以上の珪素を含む絶縁膜を組み合わせた積層膜を用いれば良い。また、膜厚は４００ｎｍ〜１．５μmとすれば良い。本実施例では、２００ｎｍ厚の窒化酸化珪素膜の上に８００ｎｍ厚の酸化珪素膜を積層した構造とする。
【０１１０】
さらに、３〜１００％の水素を含む雰囲気中で、３００〜４５０℃で１〜１２時間の熱処理を行い、水素化処理をする。この工程は熱的に励起された水素により半導体膜の不対結合手を水素終端する工程である。水素化の他の手段として、プラズマ水素化（プラズマ化して生成された水素を用いる）を行っても良い。
【０１１１】
なお、水素化処理は第１層間絶縁膜３３８を形成する間に入れても良い。即ち、２００ｎｍ厚の窒化酸化珪素膜を形成した後で上記のように水素化処理を行い、その後で残り８００ｎｍ厚の酸化珪素膜を形成してもよい。
【０１１２】
次に、第１層間絶縁膜３３８及びゲート絶縁膜３１０に対してコンタクトホールを形成し、ソース配線３３９〜３４２と、ドレイン配線３４３〜３４５を形成する。なお、本実施例ではこれらの電極を、Ｔｉ膜を１００ｎｍ、Ｔｉを含むアルミニウム膜を３００ｎｍ、Ｔｉ膜１５０ｎｍをスパッタ法で連続形成した３層構造の積層膜とする。勿論、他の導電膜でも良い。
【０１１３】
次に、５０〜５００ｎｍ（代表的には２００〜３００ｎｍ）の厚さで第１パッシベーション膜３４６を形成する。本実施例では第１パッシベーション膜３４６として３００ｎｍ厚の窒化酸化珪素膜を用いる。これは窒化珪素膜で代用しても良い。
【０１１４】
なお、窒化酸化珪素膜の形成に先立ってＨ₂、ＮＨ₃等水素を含むガスを用いてプラズマ処理を行うことは有効である。この前処理により励起された水素が第１層間絶縁膜３３８に供給され、熱処理を行うことで、第１パッシベーション膜３４６の膜質が改善される。それと同時に、第１層間絶縁膜３３８に添加された水素が下層側に拡散するため、効果的に活性層を水素化することができる。
【０１１５】
次に、図８（Ｂ）に示すように有機樹脂からなる第２層間絶縁膜３４７を形成する。有機樹脂としてはポリイミド、ポリアミド、アクリル樹脂、シロキサンの高分子化合物を材料として使用することができる。特に、第２層間絶縁膜３４７は平坦化の意味合いが強いので、平坦性に優れたアクリル樹脂が好ましい。本実施例ではＴＦＴによって形成される段差を十分に平坦化しうる膜厚でアクリル樹脂膜を形成する。好ましくは１〜５μm（さらに好ましくは２〜４μm）とすれば良い。
【０１１６】
次に、第２層間絶縁膜３４７及び第１パッシベーション膜３４６に対してコンタクトホールを形成し、ドレイン配線３４５と電気的に接続される画素電極３４８を形成する。本実施例では酸化インジウム・スズ（ＩＴＯ）膜を１１０ｎｍの厚さに形成し、パターニングを行って画素電極とする。また、酸化インジウムに２〜２０％の酸化亜鉛（ＺｎＯ）を混合した透明導電膜を用いても良い。この画素電極がＥＬ素子の陽極となる。
【０１１７】
次に、図８（Ｃ）に示すように、有機樹脂からなる保護部３４９ａ及び３４９ｂを形成する。保護部３４９ａ及び３４９ｂは１〜２μm厚のアクリル樹脂膜やポリイミド膜といった樹脂膜をパターニングして形成すれば良い。この保護部３４９ａ及び３４９ｂは図３に示したように、画素電極と画素電極との隙間及び電極ホールに形成される。
【０１１８】
次に、ＥＬ層３５０を形成する。具体的には、ＥＬ層３５０となる有機ＥＬ材料をクロロフォルム、ジクロロメタン、キシレン、トルエン、テトラヒドロフラン、Ｎ−メチルピロリドンといった溶媒に溶かしてスピンコーティング法で塗布し、その後、熱処理を行うことにより溶媒を揮発させる。こうして有機ＥＬ材料からなる被膜（ＥＬ層）が形成される。
【０１１９】
本実施例では、ＥＬ材料を８０ｎｍの厚さに成膜した後、８０〜１５０℃のホットプレートで１〜５分の熱処理を行って揮発させる。
【０１２０】
なお、ＥＬ材料としては公知の材料を用いることができる。公知の材料としては、駆動電圧を考慮すると有機材料を用いるのが好ましい。なお、本実施例ではＥＬ層３５０は単層構造とするが、必要に応じて電子注入層、電子輸送層、正孔輸送層、正孔注入層、電子阻止層もしくは正孔素子層を設けて積層構造としても良い。また、本実施例ではＥＬ素子の陰極３５１としてＭｇＡｇ電極を用いた例を示すが、公知の他の材料であっても良い。
【０１２１】
ＥＬ層３５０を形成した後、陰極（ＭｇＡｇ電極）３５１を真空蒸着法で形成する。なお、ＥＬ層３５０の膜厚は８０〜２００ｎｍ（典型的には１００〜１２０ｎｍ）、陰極３５１の厚さは１８０〜３００ｎｍ（典型的には２００〜２５０ｎｍ）とすれば良い。
【０１２２】
さらに、陰極３５１上には、保護電極３５２を設ける。保護電極３５２としてはアルミニウムを主成分とする導電膜を用いれば良い。保護電極３５２は、マスクを用いて真空蒸着法で形成すれば良い。
【０１２３】
最後に、窒化珪素膜からなる第２パッシベーション膜３５３を３００ｎｍの厚さに形成する。実際には保護電極３５２がＥＬ層を水分等から保護する役割を果たすが、さらに第２パッシベーション膜３５３を形成しておくことで、ＥＬ素子の信頼性をさらに高めることができる。
【０１２４】
本実施例の場合、図８（Ｃ）に示すように、ｎチャネル型２０５の活性層は、ソース領域３５５、ドレイン領域３５６、ＬＤＤ領域３５７及びチャネル形成領域３５８を含み、ＬＤＤ領域３５７はゲート絶縁膜３１０を挟んでゲート電極３１２と重なっている。
【０１２５】
ドレイン領域側のみにＬＤＤ領域を形成しているのは、動作速度を落とさないための配慮である。また、このｎチャネル型ＴＦＴ２０５はオフ電流値をあまり気にする必要はなく、それよりも動作速度を重視した方が良い。従って、ＬＤＤ領域３５７は完全にゲート電極に重ねてしまい、極力抵抗成分を少なくすることが望ましい。即ち、いわゆるオフセットはなくした方がよい。
【０１２６】
こうして図８（Ｃ）に示すような構造のアクティブマトリクス基板が完成する。
【０１２７】
ところで、本実施例のアクティブマトリクス基板は、画素部だけでなく駆動回路部にも最適な構造のＴＦＴを配置することにより、非常に高い信頼性を示し、動作特性も向上しうる。
【０１２８】
まず、極力動作速度を落とさないようにホットキャリア注入を低減させる構造を有するＴＦＴを、駆動回路部を形成するＣＭＯＳ回路のｎチャネル型ＴＦＴ２０５として用いる。なお、ここでいう駆動回路としては、シフトレジスタ、バッファ、レベルシフタ、サンプリング回路（サンプル及びホールド回路）などが含まれる。デジタル駆動を行う場合には、Ｄ／Ａコンバータなどの信号変換回路も含まれうる。
【０１２９】
なお、駆動回路の中でもサンプリング回路は他の回路と比べて少し特殊であり、チャネル形成領域を双方向に大電流が流れる。即ち、ソース領域とドレイン領域の役割が入れ替わるのである。さらに、オフ電流値を極力低く抑える必要があり、そういった意味でスイッチング用ＴＦＴと電流制御用ＴＦＴの中間程度の機能を有するＴＦＴを配置することが望ましい。
【０１３０】
従って、サンプリング回路を形成するｎチャネル型ＴＦＴは、図９に示すような構造のＴＦＴを配置することが望ましい。図９に示すように、ＬＤＤ領域９０１a、９０１bの一部がゲート絶縁膜９０２を介してゲート電極９０３と重なる。この効果は電流を流した際に生じるホットキャリア注入に対する劣化対策であり、サンプリング回路の場合はチャネル形成領域９０４を挟む形で両側に設ける点が異なる。
【０１３１】
なお、実際には図８（Ｃ）まで完成したら、さらに外気に曝されないように気密性の高いガラス、石英、プラスチックといったカバー材でパッケージング（封入）することが好ましい。その際、カバー材の内部に内部に酸化バリウムといった吸湿剤や酸化防止剤を配置するとよい。
【０１３２】
また、パッケージング等の処理により気密性を高めたら、基板上に形成された素子又は回路から引き回された端子と外部信号端子とを接続するためのコネクター（フレキシブルプリントサーキット：ＦＰＣ）を取り付けて製品として完成する。このような出荷できる状態にまでした状態を本明細書中ではＥＬ表示装置（またはＥＬモジュール）という。
【０１３３】
ここで本実施例のアクティブマトリクス型ＥＬ表示装置の構成を図１０の斜視図を用いて説明する。本実施例のアクティブマトリクス型ＥＬ表示装置は、ガラス基板６０１上に形成された、画素部６０２と、ゲート側駆動回路６０３と、ソース側駆動回路６０４を含む。画素部のスイッチング用ＴＦＴ６０５はｎチャネル型ＴＦＴであり、ゲート側駆動回路６０３に接続されたゲート配線６０６、ソース側駆動回路６０４に接続されたソース配線６０７の交点に配置されている。また、スイッチング用ＴＦＴ６０５のドレインは電流制御用ＴＦＴ６０８のゲートに接続されている。
【０１３４】
さらに、電流制御用ＴＦＴ６０８のソース側は電源供給線６０９に接続される。本実施例のような構造では、電源供給線６０９には接地電位（アース電位）が与えられている。また、電流制御用ＴＦＴ６０８のドレインにはＥＬ素子６１０が接続されている。また、このＥＬ素子６１０の陽極には所定の電圧（３〜１２Ｖ、好ましくは３〜５Ｖ）が加えられる。
【０１３５】
そして、外部入出力端子となるＦＰＣ６１１には駆動回路部まで信号を伝達するための接続配線６１２、６１３、及び電源供給線６０９に接続された接続配線６１４が設けられている。
【０１３６】
また、図１０に示したＥＬ表示装置の回路構成の一例を図１１に示す。本実施例のＥＬ表示装置は、ソース側駆動回路８０１、ゲート側駆動回路（Ａ）８０７、ゲート側駆動回路（Ｂ）８１１、画素部８０６を有している。なお、本明細書中において、駆動回路部とはソース側駆動回路およびゲート側駆動回路を含めた総称である。
【０１３７】
ソース側駆動回路８０１は、シフトレジスタ８０２、レベルシフタ８０３、バッファ８０４、サンプリング回路（サンプル及びホールド回路）８０５を備えている。また、ゲート側駆動回路（Ａ）８０７は、シフトレジスタ８０８、レベルシフタ８０９、バッファ８１０を備えている。ゲート側駆動回路（Ｂ）８１１も同様な構成である。
【０１３８】
ここでシフトレジスタ８０２、８０８は駆動電圧が５〜１６Ｖ（代表的には１０Ｖ）であり、回路を形成するＣＭＯＳ回路に使われるｎチャネル型ＴＦＴは図８（Ｃ）の２０５で示される構造が適している。
【０１３９】
また、レベルシフタ８０３、８０９、バッファ８０４、８１０はシフトレジスタと同様に、図８（Ｃ）のｎチャネル型ＴＦＴ２０５を含むＣＭＯＳ回路が適している。なお、ゲート配線をダブルゲート構造、トリプルゲート構造といったマルチゲート構造とすることは、各回路の信頼性を向上させる上で有効である。
【０１４０】
また、サンプリング回路８０５はソース領域とドレイン領域が反転する上、オフ電流値を低減する必要があるので、図９のｎチャネル型ＴＦＴ２０８を含むＣＭＯＳ回路が適している。
【０１４１】
また、画素部８０６は図２に示した構造の画素を配置する。
【０１４２】
なお、上記構成は、図６〜８に示した作製工程に従ってＴＦＴを作製することによって容易に実現することができる。また、本実施例では画素部と駆動回路部の構成のみ示しているが、本実施例の作製工程に従えば、その他にも信号分割回路、Ｄ／Ａコンバータ回路、オペアンプ回路、γ補正回路など駆動回路以外の論理回路を同一基板上に形成することが可能であり、さらにはメモリ部やマイクロプロセッサ等を形成しうると考えている。
【０１４３】
さらに、カバー材をも含めた本実施例のＥＬモジュールについて図１２（Ａ）、（Ｂ）を用いて説明する。なお、必要に応じて図１０、図１１で用いた符号を引用することにする。
【０１４４】
図１２（Ａ）は、図１０に示した状態にシーリング構造を設けた状態を示す上面図である。点線で示された６０２は画素部、６０３はゲート側駆動回路、６０４はソース側駆動回路である。本発明のシーリング構造は、図１０の状態に対して充填材（図示せず）、カバー材１１０１、シール材（図示せず）及びフレーム材１１０２を設けた構造である。
【０１４５】
ここで、図１２（Ａ）をＡ−Ａ’で切断した断面図を図１２（Ｂ）に示す。なお、図１２（Ａ）、（Ｂ）では同一の部位に同一の符号を用いている。
【０１４６】
図１２（Ｂ）に示すように、基板６０１上には画素部６０２、ゲート側駆動回路６０３が形成されており、画素部６０２は電流制御用ＴＦＴ２０２とそれに電気的に接続された画素電極３４８を含む複数の画素により形成される。また、ゲート側駆動回路６０３はｎチャネル型ＴＦＴ２０５とｐチャネル型ＴＦＴ２０６とを相補的に組み合わせたＣＭＯＳ回路を用いて形成される。
【０１４７】
画素電極３４８はＥＬ素子の陽極として機能する。また、画素電極３４８の両端には保護膜３４９ａが形成され、保護膜３４９ａの上にＥＬ層３５０、陰極３５１が形成される。また、その上には保護電極３５２、第２パッシベーション膜３５３が形成される。勿論、上述したようにＥＬ素子の構造を反対とし、画素電極を陰極としても構わない。
【０１４８】
本実施例の場合、保護電極３５２は全画素に共通の配線としても機能し、接続配線６１２を経由してＦＰＣ６１１に電気的に接続されている。さらに、画素部６０２及びゲート側駆動回路６０３に含まれる素子は全て第２パッシベーション膜３５３で覆われている。この第２パッシベーション膜３５３は省略することも可能であるが、各素子を外部と遮断する上で設けた方が好ましい。
【０１４９】
次に、ＥＬ素子を覆うようにして充填材１１０３を設ける。この充填材１１０３はカバー材１１０１を接着するための接着剤としても機能する。充填材１１０３としては、ＰＶＣ（ポリビニルクロライド）、エポキシ樹脂、シリコン樹脂、ＰＶＢ（ポリビニルブチラル）またはＥＶＡ（エチレンビニルアセテート）を用いることができる。この充填材１１０３の内部に乾燥剤（図示せず）を設けておくと、吸湿効果を保ち続けられるので好ましい。このとき、乾燥剤は充填材に添加されたものであっても良いし、充填材に封入されたものであっても良い。
【０１５０】
また、本実施例ではカバー材１１０１としては、ガラス、プラスチック、およびセラミックスからなる材料を用いることができる。なお、充填材１１０３の内部に予め酸化バリウム等の乾燥剤を添加しておくことは有効である。
【０１５１】
次に、充填材１１０３を用いてカバー材１１０１を接着した後、充填材１１０３の側面（露呈面）を覆うようにフレーム材１１０２を取り付ける。フレーム材１１０２はシール材（接着剤として機能する）１１０４によって接着される。このとき、シール材１１０４としては、光硬化性樹脂を用いるのが好ましいが、ＥＬ層の耐熱性が許せば熱硬化性樹脂を用いても良い。なお、シール材１１０４はできるだけ水分や酸素を透過しない材料であることが望ましい。また、シール材１１０４の内部に乾燥剤を添加してあっても良い。
【０１５２】
以上のような方式を用いてＥＬ素子を充填材１１０３に封入することにより、ＥＬ素子を外部から完全に遮断することができ、外部から水分や酸素等のＥＬ層の酸化による劣化を促す物質が侵入することを防ぐことができる。従って、信頼性の高いＥＬ表示装置を作製することができる。
【０１５３】
〔実施例２〕
実施例１において、画素電極上に有機樹脂を全面塗布した後、露光装置を用いてパターニングを行い、電極ホールおよび画素電極間の隙間に有機樹脂で埋め込んだ保護部を形成した後、ＥＬ層を形成する作製方法を示したが、露光工程が入るためにスループットが悪いので本実施例では、画素電極上に有機樹脂を全面塗布した後、パターニングを行わずにエッチバック法を用いて平坦化を行い、電極ホール及び画素電極間の隙間に埋め込まれた有機樹脂以外をエッチングする方法を示す。
【０１５４】
ここで本発明におけるＥＬ表示装置の画素部の断面構造を図１３に示す。
【０１５５】
図１３（Ａ）に示されるのは、画素電極１０４０及び画素電極１０４０に電気的に接続される電流制御用ＴＦＴである。電流制御用ＴＦＴは、基板１０１１上に下地膜１０１２が形成された後、ソース領域１０３１、ドレイン領域１０３２及びチャネル形成領域１０３４を含む活性層、ゲート絶縁膜１０１８、ゲート電極１０３５、第１層間絶縁膜１０２０、ソース配線１０３６並びにドレイン配線１０３７を有して形成される。なお、ゲート電極１０３５はシングルゲート構造となっているが、マルチゲート構造であっても良い。
【０１５６】
次に、１０３８は第１パッシベーション膜であり、膜厚は１０ｎｍ〜１μm（好ましくは２００〜５００ｎｍ）とすれば良い。材料としては、珪素を含む絶縁膜（特に窒化酸化珪素膜又は窒化珪素膜が好ましい）を用いることができる。
【０１５７】
第１パッシベーション膜１０３８の上には、各ＴＦＴを覆うような形で第２層間絶縁膜（平坦化膜と言っても良い）１０３９を形成し、ＴＦＴによってできる段差の平坦化を行う。第２層間絶縁膜１０３９としては、有機樹脂膜が好ましく、ポリイミド、ポリアミド、アクリル樹脂、シロキサンの高分子化合物を含む樹脂を材料として用いると良い。勿論、十分な平坦化が可能であれば、無機膜を用いても良い。
【０１５８】
第２層間絶縁膜１０３９によってＴＦＴによる段差を平坦化することは非常に重要である。後に形成されるＥＬ層は非常に薄いため、段差が存在することによって発光不良を起こす場合がある。従って、ＥＬ層をできるだけ平坦面に形成しうるように画素電極を形成する前に平坦化しておくことが望ましい。
【０１５９】
また、１０４０は透明導電膜からなる画素電極（ＥＬ素子の陽極に相当する）であり、第２層間絶縁膜１０３９及び第１パッシベーション膜１０３８にコンタクトホール（開孔）を開けた後、形成された開孔部において電流制御用ＴＦＴのドレイン配線１０３７に接続されるように形成される。
【０１６０】
本実施形態では、画素電極として酸化インジウムと酸化スズの化合物からなる導電膜を用いる。また、これに少量のガリウムを添加しても良い。さらに酸化インジウムと酸化亜鉛との化合物を用いることもできる。
【０１６１】
次に、画素電極上に有機樹脂を材料とする有機樹脂膜１０４１を形成する。有機樹脂としては、ポリアミド、ポリイミド、アクリル樹脂およびシロキサンの高分子化合物を含む樹脂といった材料があり、これらを使っても良いが、ここでは、アクリル樹脂であるアクリル酸エステル樹脂、アクリル酸樹脂、メタクリル酸エステル樹脂、メタクリル酸樹脂といった樹脂を用いている。
なお、シロキサンの高分子化合物を含む樹脂としては、シクロテンがある。
【０１６２】
また、ここでは画素電極上に有機樹脂を材料とする有機樹脂膜を形成させているが、絶縁膜となりうる絶縁体を用いても良い。
【０１６３】
絶縁体としては、酸化珪素や窒化酸化珪素及び窒化珪素といった珪素を含む絶縁膜を用いると良い。
【０１６４】
有機樹脂膜１０４１の膜厚（Ｄｃ）は、０．１〜２μｍが好ましいが、さらに好ましくは０．２〜０．６μｍとするのがよい。
【０１６５】
有機樹脂膜１０４１を成膜した後、有機樹脂膜１０４１を全面エッチングしてＤｃ＝０となるところでエッチングを終了させると、電極ホールに埋め込まれたアクリル樹脂が残り、保護部１０４１ｂが形成される。
【０１６６】
なお、エッチング方法としてはドライエッチングが好ましい。まず、真空チャンバー内にエッチングすべき有機樹脂材料に合わせたエッチングガスを導入した後、電極に高周波電圧を印加してプラズマを発生させ、プラズマ雰囲気でエッチングガスを分解させる。
【０１６７】
プラズマ雰囲気で分解されたエッチングガス中には、正イオン、負イオン、電子などの荷電粒子と中性活性種がバラバラの状態で存在している。なお、これらのエッチング種が、被エッチング材料に吸着されると表面化学反応が生じてエッチング生成物が生成し、このエッチング生成物が除去されると、エッチングがなされる。
【０１６８】
また、保護膜の材料としてアクリル樹脂を用いる場合、エッチングにおけるエッチングガスとして酸素を主成分とするガスを用いることが望ましい。
【０１６９】
なお、本実施例では酸素を主成分とするエッチングガスとして、酸素、ヘリウム及び四フッ化炭素（ＣＦ₄）からなるエッチングガスを用いている。また、その他の材料として、六フッ化二炭素（Ｃ₂Ｆ₆）といったフッ化炭素系のガスを用いても良い。
【０１７０】
なお、これらのエッチングガスにおいては、酸素が、エッチングガス全体の６０％以上になることが望ましい。
【０１７１】
本実施例に示すように画素電極上に有機樹脂膜をスピンコート法を用いて成膜した後、これを全面エッチングして、図１３（Ｂ）に示すように電極ホール１０４６に保護部１０４１ｂが形成されるように矢印の方向にエッチングさせる。なお、ここで形成された保護部１０４１ｂの露呈面及び画素電極１０４０の露呈面は、図１３（Ｂ）に示すように同一面内にある。
【０１７２】
なお、このときのエッチング時間は予めエッチングレートを調べておき、保護部１０４１ｂを除く画素電極１０４０上の有機樹脂膜がちょうど除去されたところでエッチングが終了するようにする。これにより、画素電極１０４０の上面と保護部１０４１ｂの上面が同一の平坦面になる。
【０１７３】
また、これらの有機樹脂を用いる際には、粘度を１０^-3Ｐａ・ｓ〜１０^-1Ｐａ・ｓとするとよい。
【０１７４】
保護部１０４１ｂを形成したら、図１３（Ｃ）に示すようにＥＬ層１０４２を形成するためにＥＬ材料を溶媒に溶解させたものがスピンコート法により成膜される。
【０１７５】
ＥＬ層１０４２が形成されると、さらに陰極１０４３及び保護電極１０４４が形成される。
【０１７６】
以上のようにして図１３（Ｃ）に示す様な構造とすることで、電極ホールの段差部分で、ＥＬ層１０４２が切断された際に生じる画素電極１０４０と陰極１０４３間での短絡の問題を解決することができる。
【０１７７】
なお、本実施例で示したように画素電極１０４０上の保護部１０４１ｂが電極ホール１０４６と同一の形状である場合の上面図を図１３（Ｄ）に示す。
【０１７８】
また、本実施例の構成は、実施例１の構成と自由に組み合わせることができる。
【０１７９】
〔実施例３〕
実施例２では、エッチングにより保護膜を形成させる方法、いわゆるエッチバック法について説明したが、エッチバック法では、保護膜の膜の種類によっては適さないことや平坦化できる領域が数μｍから数１０μｍであるといった制限があるので、化学的機械研磨（ＣＭＰ:Chemical Mechanical Polishing）を用いて保護部を形成することも可能である。そこで、本実施例も図１３を用いて説明する。
【０１８０】
本実施例においては、実施例２の図１３（Ａ）で示したように有機樹脂膜１０４１をＤｃ（＞０）の膜厚に成膜した後、有機樹脂膜１０４１に対して対向する定盤上に張られた研磨パッドに一定圧力で押しつけ、基板及び定盤をそれぞれ回転させながら研磨材（スラリー）を流し、Ｄｃ＝０になるまで研磨する、いわゆるＣＭＰを用いて保護部１０４１ｂを形成させる。
【０１８１】
ＣＭＰを行う上で使用するスラリーは、砥粒と呼ばれる研磨粒子をｐＨ調整した水溶液に分散させたものであり、被研磨膜により異なるスラリーを用いるとよい。
【０１８２】
本実施例では、被研磨膜としてアクリル樹脂を用いているので、シリカ系スラリー（ＳｉＯ₂）やセリア系スラリー（ＣｅＯ₂）およびフュームドシリカ系スラリー（ＳｉＣｌ₄）といったスラリーを用いるのが好ましい。しかし、スラリーとしては、このほかにもアルミナ系スラリー（Ａｌ₂Ｏ₃）やゼオライト系スラリーがありこれらを用いても良い。
【０１８３】
また、スラリー中の液と砥粒（シリカ粒子）との間の電位（ゼータ電位）は、加工精度に影響するのでｐＨ値を最適化することで調整する必要がある。
【０１８４】
ＣＭＰを用いて研磨する際に、研磨の終了点を見極めるのは困難である。もし研磨しすぎた場合には、画素電極まで研磨してしまうことになる。そこで、加工速度が極端に遅い膜を形成してＣＭＰのストッパーとしたり、予め実験によって、加工時間と加工速度の関係を明らかにしておき、ある一定の加工時間がきたところで、ＣＭＰを終了する手法を取ることで必要以上の研磨を防ぐことができる。
【０１８５】
以上のように、ＣＭＰを用いることで被研磨膜の膜厚や膜の種類によらずに保護部１０４１ｂを形成させることができる。
【０１８６】
なお、本実施例の構成は、実施例１〜実施例２の構成と自由に組み合わせることができる。
【０１８７】
〔実施例４〕
本実施例では本発明をパッシブ型（単純マトリクス型）のＥＬ表示装置に用いた場合について図１４を用いて説明する。図１４において、１３０１はプラスチックからなる基板、１３０６は透明導電膜からなる陽極である。なお、基板１３０１は、ガラス、石英といった材料でできていても良い。
【０１８８】
本実施例では、透明導電膜として酸化インジウムと酸化亜鉛との化合物を蒸着法により形成する。なお、図１４では図示されていないが、複数本の陽極が紙面に垂直な方向へストライプ状に配列されている。
【０１８９】
また、ストライプ状に配列された陽極１３０２の間を埋めるように本発明の保護部１３０３が形成される。保護部１３０３は陽極１３０２に沿って紙面に垂直な方向に形成されている。なお、本実施例における保護部１３０３の形成には、実施例１〜３に示した方法により同様の材料を用いて形成すればよい。
【０１９０】
次に、高分子系有機ＥＬ材料からなるＥＬ層１３０４が形成される。用いる有機ＥＬ材料は実施例１と同様のものを用いれば良い。これらのＥＬ層は保護膜１３０２によって形成された溝に沿って形成されるため、紙面に垂直な方向にストライプ状に配列される。
【０１９１】
その後、図１４では図示されていないが、複数本の陰極及び保護電極が紙面に平行な方向が長手方向となり、且つ、陽極１３０２と直交するようにストライプ状に配列されている。なお、本実施例では、陰極１３０５は、ＭｇＡｇからなり、保護電極１３０６はアルミニウム合金膜からなり、それぞれ蒸着法により形成される。また、図示されないが保護電極１３０６は所定の電圧が加えられるように、後にＦＰＣが取り付けられる部分まで配線が引き出されている。
【０１９２】
また、ここでは図示していないが保護電極１３０６を形成したら、パッシベーション膜として窒化珪素膜を設けても良い。
【０１９３】
以上のようにして基板１３０１上にＥＬ素子を形成する。なお、本実施例では下側の電極が透光性の陽極となっているため、ＥＬ層１３０４a〜１３０４cで発生した光は下面（基板１３０１）に放射される。しかしながら、ＥＬ素子の構造を反対にし、下側の電極を遮光性の陰極とすることもできる。その場合、ＥＬ層で発生した光は上面（基板１３０１とは反対側）に放射されることになる。
【０１９４】
次に、カバー材１３０７としてセラミックス基板を用意する。本実施例の構造では遮光性で良いのでセラミックス基板を用いたが、勿論、前述のようにＥＬ素子の構造を反対にした場合、カバー材は透光性のほうが良いので、プラスチックやガラスからなる基板を用いるとよい。
【０１９５】
こうしてカバー材１３０７を用意したら、乾燥剤（図示せず）として酸化バリウムを添加した充填材１３０８によりカバー材１３０７を貼り合わせる。その後、紫外線硬化樹脂からなるシール材１３０９を用いてフレーム材１３１０を取り付ける。本実施例ではフレーム材１３１０としてステンレス材を用いる。最後に異方導電性フィルム１３１１を介してＦＰＣ１３１２を取り付けてパッシブ型のＥＬ表示装置が完成する。
【０１９６】
なお、本実施例の構成は、実施例１〜実施例３のいずれの構成とも自由に組み合わせて実施することが可能である。
【０１９７】
〔実施例５〕
本発明を実施してアクティブマトリクス型のＥＬ表示装置を作製する際に、基板としてシリコン基板（シリコンウェハー）を用いることは有効である。基板としてシリコン基板を用いた場合、画素部に形成するスイッチング素子や電流制御用素子または駆動回路部に形成する駆動用素子を、従来のＩＣやＬＳＩなどに用いられているＭＯＳＦＥＴの作製技術を用いて作製することができる。
【０１９８】
ＭＯＳＦＥＴはＩＣやＬＳＩで実績があるように非常にばらつきの小さい回路を形成することが可能であり、特に電流値で階調表現を行うアナログ駆動のアクティブマトリクス型ＥＬ表示装置には有効である。
【０１９９】
なお、シリコン基板は遮光性であるので、ＥＬ層からの光は基板とは反対側に放射されるような構造とする必要がある。本実施例のＥＬ表示装置は構造的には図１２と似ているが、画素部６０２、駆動回路部６０３を形成するＴＦＴの代わりにＭＯＳＦＥＴを用いる点で異なる。
【０２００】
なお、本実施例の構成は、実施例１〜実施例４のいずれの構成とも自由に組み合わせて実施することが可能である。
【０２０１】
〔実施例６〕
本発明を実施して形成されたＥＬ表示装置は、自発光型であるため液晶表示装置に比べて明るい場所での視認性に優れ、しかも視野角が広い。従って、様々な電気器具の表示部として用いることができる。例えば、ＴＶ放送等を大画面で鑑賞するには対角３０インチ以上（典型的には４０インチ以上）のＥＬディスプレイ（ＥＬ表示装置を筐体に組み込んだディスプレイ）の表示部として本発明のＥＬ表示装置を用いるとよい。
【０２０２】
なお、ＥＬディスプレイには、パソコン用ディスプレイ、ＴＶ放送受信用ディスプレイ、広告表示用ディスプレイ等の全ての情報表示用ディスプレイが含まれる。また、その他にも様々な電気器具の表示部として本発明のＥＬ表示装置を用いることができる。
【０２０３】
その様な本発明の電気器具としては、ビデオカメラ、デジタルカメラ、ゴーグル型ディスプレイ（ヘッドマウントディスプレイ）、ナビゲーションシステム、音響再生装置（カーオーディオ、オーディオコンポ等）、ノート型パーソナルコンピュータ、ゲーム機器、携帯情報端末（モバイルコンピュータ、携帯電話、携帯型ゲーム機または電子書籍等）、記録媒体を備えた画像再生装置（具体的にはデジタルビデオディスク（ＤＶＤ）等の記録媒体を再生し、その画像を表示しうるディスプレイを備えた装置）などが挙げられる。特に、斜め方向から見ることの多い携帯情報端末は視野角の広さが重要視されるため、ＥＬ表示装置を用いることが望ましい。それら電気器具の具体例を図１５、図１６に示す。
【０２０４】
図１５（Ａ）はＥＬディスプレイであり、筐体２００１、支持台２００２、表示部２００３等を含む。本発明は表示部２００３に用いることができる。ＥＬディスプレイは自発光型であるためバックライトが必要なく、液晶ディスプレイよりも薄い表示部とすることができる。
【０２０５】
図１５（Ｂ）はビデオカメラであり、本体２１０１、表示部２１０２、音声入力部２１０３、操作スイッチ２１０４、バッテリー２１０５、受像部２１０６等を含む。本発明のＥＬ表示装置は表示部２１０２に用いることができる。
【０２０６】
図１５（Ｃ）は頭部取り付け型のＥＬディスプレイの一部（右片側）であり、本体２２０１、信号ケーブル２２０２、頭部固定バンド２２０３、表示部２２０４、光学系２２０５、ＥＬ表示装置２２０６等を含む。本発明はＥＬ表示装置２２０６に用いることができる。
【０２０７】
図１５（Ｄ）は記録媒体を備えた画像再生装置（具体的にはＤＶＤ再生装置）であり、本体２３０１、記録媒体（ＤＶＤ等）２３０２、操作スイッチ２３０３、表示部（ａ）２３０４、表示部（ｂ）２３０５等を含む。表示部（ａ）は主として画像情報を表示し、表示部（ｂ）は主として文字情報を表示するが、本発明のＥＬ表示装置はこれら表示部（ａ）、（ｂ）に用いることができる。なお、記録媒体を備えた画像再生装置には家庭用ゲーム機器なども含まれる。
【０２０８】
図１５（Ｅ）は携帯型（モバイル）コンピュータであり、本体２４０１、カメラ部２４０２、受像部２４０３、操作スイッチ２４０４、表示部２４０５等を含む。本発明のＥＬ表示装置は表示部２４０５に用いることができる。
【０２０９】
図１５（Ｆ）はパーソナルコンピュータであり、本体２５０１、筐体２５０２、表示部２５０３、キーボード２５０４等を含む。本発明のＥＬ表示装置は表示部２５０３に用いることができる。
【０２１０】
なお、将来的にＥＬ材料の発光輝度が高くなれば、出力した画像情報を含む光をレンズ等で拡大投影してフロント型若しくはリア型のプロジェクターに用いることも可能となる。
【０２１１】
また、上記電気器具はインターネットやＣＡＴＶ（ケーブルテレビ）などの電子通信回線を通じて配信された情報を表示することが多くなり、特に動画情報を表示する機会が増してきている。ＥＬ材料の応答速度は非常に高いため、ＥＬ表示装置は動画表示に好ましいが、画素間の輪郭がぼやけてしまっては動画全体もぼけてしまう。従って、画素間の輪郭を明瞭にするという本発明のＥＬ表示装置を電子装置の表示部として用いることは極めて有効である。
【０２１２】
また、ＥＬ表示装置は発光している部分が電力を消費するため、発光部分が極力少なくなるように情報を表示することが望ましい。従って、携帯情報端末、特に携帯電話や音響再生装置のような文字情報を主とする表示部にＥＬ表示装置を用いる場合には、非発光部分を背景として文字情報を発光部分で形成するように駆動することが望ましい。
【０２１３】
ここで図１６（Ａ）は携帯電話であり、本体２６０１、音声出力部２６０２、音声入力部２６０３、表示部２６０４、操作スイッチ２６０５、アンテナ２６０６を含む。本発明のＥＬ表示装置は表示部２６０４に用いることができる。なお、表示部２６０４は黒色の背景に白色の文字を表示することで携帯電話の消費電力を抑えることができる。
【０２１４】
また、図１６（Ｂ）は音響再生装置、具体的にはカーオーディオであり、本体２７０１、表示部２７０２、操作スイッチ２７０３、２７０４を含む。本発明のＥＬ表示装置は表示部２７０２に用いることができる。また、本実施例では車載用オーディオを示すが、携帯型や家庭用の音響再生装置に用いても良い。なお、表示部２７０４は黒色の背景に白色の文字を表示することで消費電力を抑えられる。これは携帯型の音響再生装置において特に有効である。
【０２１５】
以上の様に、本発明の適用範囲は極めて広く、あらゆる分野の電気器具に用いることが可能である。また、本実施例の電気器具は実施例１〜５に示したいずれの構成のＥＬ表示装置を用いても良い。
【０２１６】
〔実施例７〕
本発明を用いて作製するＥＬ素子において、三重項励起子からの燐光を発光に利用できるＥＬ材料を用いることも可能である。燐光を発光に利用できるＥＬ材料を用いた発光装置は、外部発光量子効率を飛躍的に向上させることができる。これにより、ＥＬ素子の低消費電力化、長寿命化、および軽量化が可能になる。
【０２１７】
ここで、三重項励起子を利用し、外部発光量子効率を向上させた報告を示す。
(T.Tsutsui, C.Adachi, S.Saito, Photochemical Processes in Organized Molecular Systems, ed.K.Honda, (Elsevier Sci.Pub., Tokyo,1991) p.437.)
【０２１８】
上記の論文により報告されたＥＬ材料（クマリン色素）の構造式を以下に示す。
【０２１９】
【化６】

【０２２０】
(M.A.Baldo, D.F.O'Brien, Y.You, A.Shoustikov, S.Sibley, M.E.Thompson, S.R.Forrest, Nature 395 (1998) p.151.)
【０２２１】
上記の論文により報告されたＥＬ材料（Ｐｔ錯体）の構造式を以下に示す。
【０２２２】
【化７】

【０２２３】
(M.A.Baldo, S.Lamansky, P.E.Burrrows, M.E.Thompson, S.R.Forrest, Appl.Phys.Lett.,75 (1999) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)
【０２２４】
上記の論文により報告されたＥＬ材料（Ｉｒ錯体）の構造式を以下に示す。
【０２２５】
【化８】

【０２２６】
以上のように三重項励起子からの燐光発光を利用できれば原理的には一重項励起子からの蛍光発光を用いる場合より３〜４倍の高い外部発光量子効率の実現が可能となる。
【０２２７】
なお、本実施例の構成は、実施例１〜実施例６のいずれの構成とも自由に組み合わせて実施することが可能である。
【０２２８】
【発明の効果】
本発明を実施することで、有機ＥＬ材料を成膜する際に生じる電極ホールの成膜不良を改善することができる。また、本発明においては、様々な方法及び形状で電極ホールを保護部で埋め込む方法を示しているので、条件や用途に応じて成膜する事が可能であり、陰極と陽極の間の短絡によるＥＬ層の発光不良を防ぐことができる。
【図面の簡単な説明】
【図１】 画素部の断面構造を示す図。
【図２】 画素部の断面構造を示す図。
【図３】 画素部の上面構造及び構成を示す図。
【図４】 画素部の断面構造を示す図。
【図５】 画素部の断面構造を示す図。
【図６】 ＥＬ表示装置の作製工程を示す図。
【図７】 ＥＬ表示装置の作製工程を示す図。
【図８】 ＥＬ表示装置の作製工程を示す図。
【図９】 サンプリング回路の素子構造を示す図。
【図１０】 ＥＬ表示装置の外観を示す図。
【図１１】 ＥＬ表示装置の回路ブロック構成を示す図。
【図１２】 アクティブマトリクス型のＥＬ表示装置の断面構造を示す図。
【図１３】 画素部の断面構造を示す図。
【図１４】 パッシブ型のＥＬ表示装置の断面構造を示す図。
【図１５】 電気器具の具体例を示す図。
【図１６】 電気器具の具体例を示す図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a self-luminous device (also referred to as an EL display device). In particular, a self-luminous device in which an EL element having an anode, a cathode, and a light-emitting organic material (hereinafter referred to as an organic EL material) from which EL (Electro Luminescence) is sandwiched is formed on an insulator, and the self The present invention relates to a method for manufacturing an electric appliance having a light-emitting device as a display portion (display display or display monitor).
[0002]
[Prior art]
In recent years, a display device (EL display device) using an EL element as a self-luminous element utilizing the EL phenomenon of a light-emitting organic material has been developed. Since the EL display device is a self-luminous type, it does not require a backlight like a liquid crystal display device, and has a wide viewing angle, and thus is promising as a display unit of an electric appliance.
[0003]
There are two types of EL display devices, a passive type (simple matrix type) and an active type (active matrix type), both of which are actively developed. In particular, active matrix EL display devices are currently attracting attention. In addition, low molecular organic EL materials and high molecular (polymer) organic EL materials have been studied as organic EL materials that serve as the EL layer, which can be said to be the center of the EL element, and low molecular organic EL materials are vapor deposition methods. The polymer organic EL material is formed by a coating method using a spinner.
[0004]
In either case of the low molecular organic EL material and the high molecular (polymer) organic EL material, the EL material cannot be formed in a uniform film thickness unless the film forming surface is flattened. The problem arises.
[0005]
Furthermore, when the EL layer is not uniform in thickness and part of the EL layer is not formed at the step portion, when the EL element composed of the cathode, the EL layer, and the anode is formed, there is a gap between the cathode and the anode. Electrical short circuit.
[0006]
When a short circuit occurs between the cathode and the anode, current flows in a concentrated manner between the cathode and the anode, and almost no current flows through the EL layer. As a result, the EL layer does not emit light.
[0007]
[Problems to be solved by the invention]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing an EL display device by improving the structure of an EL element. It is another object of the present invention to provide an electric appliance having such an EL display device as a display portion.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, when an organic EL material for forming an EL layer is formed, an insulator is embedded so as to flatten the uneven portion of the film formation surface, and a short circuit between the cathode and the anode in the EL element. Make the structure to prevent. Here, FIG. 1 shows a cross-sectional structure of a pixel portion of an EL display device according to the present invention.
[0009]
A switching element (specifically, a thin film transistor (TFT)) electrically connected to the pixel electrode 40 is shown in FIG. 1A. Called TFT. The current control TFT includes an active layer including a source region 31, a drain region 32, and a channel formation region 34, a gate insulating film 18, a gate electrode 35, and a first interlayer insulating film after the base film 12 is formed on the substrate 11. 20, a source wiring 36 and a drain wiring 37 are formed. The gate electrode 35 has a single gate structure, but may have a multi-gate structure.
[0010]
Next, reference numeral 38 denotes a first passivation film, and the film thickness may be 10 nm to 1 μm (preferably 200 to 500 nm). As a material, an insulating film containing silicon (in particular, a silicon nitride oxide film or a silicon nitride film is preferable) can be used.
[0011]
On the first passivation film 38, a second interlayer insulating film (which may be referred to as a flattening film) 39 is formed so as to cover each TFT, and a step formed by the TFT is flattened. The second interlayer insulating film 39 is preferably an organic resin film, and a material such as polyimide, polyamide, acrylic resin, and a resin containing a high molecular compound of siloxane may be used. Of course, an inorganic film may be used if sufficient planarization is possible.
[0012]
It is very important to flatten the step due to the TFT by the second interlayer insulating film 39. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0013]
Reference numeral 40 denotes a pixel electrode (corresponding to an anode of an EL element) made of a transparent conductive film, which is formed after a contact hole (opening) is formed in the second interlayer insulating film 39 and the first passivation film 38. The opening is formed so as to be connected to the drain wiring 37 of the current control TFT.
[0014]
In the present invention, a conductive film made of a compound of indium oxide and tin oxide is used as the pixel electrode. Further, a small amount of gallium may be added thereto. Further, a compound of indium oxide and zinc oxide or a compound of zinc oxide and gallium oxide can be used.
[0015]
In this specification, a recess formed after the pixel electrode is formed on the contact hole is referred to as an electrode hole. When the pixel electrode is formed, an EL material is formed to form an EL layer. At this time, the thickness of the EL layer in the thin film region 47 is reduced in the electrode hole 46 as shown in FIG. The extent to which the film thickness is reduced depends on the taper angle of the electrode hole, but the portion of the film formation surface that is not perpendicular to the film formation direction is difficult to be formed and tends to be thin.
[0016]
However, when the EL layer deposited here becomes thin and a cut-off portion occurs, the cathode and anode in the EL element are short-circuited, and current concentrates and flows in this short-circuit portion. . As a result, no current flows through the EL layer, so that the EL element does not emit light.
[0017]
Therefore, in order to prevent a short circuit between the cathode and the anode in the EL element, an organic resin film is formed on the pixel electrode so as to sufficiently fill the electrode hole 46, and this is patterned to form the protective portion 41b. That is, the protection part 41b is formed so as to fill the electrode hole. Note that a protective portion (not shown) may be formed so as to fill the gap between the pixel electrodes using an organic resin film.
[0018]
The organic resin film is formed by a spin coat method, exposed using a resist mask, and then etched to form a protective portion 41b as shown in FIG.
[0019]
Note that the protective portion 41b has a thickness of 0.1 to 1 μm, preferably 0.1 to 0.5 μm, at a portion that is higher than the pixel electrode when viewed from the cross section (portion indicated by Da in FIG. 1C). More preferably, the thickness is 0.1 to 0.3 μm.
[0020]
The protective portion 41b is preferably an organic resin, and a material such as a resin containing a high molecular compound of polyimide, polyamide, acrylic resin, and siloxane may be used. Furthermore, when these organic resins are used, the viscosity is 10 ^-3 Pa · s to 10 ^-1 It may be Pa · s.
[0021]
After the protective portion 41b is formed, the EL layer 42 is formed as shown in FIG. 1C, and the cathode 43 is further formed. The EL material for forming the EL layer 42 may be a low molecular organic EL material or a high molecular organic EL material.
[0022]
With the structure as shown in FIG. 1C as described above, there is a problem of short circuit between the pixel electrode 40 and the cathode 43 that occurs when the EL layer 42 is cut at the step portion of the electrode hole 46. Can be solved.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIGS. 2 is a cross-sectional view of a pixel portion of an EL display device according to the present invention, FIG. 3A is a top view thereof, and FIG. 3B is a circuit configuration thereof. Actually, a plurality of pixels are arranged in a matrix to form a pixel portion (image display portion). Note that a cross-sectional view taken along line AA ′ in FIG. 3A corresponds to FIG. Accordingly, since the same reference numerals are used in FIG. 2 and FIG. 3, both drawings should be referred to as appropriate. Further, in the top view of FIG. 3, two pixels are illustrated, but both have the same structure.
[0024]
In FIG. 2, 11 is a substrate, and 12 is an insulating film (hereinafter referred to as a base film) serving as a base. As the substrate 11, a substrate made of glass, glass ceramics, quartz, silicon, ceramics, metal, or plastic can be used.
[0025]
The base film 12 is particularly effective when a substrate containing mobile ions or a conductive substrate is used, but it need not be provided on the quartz substrate. As the base film 12, an insulating film containing silicon may be used. Note that in this specification, the “insulating film containing silicon” specifically includes silicon, oxygen, or nitrogen such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film (indicated by SiOxNy) at a predetermined ratio. An insulating film.
[0026]
In addition, it is effective to dissipate the heat generated by the TFT by providing the base film 12 with a heat dissipation effect in order to prevent the deterioration of the TFT or the EL element. Any known material can be used to provide a heat dissipation effect.
[0027]
Here, two TFTs are formed in the pixel. Reference numeral 201 denotes a switching TFT, which is an n-channel TFT, and 202 is a current control TFT, which is a p-channel TFT.
[0028]
However, in the present invention, it is not necessary to limit the switching TFT to an n-channel TFT and the current control TFT to a p-channel TFT. The switching TFT is a p-channel TFT and the current control TFT is an n-channel TFT. Alternatively, both n-channel and p-channel TFTs can be used.
[0029]
The switching TFT 201 includes a source region 13, a drain region 14, LDD regions 15a to 15d, an active layer including a high concentration impurity region 16 and channel forming regions 17a and 17b, a gate insulating film 18, gate electrodes 19a and 19b, and a first interlayer. An insulating film 20, a source wiring 21, and a drain wiring 22 are formed.
[0030]
As shown in FIG. 3, the gate electrodes 19a and 19b have a double gate structure in which the gate electrodes 19a and 19b are electrically connected by a gate wiring 211 formed of a different material (a material having a lower resistance than the gate electrodes 19a and 19b). ing. Of course, not only a double gate structure but also a so-called multi-gate structure (a structure including an active layer having two or more channel formation regions connected in series) such as a single gate or a triple gate structure may be used. The multi-gate structure is extremely effective in reducing the off-current value. In the present invention, the switching element 201 of the pixel has a multi-gate structure to realize a switching element with a low off-current value.
[0031]
The active layer is formed of a semiconductor film including a crystal structure. That is, a single crystal semiconductor film, a polycrystalline semiconductor film, or a microcrystalline semiconductor film may be used. The gate insulating film 18 may be formed of an insulating film containing silicon. Any conductive film can be used for the gate electrode, the source wiring, or the drain wiring.
[0032]
Further, in the switching TFT 201, the LDD regions 15a to 15d are provided so as not to overlap the gate electrodes 19a and 19b with the gate insulating film 18 interposed therebetween. Such a structure is very effective in reducing the off-current value.
[0033]
Note that it is more preferable to provide an offset region (a region formed of a semiconductor layer having the same composition as the channel formation region to which no gate voltage is applied) between the channel formation region and the LDD region in order to reduce the off-current value. In the case of a multi-gate structure having two or more gate electrodes, a high-concentration impurity region provided between channel formation regions is effective in reducing the off-current value.
[0034]
Next, the current control TFT 202 includes an active layer including the source region 31, the drain region 32, and the channel formation region 34, the gate insulating film 18, the gate electrode 35, the first interlayer insulating film 20, the source wiring 36, and the drain wiring 37. Formed. The gate electrode 35 has a single gate structure, but may have a multi-gate structure.
[0035]
As shown in FIG. 2, the drain of the switching TFT is connected to the gate of the current control TFT 202. Specifically, the gate electrode 35 of the current control TFT 202 is electrically connected to the drain region 14 of the switching TFT 201 via the drain wiring (also referred to as connection wiring) 22. The source wiring 36 is connected to the power supply line 212.
[0036]
The current control TFT 202 is an element for controlling the amount of current injected into the EL element 203, but it is not preferable to flow a large amount of current in consideration of deterioration of the EL element. Therefore, it is preferable to design the channel length (L) to be long so that an excessive current does not flow through the current control TFT 202. Desirably, it is set to 0.5 to 2 μA (preferably 1 to 1.5 μA) per pixel.
[0037]
The length (width) of the LDD region formed in the switching TFT 201 may be 0.5 to 3.5 μm, typically 2.0 to 2.5 μm.
[0038]
Further, as shown in FIG. 3, the wiring 36 which becomes the gate electrode 35 of the current control TFT 202 overlaps with the semiconductor film 51 formed simultaneously with the active layer through the gate insulating film in the region indicated by 50. At this time, a capacitor is formed in a region indicated by 50 and functions as a holding capacitor 50 for holding a voltage applied to the gate electrode 35 of the current control TFT 202. Further, the storage capacitor 50 forms a capacitor formed by the wiring 36 serving as a gate electrode, a first interlayer insulating film (not shown), and the power supply line 212. The drain of the current control TFT is connected to the power supply line 212, and a constant voltage is always applied.
[0039]
Further, from the viewpoint of increasing the amount of current that can be passed, the thickness of the active layer (especially the channel formation region) of the current control TFT 202 may be increased (preferably 50 to 100 nm, more preferably 60 to 80 nm). It is valid. Conversely, in the case of the switching TFT 201, from the viewpoint of reducing the off-current value, the thickness of the active layer (especially the channel formation region) should be reduced (preferably 20 to 50 nm, more preferably 25 to 40 nm). Is also effective.
[0040]
Next, reference numeral 38 denotes a first passivation film, and the film thickness may be 10 nm to 1 μm (preferably 200 to 500 nm). As a material, an insulating film containing silicon (in particular, a silicon nitride oxide film or a silicon nitride film is preferable) can be used.
[0041]
On the first passivation film 38, a second interlayer insulating film (which may be referred to as a flattening film) 39 is formed so as to cover each TFT, and a step formed by the TFT is flattened. The second interlayer insulating film 39 is preferably an organic resin film made of an organic resin, and a material such as an acrylic resin, a resin containing a polyimide, a polyamide, and a polymer compound of siloxane may be used. Needless to say, a film made of an inorganic material may be used as long as sufficient planarization is possible.
[0042]
It is very important to flatten the step due to the TFT by the second interlayer insulating film 39. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0043]
Reference numeral 40 denotes a pixel electrode (corresponding to an anode of an EL element) made of a transparent conductive film, which is formed after a contact hole (opening) is formed in the second interlayer insulating film 39 and the first passivation film 38. It is formed to be connected to the drain wiring 37 of the current control TFT 202 in the opening portion.
[0044]
In this embodiment, a conductive film made of a compound of indium oxide and tin oxide is used as the pixel electrode. Further, a small amount of gallium may be added thereto. Furthermore, a compound of indium oxide and zinc oxide can also be used.
[0045]
Next, an organic resin film made of an organic resin is formed on the pixel electrode by a spin coating method so as to fill the electrode hole 46 on the pixel electrode. Here, an acrylic resin is used as the organic resin film.
[0046]
Further, although an organic resin film made of an organic resin is formed on the pixel electrode, an insulator that can be an insulating film may be used. Note that as the insulator, an inorganic material containing silicon such as silicon oxide, silicon nitride oxide, or silicon nitride may be used.
[0047]
After forming an acrylic resin film on the entire surface, exposure is performed using a resist mask, and etching is performed to form the protective portions 41a and 41b shown in FIG.
[0048]
The protection part 41b refers to a part where the electrode hole in the pixel electrode is embedded with acrylic resin. Further, the protection part 41a is provided in the gap between the pixel electrodes. The gap between the pixel electrodes refers to a portion where the pixel electrodes are not formed in the pixel portion where the plurality of pixel electrodes are formed, for example, a portion between the pixel electrodes. This is because when the etching is performed to form the protective portion, if the material forming the second interlayer insulating film is the material forming the protective portion between the pixel electrodes, the second interlayer insulating film is also etched at the same time. This is because there is a possibility that it will end.
[0049]
The protective portions 41a and 41b have a thickness of 0.1-1 μm, preferably 0.1-0.5 μm, more preferably 0.1-0. It should be 3 μm.
[0050]
Moreover, although the case where an acrylic resin is used as the organic resin is shown for the protective portions 41a and 41b, a resin containing a high molecular compound of siloxane such as polyimide, polyamide, and cycloten may be used as a material. Furthermore, when these organic resins are used, the viscosity is 10 ^-3 Pa · s to 10 ^-1 It may be Pa · s.
[0051]
By providing the protection part 41b as described above and filling the electrode hole with an organic resin, the problem of a short circuit between the pixel electrode 40 (anode) and the cathode 43 that occurs when the EL layer 42 is cut is solved. be able to.
[0052]
A method for manufacturing the protection part 41b will be described with reference to FIGS.
In FIG. 4A, an organic resin film is formed on the pixel electrode 40 and then a protective portion 41b is formed by patterning. Da is the film thickness of the organic resin film. When this film thickness is reduced, a depression is formed at the upper portion as in the protective portion 41b of FIG.
[0053]
The degree of the depression depends on the taper angle of the electrode hole and the film thickness of the organic resin film. May not be able to fulfill.
[0054]
On the other hand, when the thickness of the organic resin film is increased, a step is generated again. Therefore, as a method for solving this, after forming an organic resin film with a film thickness of Db as shown in FIG. 4B, a protective portion 41b is formed by patterning, and the entire surface is etched to increase the film thickness. Let it be Da. Thereby, as shown in FIG. 4C, the upper portion is flattened, and the protective portion 41b having an appropriate film thickness can be formed.
[0055]
However, when the method shown in FIG. 4B is used, the pixel electrode exposed on the surface at the time of etching after patterning of the protective portion 41b is also exposed to the etching environment. Therefore, a manufacturing method in consideration of this point will be described with reference to FIGS.
[0056]
First, as shown in FIG. 5A, an organic resin film is formed on the pixel electrode 40 with a film thickness Db. This is made a film thickness Da by etching the entire surface. Furthermore, the protection part 41b is formed by patterning this.
[0057]
The protective portion 41b may be formed by patterning after forming an organic resin as shown in FIG. 4A, or by etching the entire surface after patterning as shown in FIG. 4B. May be. Further, as shown in FIG. 5A, patterning may be performed after the entire surface is etched.
[0058]
As shown in FIG. 5, the outer diameter Rb of the protection part 41 b is in a relationship of Rb> Ra with respect to the inner diameter Ra of the electrode hole 46. Note that the protective portion 41b described with reference to FIG. 4 or FIG. 5 has a structure shown in FIG. That is, the solid line 41b in FIG. 5C matches the outer shape of the protection part 41b, and the broken line 41b in FIG. 5C matches the inner diameter of the electrode hole 46.
[0059]
Next, the EL layer 42 is formed. Here, a method of forming an EL layer by forming a film obtained by dissolving a polymer organic EL material in a solvent by a spin coating method will be described. Here, the case where a high molecular organic EL material is used as the organic EL material for forming the EL layer will be described as an example, but a low molecular organic EL material can also be used.
[0060]
Typical polymer organic EL materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.
[0061]
There are various types of PPV organic EL materials. For example, the following molecular formulas have been announced.
("H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer," Polymers for Light Emitting Diodes ", Euro Display, Proceedings, 1999, p. 33-37")
[0062]
[Chemical 1]

[0063]
[Chemical 2]

[0064]
Further, polyphenylvinyl having a molecular formula described in JP-A-10-92576 can also be used. The molecular formula is:
[0065]
[Chemical 3]

[0066]
[Formula 4]

[0067]
The PVK organic EL material has the following molecular formula.
[0068]
[Chemical formula 5]

[0069]
The polymer organic EL material can be applied by dissolving in a solvent in a polymer state, or can be polymerized after being dissolved in a solvent and applied in a monomer state. When applied in the monomer state, a polymer precursor is first formed and polymerized by heating in vacuum to a polymer.
[0070]
As a specific EL layer, cyanopolyphenylene vinylene may be used for an EL layer emitting red light, polyphenylene vinylene may be used for an EL layer emitting green light, and polyphenylene vinylene or polyalkylphenylene may be used for an EL layer emitting blue light. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm).
[0071]
However, the above example is an example of the organic EL material that can be used as the EL layer of the present invention, and it is not necessary to limit to this.
[0072]
Typical solvents for dissolving the organic EL material include toluene, xylene, chlorobenzene, dichlorobenzene, anisole, chloroform, dichloromethane, γ-butyllactone, butyl cellosolve, cyclohexane, NMP (N-methyl-2-pyrrolidone), Examples of the solvent include cyclohexanone, dioxane, and THF (tetrahydrofuran).
[0073]
Further, when the EL layer 42 is formed, the EL layer easily deteriorates due to the presence of moisture and oxygen, so that the treatment atmosphere is an atmosphere with little moisture and oxygen and is performed in an inert gas such as nitrogen or argon. desirable. Further, as the processing atmosphere, since the evaporation rate of the solvent in which the EL material is dissolved can be controlled, the used solvent atmosphere may be used. In order to implement these, it is desirable to install the thin film forming apparatus of FIG. 1 in a clean booth filled with an inert gas and perform a light emitting layer forming process in the atmosphere.
[0074]
Further, as a method for forming the EL layer, an ink jet method or the like may be used in addition to the spin coating method shown here.
[0075]
In addition, when an EL layer is formed using a low molecular organic EL material, an evaporation method or the like can be used. A known material can be used as the low molecular weight organic EL material.
[0076]
After the EL layer 42 is formed as described above, the cathode 43, the protective electrode 44, and the second passivation film 45 made of a light-shielding conductive film are formed next. In the present embodiment, a conductive film made of MgAg is used as the cathode 43, and a conductive film made of aluminum is used as the protective electrode 44. Further, as the second passivation film 45, a silicon nitride film having a thickness of 10 nm to 1 μm (preferably 200 to 500 nm) is used.
[0077]
Since the EL layer is vulnerable to heat as described above, it is desirable that the cathode 43 and the second passivation film 45 be formed at as low a temperature as possible (preferably in a temperature range from room temperature to 120 ° C.). Therefore, it can be said that a plasma CVD method, a vacuum deposition method, or a solution coating method (spin coating method) is a desirable film forming method.
[0078]
The completed substrate is called an active matrix substrate, and a counter substrate (not shown) is provided so as to face the active matrix substrate. In this embodiment, a glass substrate is used as the counter substrate. As the counter substrate, a substrate made of plastic or ceramics may be used.
[0079]
Further, the active matrix substrate and the counter substrate are bonded with a sealant (not shown) to form a sealed space (not shown). In this embodiment, the sealed space is filled with argon gas. Of course, it is also possible to arrange a desiccant such as barium oxide or an antioxidant in the sealed space.
[0080]
Furthermore, if a metal having a low work function and easily oxidized or a hygroscopic metal is formed on the surface of the counter substrate on the active matrix substrate side, a function of capturing oxygen and a hygroscopic function can be provided. Note that it is more effective to form a film of these metals after forming irregularities on the counter substrate with an organic resin such as a photosensitive acrylic resin because the surface area can be increased.
[0081]
【Example】
[Example 1]
A method for simultaneously manufacturing TFTs of a pixel portion and a driver circuit portion provided in the periphery thereof in an embodiment of the present invention will be described with reference to FIGS. However, in order to simplify the description, a CMOS circuit, which is a basic circuit, is illustrated with respect to the drive circuit.
[0082]
First, as shown in FIG. 6A, a base film 301 is formed to a thickness of 300 nm over a glass substrate 300. In this embodiment, a 100 nm thick silicon nitride oxide film and a 200 nm silicon nitride oxide film are stacked as the base film 301. At this time, the nitrogen concentration in contact with the glass substrate 300 is preferably set to 10 to 25 wt%. Of course, the element may be formed directly on the quartz substrate without providing a base film.
[0083]
Next, an amorphous silicon film (not shown) having a thickness of 50 nm is formed on the base film 301 by a known film formation method. Note that the semiconductor film is not limited to an amorphous silicon film, and any semiconductor film including an amorphous structure (including a microcrystalline semiconductor film) may be used. Further, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used. The film thickness may be 20 to 100 nm.
[0084]
Then, the amorphous silicon film is crystallized by a known technique to form a crystalline silicon film (also referred to as a polycrystalline silicon film or a polysilicon film) 302. Known crystallization methods include a thermal crystallization method using an electric furnace, a laser annealing crystallization method using laser light, and a lamp annealing crystallization method using infrared light. In this embodiment, crystallization is performed using excimer laser light using XeCl gas.
[0085]
In this embodiment, a pulse oscillation type excimer laser beam processed into a linear shape is used. However, a rectangular shape, a continuous oscillation type argon laser beam, or a continuous oscillation type excimer laser beam may be used. .
[0086]
In this embodiment, a crystalline silicon film is used as an active layer of a TFT, but an amorphous silicon film can also be used. It is also possible to form the active layer of the switching TFT that needs to reduce the off-current with an amorphous silicon film and form the active layer of the current control TFT with a crystalline silicon film. Since the amorphous silicon film has low carrier mobility, it is difficult for an electric current to flow and an off current is difficult to flow. That is, the advantages of both an amorphous silicon film that hardly allows current to flow and a crystalline silicon film that easily allows current to flow can be utilized.
[0087]
Next, as shown in FIG. 6B, a protective film 303 made of a silicon oxide film is formed on the crystalline silicon film 302 to a thickness of 130 nm. This thickness may be selected in the range of 100 to 200 nm (preferably 130 to 170 nm). Any other film may be used as long as it is an insulating film containing silicon. This protective film 303 is provided in order to prevent the crystalline silicon film from being directly exposed to plasma when an impurity is added and to enable fine concentration control.
[0088]
Then, resist masks 304 a and 304 b are formed thereon, and an impurity element imparting n-type (hereinafter referred to as an n-type impurity element) is added through the protective film 303. Note that as the n-type impurity element, an element typically belonging to Group 15, typically phosphorus or arsenic can be used. In this example, phosphine (PH _Three ) Using a plasma (ion) doping method in which plasma is excited without mass separation, and phosphorus is 1 × 10 ¹⁸ atoms / cm ^Three Add at a concentration of Of course, an ion implantation method for performing mass separation may be used.
[0089]
In the n-type impurity region 305 formed by this process, an n-type impurity element contains 2 × 10 6. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three (Typically 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three ) Adjust the dose so that it is included at the concentration of
[0090]
Next, as shown in FIG. 6C, the protective film 303 and the resists 304a and 304b are removed, and the added elements belonging to Group 15 are activated. As the activation means, a known technique may be used. In this embodiment, activation is performed by irradiation with excimer laser light. Of course, the pulse oscillation type or the continuous oscillation type may be used, and it is not necessary to limit to the excimer laser beam. However, since the purpose is to activate the added impurity element, it is preferable to irradiate with energy that does not melt the crystalline silicon film. Note that laser light may be irradiated with the protective film 303 attached.
[0091]
Note that activation by heat treatment may be used in combination with the activation of the impurity element by the laser beam. When activation by heat treatment is performed, heat treatment at about 450 to 550 ° C. may be performed in consideration of the heat resistance of the substrate.
[0092]
By this step, an end portion of the n-type impurity region 305, that is, a boundary portion (junction portion) between the n-type impurity region 305 and a region not added with the n-type impurity element is clarified. This means that when the TFT is later completed, the LDD region and the channel formation region can form a very good junction.
[0093]
Next, as shown in FIG. 6D, unnecessary portions of the crystalline silicon film are removed, and island-shaped semiconductor films (hereinafter referred to as active layers) 306 to 309 are formed.
[0094]
Next, as illustrated in FIG. 6E, a gate insulating film 310 is formed so as to cover the active layers 306 to 309. As the gate insulating film 310, an insulating film containing silicon with a thickness of 10 to 200 nm, preferably 50 to 150 nm may be used. This may be a single layer structure or a laminated structure. In this embodiment, a silicon nitride oxide film having a thickness of 110 nm is used.
[0095]
Next, a conductive film having a thickness of 200 to 400 nm is formed and patterned to form gate electrodes 311 to 315. The ends of the gate electrodes 311 to 315 can be tapered. Note that in this embodiment, the gate electrode and a wiring (hereinafter referred to as a gate wiring) electrically connected to the gate electrode are formed using different materials. Specifically, a material having a resistance lower than that of the gate electrode is used for the gate wiring. This is because a material that can be finely processed is used for the gate electrode, and a material that has a low wiring resistance is used for the gate wiring even though it cannot be finely processed. Of course, the gate electrode and the gate wiring may be formed of the same material.
[0096]
The gate electrode may be formed of a single-layer conductive film, but it is preferable to form a stacked film of two layers or three layers as necessary. Any known conductive film can be used as the material of the gate electrode. However, a material that can be finely processed as described above, specifically, that can be patterned to a line width of 2 μm or less is preferable.
[0097]
Typically, a film made of an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si), or a nitride film of the element (Typically a tantalum nitride film, a tungsten nitride film, a titanium nitride film), an alloy film (typically, a Mo—W alloy, a Mo—Ta alloy), or a silicide film of the above elements (typical) Specifically, a tungsten silicide film or a titanium silicide film) can be used. Of course, it may be used as a single layer or may be laminated.
[0098]
In this embodiment, a laminated film composed of a tantalum nitride (TaN) film having a thickness of 50 nm and a tantalum (Ta) film having a thickness of 350 nm is used. This may be formed by sputtering. Further, when an inert gas such as Xe or Ne is added as a sputtering gas, peeling of the film due to stress can be prevented.
[0099]
At this time, the gate electrode 312 is formed so as to overlap a part of the n-type impurity region 305 with the gate insulating film 310 interposed therebetween. This overlapped portion later becomes an LDD region overlapping with the gate electrode. Note that although the gate electrodes 313 and 314 appear to be two in the cross section, they are actually electrically connected.
[0100]
Next, as shown in FIG. 7A, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligning manner using the gate electrodes 311 to 315 as a mask. The impurity regions 316 to 323 thus formed are adjusted so that phosphorus is added at a concentration of 1/2 to 1/10 (typically 1/3 to 1/4) of the n-type impurity region 305. Specifically, 1 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three (Typically 3x10 ¹⁷ ~ 3x10 ¹⁸ atoms / cm ^Three ) Is preferred.
[0101]
Next, as shown in FIG. 7B, resist masks 324a to 324d are formed so as to cover the gate electrodes and the like, and an n-type impurity element (phosphorus in this embodiment) is added to contain phosphorus at a high concentration. Impurity regions 325 to 329 are formed. Again, phosphine (PH _Three The concentration of phosphorus in this region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ^{twenty one} atoms / cm ^Three ).
[0102]
Although the source region and the drain region of the n-channel TFT are formed by this process, in the switching TFT, a part of the n-type impurity regions 319 to 321 formed in the process of FIG. This remaining region corresponds to the LDD regions 15a to 15d of the switching TFT 201 in FIG.
[0103]
Next, as shown in FIG. 7C, the resist masks 324a to 324d are removed, and a new resist mask 332 is formed. Then, a p-type impurity element (boron in this embodiment) is added to form impurity regions 333 to 336 containing boron at a high concentration. Here, diborane (B ₂ H ₆ 3 × 10 by ion doping method using ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three (Typically 5 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three B) Add boron to achieve a concentration.
[0104]
The impurity regions 333 to 336 are already 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three However, the boron added here is added at a concentration at least three times that of phosphorus. Therefore, the n-type impurity region formed in advance is completely inverted to the p-type and functions as a p-type impurity region.
[0105]
Next, after removing the resist mask 332, the n-type or p-type impurity element added at each concentration is activated. As the activation means, furnace annealing, laser annealing, and lamp annealing can be used. In this embodiment, heat treatment is performed in an electric furnace in a nitrogen atmosphere at 550 ° C. for 4 hours.
[0106]
At this time, it is important to eliminate oxygen in the atmosphere as much as possible. This is because the presence of even a small amount of oxygen oxidizes the exposed surface of the gate electrode, which increases resistance and makes it difficult to make ohmic contact later. Therefore, the oxygen concentration in the treatment atmosphere in the activation step is 1 ppm or less, preferably 0.1 ppm or less.
[0107]
Next, when the activation process is completed, a gate wiring 337 having a thickness of 300 nm is formed as shown in FIG. As a material for the gate wiring 337, a metal containing aluminum (Al) or copper (Cu) as a main component (occupying 50 to 100% as a composition) may be used. As shown in FIG. 3, the gate wiring 211 and the switching TFT gate electrodes 19a and 19b (313 and 314 in FIG. 6E) are electrically connected as shown in FIG.
[0108]
With such a structure, the wiring resistance of the gate wiring can be extremely reduced, so that an image display region (pixel portion) having a large area can be formed. That is, the pixel structure of this embodiment is extremely effective in realizing an EL display device having a screen size of 10 inches or more (or 30 inches or more) diagonally.
[0109]
Next, as shown in FIG. 8A, a first interlayer insulating film 338 is formed. As the first interlayer insulating film 338, an insulating film containing silicon may be used as a single layer, or a stacked film in which two or more kinds of insulating films containing silicon are combined may be used. The film thickness may be 400 nm to 1.5 μm. In this embodiment, a structure is formed in which a silicon oxide film having a thickness of 800 nm is stacked on a silicon nitride oxide film having a thickness of 200 nm.
[0110]
Further, a hydrogenation treatment is performed by performing a heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step in which the dangling bonds of the semiconductor film are terminated with hydrogen by thermally excited hydrogen. As another means for hydrogenation, plasma hydrogenation (using hydrogen generated by plasmatization) may be performed.
[0111]
Note that the hydrogenation treatment may be performed while the first interlayer insulating film 338 is formed. That is, a hydrogenation treatment may be performed as described above after a 200 nm thick silicon nitride oxide film is formed, and then the remaining 800 nm thick silicon oxide film may be formed.
[0112]
Next, contact holes are formed in the first interlayer insulating film 338 and the gate insulating film 310, and source wirings 339 to 342 and drain wirings 343 to 345 are formed. In this embodiment, these electrodes are formed as a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film 150 nm is continuously formed by sputtering. Of course, other conductive films may be used.
[0113]
Next, a first passivation film 346 is formed with a thickness of 50 to 500 nm (typically 200 to 300 nm). In this embodiment, a silicon nitride oxide film having a thickness of 300 nm is used as the first passivation film 346. This may be replaced by a silicon nitride film.
[0114]
Prior to the formation of the silicon nitride oxide film, H ₂ , NH _Three It is effective to perform plasma treatment using a gas containing isohydrogen. Hydrogen excited by this pretreatment is supplied to the first interlayer insulating film 338 and heat treatment is performed, whereby the film quality of the first passivation film 346 is improved. At the same time, hydrogen added to the first interlayer insulating film 338 diffuses to the lower layer side, so that the active layer can be effectively hydrogenated.
[0115]
Next, as shown in FIG. 8B, a second interlayer insulating film 347 made of an organic resin is formed. As the organic resin, a polymer compound of polyimide, polyamide, acrylic resin, or siloxane can be used as a material. In particular, since the second interlayer insulating film 347 has a strong meaning of flattening, an acrylic resin excellent in flatness is preferable. In this embodiment, the acrylic resin film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. The thickness is preferably 1 to 5 μm (more preferably 2 to 4 μm).
[0116]
Next, contact holes are formed in the second interlayer insulating film 347 and the first passivation film 346, and a pixel electrode 348 that is electrically connected to the drain wiring 345 is formed. In this embodiment, an indium tin oxide (ITO) film having a thickness of 110 nm is formed and patterned to form a pixel electrode. Alternatively, a transparent conductive film in which 2 to 20% zinc oxide (ZnO) is mixed with indium oxide may be used. This pixel electrode becomes the anode of the EL element.
[0117]
Next, as shown in FIG. 8C, protective portions 349a and 349b made of an organic resin are formed. The protective portions 349a and 349b may be formed by patterning a resin film such as an acrylic resin film or a polyimide film having a thickness of 1 to 2 μm. As shown in FIG. 3, the protective portions 349a and 349b are formed in a gap between the pixel electrode and the pixel electrode and an electrode hole.
[0118]
Next, the EL layer 350 is formed. Specifically, the organic EL material to be the EL layer 350 is dissolved in a solvent such as chloroform, dichloromethane, xylene, toluene, tetrahydrofuran, N-methylpyrrolidone and applied by a spin coating method, and then the heat treatment is performed to volatilize the solvent. Let Thus, a film (EL layer) made of an organic EL material is formed.
[0119]
In this embodiment, the EL material is deposited to a thickness of 80 nm and then volatilized by heat treatment for 1 to 5 minutes on a hot plate at 80 to 150 ° C.
[0120]
Note that a known material can be used as the EL material. As the known material, it is preferable to use an organic material in consideration of the driving voltage. Note that although the EL layer 350 has a single layer structure in this embodiment, an electron injection layer, an electron transport layer, a hole transport layer, a hole injection layer, an electron blocking layer, or a hole element layer are provided as necessary. A laminated structure may be used. In this embodiment, an example in which an MgAg electrode is used as the cathode 351 of the EL element is shown, but other known materials may be used.
[0121]
After the EL layer 350 is formed, a cathode (MgAg electrode) 351 is formed by a vacuum evaporation method. Note that the EL layer 350 may have a thickness of 80 to 200 nm (typically 100 to 120 nm), and the cathode 351 may have a thickness of 180 to 300 nm (typically 200 to 250 nm).
[0122]
Further, a protective electrode 352 is provided on the cathode 351. As the protective electrode 352, a conductive film containing aluminum as its main component may be used. The protective electrode 352 may be formed by a vacuum evaporation method using a mask.
[0123]
Finally, a second passivation film 353 made of a silicon nitride film is formed to a thickness of 300 nm. Actually, the protective electrode 352 plays a role of protecting the EL layer from moisture and the like, but the reliability of the EL element can be further improved by forming the second passivation film 353.
[0124]
In the case of this embodiment, as shown in FIG. 8C, the active layer of the n-channel type 205 includes a source region 355, a drain region 356, an LDD region 357, and a channel formation region 358, and the LDD region 357 has gate insulation. The gate electrode 312 overlaps with the film 310 interposed therebetween.
[0125]
The reason why the LDD region is formed only on the drain region side is to prevent the operation speed from being lowered. In addition, the n-channel TFT 205 does not need to care about the off-current value, and it is better to focus on the operation speed than that. Therefore, it is desirable that the LDD region 357 is completely overlapped with the gate electrode and the resistance component is reduced as much as possible. That is, it is better to eliminate the so-called offset.
[0126]
Thus, an active matrix substrate having a structure as shown in FIG. 8C is completed.
[0127]
By the way, the active matrix substrate of this embodiment can provide extremely high reliability and improve the operating characteristics by arranging TFTs having an optimal structure not only in the pixel portion but also in the drive circuit portion.
[0128]
First, a TFT having a structure that reduces hot carrier injection so as not to decrease the operating speed as much as possible is used as an n-channel TFT 205 of a CMOS circuit that forms a drive circuit portion. Note that the drive circuit here includes a shift register, a buffer, a level shifter, a sampling circuit (sample and hold circuit), and the like. In the case of performing digital driving, a signal conversion circuit such as a D / A converter may be included.
[0129]
Note that the sampling circuit in the driver circuit is a little special compared to other circuits, and a large current flows in both directions in the channel formation region. That is, the roles of the source region and the drain region are interchanged. Furthermore, it is necessary to keep the off-current value as low as possible, and in that sense, it is desirable to dispose a TFT having an intermediate function between the switching TFT and the current control TFT.
[0130]
Therefore, it is desirable to arrange a TFT having a structure as shown in FIG. 9 as the n-channel TFT forming the sampling circuit. As shown in FIG. 9, part of the LDD regions 901a and 901b overlaps with the gate electrode 903 with the gate insulating film 902 interposed therebetween. This effect is a countermeasure against deterioration against hot carrier injection that occurs when a current is passed. In the case of a sampling circuit, it is different in that it is provided on both sides with a channel formation region 904 interposed therebetween.
[0131]
Actually, after completion of FIG. 8C, it is preferable to package (enclose) with a cover material such as highly airtight glass, quartz, or plastic so as not to be exposed to the outside air. At that time, a hygroscopic agent such as barium oxide or an antioxidant may be disposed inside the cover material.
[0132]
In addition, when the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting the terminal routed from the element or circuit formed on the substrate and the external signal terminal is attached. Completed as a product. In this specification, such a state that can be shipped is referred to as an EL display device (or EL module).
[0133]
Here, the configuration of the active matrix EL display device of this embodiment will be described with reference to the perspective view of FIG. The active matrix EL display device of this embodiment includes a pixel portion 602, a gate side driver circuit 603, and a source side driver circuit 604 formed on a glass substrate 601. The switching TFT 605 in the pixel portion is an n-channel TFT, and is arranged at the intersection of the gate wiring 606 connected to the gate side driving circuit 603 and the source wiring 607 connected to the source side driving circuit 604. The drain of the switching TFT 605 is connected to the gate of the current control TFT 608.
[0134]
Further, the source side of the current control TFT 608 is connected to the power supply line 609. In the structure as in this embodiment, a ground potential (ground potential) is applied to the power supply line 609. An EL element 610 is connected to the drain of the current control TFT 608. A predetermined voltage (3 to 12 V, preferably 3 to 5 V) is applied to the anode of the EL element 610.
[0135]
The FPC 611 serving as an external input / output terminal is provided with connection wirings 612 and 613 for transmitting signals to the drive circuit portion, and connection wiring 614 connected to the power supply line 609.
[0136]
FIG. 11 shows an example of a circuit configuration of the EL display device shown in FIG. The EL display device of this embodiment includes a source side driver circuit 801, a gate side driver circuit (A) 807, a gate side driver circuit (B) 811, and a pixel portion 806. Note that in this specification, a drive circuit portion is a generic name including a source side drive circuit and a gate side drive circuit.
[0137]
The source side driver circuit 801 includes a shift register 802, a level shifter 803, a buffer 804, and a sampling circuit (sample and hold circuit) 805. The gate side driver circuit (A) 807 includes a shift register 808, a level shifter 809, and a buffer 810. The gate side driver circuit (B) 811 has a similar structure.
[0138]
Here, the driving voltages of the shift registers 802 and 808 are 5 to 16 V (typically 10 V), and an n-channel TFT used in a CMOS circuit forming the circuit has a structure indicated by 205 in FIG. Is suitable.
[0139]
As the level shifters 803 and 809 and the buffers 804 and 810, a CMOS circuit including the n-channel TFT 205 in FIG. In addition, it is effective in improving the reliability of each circuit that the gate wiring has a multi-gate structure such as a double gate structure or a triple gate structure.
[0140]
In addition, since the sampling circuit 805 needs to reduce the off current value in addition to the inversion of the source region and the drain region, a CMOS circuit including the n-channel TFT 208 in FIG. 9 is suitable.
[0141]
In addition, the pixel portion 806 includes pixels having the structure shown in FIG.
[0142]
In addition, the said structure can be easily implement | achieved by manufacturing TFT according to the manufacturing process shown to FIGS. Further, in this embodiment, only the configuration of the pixel portion and the drive circuit portion is shown. However, according to the manufacturing process of this embodiment, a signal dividing circuit, a D / A converter circuit, an operational amplifier circuit, a γ correction circuit, etc. It is considered that logic circuits other than the drive circuit can be formed on the same substrate, and further, a memory portion, a microprocessor, and the like can be formed.
[0143]
Further, the EL module of this embodiment including the cover material will be described with reference to FIGS. Note that the reference numerals used in FIGS. 10 and 11 are cited as necessary.
[0144]
FIG. 12A is a top view showing a state in which a sealing structure is provided in the state shown in FIG. Reference numeral 602 indicated by a dotted line denotes a pixel portion, 603 denotes a gate side driver circuit, and 604 denotes a source side driver circuit. The sealing structure of the present invention is a structure in which a filler (not shown), a cover material 1101, a seal material (not shown), and a frame material 1102 are provided in the state of FIG.
[0145]
Here, FIG. 12B is a cross-sectional view taken along line AA ′ of FIG. In FIGS. 12A and 12B, the same reference numerals are used for the same parts.
[0146]
As shown in FIG. 12B, a pixel portion 602 and a gate side driver circuit 603 are formed over a substrate 601, and the pixel portion 602 includes a current control TFT 202 and a pixel electrode 348 electrically connected thereto. A plurality of pixels are included. The gate driver circuit 603 is formed using a CMOS circuit in which an n-channel TFT 205 and a p-channel TFT 206 are complementarily combined.
[0147]
The pixel electrode 348 functions as an anode of the EL element. In addition, a protective film 349a is formed on both ends of the pixel electrode 348, and an EL layer 350 and a cathode 351 are formed on the protective film 349a. A protective electrode 352 and a second passivation film 353 are formed thereon. Of course, as described above, the structure of the EL element may be reversed and the pixel electrode may be a cathode.
[0148]
In this embodiment, the protective electrode 352 also functions as a wiring common to all pixels, and is electrically connected to the FPC 611 through the connection wiring 612. Further, all elements included in the pixel portion 602 and the gate side driving circuit 603 are covered with the second passivation film 353. Although the second passivation film 353 can be omitted, it is preferable to provide the second passivation film 353 to shield each element from the outside.
[0149]
Next, a filler 1103 is provided so as to cover the EL element. This filler 1103 also functions as an adhesive for bonding the cover material 1101. As the filler 1103, PVC (polyvinyl chloride), epoxy resin, silicon resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant (not shown) inside the filler 1103 because the moisture absorption effect can be maintained. At this time, the desiccant may be added to the filler, or may be sealed in the filler.
[0150]
In this embodiment, as the cover material 1101, a material made of glass, plastic, and ceramics can be used. It is effective to add a desiccant such as barium oxide in the interior of the filler 1103 in advance.
[0151]
Next, after the cover material 1101 is bonded using the filler 1103, the frame material 1102 is attached so as to cover the side surface (exposed surface) of the filler 1103. The frame material 1102 is bonded by a seal material (functioning as an adhesive) 1104. At this time, a photocurable resin is preferably used as the sealant 1104, but a thermosetting resin may be used if the heat resistance of the EL layer permits. Note that the sealing material 1104 is preferably a material that does not transmit moisture and oxygen as much as possible. Further, a desiccant may be added inside the sealing material 1104.
[0152]
By encapsulating the EL element in the filler 1103 using the above-described method, the EL element can be completely blocked from the outside, and a substance that promotes deterioration due to oxidation of the EL layer such as moisture or oxygen from the outside can be obtained. Intrusion can be prevented. Accordingly, a highly reliable EL display device can be manufactured.
[0153]
[Example 2]
In Example 1, after applying an organic resin over the entire surface of the pixel electrode, patterning is performed using an exposure apparatus to form a protective portion embedded in the gap between the electrode hole and the pixel electrode with the organic resin, and then the EL layer is formed. In this embodiment, an organic resin is applied over the entire surface of the pixel electrode, and then planarization is performed using an etch-back method without patterning. This is a method for etching other than the organic resin embedded in the gap between the electrode hole and the pixel electrode.
[0154]
Here, FIG. 13 shows a cross-sectional structure of a pixel portion of an EL display device according to the present invention.
[0155]
FIG. 13A shows a pixel electrode 1040 and a current control TFT electrically connected to the pixel electrode 1040. The current control TFT includes an active layer including a source region 1031, a drain region 1032, and a channel formation region 1034, a gate insulating film 1018, a gate electrode 1035, and a first interlayer insulating film after a base film 1012 is formed on a substrate 1011. 1020, a source wiring 1036 and a drain wiring 1037 are formed. Note that the gate electrode 1035 has a single gate structure, but may have a multi-gate structure.
[0156]
Next, reference numeral 1038 denotes a first passivation film, and the film thickness may be 10 nm to 1 μm (preferably 200 to 500 nm). As a material, an insulating film containing silicon (in particular, a silicon nitride oxide film or a silicon nitride film is preferable) can be used.
[0157]
On the first passivation film 1038, a second interlayer insulating film (which may be referred to as a planarization film) 1039 is formed so as to cover each TFT, and a step formed by the TFT is planarized. The second interlayer insulating film 1039 is preferably an organic resin film, and a resin containing a polymer compound of polyimide, polyamide, acrylic resin, or siloxane is preferably used as the material. Of course, an inorganic film may be used if sufficient planarization is possible.
[0158]
It is very important to flatten the step due to the TFT by the second interlayer insulating film 1039. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0159]
Reference numeral 1040 denotes a pixel electrode (corresponding to an anode of an EL element) made of a transparent conductive film, which is formed after a contact hole (opening) is formed in the second interlayer insulating film 1039 and the first passivation film 1038. The opening is formed so as to be connected to the drain wiring 1037 of the current control TFT.
[0160]
In this embodiment, a conductive film made of a compound of indium oxide and tin oxide is used as the pixel electrode. Further, a small amount of gallium may be added thereto. Furthermore, a compound of indium oxide and zinc oxide can also be used.
[0161]
Next, an organic resin film 1041 using an organic resin as a material is formed over the pixel electrode. Examples of the organic resin include materials such as polyamide, polyimide, acrylic resin, and a resin containing a high molecular compound of siloxane, and these may be used. Here, acrylic ester resin, acrylic resin, methacrylic resin, which are acrylic resins, may be used. Resins such as acid ester resins and methacrylic acid resins are used.
As a resin containing a high molecular compound of siloxane, there is cycloten.
[0162]
Here, an organic resin film made of an organic resin is formed over the pixel electrode, but an insulator that can be an insulating film may be used.
[0163]
As the insulator, an insulating film containing silicon such as silicon oxide, silicon nitride oxide, or silicon nitride is preferably used.
[0164]
The film thickness (Dc) of the organic resin film 1041 is preferably 0.1 to 2 μm, more preferably 0.2 to 0.6 μm.
[0165]
After the organic resin film 1041 is formed, the entire surface of the organic resin film 1041 is etched to terminate the etching when Dc = 0, so that the acrylic resin embedded in the electrode holes remains, and the protective portion 1041b is formed.
[0166]
Note that dry etching is preferable as an etching method. First, after introducing an etching gas suitable for the organic resin material to be etched into the vacuum chamber, a high frequency voltage is applied to the electrodes to generate plasma, and the etching gas is decomposed in a plasma atmosphere.
[0167]
In the etching gas decomposed in the plasma atmosphere, charged particles such as positive ions, negative ions, and electrons and neutral active species exist in a discrete state. When these etching species are adsorbed to the material to be etched, a surface chemical reaction occurs to generate an etching product. When the etching product is removed, etching is performed.
[0168]
In the case where an acrylic resin is used as the material for the protective film, it is desirable to use a gas mainly composed of oxygen as an etching gas in etching.
[0169]
In this embodiment, oxygen, helium, and carbon tetrafluoride (CF) are used as etching gases mainly composed of oxygen. _Four Is used. Other materials include dicarbon hexafluoride (C ₂ F ₆ ) May be used.
[0170]
In these etching gases, oxygen is desirably 60% or more of the entire etching gas.
[0171]
As shown in this embodiment, after an organic resin film is formed on the pixel electrode by using a spin coating method, the whole surface is etched to form a protective portion 1041b in the electrode hole 1046 as shown in FIG. Etch in the direction of the arrow to form. Note that the exposed surface of the protection portion 1041b and the exposed surface of the pixel electrode 1040 formed here are in the same plane as shown in FIG.
[0172]
Note that the etching time at this time is checked in advance, and the etching is finished when the organic resin film on the pixel electrode 1040 except the protective portion 1041b is just removed. Thereby, the upper surface of the pixel electrode 1040 and the upper surface of the protection part 1041b become the same flat surface.
[0173]
When these organic resins are used, the viscosity is 10 ^-3 Pa · s to 10 ^-1 It may be Pa · s.
[0174]
When the protective portion 1041b is formed, a material in which an EL material is dissolved in a solvent is formed by a spin coating method in order to form the EL layer 1042, as shown in FIG.
[0175]
When the EL layer 1042 is formed, a cathode 1043 and a protective electrode 1044 are further formed.
[0176]
With the structure as shown in FIG. 13C as described above, there is a problem of short circuit between the pixel electrode 1040 and the cathode 1043 that occurs when the EL layer 1042 is cut at the step portion of the electrode hole. Can be solved.
[0177]
Note that a top view in the case where the protective portion 1041b over the pixel electrode 1040 has the same shape as the electrode hole 1046 as shown in this embodiment is shown in FIG.
[0178]
Further, the configuration of the present embodiment can be freely combined with the configuration of the first embodiment.
[0179]
Example 3
In the second embodiment, a method for forming a protective film by etching, a so-called etch back method, has been described. However, the etch back method is not suitable depending on the type of the protective film, and an area that can be planarized is several μm to several tens μm. Therefore, it is also possible to form the protective portion using chemical mechanical polishing (CMP). Therefore, this embodiment will also be described with reference to FIG.
[0180]
In this embodiment, as shown in FIG. 13A of Embodiment 2, the organic resin film 1041 is formed to a film thickness of Dc (> 0), and then the surface plate facing the organic resin film 1041. The protective portion 1041b is formed using so-called CMP, in which the polishing pad (slurry) is flowed while pressing the polishing pad stretched on the substrate with a constant pressure and rotating the substrate and the surface plate, and polishing is performed until Dc = 0. .
[0181]
The slurry used for CMP is obtained by dispersing abrasive particles called abrasive grains in a pH-adjusted aqueous solution, and a different slurry may be used depending on the film to be polished.
[0182]
In this embodiment, since acrylic resin is used as the film to be polished, silica-based slurry (SiO ₂ ) And ceria-based slurry (CeO) ₂ ) And fumed silica-based slurry (SiCl) _Four It is preferable to use a slurry such as However, as the slurry, alumina-based slurry (Al ₂ O _Three ) Or zeolite-based slurry, and these may be used.
[0183]
Moreover, since the electric potential (zeta electric potential) between the liquid in a slurry and an abrasive grain (silica particle) influences a processing precision, it is necessary to adjust by optimizing pH value.
[0184]
When polishing using CMP, it is difficult to determine the end point of polishing. If it is excessively polished, the pixel electrode is also polished. Therefore, a method of forming a film with extremely slow processing speed as a stopper for CMP or clarifying the relationship between processing time and processing speed through experiments in advance and terminating CMP when a certain processing time has come. Unnecessary polishing can be prevented by removing.
[0185]
As described above, by using CMP, the protective portion 1041b can be formed regardless of the thickness of the film to be polished and the type of film.
[0186]
The configuration of this embodiment can be freely combined with the configurations of Embodiments 1 and 2.
[0187]
Example 4
In this embodiment, the case where the present invention is used in a passive type (simple matrix type) EL display device will be described with reference to FIG. In FIG. 14, 1301 is a substrate made of plastic, and 1306 is an anode made of a transparent conductive film. Note that the substrate 1301 may be made of a material such as glass or quartz.
[0188]
In this embodiment, a compound of indium oxide and zinc oxide is formed as a transparent conductive film by a vapor deposition method. Although not shown in FIG. 14, a plurality of anodes are arranged in stripes in a direction perpendicular to the paper surface.
[0189]
In addition, the protection portion 1303 of the present invention is formed so as to fill the space between the anodes 1302 arranged in a stripe shape. The protection part 1303 is formed along the anode 1302 in a direction perpendicular to the paper surface. In addition, what is necessary is just to form the protective part 1303 in a present Example using the same material by the method shown in Examples 1-3.
[0190]
Next, an EL layer 1304 made of a polymer organic EL material is formed. The same organic EL material as that used in Example 1 may be used. Since these EL layers are formed along the grooves formed by the protective film 1302, they are arranged in stripes in a direction perpendicular to the paper surface.
[0191]
Thereafter, although not shown in FIG. 14, a plurality of cathodes and protective electrodes are arranged in stripes so that the direction parallel to the paper surface is the longitudinal direction and perpendicular to the anode 1302. In this embodiment, the cathode 1305 is made of MgAg, and the protective electrode 1306 is made of an aluminum alloy film, which are formed by vapor deposition. Further, although not shown, the protective electrode 1306 is extended to a portion where an FPC is attached later so that a predetermined voltage is applied.
[0192]
Although not shown here, when the protective electrode 1306 is formed, a silicon nitride film may be provided as a passivation film.
[0193]
As described above, an EL element is formed over the substrate 1301. In this embodiment, since the lower electrode is a light-transmitting anode, light generated in the EL layers 1304a to 1304c is emitted to the lower surface (substrate 1301). However, the structure of the EL element can be reversed, and the lower electrode can be a light-shielding cathode. In that case, light generated in the EL layer is emitted to the upper surface (the side opposite to the substrate 1301).
[0194]
Next, a ceramic substrate is prepared as the cover material 1307. In the structure of the present embodiment, a ceramic substrate was used because the light shielding property was sufficient. Of course, when the structure of the EL element is reversed as described above, the cover material should be translucent, so it is made of plastic or glass. A substrate may be used.
[0195]
When the cover material 1307 is prepared in this way, the cover material 1307 is bonded with a filler 1308 to which barium oxide is added as a desiccant (not shown). Thereafter, the frame material 1310 is attached using a sealing material 1309 made of an ultraviolet curable resin. In this embodiment, a stainless steel material is used as the frame material 1310. Finally, an FPC 1312 is attached via an anisotropic conductive film 1311 to complete a passive EL display device.
[0196]
In addition, the structure of a present Example can be implemented in combination with any structure of Example 1- Example 3 freely.
[0197]
Example 5
When an active matrix EL display device is manufactured by implementing the present invention, it is effective to use a silicon substrate (silicon wafer) as a substrate. When a silicon substrate is used as the substrate, the switching element formed in the pixel portion, the current control element, or the drive element formed in the drive circuit portion is used with a MOSFET manufacturing technique used in conventional ICs and LSIs. Can be produced.
[0198]
A MOSFET can form a circuit with very little variation, as proven in ICs and LSIs, and is particularly effective for an analog-driven active matrix EL display device that expresses gradation with current values.
[0199]
Note that since the silicon substrate is light-shielding, it is necessary to have a structure in which light from the EL layer is emitted to the side opposite to the substrate. The EL display device of this embodiment is structurally similar to that of FIG. 12, but differs in that MOSFETs are used instead of TFTs forming the pixel portion 602 and the drive circuit portion 603.
[0200]
In addition, the structure of a present Example can be implemented in combination with any structure of Example 1- Example 4 freely.
[0201]
Example 6
An EL display device formed by implementing the present invention is a self-luminous type, and thus has excellent visibility in a bright place as compared with a liquid crystal display device, and has a wide viewing angle. Therefore, it can be used as a display unit of various electric appliances. For example, in order to view TV broadcasts on a large screen, the EL of the present invention can be used as a display unit of an EL display (a display in which an EL display device is incorporated in a housing) having a diagonal size of 30 inches or more (typically 40 inches or more). A display device may be used.
[0202]
The EL display includes all information display displays such as a personal computer display, a TV broadcast receiving display, and an advertisement display. In addition, the EL display device of the present invention can be used as a display portion of various electric appliances.
[0203]
Such electric appliances of the present invention include a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game machine, a mobile phone. Information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), image playback device equipped with a recording medium (specifically, playback of a recording medium such as a digital video disc (DVD), and display the image) And a device equipped with a display that can be used. In particular, since a portable information terminal that is often viewed from an oblique direction emphasizes the wide viewing angle, it is desirable to use an EL display device. Specific examples of these electric appliances are shown in FIGS.
[0204]
FIG. 15A illustrates an EL display which includes a housing 2001, a support base 2002, a display portion 2003, and the like. The present invention can be used for the display portion 2003. Since the EL display is a self-luminous type, a backlight is not necessary, and a display portion thinner than a liquid crystal display can be obtained.
[0205]
FIG. 15B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The EL display device of the present invention can be used for the display portion 2102.
[0206]
FIG. 15C shows a part of the head-mounted EL display (on the right side). Including. The present invention can be used for the EL display device 2206.
[0207]
FIG. 15D shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2301, a recording medium (DVD or the like) 2302, an operation switch 2303, a display portion (a) 2304, a display portion. (B) 2305 and the like are included. The display unit (a) mainly displays image information, and the display unit (b) mainly displays character information. The EL display device of the present invention can be used for these display units (a) and (b). Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0208]
FIG. 15E illustrates a portable (mobile) computer, which includes a main body 2401, a camera portion 2402, an image receiving portion 2403, operation switches 2404, a display portion 2405, and the like. The EL display device of the present invention can be used for the display portion 2405.
[0209]
FIG. 15F illustrates a personal computer, which includes a main body 2501, a housing 2502, a display portion 2503, a keyboard 2504, and the like. The EL display device of the present invention can be used for the display portion 2503.
[0210]
If the light emission luminance of the EL material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used for a front type or rear type projector.
[0211]
In addition, the electric appliances often display information distributed through electronic communication lines such as the Internet or CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the response speed of the EL material is very high, the EL display device is preferable for moving image display. However, if the contour between pixels is blurred, the entire moving image is blurred. Therefore, it is extremely effective to use the EL display device of the present invention for clarifying the contour between pixels as a display portion of an electronic device.
[0212]
In addition, since the EL display device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Accordingly, when an EL display device is used for a display unit mainly including character information such as a portable information terminal, particularly a mobile phone or a sound reproduction device, the character information is formed by the light emitting portion with the non-light emitting portion as the background. It is desirable to drive.
[0213]
Here, FIG. 16A shows a mobile phone, which includes a main body 2601, an audio output portion 2602, an audio input portion 2603, a display portion 2604, operation switches 2605, and an antenna 2606. The EL display device of the present invention can be used for the display portion 2604. Note that the display portion 2604 can suppress power consumption of the mobile phone by displaying white characters on a black background.
[0214]
FIG. 16B shows a sound reproducing device, specifically a car audio, which includes a main body 2701, a display portion 2702, and operation switches 2703 and 2704. The EL display device of the present invention can be used for the display portion 2702. Moreover, although the vehicle-mounted audio is shown in the present embodiment, it may be used for a portable or household sound reproducing device. Note that the display portion 2704 can suppress power consumption by displaying white characters on a black background. This is particularly effective in a portable sound reproducing apparatus.
[0215]
As described above, the application range of the present invention is extremely wide and can be used for electric appliances in various fields. In addition, as the electric appliance of this embodiment, the EL display device having any configuration shown in Embodiments 1 to 5 may be used.
[0216]
Example 7
In an EL element manufactured using the present invention, an EL material that can use phosphorescence from triplet excitons for light emission can also be used. A light-emitting device using an EL material that can use phosphorescence for light emission can dramatically improve external light emission quantum efficiency. This makes it possible to reduce the power consumption, extend the life, and reduce the weight of the EL element.
[0217]
Here, a report of using triplet excitons to improve the external emission quantum efficiency is shown.
(T. Tsutsui, C. Adachi, S. Saito, Photochemical Processes in Organized Molecular Systems, ed. K. Honda, (Elsevier Sci. Pub., Tokyo, 1991) p.437.)
[0218]
The structural formula of the EL material (coumarin dye) reported by the above paper is shown below.
[0219]
[Chemical 6]

[0220]
(MABaldo, DFO'Brien, Y.You, A.Shoustikov, S.Sibley, METhompson, SRForrest, Nature 395 (1998) p.151.)
[0221]
The structural formula of the EL material (Pt complex) reported by the above paper is shown below.
[0222]
[Chemical 7]

[0223]
(MABaldo, S. Lamansky, PEBurrrows, METhompson, SRForrest, Appl.Phys.Lett., 75 (1999) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)
[0224]
The structural formula of the EL material (Ir complex) reported by the above paper is shown below.
[0225]
[Chemical 8]

[0226]
As described above, if phosphorescence emission from triplet excitons can be used, in principle, it is possible to realize an external emission quantum efficiency that is 3 to 4 times higher than that in the case of using fluorescence emission from singlet excitons.
[0227]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Example 1- Example 6. FIG.
[0228]
【The invention's effect】
By practicing the present invention, it is possible to improve the film formation failure of the electrode hole that occurs when the organic EL material is formed. Further, in the present invention, since the method of embedding the electrode hole with the protective part in various methods and shapes is shown, it is possible to form a film according to conditions and applications, and by short circuit between the cathode and the anode. A light emission failure of the EL layer can be prevented.
[Brief description of the drawings]
FIG. 1 shows a cross-sectional structure of a pixel portion.
FIG. 2 illustrates a cross-sectional structure of a pixel portion.
FIG. 3 is a diagram showing a top structure and a configuration of a pixel portion.
FIG. 4 illustrates a cross-sectional structure of a pixel portion.
FIG. 5 illustrates a cross-sectional structure of a pixel portion.
6A and 6B illustrate a manufacturing process of an EL display device.
FIG. 7 illustrates a manufacturing process of an EL display device.
FIG. 8 illustrates a manufacturing process of an EL display device.
FIG. 9 is a diagram showing an element structure of a sampling circuit.
FIG. 10 illustrates an appearance of an EL display device.
FIG. 11 is a diagram showing a circuit block configuration of an EL display device.
FIG. 12 illustrates a cross-sectional structure of an active matrix EL display device.
FIG. 13 shows a cross-sectional structure of a pixel portion.
FIG 14 illustrates a cross-sectional structure of a passive EL display device.
FIG. 15 is a diagram showing a specific example of an electric appliance.
FIG. 16 is a diagram showing a specific example of an electric appliance.

Claims (4)

A first electrode;
An insulator provided on the first electrode;
An EL layer provided on the first electrode and the insulator;
A second electrode provided on the EL layer,
The first electrode has an electrode hole;
The insulator is embedded in the entire electrode hole;
The self-luminous device according to claim 1, wherein the insulator has a portion raised from the surface of the first electrode, and the upper surface of the insulator has flatness. An insulating film having a contact hole;
A first electrode provided in the contact hole and on the insulating film;
An insulator provided on the first electrode;
An EL layer provided on the first electrode and the insulator;
A second electrode provided on the EL layer,
The first electrode has a recess formed by providing the first electrode in the contact hole;
The insulator is embedded in the entire recess;
The self-luminous device according to claim 1, wherein the insulator has a portion raised from the surface of the first electrode, and the upper surface of the insulator has flatness. Forming a first electrode having an electrode hole;
Forming an insulating organic resin film covering the entire surface of the first electrode;
Forming an insulator provided in the electrode hole by patterning the organic resin film after the entire surface of the insulating organic resin film is etched;
Forming an EL layer on the first electrode and the insulator;
Forming a second electrode on the EL layer,
The insulator is embedded in the entire electrode hole;
The method for manufacturing a self-luminous device, wherein the insulator has a portion raised from the surface of the first electrode, and the upper surface of the insulator has flatness. Forming a contact hole in the insulating film;
Forming a first electrode in the contact hole and on the insulating film, and forming a recess generated by providing the first electrode in the contact hole;
Forming an insulating organic resin film covering the entire surface of the first electrode;
A step of forming an insulator provided in the recess by patterning the organic resin film after the entire surface etching of the insulating organic resin film surface;
Forming an EL layer on the first electrode and the insulator;
Forming a second electrode on the EL layer,
The insulator is embedded in the entire recess;
The method for manufacturing a self-luminous device, wherein the insulator has a portion raised from the surface of the first electrode, and the upper surface of the insulator has flatness.

Images