JP4809628B2 - Communications system - Google Patents

Description

  The present invention relates to a communication system that performs scramble processing when data is transmitted from a transmission device to a reception device.

When transmitting data from the transmission device to the reception device, a broadband amplifier circuit is used for the reception device. When a plurality of such amplifier circuits are connected, since the direct current is cut off between the amplifier circuits and between the amplifier circuit and the logic circuit, a communication code that makes the appearance probabilities of “1” and “0” as uniform as possible is desired. It was rare. If the appearance probabilities of “1” and “0” are non-uniform, normal data reproduction cannot be performed by the receiving device, resulting in a communication system with low reliability. In addition, when the transmission path code between the transmission apparatus and the reception apparatus is an NRZ (Non-Return Zero) code, not only the appearance probabilities of “1” and “0” are equalized, but also clock recovery with high accuracy. Be able to,
It is also required that the transmission line code has a high alternation frequency between “1” and “0”. When the frequency of alternation between “1” and “0” becomes low, the clock cannot be normally reproduced by the receiving apparatus, and the communication system becomes low in reliability.

  When the transmission device and the reception device are installed relatively close to each other, parallel data communication using a metallic flat cable has been performed between the conventional transmission device and the reception device. In recent years, realization of serial data communication is desired in accordance with a request for reducing cable space. In the conventional serial data communication, an 8B10B (8 Binary to 10 Binary) conversion code is used. The 8B10B conversion code is a code that adds a 2-bit redundant code to 8-bit data to make the appearance probabilities of “1” and “0” closer to each other. However, the 8B10B code conversion cannot sufficiently equalize the appearance probabilities of “1” and “0”, and there is a problem that the logic circuit scale to be realized is large.

On the other hand, a technique for making the appearance probabilities of “1” and “0” close to each other using a scramble pattern has also been developed (for example, see Patent Document 1). This is a parallel scrambler provided with an initial value input terminal so that an initial value of a scramble pattern can be set.
JP-A-5-075600

  In the technology disclosed in Patent Document 1, in data communication in which a plurality of data is multiplexed and sufficiently randomness is ensured, the appearance probabilities of “1” and “0” are equalized by one scrambling process. can do. However, if the data before multiplexing is scrambled only once, there is a high probability that the data to be scrambled matches the scramble pattern, and even if the appearance probabilities of “1” and “0” are uniform throughout, In particular, there was a problem of non-uniformity. If it becomes locally non-uniform, the replacement frequency of “1” and “0” also becomes low.

  Accordingly, in order to solve the above problems, the present invention provides a highly reliable communication system in which the appearance probabilities of “1” and “0” are locally equal in the data signal between the transmission device and the reception device. The purpose is to provide.

  In order to achieve the above object, the communication system according to the first aspect of the present invention is a communication system that performs scramble processing multiple times with a plurality of different scramble patterns.

Specifically, the present first invention, the data is either M-sequence, Gold sequence, and Barker sequence, and the m (m is a positive integer) m times scrambled with different scrambling patterns, m times A transmission device that transmits the data scrambled m times so that the occurrence probabilities of “1” and “0” in the scrambled data are uniform both locally and locally, and the scrambled data from the transmission device A receiving device that receives the received data, descrambles the received data m times with the m scrambling patterns, and outputs the data descrambled m times.

  In the first invention of this application, by performing scramble processing a plurality of times with a plurality of different scramble patterns, the appearance probabilities of “1” and “0” of the transmission line codes are evenly localized, and a highly reliable communication system is provided. be able to.

In the second invention of this application, the scramble process for scrambling each of n (n is a positive integer) data having the same bit rate with a scramble pattern shifted by a different number of bits is one of an M series, a Gold series, and a Barker series. And m (m is a positive integer) different scramble patterns m times, the data scrambled m times is parallel-serial converted, and the data scrambled m times and parallel-serial converted is “1” and “0”. And the transmission device for transmitting parallel-serial converted serial data, and after receiving the parallel-serial converted serial data from the transmission device, The received serial data is serial-parallel converted, and the serial-parallel converted n data is converted into the number of bits shifted in the transmission device A receiving apparatus that outputs m pieces of data descrambled m times by repeating the descrambling process that is descrambled by a scramble pattern shifted by the same number of bits. It is.

  In the second invention of the present application, the parallel data is scrambled a plurality of times with a plurality of different scramble patterns, so that the appearance probability of transmission line codes “1” and “0” can be locally generated using a low-speed circuit. The communication system becomes even and highly reliable.

  In the first invention of the present application and the second invention of the present application, the transmitting device transmits the m scramble patterns together with the scrambled data, and the receiving device receives the transmitted m scramble patterns. The descrambling process may be performed using the received m scramble patterns.

  In the present invention, by simultaneously transmitting the scramble pattern together with the scrambled data, it is possible to eliminate generation of the scramble pattern in the receiving apparatus. Further, the appearance probabilities of “1” and “0” of the transmission line codes are further equalized, and a highly reliable communication system can be achieved.

  In the communication system of the present invention, at least one scramble pattern among the m scramble patterns may be used for frame synchronization.

  In the present invention, the frame synchronization pattern generation circuit can be eliminated by using the scramble pattern generated by the scramble pattern generation circuit for frame synchronization.

  In the communication system according to the present invention, the scramble pattern used for the frame synchronization may be a pattern fixed to periodic “1” or “0”.

  In the present invention, frame synchronization can be easily achieved by detecting a periodic fixed pattern of “1” or “0”.

  According to the present invention, in the data signal from the transmission device to the reception device, the appearance probabilities of “1” and “0” are locally equal, and a highly reliable communication system can be provided.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiment described below is an example of the configuration of the present invention, and the present invention is not limited to the following embodiment.

(Embodiment 1)
FIG. 1 shows a transmitting apparatus having a scramble processing function according to an embodiment of the present invention, and FIG. 3 shows a receiving apparatus having a descramble processing function by receiving data from the transmitting apparatus of FIG.

  The transmitting apparatus shown in FIG. 1 scrambles data m times (m is a positive integer) different scramble patterns, and transmits the data scrambled m times. In FIG. 1, 11 is a data input terminal for inputting data to the transmitter, 21-1, 21-2,... 21-m are scramble pattern generating circuits for generating m scramble patterns, 31-1, 31. −2,... 31-m is an exclusive OR circuit, 41 is a clock output circuit for supplying a clock signal, 61 is a multiplexing circuit for multiplexing signals necessary for transmitting a transmission signal to the communication medium, 71 Is an output terminal of the transmitter. The connection of the power supply circuit and the ground realized by a normal technique is omitted. The clock signal from the clock output circuit 41 is also omitted except for the scramble pattern generation circuits 21-1, 21-2,... 21-m, but is appropriately supplied to necessary circuits.

  Signals in each part of the transmission apparatus are shown in FIG. 2 (1) shows data input to the data input terminal 11, and FIGS. 2 (2), 2 (3), and 2 (4) show scramble pattern generation circuits 21-1, 21-2,. The scramble pattern generated by 21-m, FIGS. 2 (5), 2 (6), and 2 (7) are scrambled by the exclusive OR circuits 31-1, 31-2, and 31-m, respectively. Represents data. In FIG. 2, description will be made assuming that m = 3. “X” represents exclusive OR processing.

  The operation of the transmission apparatus of this embodiment will be described using the reference numerals in FIGS. The scramble pattern generation circuits 21-1, 21-2,... 21-m are different from each other according to the clock supplied from the clock output circuit 41 (FIG. 2 (2), FIG. 2 (3), FIG. 4)) is generated. Data from the data input terminal 11 (FIG. 2 (1)) is scrambled by the exclusive OR circuit 31-1 with the scramble pattern (FIG. 2 (2)) from the scramble pattern generating circuit 21-1 (FIG. 2 (2)). FIG. 2 (5)). The scrambled data is scrambled by the exclusive OR circuit 31-2 with the scramble pattern (FIG. 2 (3)) from the scramble pattern generation circuit 21-2 (FIG. 2 (6)). The scrambled data is further scrambled by the exclusive OR circuit 31-3 with the scramble pattern (FIG. 2 (4)) from the scramble pattern generation circuit 21-m (FIG. 2 (7)). Thus, the data to be transmitted is scrambled m times with m different scramble patterns. Thereafter, bits necessary for communication are added by the multiplexing circuit 61 and output from the output terminal 71. The bits necessary for communication are a frame synchronization signal indicating the start time of the frame, the start timing of each scramble pattern, and a maintenance monitoring signal. As described above, the data scrambled m times in FIG. 2 (7) is sufficiently randomized, so that the appearance probabilities of “1” and “0” are locally equal.

  The receiving device in FIG. 3 receives the scrambled data from the transmitting device via the communication medium, and then descrambles m times with the m scramble patterns, and outputs the reproduced data. 3, 72 is an input terminal for inputting data to the receiving device, 22-1, 22-2,... 22-m are scramble pattern generating circuits 21-m,. , 21-1 scramble pattern generation circuit for generating m scramble patterns, 35-1, 35-2,... 35-m are exclusive OR circuits, and 42 is a clock output circuit for supplying a clock signal. , 62 is a demultiplexing circuit for demultiplexing a signal necessary for receiving a received signal from the communication medium, and 15 is a data output terminal of the receiving apparatus. The connection of the power supply circuit and the ground realized by a normal technique is omitted. The clock extraction circuit is also omitted. The clock extraction circuit extracts a clock signal from the data received on the receiving side. The clock output circuit 42 supplies the clock signal extracted by the clock extraction circuit to each circuit of the receiving apparatus. The clock signal from the clock output circuit 42 is also omitted from connection, but is supplied to necessary circuits including the scramble pattern generation circuits 22-1, 22-2,.

  A signal in each part of the receiving apparatus can be described with reference to FIG. Since the receiving apparatus in FIG. 3 operates in reverse to the transmitting apparatus in FIG. 1, the output signal of the demultiplexing circuit 62 in FIG. 3 is the same as that in FIG. The scramble patterns generated by the scramble pattern generation circuits 22-1, 22-2,..., 22-m are the same as those in FIGS. 2 (4), 2 (3), and 2 (2), respectively. The descrambled data output by the exclusive OR circuits 35-1, 35-2,... 35-m are the same as those in FIGS. 2 (6), 2 (5), and 2 (1), respectively. . In FIG. 2, it is assumed that m = 3.

  The operation of the receiving apparatus of this embodiment will be described using the reference numerals in FIGS. The scramble pattern generation circuits 22-1, 22-2,... 22-m are different from each other according to the clock supplied from the clock output circuit 42 (FIG. 2 (4), FIG. 2 (3), FIG. 2)). Data from the input terminal 72 is separated into bits necessary for communication by the demultiplexing circuit 62 and output to the exclusive OR circuit 35-1 (FIG. 2 (7)). The exclusive OR circuit 35-1 performs descrambling with the scramble pattern (FIG. 2 (4)) from the scramble pattern generation circuit 22-1 (FIG. 2 (6)). The descrambled data is descrambled by the exclusive OR circuit 35-2 with the scramble pattern (FIG. 2 (3)) from the scramble pattern generation circuit 22-2 (FIG. 2 (5)). The descrambled data is further descrambled by the exclusive OR circuit 35-m with the scramble pattern (FIG. 2 (2)) from the scramble pattern generation circuit 22-m (FIG. 2 (1)). ). In this way, the received data is descrambled m times with m different scramble patterns, and the original data is obtained (FIG. 2 (1)).

  The communication medium may be a metal wire or an optical fiber. In particular, when an optical fiber is used, high-speed data is resistant to external noise and enables long-distance communication. When an optical fiber is used as the communication medium, the transmission device includes an optical transmission circuit including a light emitting element, and the reception device includes an optical reception circuit including a light receiving element. The same applies to the following embodiments.

  As the scramble pattern, a data series having a low autocorrelation such as an M series, a Gold series, and a Barker series is desirable. In addition, when using a plurality of scramble patterns, different patterns are desirable. For example, in the case of a data series having a different number of stages of M series, since the repetition period is different, the randomness is further increased. The same applies to the following embodiments.

  As described above, when data that has been scrambled m times with m different scramble patterns is transmitted in the transmission apparatus, the reception data in the reception apparatus is evenly localized in the appearance probability of “1” and “0”. Since data recovery and clock recovery are facilitated, a highly reliable communication system can be obtained.

(Embodiment 2)
FIG. 4 shows a transmitting apparatus having a scramble processing function according to an embodiment of the present invention, and FIG. 6 shows a receiving apparatus having a descramble processing function by receiving data from the transmitting apparatus of FIG.

  The transmission apparatus shown in FIG. 4 scrambles data m times (m is a positive integer) different scramble patterns, and transmits the scrambled data together with the scrambled data m times. In FIG. 4, the same reference numerals as those in FIG. 1 have the same meanings, so the description of the same reference numerals is omitted. However, the multiplexing circuit 61 in FIG. 4 multiplexes the scrambled data and the scramble pattern.

  FIG. 5 shows signals in each part of the transmission apparatus. 5 (1) shows data to the data input terminal 11, and FIGS. 5 (2), 5 (3) and 5 (4) show scramble pattern generation circuits 21-1, 21-2,. FIG. 5 (5), FIG. 5 (6), and FIG. 5 (7) show the scrambled data output by the exclusive OR circuits 31-1, 31-2, and 31-m, respectively. To express. In FIG. 5, it is assumed that m = 3. “X” represents exclusive OR processing.

  The operation of the transmission apparatus of this embodiment will be described using the reference numerals in FIGS. The scramble pattern generation circuits 21-1, 21-2,..., 21-m are different from each other according to the clock supplied from the clock output circuit 41 by the clock supplied from the clock output circuit 41 (FIG. 5 (2)). 5 (3) and FIG. 5 (4)), and the exclusive OR circuits 31-1, 31-2,... 31-m are scrambled m times (FIG. 5 (5), FIG. 5). (6) and FIG. 5 (7)) are the same as in the transmission apparatus of the embodiment. Thereafter, the multiplexing circuit 61 multiplexes the scrambled data and the scramble pattern used for the scramble process (FIG. 5 (8)). Further, bits necessary for communication are added and output from the output terminal 71. The bits necessary for communication are a frame synchronization signal indicating the start time of the frame and a maintenance monitoring signal.

  As described above, since the data and the scrambled pattern multiplexed signal m times scrambled in FIG. 5 (8) are sufficiently randomized, the appearance probabilities of “1” and “0” are local. Evenly. Further, since the scramble pattern is transmitted simultaneously, it is not necessary to transmit the start timing of the scramble pattern.

  The receiving device in FIG. 6 receives the scrambled data from the transmitting device via the communication medium, then descrambles m times with the m scramble patterns, and outputs the reproduced data. In FIG. 6, the same reference numerals as those in FIG. 3 have the same meanings, so the description of the same reference numerals is omitted. However, the demultiplexing circuit 62 in FIG. 6 demultiplexes the scramble pattern from the received signal.

  A signal in each part of the receiving apparatus can be described with reference to FIG. Since the receiving apparatus in FIG. 6 operates in reverse to the transmitting apparatus in FIG. 4, the output signal of the demultiplexing circuit 62 in FIG. 6 is the same as that in FIG. 5 (7). The scramble pattern to be demultiplexed by the demultiplexing circuit 62 is the same as in FIGS. 5 (4), 5 (3), and 5 (2). The descrambled data output from the exclusive OR circuits 35-1, 35-2,... 35-m are the same as those in FIGS. 5 (6), 5 (5), and 5 (1), respectively. . In FIG. 5, it is assumed that m = 3.

  The operation of the receiving apparatus of this embodiment will be described using the reference numerals in FIGS. Bits necessary for communication are separated from data from the input terminal 72 by the demultiplexing circuit 62 (FIG. 5 (8)), and the data scrambled m times is output to the exclusive OR circuit 35-1 ( FIG. 5 (7)). The demultiplexing circuit 62 demultiplexes different scramble patterns (FIG. 5 (4), FIG. 5 (3), FIG. 5 (2)), and demultiplexes the scramble patterns into exclusive OR circuits 35-1, 35-2. ... To 35-m. The exclusive OR circuit 35-1 performs descrambling with the scramble pattern (FIG. 5 (4)) from the scramble pattern generation circuit 22-1 (FIG. 5 (6)). The descrambled data is descrambled by the exclusive OR circuit 35-2 with the scramble pattern (FIG. 5 (3)) from the scramble pattern generation circuit 22-2 (FIG. 5 (5)). The descrambled data is further descrambled by the exclusive OR circuit 35-m with the scramble pattern (FIG. 5 (2)) from the scramble pattern generation circuit 22-m (FIG. 5 (1)). ). In this way, the received data is descrambled m times with m different scramble patterns, and the original data is obtained (FIG. 5 (1)). In this way, the original data is obtained by m times of descrambling, and the receiving device does not require a scramble pattern generation circuit.

  Here, the multiplexing circuit 61 in FIG. 4 does not add a frame synchronization signal, and the demultiplexing circuit 62 in FIG. 6 converts at least one scrambled pattern out of m scrambled patterns subjected to parallel-serial conversion into a frame. It may be used for synchronization.

 Further, if the scramble pattern used for frame synchronization is a pattern fixed to “1” or “0” periodically, establishment of frame synchronization is facilitated. Periodic patterns fixed to “1” or “0” include patterns in which a violation is formed in only one place in the alternating series of “1” and “0”, and 1 bit is set to “1” or “0”. The pattern etc. which used as the complementary code can be illustrated.

  As described above, when the transmitter device transmits data scrambled m times with m different scramble patterns and a signal in which the scramble pattern is multiplexed, the data is sufficiently randomized. Since the appearance probabilities of “1” and “0” are evenly locally and data reproduction and clock reproduction are easy, a highly reliable communication system can be obtained. Further, it is not necessary to transmit the start timing of the scramble pattern on the transmission side, and a scramble pattern generation circuit is not necessary on the reception side.

(Embodiment 3)
FIG. 7 shows a transmission apparatus having a scramble processing function according to an embodiment of the present invention, and FIG. 9 shows a reception apparatus having a descramble processing function by receiving data from the transmission apparatus of FIG.

  The transmitter shown in FIG. 7 performs m (m is a positive integer) different scramble patterns for scrambling each of the n bits (n is a positive integer) of the same bit rate with a scramble pattern shifted by a different number of bits. The data that has been repeated m times and scrambled m times is subjected to parallel-serial conversion and serial data is transmitted.

  7, 11, 12, and 13 are data input terminals for inputting data to the transmission device, 21-1 and 21-2 are scramble pattern generation circuits that generate different scramble patterns, 31-1, 32-1, 33- 1, 31-2, 32-2, and 33-2 are exclusive OR circuits, 41 is a clock output circuit that supplies a clock signal, 51-1 and 51-2 are shift register circuits, and 61 is a transmission signal to a communication medium. A multiplexing circuit 71 that multiplexes signals necessary for transmitting the signal, 71 is an output terminal of the transmitting apparatus. The connection of the power supply circuit and the ground realized by a normal technique is omitted. The clock signal from the clock output circuit 41 is also omitted except for the scramble pattern generation circuits 21-1 and 21-2, but is appropriately supplied to necessary circuits.

  FIG. 8 shows signals in each part of the transmission apparatus. 8 (1), FIG. 8 (2), and FIG. 8 (3) are data input to the data input terminals 11, 12, and 13, respectively, and FIG. 8 (4) and FIG. 8 (5) are scramble pattern generation circuits. The scramble patterns generated by 21-1 and 21-2, FIGS. 8 (6), 8 (7), and 8 (8) are output from the exclusive OR circuits 31-1, 32-1, and 33-1, respectively. 8 (9), FIG. 8 (10), and FIG. 8 (11) represent the scrambled data output by the exclusive OR circuits 31-2, 32-2, and 33-2, respectively. . In FIG. 8, description will be made assuming that m = 2 and n = 3. “X” represents exclusive OR processing.

  The operation of the transmission apparatus of the present embodiment will be described using the reference numerals in FIGS. The scramble pattern generation circuits 21-1 and 21-2 generate different scramble patterns (FIG. 8 (4) and FIG. 8 (5)) by the clock supplied from the clock output circuit 41, respectively. Different scramble patterns are output to the shift register circuits 51-1 and 51-2, shifted by different numbers of bits, and then exclusive-OR circuits 31-1, 32-1, 33-1, 31-2, and 32. -2, 33-2. In FIG. 8, the original scramble patterns (FIGS. 8 (4) and 8 (5)) are shifted by 1 bit, 2 bits, and 3 bits, respectively, by the shift register circuits 51-1 and 51-2.

  The data (FIG. 8 (1)) from the data input terminal 11 is scrambled from the shift register circuit 51-1 by the exclusive OR circuit 31-1 (a pattern obtained by shifting 1 bit of FIG. 8 (4)). It is scrambled (FIG. 8 (6)). The scrambled data is scrambled by the exclusive OR circuit 31-2 with the scramble pattern from the shift register circuit 51-2 (a pattern obtained by shifting FIG. 8 (5) by 1 bit) (FIG. 8 (9)). )).

  Similarly, the data from the data input terminal 12 (FIG. 8 (2)) is obtained by shifting the scramble pattern (FIG. 8 (4) from the shift register circuit 51-1 by 2 bits by the exclusive OR circuit 32-1. The pattern is scrambled (FIG. 8 (7)). The scrambled data is scrambled by the exclusive OR circuit 32-2 with the scramble pattern (pattern obtained by shifting FIG. 8 (5) by 2 bits) from the shift register circuit 51-2 (FIG. 8 (10)). )).

  Similarly, the data from the data input terminal 13 (FIG. 8 (3)) is shifted by 3 bits from the scramble pattern (FIG. 8 (4) from the shift register circuit 51-1 by the exclusive OR circuit 33-1. The pattern is scrambled (FIG. 8 (8)). The scrambled data is scrambled by the exclusive OR circuit 32-2 with the scramble pattern (pattern obtained by shifting FIG. 8 (5) by 3 bits) from the shift register circuit 51-2 (FIG. 8 (11)). )).

  In this manner, n pieces of data having the same bit rate are each scrambled m times with m pieces of scramble patterns shifted by different numbers of bits. Thereafter, parallel-to-serial conversion is performed by the multiplexing circuit 61 (FIG. 8 (12)), and bits necessary for communication are added and output from the output terminal 71. The bits necessary for communication are a frame synchronization signal indicating the start time of the frame, the start timing of each scramble pattern, and a maintenance monitoring signal.

  As described above, since the data that has been scrambled m times and parallel-serial converted as shown in FIG. 8 (12) is sufficiently randomized, the appearance probabilities of “1” and “0” are locally Will be even. Since such scramble processing is performed on parallel input parallel data, a circuit operating at a low speed is sufficient. In addition, since the scramble process is performed on the parallel data of each parallel input with the scramble pattern from one scramble pattern generation circuit, it is not necessary to provide a different scramble pattern generation circuit for each parallel input data. Furthermore, since the scramble pattern from the scramble pattern generation circuit is shifted by a different number of bits and scrambled with respect to parallel data of each parallel input, the scrambled data is converted into serial data by parallel-to-serial conversion. Correlation is small between adjacent data.

  9 receives serial data subjected to parallel-serial conversion from the transmission device via the communication medium, and then performs serial-parallel conversion on the received serial data, and n pieces of data obtained by serial-parallel conversion. Is repeatedly descrambled m times with m different scramble patterns, and outputs n pieces of data that have been descrambled m times. To do. In FIG. 9, 72 is an input terminal for inputting data to the receiving device, and 22-1 and 22-2 are scramble patterns that generate the same scramble patterns as the scramble pattern generation circuits 21-2 and 21-1 shown in FIG. 37-1, 36-1, ... 37-1, 35-2, 36-2, ... 37-2 are exclusive OR circuits, 42 is a clock output circuit for supplying a clock signal, Reference numeral 62 denotes a demultiplexing circuit for demultiplexing a signal necessary for receiving a reception signal from a communication medium and serial-to-parallel conversion of serial data, 52-1, 52-2 are shift register circuits, 15, 16, 17 are Data output terminal of the receiving device. The connection of the power supply circuit and the ground realized by a normal technique is omitted. The clock signal from the clock output circuit 42 is also omitted from connection, but is supplied to necessary circuits including the scramble pattern generation circuits 22-1 and 22-2.

  The signals in each part of the receiving apparatus can be described with reference to FIG. Since the receiving apparatus in FIG. 9 operates in reverse to the transmitting apparatus in FIG. 7, the output signal to the exclusive OR circuits 35-1, 36-1,... 37-1 of the demultiplexing circuit 62 in FIG. Is the same as FIG. 8 (9), FIG. 8 (10), and FIG. 8 (11). The scramble patterns generated by the scramble pattern generation circuits 22-1 and 22-2 are the same as those in FIGS. 8 (5) and 8 (4), respectively. The descrambled data output from the exclusive OR circuits 35-1, 36-1,... 37-1 are the same as those in FIGS. 8 (6), 8 (7), and 8 (7), respectively. . The descrambled data output by the exclusive OR circuits 35-2, 36-2,... 37-2 are the same as those in FIGS. 8 (1), 8 (2), and 8 (3), respectively. . In FIG. 8, it is assumed that m = 2 and n = 3.

  The operation of the receiving apparatus of this embodiment will be described using the reference numerals in FIGS. The scramble pattern generation circuits 22-1 and 22-2 are respectively scrambled by the clock supplied from the clock output circuit 42 as the scramble pattern generation circuits 21-2 and 21-1 shown in FIG. 7 (FIG. 8 (5), FIG. 8 (4)). The two scramble patterns are respectively output to the shift register circuits 52-1, 52-2, and after being shifted by a different number of bits, the exclusive OR circuits 35-1, 36-1, 37-1, 35-2, 36-2 and 37-2. In FIG. 8, the original scramble pattern (FIGS. 8 (5) and 8 (4)) is shifted by 1 bit, 2 bits, and 3 bits, respectively, by the shift register circuits 52-1 and 52-2.

  Bits necessary for communication are separated from the input terminal 72 by the demultiplexing circuit 62 and output to the exclusive OR circuits 35-1, 36-1,... 37-1 (FIG. 8 (9 ), FIG. 8 (10), FIG. 8 (11)). The exclusive OR circuits 35-1, 36-1,... 37-1 shift the scramble pattern from the shift register circuit 52-1 (the scramble pattern of FIG. 8 (5) by 1, 2, and 3 bits, respectively). The pattern is descrambled (FIG. 8 (6), FIG. 8 (7), FIG. 8 (8)). The descrambled data is converted by the exclusive OR circuits 35-2, 36-2, and 37-2 from the scramble pattern of the shift register circuit 52-2 (the scramble pattern of FIG. Descramble processing is performed using a pattern shifted by 3 bits (FIG. 8 (1), FIG. 8 (2), and FIG. 8 (3)). In this manner, the received serial data is serial-parallel converted, and the serial-parallel converted n data is descrambled with a scramble pattern shifted by the same number of bits as the number of bits shifted in the transmission device, By repeating m times with m different scramble patterns, the original parallel data is obtained (FIG. 8 (1), FIG. 8 (2), FIG. 8 (3)).

  As described above, the scramble process of scrambling each of the n pieces of data having the same bit rate with a scramble pattern shifted by a different number of bits in the transmitting apparatus is repeated m times with m different scramble patterns, and the scrambled data m times. When the serial data is transmitted after parallel-serial conversion, the received data has a uniform appearance probability of “1” and “0” locally, and data reproduction and clock reproduction are facilitated. It can be set as a highly reliable communication system. Also, a low speed circuit can be applied to scramble and descramble parallel data. Furthermore, since the scramble pattern from the scramble pattern generation circuit is shifted by a different number of bits and scrambled for each parallel data, the scrambled data is converted into serial data by converting the scrambled data into serial data. Correlation between data is small.

(Embodiment 4)
FIG. 10 shows a transmitting apparatus having a scramble processing function according to an embodiment of the present invention, and FIG. 12 shows a receiving apparatus having a descramble processing function by receiving data from the transmitting apparatus of FIG.

  The transmitting apparatus shown in FIG. 10 repeats m times of scramble processing that scrambles n data of the same bit rate with scramble patterns shifted by different number of bits, m times with m different scramble patterns (m is a positive integer). Then, the scrambled data and the scramble pattern are parallel-serial converted and serial data is transmitted.

  In FIG. 10, the same reference numerals as those in FIG. 7 have the same meaning, and thus the description of the same reference numerals is omitted. However, the multiplexing circuit 61 in FIG. 10 multiplexes the scrambled data and the scramble pattern.

  FIG. 11 shows signals in each part of the transmission apparatus. 11 (1), 11 (2), and 11 (3) are data input to the data input terminals 11, 12, and 13, respectively, and FIGS. 11 (4) and 11 (5) are scramble pattern generation circuits. The scramble patterns generated by 21-1 and 21-2, FIGS. 11 (6), 11 (7), and 11 (8) are output by the exclusive OR circuits 31-1, 32-1, and 33-1, respectively. 11 (9), FIG. 11 (10), and FIG. 11 (11) show the scrambled data output by the exclusive OR circuits 31-2, 32-2, and 33-2, respectively. . In FIG. 11, description will be made assuming that m = 2 and n = 3. “X” represents exclusive OR processing.

  The operation of the transmission apparatus of the present embodiment will be described using the reference numerals in FIGS. The scramble pattern generation circuits 21-1 and 21-2 generate different scramble patterns (FIG. 11 (4) and FIG. 11 (5)) according to the clock supplied from the clock output circuit 41. Different scramble patterns are output to the shift register circuits 51-1 and 51-2, shifted by different numbers of bits, and then exclusive-OR circuits 31-1, 32-1, 33-1, 31-2, and 32. -2, 33-2. In FIG. 11, the original scramble pattern (FIGS. 11 (4) and 11 (5)) is shifted by 1 bit, 2 bits, and 3 bits by shift register circuits 51-1 and 51-2, respectively.

  The data from the data input terminal 11 (FIG. 11 (1)) is scrambled from the shift register circuit 51-1 by the exclusive OR circuit 31-1 (a pattern obtained by shifting 1 bit of FIG. 11 (4)). It is scrambled (FIG. 11 (6)). The scrambled data is scrambled by the exclusive OR circuit 31-2 with the scramble pattern from the shift register circuit 51-2 (a pattern obtained by shifting FIG. 11 (5) by 1 bit) (FIG. 11 (9) )).

  Similarly, the data from the data input terminal 12 (FIG. 11 (2)) is obtained by shifting the scramble pattern (FIG. 11 (4) from the shift register circuit 51-1 by 2 bits by the exclusive OR circuit 32-1. The pattern is scrambled (Fig. 11 (7)). The scrambled data is scrambled by the exclusive OR circuit 32-2 with the scramble pattern (pattern obtained by shifting FIG. 11 (5) by 2 bits) from the shift register circuit 51-2 (FIG. 11 (10)). )).

  Similarly, the data from the data input terminal 13 (FIG. 11 (3)) is shifted by 3 bits from the scramble pattern (FIG. 11 (4) from the shift register circuit 51-1 by the exclusive OR circuit 33-1. The pattern is scrambled (FIG. 11 (8)). The scrambled data is scrambled by the exclusive OR circuit 32-2 with a scramble pattern (pattern obtained by shifting FIG. 11 (5) by 3 bits) from the shift register circuit 51-2 (FIG. 11 (11 )).

  In this manner, n pieces of data having the same bit rate are each scrambled m times with m pieces of scramble patterns shifted by different numbers of bits. Thereafter, the multiplexing circuit 61 performs parallel-serial conversion of the scrambled data and the scramble pattern used for the scramble process (FIG. 11 (12)). Further, bits necessary for communication are added and output from the output terminal 71. The bits necessary for communication are a frame synchronization signal indicating the start time of the frame and a maintenance monitoring signal.

  As described above, since the data that has been scrambled m times and parallel-serial converted as shown in FIG. 11 (12) is sufficiently randomized, the occurrence probabilities of “1” and “0” are locally Will be even. Since such scramble processing is performed on parallel input parallel data, a circuit operating at a low speed is sufficient. Further, since the scramble pattern is transmitted simultaneously, it is not necessary to transmit the start timing of the scramble pattern. In addition, since the scramble process is performed on the parallel data of each parallel input with the scramble pattern from one scramble pattern generation circuit, it is not necessary to provide a different scramble pattern generation circuit for each parallel input data. Furthermore, since the scramble pattern from the scramble pattern generation circuit is shifted by a different number of bits and scrambled with respect to parallel data of each parallel input, the scrambled data is converted into serial data by parallel-to-serial conversion. Correlation is small between adjacent data.

  12 receives serial data subjected to parallel-serial conversion from the transmission device via a communication medium, and then performs serial-parallel conversion on the received serial data, and n data subjected to serial-parallel conversion. Is repeatedly descrambled m times with m different scramble patterns, and n pieces of descrambled data are output. In FIG. 12, the same reference numerals as those in FIG. 9 have the same meaning, and thus the description of the same reference numerals is omitted. However, the demultiplexing circuit 62 in FIG. 12 demultiplexes the scramble pattern from the received signal.

  A signal in each part of the receiving apparatus can be described with reference to FIG. Since the receiving apparatus in FIG. 12 operates in reverse to the transmitting apparatus in FIG. 10, an output signal to the exclusive OR circuits 35-1, 36-1,... 37-1 of the demultiplexing circuit 62 in FIG. Is the same as FIG. 11 (9), FIG. 11 (10), and FIG. 11 (11). The scramble patterns generated by the scramble pattern generation circuits 22-1 and 22-2 are the same as those in FIGS. 11 (5) and 11 (4), respectively. The descrambled data output from the exclusive OR circuits 35-1, 36-1,... 37-1 are the same as those in FIGS. 11 (6), 11 (7), and 11 (7), respectively. . The descrambled data output by the exclusive OR circuits 35-2, 36-2,... 37-2 are the same as those in FIGS. 11 (1), 11 (2), and 11 (3), respectively. . In FIG. 11, description is made assuming that m = 2 and n = 3.

  The operation of the receiving apparatus of this embodiment will be described using the reference numerals in FIGS. 11 and 12. The data from the input terminal 72 is separated into two scramble patterns by the demultiplexing circuit 62. The two scramble patterns are respectively output to the shift register circuits 52-1, 52-2, and after being shifted by a different number of bits, the exclusive OR circuits 35-1, 36-1, 37-1, 35-2, 36-2 and 37-2. In FIG. 11, the original scramble pattern (FIGS. 11 (5) and 11 (4)) is shifted by 1 bit, 2 bits, and 3 bits by shift register circuits 52-1 and 52-2, respectively.

  Bits necessary for communication are separated from the data from the input terminal 72 by the demultiplexing circuit 62, and the data scrambled m times are serial-parallel converted, and exclusive OR circuits 35-1, 36-1,. .. 37-1 (FIG. 11 (9), FIG. 11 (10), FIG. 11 (11)). The exclusive OR circuits 35-1, 36-1,... 37-1 shift the scramble pattern from the shift register circuit 52-1 (the scramble pattern of FIG. 11 (5) by 1, 2, and 3 bits, respectively). The pattern is descrambled (FIG. 11 (6), FIG. 11 (7), FIG. 11 (8)). The descrambled data is converted by the exclusive OR circuits 35-2, 36-2, and 37-2 from the scramble pattern of the shift register circuit 52-2 (the scramble pattern of FIG. A descrambling process is performed with a pattern shifted by 3 bits (FIG. 11 (1), FIG. 11 (2), and FIG. 11 (3)). In this manner, the received serial data is serial-parallel converted, and the serial-parallel converted n data is descrambled with a scramble pattern shifted by the same number of bits as the number of bits shifted in the transmission device, When it is repeated m times with m different scramble patterns, the original parallel data is obtained (FIG. 11 (1), FIG. 11 (2), FIG. 11 (3)).

  Here, the multiplexing circuit 61 in FIG. 10 does not add a frame synchronization signal, and the demultiplexing circuit 62 in FIG. 12 converts at least one scrambled pattern out of m scrambled patterns subjected to parallel-serial conversion into a frame. It may be used for synchronization.

  Further, if the scramble pattern used for frame synchronization is a pattern fixed to “1” or “0” periodically, establishment of frame synchronization is facilitated. Periodic patterns fixed to “1” or “0” include patterns in which a violation is formed in only one place in the alternating series of “1” and “0”, and 1 bit is set to “1” or “0”. The pattern etc. which used as the complementary code can be illustrated.

  As described above, the scramble process of scrambling each of the n pieces of data having the same bit rate with a scramble pattern shifted by a different number of bits in the transmitting apparatus is repeated m times with m different scramble patterns, and the scrambled data m times. When the serial data is transmitted after parallel-serial conversion, the received data has a uniform appearance probability of “1” and “0” locally, and data reproduction and clock reproduction are facilitated. It can be set as a highly reliable communication system. Also, a low speed circuit can be applied to scramble and descramble parallel data. Further, it is not necessary to transmit the start timing of the scramble pattern on the transmission side, and a scramble pattern generation circuit is not necessary on the reception side. Furthermore, since the scramble pattern from the scramble pattern generation circuit is shifted by a different number of bits and scrambled for each parallel data, the scrambled data is converted into serial data by converting the scrambled data into serial data. Correlation between data is small.

  The communication system of the present invention can be applied not only to a transmission device and a reception device that communicate with a metallic line, but also to a transmission device and a reception device that communicate using an optical fiber.

It is a figure explaining the structure of the transmitter which concerns on embodiment of this invention. It is a figure explaining the signal in the transmitter and receiver which concern on embodiment of this invention. It is a figure explaining the structure of the receiver which concerns on embodiment of this invention. It is a figure explaining the structure of the transmitter which concerns on embodiment of this invention. It is a figure explaining the signal in the transmitter and receiver which concern on embodiment of this invention. It is a figure explaining the structure of the receiver which concerns on embodiment of this invention. It is a figure explaining the structure of the transmitter which concerns on embodiment of this invention. It is a figure explaining the signal in the transmitter and receiver which concern on embodiment of this invention. It is a figure explaining the structure of the receiver which concerns on embodiment of this invention. It is a figure explaining the structure of the transmitter which concerns on embodiment of this invention. It is a figure explaining the signal in the transmitter and receiver which concern on embodiment of this invention. It is a figure explaining the structure of the receiver which concerns on embodiment of this invention.

Explanation of symbols

11-13: Data input terminals 15-17: Data output terminal 21: Scramble pattern generation circuit 22: Scramble pattern generation circuits 31-33: Exclusive OR circuit 35-37: Exclusive OR circuit 41: Clock output circuit 42 : Clock output circuit 51: shift register circuit 52: shift register circuit 61: multiplexing circuit 62: demultiplexing circuit 71: output terminal 72: input terminal

Claims (5)

The data is one of M series, Gold series and Barker series and is scrambled m times with m (m is a positive integer) different scramble patterns, and “1” and “0” in the data scrambled m times. A transmission device that transmits the data scrambled m times so that the occurrence probability of “
A receiving device that, after receiving the scrambled data from the transmitting device, descrambles the received data m times with the m scramble patterns, and outputs the data descrambled m times. Communications system. The scramble processing for scrambling each of n pieces (n is a positive integer) of the same bit rate with a scramble pattern shifted by a different number of bits is one of M series, Gold series and Barker series, and m (m Is a positive integer) and is repeated m times, and the data scrambled m times is parallel-serial converted, and the appearance probability of “1” and “0” in the data scrambled and parallel-serial converted m times However, a transmission device that transmits serial data that is parallel-serial converted so as to be even locally,
After receiving the parallel-serial converted serial data from the transmission device, the received serial data is serial-parallel converted, and the serial-parallel converted n data is the number of bits shifted in the transmission device and A communication system comprising: a receiving device that repeats a descrambling process that is descrambled by a scramble pattern shifted by the same number of bits m times with the m different scramble patterns, and outputs n data that has been descrambled m times . The transmitter transmits the m scramble patterns together with the scrambled data;
3. The communication system according to claim 1, wherein the receiving device receives the transmitted m scramble patterns and performs descrambling using the received m scramble patterns. 4. .   The communication system according to claim 3, wherein at least one scramble pattern among the m scramble patterns is used for frame synchronization. 5. The communication system according to claim 4, wherein the scramble pattern used for the frame synchronization is a pattern fixed to periodic “1” or “0”.

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