JP4806716B2 - Communication quality control apparatus and communication quality control method - Google Patents

Description

  The present invention relates to a communication quality control apparatus and a communication quality control method.

  In addition to data communication, various communication services such as voice calls and videophones are provided via the Internet. Along with such diversification, in order to achieve both flexibility and high speed, each queue (Queue), scheduler, and shaper (Shaper) are connected by a selector, and a handshake of a transmission request and a request acceptance signal is performed. The QoS (Quality of Service) method used has been proposed (see, for example, Patent Documents 1 and 2). Note that QoS is a technique for guaranteeing a certain communication quality when a bandwidth for communication is reserved on a network.

  Furthermore, a scheduling method used for this QoS method has been proposed (see, for example, Patent Documents 3 and 4). In this method, the weight specified for each input is time-divided every clock cycle, or a value proportional to the weight of each input is added to the counter installed at each input by changing the addition value. The input which is 0 or positive and receives the transmission request is selected by round robin, and the transmission request is transmitted (transmitted) to the subsequent stage. The round robin is a method for eliminating the bias of input selected by allocating resources in order.

  The conventional communication quality control device subtracts the length of the request packet from the selected input counter at the time of transmission, and lowers the transmission opportunity from other inputs. If the added value is small, the output rate is lowered by increasing the time until the next transmission opportunity. On the other hand, if the added value is large, the output rate is increased by shortening the time until the next transmission opportunity. Thereby, weighted fair control is performed.

  When the transmission request packet is output, the transmission acceptance signal is returned via the path through which the transmission request has passed. When this transmission acceptance signal is received, the acceptance signal is transmitted in response to the transmission request input selected previously.

JP 2005-31409 A JP 2005-323230 A JP 2007-110483 A JP 2007-110515 A

  However, since the conventional communication quality control device selects the wrong input when the next packet to be transmitted is selected immediately after the acceptance signal is transmitted, the selection is not performed for a certain period of time (a variable called WaitCnt is counted down). The input selection is started after a certain period of time has elapsed (when the variable WaitCnt becomes 0). Since the accuracy and the operation speed are affected, the conventional communication quality control apparatus must add a value proportional to the above-described weight even during this fixed period. However, if a transmission request is not received, the input counter is positive, a transmission acceptance signal is received, or WaitCnt becomes 0, the conventional communication quality control device uses the value stored in the counter. Must return to the total counter. For this reason, the conventional communication quality control apparatus is complicated in processing, and each input must have a register corresponding to a negative number of the maximum frame size, and must have registers when they all return to the total counter. Therefore, the circuit scale becomes large.

  In addition, when the weight range becomes large (for example, 1: 15 → 1: 255), the conventional communication quality control device cannot accurately add to the counter. This is because 1 is added to an input counter at the time of addition, and 255 is added at one time to some other input, and packets may be transmitted in bursts. . For example, when the packet length accumulated in the input to which 255 is added is 64 bytes, there is a possibility that 3 packets (255/64 = 3.98) are transmitted at a time.

  Also, the scheduling method proposed in the prior art cannot execute priority control or weighted fair control at the same time, and is forced to perform exclusive operations. Therefore, in order to perform weighted fair control after priority control or perform priority control after weighted fair control, a conventional communication quality control device requires a selector for changing the connection relationship such as a scheduler. To do. Therefore, there is a problem that the circuit scale further increases.

  In the prior art, the speed of adding the weight to each input must match the maximum performance handled by the scheduler. For this reason, the conventional communication quality control device needs to take one of the following measures: parallelization of the adder circuit / increase in operating frequency / increase in the addition unit, or an increase in circuit scale, power consumption, This causes problems such as an increase in design complexity and a decrease in scheduling accuracy.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a communication quality control apparatus and a communication quality control method capable of reducing the circuit scale and improving the scheduling accuracy. It is in.

In order to solve the above-described problem, the present invention determines an output priority based on a weight value set for each input port of a scheduling circuit, and transmits a transmission packet allocated to each input port according to the output priority order. In the communication quality control apparatus, the scheduling circuit includes at least a priority among a transmission packet transmission request, a priority, a quotient, and a round robin value, which are a plurality of reference values held for each input port. And an input selection comparison value generation unit that generates an input selection comparison value, a selection unit that compares the input selection comparison value and selects an input port having the smallest value, and the maximum value is A calculation unit that divides the frame length of a transmission packet for a small input port by a weight value set for the input port; and The quotient and the remainder that are the division results are used as one of the plurality of reference values when the input selection comparison value generation means generates the input selection comparison value when the input port is selected next time. And holding means that holds the group number assigned to the input port having the smallest value when the group number assigned to the input port matches the group number assigned to the input port having the smallest value. The quotient and remainder for the input port with the same group number as the number are overwritten by the quotient and remainder for the input port with the smallest value, and the group number assigned to the input port becomes the input port with the smallest value. If the group number does not match, the quotient for the other input port that does not match the group number is set to the input port with the smallest value. And control means for reducing quotient for a communication quality control unit, it characterized in that it comprises a.

  Further, in the present invention according to the above invention, the input selection comparison value generating means performs weighted fair control, priority control, weighted fair control and priority control, or priority control and weighted fair control. The combination of reference values for generating the input selection comparison value is changed to generate the input selection comparison value.

In order to solve the above-described problem, the present invention determines an output priority based on a weight value set for each input port of the scheduling circuit, and is assigned to each input port according to the output priority order. In the communication quality control method for outputting a transmission packet, at least a priority among transmission request, priority, quotient, and round robin value of a transmission packet, which are a plurality of reference values held for each input port of the scheduling circuit And the quotient are combined to generate an input selection comparison value, the input selection comparison value is compared, the input port having the smallest value is selected, and the transmission packet for the input port having the smallest value Dividing the frame length by the weight value set for the input port, and the quotient and remainder as a result of the division , The next time the input port selection, the step of holding against the input port, the group number assigned to the input port is the most value smaller as said plurality of reference values in generating the input selection comparison value If it matches the group number assigned to the input port, the quotient and the remainder for the input port assigned the same group number as the group number assigned to the input port with the smallest value are the highest value. If the group number assigned to the input port does not match the group number assigned to the input port with the smallest value, the group number does not match. communication quality control, characterized in that it comprises the steps of subtracting the quotient with respect to other input ports quotient with respect to the most value is less input ports, the It is the law.

  Further, the present invention is the above invention, wherein the input selection comparison value is determined based on whether the weighted fair control, priority control, weighted fair control and priority control, or priority control and weighted fair control is executed. It is generated by changing the combination of reference values.

  According to the present invention, the communication quality control apparatus can greatly reduce the performance required for the addition / subtraction process, and can obtain the advantages that the circuit scale can be reduced and the scheduling accuracy can be improved.

  Further, according to the present invention, it is possible to realize only priority control / only weighted fair control / preceding priority control / backward weighted fair control / preceding weighted fair control / backward priority control. Thus, it is possible to eliminate the selector that was necessary in the above-described method, and the advantage that the circuit scale can be further reduced can be obtained.

It is a block diagram which shows the structure of the QoS circuit by 1st Embodiment of this invention. It is a conceptual diagram which shows the cumulative value in the case of performing a floating point operation, a fixed point operation in which the remainder is included in the calculation, or a fixed point operation in which the remainder is not included in the calculation with respect to the frame length. It is a conceptual diagram which shows an example of how each register value changes in WFQ (Weighted Fair Queuing: Weighted fair control) of 3 inputs. It is a block diagram which shows the structure of the scheduling circuit 10 by this 1st Embodiment. 5 is a flowchart for explaining an operation during WFQ or preceding-stage PQ (Priority queuing) priority WFQ control in the first embodiment. 6 is a flowchart for explaining an operation during PQ or front-stage WFQ rear-stage PQ control in the first embodiment. It is a conceptual diagram which shows the comparison value for input selection at the time of WFQ or front stage PQ back stage WFQ control. It is a conceptual diagram which shows the comparison value for input selection at the time of PQ or front stage WFQ back stage PQ control. It is a conceptual diagram which shows the numerical value (dividend) divided by the input weight. It is a conceptual diagram which shows the operation | movement outline | summary in WFQ mode. It is a conceptual diagram which shows the operation | movement outline | summary in the back | latter stage WFQ mode by the front | former stage PQ. It is a conceptual diagram which shows the operation | movement outline | summary in PQ mode. It is a conceptual diagram which shows the operation | movement outline | summary in the back | latter stage PQ mode by the front | former stage WFQ. It is a block diagram which shows the structure of the QoS circuit by 2nd Embodiment of this invention.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

A. First Embodiment First, a first embodiment of the present invention will be described.
FIG. 1 is a block diagram showing a configuration of a QoS circuit according to the first embodiment of the present invention. In the figure, a packet input to the QoS circuit is subjected to reception processing in the reception unit 1 and supplied to an identification unit 2 and a first-in first-out (FIFO) 3. In the identification unit 2, for example, quality classification is performed based on a TOS (Type Of Service) value, an IP address, and a port number, and the result is supplied to the identification result generation unit 4. The TOS value is included in the header of the IP packet, and is used for designating the processing priority for the purpose of controlling QoS.

  The identification result generation unit 4 generates control information (packet length, virtual quality class, output port, etc.) used in the QoS circuit and supplies it to the transmission packet generation unit 5. The transmission packet generation unit 5 receives control information from the identification result generation unit 4 to read data from the FIFO 3, rewrites packets associated with TTL (Time To Live) subtraction and NAT (Network Address Translation) processing, The data received from the identification result generation unit 4 is supplied to the packet writing unit 6.

  Note that the TTL subtraction is a process for subtracting the lifetime of a packet (TTL) when performing packet transfer processing and preventing a data destination from being found and falling into an infinite loop. The NAT process is a process for mutually converting a local address and a global address used in the network.

  The packet writing unit 6 stores the received packet and the identification result in the packet buffer 7. Further, the packet writing unit 6 generates packet information regarding the written packet from the identification result and the like, and passes it to the queue unit 8. The queue unit 8 is a memory, for example, and has a queue that holds packet information for each of a plurality of interfaces. The queue determination unit 9 determines the received packet information from the virtual quality class, the output port, and the like, which are control information for determining which queue of which interface among the plurality of interfaces is to be queued. Ing. If the queue is empty, the queue determination unit 9 causes the scheduling circuit 10 to transmit a transmission request, a frame length, and a queue number for each queue of the queue unit 8. The scheduling circuit 10 performs scheduling by priority control, weighted round robin, shaping, or the like according to the availability of the destination of the received information and the internal state, and sends it to the packet reading unit 11.

  The weighted round robin means that resources are allocated in order according to weighting. Shaping is a method for guaranteeing communication performance by controlling traffic on a network and delaying packets.

  The packet reading unit 11 that has received the transmission request acquires packet information from the queue unit 8 from the queue number corresponding to the received request, and reads information such as the position in the packet buffer 7 where the packet requested for transmission is located. Further, the packet reading unit 11 checks whether the packet can be transmitted to the transmission unit 12. If possible, the packet reading unit 11 reads the packet from the packet buffer 7 according to the previously acquired position, and sends the packet to the transmission unit 12. Send it out. Further, the packet reading unit 11 also sends a transmission request acceptance signal to the scheduling circuit 10.

  The transmission unit 12 monitors the output state, notifies the packet reading unit 11 whether the packet is ready to be transmitted, and transmits the packet received from the packet reading unit 11 according to the output format. . Further, the queue unit 8 that has received the acceptance signal deletes the first queue queued in the queue, and if the next queue remains as a result, sends a transmission request for the queue to the scheduling circuit 10. To do.

  Next, an embodiment of the scheduling circuit 10 will be described in detail. Before that, the basic operation of the above-described weighted fair control circuit will be described. In the above description, the above-described weighted fair control circuit has been described as adding a value proportional to the weight, but in the following, this will be described as subtraction. Similarly, at the time of packet transmission, it has been described that the input counter is subtracted by the packet length.

(S1) The already described weighted fair control circuit receives a transmission request from the queue unit 8.

(S2) The packet information and the transmission request from the input selected for output are output to the packet reading unit 11.

(S3) The packet length of the packet requested for transmission is added to the counter of the input port selected for output.

(S4) The weight value preset for each input port is subtracted from the counter of each input port at a predetermined cycle (for example, every system clock). This subtraction stops when there is no transmission request for the input (when WaitCnt is 0 and no transmission request is detected), and a negative number is returned to the total counter.

(S5) When an acceptance signal is received from the packet reading unit 11, the acceptance signal is output to the queue unit 8.

(S6) A value of JudgeWait, which is an upper limit value of waiting, is set in WaitCnt, which is a counter that performs waiting control.

(S7) The value of WaitCnt is subtracted by 1 at a predetermined cycle (for example, every system clock) until the value of WaitCnt becomes 0.

(S8) When the value of WaitCnt becomes 0, the input port whose input counter value is 0 or less is selected.

  That is, the above-described weighted fair control circuit subtracts the weight value at a predetermined period in step S4, and sets a request from the input port that has become 0 or less as a transmission request to the packet reading unit 11. In addition, when the plurality of weighted fair control circuits are 0 or less, the input is selected by round robin (to step S2 above). The input counter adds the frame length in step S3 when the transmission request is output to the packet reading unit 11. When there is no transmission request to the input port, step S1 is performed, and the next transmission request is received.

  As described above, the previously described weighted fair control circuit can appropriately control the transmission timing of the transmission request to the packet reading unit 11 by controlling the counter.

  The operation of the WFQ (Weighted Fair Queuing) circuit described above is expressed by mathematical formulas, and based on this, the basic principle of WFQ control of the present embodiment will be described below.

  In the WFQ control according to the present embodiment, when the input counter is cnt [i] (i is the input port number), the weight value is weight [i] (i is the input port number), and the frame length is flen, each input Since the value of the counter cnt [i] is subtracted by the weight value at a predetermined period, the following equation (1) is obtained.

cnt [i] = cnt [i] -weight [i] (1)
However, cnt [i]> 0

When both sides of the above formula (1) are divided by weight [i],
cnt [i] / weight [i] = cnt [i] / weight [i] -1
It becomes.

  Here, when CNT [i] = cnt [i] / weight [i], it is expressed by the following equation (2).

CNT [i] = CNT [i] -1 (2)

  In this case, cnt [i] first becomes 0 or less obviously when | CNT [i] | is the smallest input. From this, the scheduling circuit 10 continues to subtract weight [i] as shown in Equation (1), and selects an input port whose value is 0 or less. Alternatively, the scheduling circuit 10 can select an input port for sending a transmission request by comparing the sizes of CNT [i], rather than waiting for the value to become 0 or less, thereby speeding up arithmetic processing. Can be planned.

  The cnt [i] of each input port is updated by continuing to subtract weight [i] from cnt [i] until the cnt [i] of a certain input port becomes 0 or less. Therefore, assuming that the minimum value of CNT [i] of all inputs is CNTmin, by subtracting CNT [i] corresponding to each input port by CNTmin, until cnt [i] of a certain input port becomes 0 or less, This is the same as continuing to subtract weight [i] from cnt [i] of each input port.

  That is, the scheduling circuit 10 can update CNT [i] corresponding to each input port by calculating CNT [i] = CNT [i] −CNTmin. For this reason, the scheduling circuit 10 can simplify the processing and speed up the arithmetic processing as compared with the case of continuing to subtract weight [i] until cnt [i] becomes 0 or less. This part is very different from the conventional one.

  Further, when sending a transmission request to the packet reading unit 11, it is necessary to add the frame length flen to cnt [i]. That is, CNT [i] can be expressed by the following formula (3).

CNT [i] = (cnt [i] + flen) / weight [i] = CNT [i] + flen / weight [i] (3)

  In the above formula (3), it is conceivable that the calculation of flen / weight [i] is performed in floating point, but division of floating point generally increases the calculation cost (circuit scale, etc.). Therefore, in addition to dividing by floating point, dividing by fixed point is also conceivable. It is preferable to use a fixed point in terms of hardware and high-speed processing.

  However, because there is a fixed point, there are cases where it cannot be divided, and the remainder R [i] causes a cumulative error. Therefore, as shown in the following equation (4), by adding the remainder to the frame length flen at the time of the next calculation, the scheduling circuit 10 can reduce the accumulated error to 0, and the problem of performing fixed-point division is solved. The If the value of CNT [i] before the division is CNT ′ [i], the quotient resulting from the division is Q [i], and the remainder is R [i], it can be expressed by the following equation (4). it can.

CNT [i] = CNT ′ [i] + flen / weight [i] = CNT ′ [i] + (flen−R [i]) / weight [i] + R [i] / weight [i]
= CNT '[i] + Q [i] + R [i] / weight [i] (4)

  It becomes. When the next division opportunity is obtained, it is similarly expressed by the following equation (5).

CNT [i] = CNT ′ [i] + flen / weight [i]
= CNT ″ [i] + Q ′ [i] + R ′ [i] / weight [i] + flen / weight [i]
= CNT ″ [i] + Q ′ [i] + (flen + R ′ [i] −R [i]) / weight [i] + R [i] / weight [i]
= CNT ″ [i] + Q ′ [i] + Q [i] + R [i] / weight [i]
...... (5)

  Here, CNT ″ [i] is the value of CNT [i] two times before the division, and Q ′ and R ′ are the quotient and the remainder when the previous division is performed. Since R satisfies 0 ≦ R <weight [i], the accumulated error falls within weight [i].

  For example, FIG. 2 is a conceptual diagram showing a cumulative value in the case of performing a floating point operation, a fixed point operation in which a remainder is included in the calculation, or a fixed point operation in which a remainder is not included in the calculation with respect to the frame length. If a fixed-point operation in which the remainder according to the above-described embodiment is included in the calculation is used, the difference from the accumulated result of the floating-point operation is only after the decimal point. However, it is shown that errors are accumulated one after the other in the case of fixed-point arithmetic that does not perform extra addition.

  Further, by dividing the CNT [i] and flen by m bits to the left by the maximum value m (the maximum value that can be taken by weight [i]) for division, division is not necessary, and only bit combination is required. The processing time can be further reduced. Specifically, it is represented by the following formula (6).

CNT [i] << m-R [i] = CNT [i] << m- (flen << m + R '[i]) / weight [i] (6)

  Here, R ′ [i] is the remainder of the division performed when the previous input i was selected as the transmission request. As described above, the scheduling circuit 10 does not use the value of the input counter cnt [i], but uses CNT [i] obtained by dividing cnt [i] by weight [i] and its minimum value CNTmin. It is possible to easily perform an update process by selecting an input for sending a transmission request and subtracting by a weight value, and the calculation time can be increased.

  In addition, in the calculation for adding the packet length when the packet is sent to the packet reading unit 11 and updating the value of CNT [i], the scheduling circuit 10 uses the remainder when using a fixed point as described above. By appropriately processing the error accumulation due to the above, the value of CNT [i] can be updated by a simple process, and the calculation process can be speeded up.

  FIG. 3 is a conceptual diagram showing an example of how each register value changes in a WFQ with three inputs. In the initial state (0), a transmission request is received at input 0 and input 1 at time t1 when there is no input. At this time, since cnt [i] has the smallest input 0, the input 0 is selected, and (1000 << 5 + 2) / 3 = 10667. Also, 1000 which was the value of cnt [0] is subtracted from other inputs. Since input 2 becomes negative after subtraction, cnt [2] becomes 0. Also, since the most recently selected round robin value is the largest value, round [0] is changed from 3 to 3, and the round [i] of each other input is decremented by 3 or more. Although it is necessary, since the transmitted value is 3, which is the largest value, no decrement is performed.

  A transmission request is also received at input 2 at time t2 in state (1). Since cnt [2] is the smallest, cnt [2] is selected and 0 is subtracted from each input. cnt [2] is from (100 << 5 + 0) / 1 to 3200. The round robin value round [2] changes from 2 to 3, and the other input round [i] that is 2 or more is decremented, and the input 0 round [0] changes from 3 to 2. By repeating this, the scheduling circuit 10 performs WFQ processing.

  By the way, the following is considered at the stage of selecting an input port. In normal WFQ (weighted fair control), an input having the smallest counter value CNT [i] is selected. By combining the priority value with the MSB side and LSB side of this CNT [i], the following is performed. Selection rules.

(When the priority value is combined with the MSB side)
The one with the smaller priority value has priority over the subsequent CNT [i]. If the priority values are the same, an input with a small CNT [i] is selected.

(When the priority value is combined with the LSB side)
CNT [i] takes precedence and the priority value is ignored unless the CNT [i] values are the same. When CNT [i] is the same, an input with a low priority value is selected.

  Using this rule, the scheduling circuit 10 can eliminate the selector that has been conventionally required to change the connection of the PQ (priority control) / WFQ (weighted fair control) scheduler.

  FIG. 4 is a block diagram showing a configuration of the scheduling circuit 10 according to the first embodiment based on the basic principle of the present invention described above. The scheduling circuit 10 includes a control circuit 101, a control table 102, and an arithmetic circuit 103. The control table 102 includes, for each input port, a transmission request (not 0, 1) indicating whether a transmission request is received at the input port, the frame length of the transmission request packet requested for the input port, Group number for controlling the input port, WFQ weight, PQ priority, round robin value used for performing round robin control, quotient indicating the above CNT [i] for the input, remainder of CNT [i] Remember. The control circuit 101 holds the above-described JudgeWait and WaitCnt and stores the set operation mode. The control circuit 101 executes processes shown in FIGS. 5 and 6 to be described later according to various values stored in the control table 102. The arithmetic circuit 103 performs addition / subtraction, division and the like accompanying the processing by the control circuit 101.

Next, the operation of the scheduling circuit 10 during WFQ or front-stage PQ rear-stage WFQ control will be described.
FIG. 5 is a flowchart for explaining the operation during WFQ or front-stage PQ rear-stage WFQ control in the first embodiment. The control circuit 101 determines whether or not a transmission request has been received at any of the input ports (step Sa1). If the transmission request has not been received (NO in step Sa1), the transmission request is received. This determination is made until.

  On the other hand, when a transmission request is received at any one of the input ports (YES in step Sa1), the control circuit 101 uses the input n (0 to N) as information for comparison as shown in FIG. The transmission request, the quotient, the round robin counter, and the priority value are concatenated to create an input selection comparison value (step Sa2). Concatenation is one method for simply performing comparison, and since comparison priority order is performed from the left, comparison may be performed for each element, but when the search bit length can be increased using hardware or the like, Processing time is shorter when compared at once.

  Here, FIG. 10 is a conceptual diagram showing an operation outline in the WFQ mode, and FIG. 11 is a conceptual diagram showing an operation outline in the preceding stage PQ and in the subsequent stage WFQ mode. In the case of the WFQ mode, for example, as shown in FIG. 10, in the scheduling circuit 10, groups 0 to 3, priority 7, weights 24, 89, 8 and 254 are set to the input ports 0 to 3, respectively. Has been. In this case, the band division is output at a ratio of input port 0: input port 1: input port 2: input port 3 = 24: 89: 8: 254.

  Further, in the case of the post-stage WFQ mode in the pre-stage PQ, for example, as shown in FIG. 11, in the scheduling circuit 10, the input ports 0 to 3 are assigned to groups 0, 0, 1, 3, respectively, priority 0, 1, 1, 0 and weights 24, 24, 254, 254 are set. In this case, the output priority order of the front stage PQ (group 0) is the input port 0: high priority, the input port 1: low priority, the front stage PQ (group 1) is the input port 2: low priority, and the input port 3: high priority. Band division is PQ (group 0) output: PQ (group 1) output = 24: 254.

  Next, the control circuit 101 compares the input selection comparison values of the inputs n (0 to N) to obtain the input Nmin having the smallest input selection comparison value (step Sa3). In this comparison, the bit inversion of the input request is set to MSB. When there is a transmission request, the bit of the input request is 1, and when it does not exist, the bit of the input request is 0. . Naturally, since 0 (with transmission request) is selected as the minimum value, it is possible to determine whether there is a transmission request by comparing the size. If the MSB is 1 as a result of searching for the minimum value, it indicates that there is no input requesting transmission, and it is possible to easily determine whether there is a transmission request for any of the inputs. It becomes.

  Next, the control circuit 101 transmits the frame length and the transmission request of the input Nmin having the minimum input selection comparison value for each input to the packet reading unit 11 (step Sa4). Incidentally, a round robin counter is also connected to the input selection comparison value. This is because, when obtaining the minimum value, if the same value exists, or if there are inputs that become 0 or less at the same time, it is necessary to round and select the corresponding input when performing WFQ processing. . In this process, tmp = input 0 round robin counter, input 0 round robin counter = input 1 round robin counter, input 1 round robin counter = input 2 round robin counter, input 2 round robin counter = input 3 round robin counter, This is realized by setting the input 3-round robin counter = tmp.

  Alternatively, a method of realizing round robin by using another storage means without using this round robin value and selecting the least transmitted input from the past transmission history can be considered. For example, when the number of input ports is 4, when input 2 is selected as a transmission request port, each input i round robin value having a value larger than the input 2 round robin counter is decremented by 1 and input 2 rounds Robin value = 3. By doing this, it will have the values 3, 2, 1, 0 in the order of the most recent transmission, and if the parameter values are exactly the same in the minimum value comparison, the input that has not transmitted the most in the past will be selected. Become.

  Next, the arithmetic circuit 103 divides the dividend generated by combining (adding) the remainder of the input having the minimum value to the frame length of the packet requested to be transmitted by the weight of the input Nmin, and the quotient and remainder of the control table 102. Is updated (step Sa5). This combination (addition) can be realized by a concatenation process as shown in Equation (6) and FIG. 9, and the amount of calculation processing can be reduced. The quotient and remainder are set as the quotient and remainder corresponding to the input port of the control table 102.

  Next, the control circuit 101 determines whether the group number of the input n (0 to N) matches the group number of the input Nmin (step Sa6). The quotient / remainder for the input port belonging to the same group as the input Nmin having the minimum value is overwritten by the quotient / remainder of the input Nmin having the minimum value (step Sa7). On the other hand, for other input quotients that do not match, the quotient of input Nmin having the minimum value is subtracted from the quotient of other input n (step Sa8). However, when the quotient is reduced and becomes negative, the quotient is set to 0. In some cases, the remainder is set to zero.

  As a result, when the operation mode is the WFQ (FIG. 10) or the previous-stage PQ latter-stage WFQ (FIG. 11) mode, the same group always has the same quotient / remainder. You will have a quotient and a remainder. Since the values used for the minimum value comparison are in the form shown in FIG. 7, the prioritization within a certain group is determined by the priority assigned to the LSB side, so that the WFQ or the previous-stage PQ latter-stage WFQ operation is performed.

  Finally, it waits until WaitCnt expires (step Sa9), and adjusts the time until the start of reception of the next transmission request. That is, the QoS circuit controlled by the transmission / reception of the request / acceptance signal shown in FIG. 1 needs to adjust the request reception time after the transmission is accepted. When this WaitCnt receives an acceptance signal from the packet reading unit 11, it writes the value of JudgeWait set in advance in WaitCnt of the control circuit 101. Then, an acceptance signal is transmitted to the queue unit 8 connected to the selected input. WaitCnt is subtracted at a predetermined cycle (for example, every system clock). Subtraction is repeatedly performed until the value of WaitCnt becomes 0, and when it becomes 0, the subtraction of WaitCnt is stopped. When the value of WaitCnt becomes 0, the process returns to the minimum value selection and the minimum input is selected.

Next, the operation at the time of PQ or front-stage WFQ rear-stage PQ control will be described.
FIG. 6 is a flowchart for explaining the operation at the time of PQ or front-stage WFQ rear-stage PQ control in the first embodiment. In the flowchart shown in FIG. 6, the difference from FIG. 5 is the processing in step Sb2 and step Sb6 and subsequent steps.

  FIG. 12 is a conceptual diagram showing an outline of the operation in the PQ mode, and FIG. 13 is a conceptual diagram showing an outline of the operation in the rear stage PQ mode in the preceding stage WFQ. In the PQ mode, for example, as shown in FIG. 12, in the scheduling circuit 10, priority levels 0 to 3 and weights 255 are set for the input ports 0 to 3, respectively. The output priority order is input port 0: high priority, the priority order decreases sequentially, and input port 3: low priority.

  In the case of the front stage WFQ and the rear stage PQ mode, for example, as shown in FIG. 13, in the scheduling circuit 10, the input ports 0 to 3 have priority levels 0, 0, 1, 1, weights 24, 89, 8, and 254 are set. In this case, the bandwidth division is input port 0: input port 1 = 24: 89 at the preceding stage WFQ (0), and input port 2: input port 3 = 8: 254 at the preceding stage WFQ (1). The output priority is WFQ (0): High priority and WFQ (1): Low priority.

  When the operation mode is PQ, front WFQ, and rear PQ mode, as shown in FIG. 8, the control circuit 101 uses the transmission request, priority, quotient, and input n (0 to N) as information for comparison. The values of the round robin counter are concatenated to create an input selection comparison value (step Sb2). In this case as well, comparison may be performed for each element.

  When the operation mode is PQ or the previous-stage WFQ latter-stage PQ mode, the control circuit 101 determines whether the priority of the input n (0 to N) matches the priority of the input Nmin (step Sb6). If they match, the quotient of the input Nmin having the minimum value is subtracted from the quotient for the input n having the same priority as the input Nmin having the minimum value. However, when the quotient is reduced and becomes negative, the quotient is set to 0. In some cases, the remainder is set to zero.

  In this case, the influence of the WFQ operation shown above only affects the same priority (in other words, a group). As a result, the WFQ operation is performed within the same priority. However, in the minimum value comparison, since the priority comparison exists on the MSB side, PQ or PQ or The operation of the front stage WFQ and the rear stage PQ is performed.

B. Second Embodiment A second embodiment of the present invention will be described.
FIG. 14 is a block diagram showing a configuration of a QoS circuit according to the second embodiment of the present invention. It should be noted that portions corresponding to those in FIG. The difference from the configuration shown in FIG. 1 is that a transmission packet generation unit 5 that performs packet rewriting such as TTL subtraction or IP address rewriting after packet transmission is arranged between the packet reading unit 11 and the transmission unit 12. In the point.

  The advantage of the configuration shown in FIG. 14 is that the packet (FIFO 3 in FIG. 1) up to packet writing can be eliminated because the packet can be written to the packet buffer 7 immediately after reception. However, it is necessary to store in the queue unit 8 information for performing packet rewriting after reading the packet. For this reason, the circuit scale of the queue unit 8 may increase depending on the size of the queue unit 8, but since the FIFO 3 is eliminated, the circuit scale of the device may be reduced. Which of the configurations of FIG. 1 and FIG. 14 is used may be selected by comparing circuit scales based on the size of the FIFO 3 and the size of the queue unit 8.

  According to the first and second embodiments described above, the scheduling circuit 10 can perform a subtraction process for each input only when a packet transmission request is made, and can greatly reduce the required performance for the addition / subtraction process. Can be reduced and the scheduling accuracy can be improved.

  Further, the scheduling circuit 10 can change the combination of various counters used at the time of transmission packet selection in weighted fair control and change some processing methods, so that priority control only / weighted fair control only / previous priority control / backward weighted fairness Control / pre-stage weighted fair control and post-stage priority control can be realized, the selector required in the conventional method can be eliminated, and the circuit scale can be further reduced.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

  The present invention is suitable for a communication quality control apparatus and a communication quality control method for performing packet transmission / reception processing.

DESCRIPTION OF SYMBOLS 1 ... Reception part, 2 ... Identification part, 3 ... FIFO, 4 ... Identification result generation part, 5 ... Transmission packet generation part, 6 ... Packet writing part, 7 ... Packet buffer, 8 ... Queue part, 9 ... Key determination part, DESCRIPTION OF SYMBOLS 10 ... Scheduling circuit, 11 ... Packet reading part, 12 ... Transmission part, 101 ... Control circuit, 102 ... Control table, 103 ... Arithmetic circuit

Claims (4)

In the communication quality control apparatus for determining the output priority based on the weight value set for each input port of the scheduling circuit and outputting the transmission packet allocated to each input port according to the output priority order,
The scheduling circuit includes:
A comparison value for input selection is generated by combining at least the priority and the quotient among the transmission packet transmission request, priority, quotient, and round robin value, which are a plurality of reference values held for each input port. Input selection comparison value generating means to
Selecting means for comparing the input selection comparison values and selecting the input port having the smallest value;
A calculation means for dividing the frame length of the transmission packet for the input port having the smallest value by the weight value set for the input port;
The quotient and the remainder, which are the division results by the calculation means, are input as one of the plurality of reference values when the input selection comparison value generation means generates the input selection comparison value at the next input port selection. Holding means for holding against the port ;
When the group number assigned to the input port matches the group number assigned to the input port having the smallest value, the same group number as the group number assigned to the input port having the smallest value is set. The quotient and remainder for the input port assigned are overwritten by the quotient and remainder for the input port with the smallest value, and the group number assigned to the input port is the same as the group number assigned to the input port with the smallest value. If not, control means for subtracting the quotient for the other input port whose group number does not match by the quotient for the input port having the smallest value;
A communication quality control apparatus comprising: The input selection comparison value generating means includes
Depending on whether to perform weighted fair control, priority control, weighted fair control and priority control, or priority control and weighted fair control, the combination of reference values for generating the input selection comparison value is changed, Generating the input selection comparison value;
The communication quality control apparatus according to claim 1. In a communication quality control method for determining an output priority based on a weight value set for each input port of a scheduling circuit and outputting a transmission packet allocated to each input port according to the output priority order,
Comparison of input selection by combining at least priority and quotient among transmission request, priority, quotient, and round robin value, which are a plurality of reference values held for each input port of the scheduling circuit. Generating a value;
Comparing the input selection comparison value and selecting the input port with the smallest value;
Dividing the frame length of the transmission packet for the input port with the smallest value by the weight value set for the input port;
Holding the quotient and the remainder as the division result for the input port as the plurality of reference values when generating the input selection comparison value at the next input port selection ;
When the group number assigned to the input port matches the group number assigned to the input port having the smallest value, the same group number as the group number assigned to the input port having the smallest value is set. The quotient and remainder for the input port assigned are overwritten by the quotient and remainder for the input port with the smallest value, and the group number assigned to the input port is the same as the group number assigned to the input port with the smallest value. If not, subtracting the quotient for the other input port that does not match the group number by the quotient for the input port with the smallest value;
A communication quality control method comprising: The input selection comparison value is
Depending on whether to perform weighted fair control, priority control, weighted fair control and priority control, or priority control and weighted fair control, the combination of the plurality of reference values is generated,
The communication quality control method according to claim 3.

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