JP4803079B2 - Demodulator - Google Patents

Description

  The present invention relates to a demodulation device capable of demodulating a signal of a predetermined modulation method.

  In recent years, in mobile communication systems such as mobile phones, systems using various communication methods such as W-CDMA (Wideband-Code Division Multiple Access), GSM (Global System for Mobile Communications), EDGE (Enhanced Data GSM Environment), etc. Has been put to practical use. As a modulation method of these communication methods, PSK (Phase Shift Keying) and GMSK (Gaussian filtered MSK) are used.

  As the digital demodulation circuit in the above-described modulation system, a synchronous detection circuit that performs carrier recovery of an input modulated wave using a voltage controlled oscillator (VCO) of a PLL (Phase Lock Loop) loop has been used (for example, patent document) 1). This demodulator circuit is called a Costas demodulator circuit. The input modulated wave is detected by two synchronous detectors using oscillation signals whose phases are different from each other by 90 °, and the detected signal is subjected to multilevel discrimination and output as reproduction data. At the same time, the VCO is controlled according to an error signal when the arrangement of the detection signals deviates from the normal position, and phase synchronization is performed.

A modified Costas demodulator circuit is also used as the digital demodulator circuit in the above modulation method (see, for example, Patent Document 2). In the modified Costas demodulator, an in-phase detection output is obtained from the modulated wave input from the input terminal via the first multiplier and the first low-pass filter, and the second multiplier and the second multiplier A quadrature detection output is obtained through a low-pass filter. The in-phase detection output and the quadrature detection output are input to the data recovery circuit and are input to the third multiplier. Here, when there is a frequency error or phase error in the detection output, the output of the third multiplier and the timing output from the clock recovery circuit are multiplied by the fourth multiplier and passed through the loop filter. An error signal is input to the VCO, and the VCO is controlled. Based on this, the regenerated carrier wave is input from the VCO to the second multiplier via the first multiplier and the π / 2 phase shifter. The demodulated data output and the timing clock synchronized with the demodulated data output are output from the data recovery circuit and the clock recovery circuit, respectively.
JP-A-6-216769 Japanese Patent Laid-Open No. 9-69861

  However, in the above conventional demodulation circuit, there is a demand for easily reproducing the timing of symbol point extraction. In addition, the conventional demodulation circuit cannot demodulate a plurality of modulation signals using the same circuit. The timing of signal symbol point extraction varies depending on the modulation method. For this reason, as a configuration for receiving signals of a plurality of modulation schemes by the same circuit, a configuration in which parameters are changed according to the modulation scheme and the timing of symbol point extraction is reproduced can be considered, but the circuit is complicated and large in scale. Therefore, there is a problem that the manufacturing cost is increased.

  An object of the present invention is to easily reproduce the symbol timing of a signal of a predetermined modulation system.

In order to solve the above-described problem, a demodulator according to claim 1 provides:
A burst signal divided into an I component and a Q component by a predetermined modulation method is delayed by a delay time obtained by multiplying the symbol time by a value that is an integral multiple of π when multiplied by the symbol rotation amount of the predetermined modulation method. An inner product value calculation unit that calculates an inner product value of the divided burst signal and the delayed burst signal and outputs the inner product value signal;
An absolute value calculation unit that calculates an absolute value of the inner product value signal and outputs the absolute value signal;
A maximum value detecting unit for detecting a maximum value of the absolute value signal and outputting it as a symbol timing signal;
A first symbol point extraction unit that extracts a symbol point of the I component signal based on the symbol timing signal;
A second symbol point extracting unit for extracting a symbol point of the Q component signal based on the symbol timing signal;
A phase detector for detecting the phase of the extracted symbol points;
A demodulator that reversely rotates and demodulates the signal of the symbol point from which the phase has been detected based on the predetermined modulation method.

The invention according to claim 2 is the demodulator according to claim 1,
A first equalizing filter for removing intersymbol interference of the I component of the burst signal divided and input into the I component and the Q component of the predetermined communication method;
A second equalizing filter for removing intersymbol interference of the Q component of the divided burst signal,
The inner product value calculation unit is configured to delay the I- and Q-component signals from which the inter-symbol interference has been removed by the delay time, and to remove the inter-symbol interference from the burst signal and the delayed burst. The inner product value with the signal is calculated and output as an inner product value signal,
The first symbol point extraction unit extracts a symbol point of an I component signal from which the inter-symbol interference is removed based on the symbol timing signal,
The second symbol point extraction unit extracts a symbol point of a Q component signal from which the inter-symbol interference is removed based on the symbol timing signal.

The invention according to claim 3 is the demodulator according to claim 1 or 2,
The inner product value calculation unit includes:
A first delay unit that delays the I component signal by the delay time;
A second delay unit that delays the Q component signal by the delay time;
A first multiplier that multiplies the I-component signal from which the inter-symbol interference has been removed and the time-delayed I-component signal and outputs the result as a first multiplied signal;
A second multiplier that multiplies the Q-component signal from which the intersymbol interference has been removed and the time-delayed Q-component signal and outputs the result as a second multiplied value signal;
A first adder that adds the first and second multiplication value signals and outputs the result as the inner product value signal.

The invention according to claim 4
A first equalizing filter that removes intersymbol interference of the I component of the burst signal that is divided and input into a plurality of I and Q components of different modulation schemes;
A second equalizing filter for removing intersymbol interference of the Q component of the divided burst signal;
The I- and Q-component training sequence signals from which the inter-symbol interference has been removed are delayed by a delay time obtained by multiplying the symbol time by a value that is an integral multiple of π when multiplied by the symbol rotation amount of the different modulation method. An inner product value computing unit that computes an inner product value of the burst signal from which the inter-symbol interference has been removed and the delayed burst signal and outputs the inner product value signal;
An absolute value calculation unit that calculates an absolute value of the inner product value signal and outputs the absolute value signal;
A maximum value detecting unit for detecting a maximum value of the absolute value signal and outputting it as a symbol timing signal;
A first symbol point extraction unit that extracts a symbol point of an I-component signal from which the inter-symbol interference is removed based on the symbol timing signal;
A second symbol point extraction unit that extracts a symbol point of a Q-component signal from which the inter-symbol interference is removed based on the symbol timing signal;
A phase detector for detecting the phase of the extracted symbol points;
A modulation scheme determination unit that determines a modulation scheme based on the phase of the detected symbol point;
And a demodulator that demodulates the signal of the symbol point from which the phase is detected based on the determined modulation method.

The invention according to claim 5 is the demodulator according to claim 4,
The inner product value calculation unit includes:
A first delay unit that delays the I-component signal from which the intersymbol interference is removed by the delay time;
A second delay unit that delays the signal of the Q component from which the intersymbol interference is removed by the delay time;
A first multiplier that multiplies the I-component signal from which the inter-symbol interference has been removed and the time-delayed I-component signal and outputs the result as a first multiplied value signal;
A second multiplier that multiplies the Q-component signal from which the intersymbol interference has been removed and the time-delayed Q-component signal and outputs the result as a second multiplied value signal;
A first adder that adds the first and second multiplication value signals and outputs the result as the inner product value signal.

The invention according to claim 6 is the demodulator according to claim 4 or 5,
A symbol reverse rotation unit configured to reversely rotate the symbol point from which the phase is detected based on the determined modulation method;
The demodulator demodulates the signal of the reversely rotated symbol point based on the determined modulation method.

The invention according to claim 7 is the demodulator according to claim 4 or 5,
The demodulating unit demodulates a signal based on the determined modulation scheme, taking into account the phase rotation given on the transmission side, on the symbol point where the phase is detected.

The invention according to claim 8 is the demodulation apparatus according to any one of claims 1 to 7,
A moving average value calculating unit that calculates a moving average value using the absolute value signal separated by a symbol time and outputs it as a moving average value signal while continuously moving the calculation range,
The maximum value detection unit detects a maximum value of the moving average value signal and outputs the maximum value as a symbol timing signal.

The invention according to claim 9 is the demodulator according to claim 8,
The moving average value calculator is
At least one stage of a set of a third delay unit that delays the absolute value signal by a symbol time and a second adder that adds the absolute value signal and the absolute value signal delayed by the symbol time is provided. And

  According to the first, second, and third aspects of the present invention, the symbol timing of a signal of a predetermined modulation method can be easily reproduced.

  According to the fourth, fifth, and sixth aspects of the present invention, the symbol timing of a plurality of signals of different modulation schemes can be easily reproduced with the same configuration. In addition, since the demodulation (decoding) process can be performed after the symbol point is determined, the circuit scale can be reduced.

  According to the seventh aspect of the present invention, the demodulator can demodulate in consideration of the symbol point phase rotation unit, and the apparatus configuration can be simplified.

  According to the eighth aspect of the present invention, the symbol timing can be reproduced more accurately.

  According to invention of Claim 9, a moving average value calculating part can be comprised easily.

  Hereinafter, with reference to the drawings, a first embodiment of the present invention and a first modification thereof, and a second embodiment and a second modification thereof will be described in order. However, the scope of the invention is not limited to the illustrated examples.

(First embodiment)
A first embodiment according to the present invention will be described with reference to FIGS. First, with reference to FIG. 1 and FIG. 2, the device configuration of the demodulation device 100 corresponding to one modulation system of the present embodiment will be described. FIG. 1 shows an internal configuration of the demodulator 100. FIG. 2 shows an internal configuration of the moving average value calculation unit 16.

  Demodulation apparatus 100 of the present embodiment is an apparatus that receives and demodulates a signal whose communication method is GSM. The GSM modulation method is GMSK (BPSK).

  As shown in FIG. 1, the demodulator 100 includes an inner product value calculation unit 40, an absolute value calculation unit 15, a moving average value calculation unit 16, a maximum value detection unit 17, and first and second symbol point extractions. Symbol point extraction units 18a and 18b as a unit, a phase detection unit 19, and a demodulation unit 20 are provided. The inner product value calculation unit 40 includes 2T delay units 12a and 12b as first and second delay units, multipliers 13a and 13b as first and second multipliers, and addition as a first adder. And a container 14.

  As illustrated in FIG. 2, the moving average value calculation unit 16 includes T delay units 1611 to 161n (n is an integer of 1 or more) as third delay units and adders 1621 to 162n as second adders. And comprising.

  A GSM burst signal including data modulated by the BPSK modulation scheme is transmitted by a transmission device (not shown), and the demodulation device 100 receives the transmitted burst signal. Specifically, the transmitted burst signal is received by an antenna (not shown) of the demodulator 100, and the received signal is converted into an IF (Intermediate Frequency) by a tuner (not shown). The IF-converted received signal is converted into a digital signal by an A / D (Analog to Digital) converter (not shown), and the digital signal is divided into an I component and a Q component by an IQ signal divider (not shown). .

  The inner product value calculator 40 calculates the inner product value of the received signal of the burst signal and the received signal of the burst signal after 2T delay. 2T is twice the symbol time T.

  The 2T delay units 12a and 12b give a 2T delay to the I component and Q component of the divided received signal, respectively, and output the result. The multipliers 13a and 13b respectively multiply the I component and Q component of the divided received signal by the I component and Q component of the received signal after 2T delay input from the 2T delay units 12a and 12b, The multiplication value signal is output. The adder 14 adds the multiplication value signals input from the multipliers 13a and 13b and outputs the result as an addition value signal. The absolute value calculator 15 calculates the absolute value of the added value signal input from the adder 14 and outputs it as an absolute value signal.

  The moving average value calculation unit 16 has a function of performing an average calculation using absolute values separated by a symbol time T while continuously moving the calculation range. Specifically, the moving average value calculation unit 16 calculates a moving average of symbol time T intervals of the absolute value signal input from the absolute value calculation unit 15 and outputs it as a moving average value signal. More specifically, in the moving average value calculation unit 16, the T delay unit 1611 outputs the absolute value signal input from the absolute value calculation unit 15 with a symbol time T delay. The adder 1621 adds the absolute value signal input from the absolute value calculation unit 15 and the absolute value signal after T delay input from the T delay unit 1611 and outputs the result. The T delay unit 161m (m: an integer satisfying 2 ≦ m ≦ n) outputs the absolute value signal input from the T delay unit 161 (m−1) after being delayed by a symbol time T. The adder 162m adds the absolute value signal input from the adder 162 (m−1) and the absolute value signal after m · T delay input from the delay unit 161m and outputs the result. In this way, the adder 162n outputs the added value as a moving average value signal.

  The maximum value detection unit 17 acquires the timing of the maximum value of the burst signal from the moving average value signal input from the moving average value calculation unit 16, and outputs it as a symbol point extraction timing signal. The symbol point extraction units 18a and 18b extract the symbol points of the I component and Q component of the received signal based on the symbol point extraction timing signal input from the maximum value detection unit 17, respectively.

  The phase detection unit 19 detects and outputs the phase of the symbol point input from the symbol point extraction units 18a and 18b.

  Based on the GMSK (BPSK) modulation scheme, the demodulator 20 demodulates (decodes) the symbol points input from the phase detector 19 in consideration of the amount of phase rotation, and acquires and outputs a data signal.

  Next, a burst signal of GMSK (BPSK) will be described with reference to FIGS. 3 (a), 4 (a), and 4 (b). FIG. 3A shows a BPSK constellation. FIG. 4A shows the configuration of the format format of the burst signal 30. FIG. 4B shows a BPSK training sequence pattern.

As shown in FIG. 3A, when the modulation method is GMSK (BPSK), symbol points of data d _i = 0, 1 are assigned to the positions of black dots on the I (in-phase component) -Q (quadrature component) plane. .

  On the transmitting device side, the symbol points are phase-shifted (phase shifted) by a predetermined amount for each symbol in accordance with the communication method (modulation method). In the case of GSM, for each symbol, the phase of the symbol point is increased by 0 by π / 2 (0, π / 2, (π / 2) × 2, (π / 2) × 3,...) Phase is rotated. .

  The format of the burst signal received and input by the demodulator 100 has a predetermined format, and is the format of the burst signal 30 as shown in FIG. The burst signal 30 includes a tail bit 31, data 32, a training sequence 33, data 34, and a tail bit 35. As shown in FIG. 4B, the training sequence 33 is a predetermined pattern in which values on the I axis are continuous in GMSK.

  Next, the operation of the demodulation device 100 will be described. First, in the demodulator 100, the burst signal 30 transmitted from the transmitter is received, converted into IF and digital, and the burst signal 30 is divided into an I component and a Q component and input.

  The I component and Q component of the input burst signal 30 are delayed by 2T by the 2T delay units 12a and 12b, respectively. As described above, the symbol rotation amount added on the transmission side is π / 2 in GSM (GMSK). For this reason, when the delay is 2T, the symbol rotation amount becomes π larger by GMSK than before the delay.

  The multipliers 13a and 13b and the adder 14 then (I component of the burst signal 30) × (I component after 2T delay of the burst signal 30) + (Q component of the burst signal 30) × (2T of the burst signal 30). Q component after delay) is calculated. That is, the inner product value of the burst signal 30 and the burst signal 30 after 2T delay is calculated. This inner product value is also expressed as | A || B | cos θ. However, | A | and | B | are the amplitudes of the burst signal 30 and the burst signal 30 after 2T delay, respectively, and are fixed values. θ is an angle between the burst signal 30 and the burst signal 30 after 2T delay.

  In the training sequence 33 of the burst signal 30, the phase is only 0 or π at the symbol point on the I axis in GMSK, so cos θ = ± 1 at this symbol point. Therefore, the absolute value calculation unit 15 calculates the absolute value signal of the inner product value. That is, in GMSK, the timing at which the absolute value of the inner product value becomes the maximum is the symbol point extraction timing.

  Then, the moving average value calculation unit 16 calculates a moving average value signal of the absolute value signal of the inner product value. By taking the moving average value, the absolute value signal of the inner product value becomes more accurate. In the moving average value calculation unit 16, the absolute value signal of the inner product value becomes more accurate as the number of stages (the combination of the T delay unit 161i and the adder 162i) increases.

  Then, the maximum value detector 17 detects the timing signal of the symbol point from the maximum value of the moving average signal of the absolute value of the inner product value of the burst signal 30. The symbol point extraction units 18 a and 18 b extract symbol points from the I component and Q component of the burst signal 30 based on the symbol point timing signal input from the maximum value detection unit 17.

  Then, the phase detection unit 19 detects the phase of the extracted symbol point. The phase difference between successive symbol points of the burst signal 30 is ± π / 2 in GMSK.

  The phase of the symbol point detected by the phase detector 19 is the reverse rotation of the symbol rotation amount (0, π / 2,..., GMSK) phase-shifted on the transmission side by the demodulator 20 based on the GMSK modulation method. In consideration of the above, it is demodulated by a demodulation method corresponding to the modulation method (GMSK).

  The demodulator 20 determines whether the IQ plane is divided into two regions based on the positive and negative of the I axis, and outputs a demodulated signal corresponding to the position of the input signal. Alternatively, the demodulating unit 20 may output a demodulated signal with respect to GMSK (BPSK) depending on where in the eight regions. In this case, for example, among the eight regions, a region where the I axis is positive can be set to 1, and a negative region can be set to 0. Note that the phase of the signal input to the demodulator 20 may be rotated. In this case, the demodulator 20 corrects the pattern by matching a known bit pattern embedded in a part of the received signal. .

  In the demodulator 100, since the communication method is fixed by GSM, symbol point timing extraction (in the maximum value detection unit 17) is performed on an arbitrary portion of the burst signal 30 (training sequence 33, data 32, 34, etc.). Timing signal output) is possible.

  Further, in the demodulator 100, since the modulation method is only GMSK, the GMSK modulation has constant envelope characteristics (moving on the circumference of the IQ plane) and the phase difference between consecutive symbols is ± Due to the large value of π / 2, the symbol timing can be reproduced even if the equalizing filter for removing intersymbol interference is omitted.

  Here, specific examples of various signal values relating to symbol point extraction of the received burst signal will be described with reference to FIG. FIG. 5A shows an inner product value signal in the demodulator 100. FIG. 5B also shows the absolute value signal. FIG. 5C shows the moving average value signal. The horizontal axis of FIGS. 5A to 5C is the time normalized by the symbol time T (T = 1), and the same applies to the following figures.

  Since the modulation method is GMSK, the inner product value signal of the burst signal and the burst signal after 2T delay output from the adder 14 is as shown in FIG. 5A, for example. The absolute value signal of the inner product value output from the absolute value calculation unit 15 is as shown in FIG. The moving average value signal of the absolute value of the inner product value output from the moving average value calculation unit 16 has a plurality of maximum values as shown in FIG. 5 (c), each representing the timing of symbol point extraction. Yes.

  As described above, according to the demodulator 100, the symbol timing of a burst signal whose communication method is GSM (modulation method is GMSK (BPSK)) can be easily reproduced. In addition, since the demodulation (decoding) process can be performed after the symbol point is determined, the circuit scale can be reduced.

(First modification)
A modification of the first embodiment will be described with reference to FIGS. Since the demodulator 100A of the present modification has the same components as the demodulator 100, the same reference numerals are given to the same parts of the demodulator 100A as those of the demodulator 100, and different parts from the demodulator 100 are mainly used. explain.

  First, the apparatus configuration of the present embodiment will be described with reference to FIG. FIG. 6 shows the internal configuration of the demodulation device 100A.

  As illustrated in FIG. 6, the demodulator 100 </ b> A is a device that demodulates a received burst signal having a communication scheme of GSM (modulation scheme is GMSK (BPSK)), similar to the demodulator 100.

  The demodulating device 100A includes equalizing filters 11a and 11b as first and second equalizing filters, an inner product value calculating unit 40, an absolute value calculating unit 15, a moving average value calculating unit 16, and a maximum value detecting unit 17. The symbol point extracting units 18a and 18b, the phase detecting unit 19, and the demodulating unit 20 are provided. The inner product value calculation unit 40 includes 2T delay units 12a and 12b, multipliers 13a and 13b, and an adder 14.

  The equalizing filters 11a and 11b respectively remove interference between I component and Q component symbols of the received signal of the input burst signal and output the result. The 2T delay units 12a and 12b give a 2T delay to the I and Q components of the received signals input from the equalizing filters 11a and 11b, respectively, and output the delayed signals. Based on the symbol point extraction timing signal input from the maximum value detection unit 17, the symbol point extraction units 18a and 18b respectively receive the symbol points of the I component and Q component of the reception signal input from the equalization filters 11a and 11b. To extract.

  Here, specific examples of various signal values relating to symbol point extraction of the received burst signal will be described with reference to FIG. FIG. 7A shows an inner product value signal in the demodulator 100A. FIG. 7B also shows the absolute value signal. FIG. 7C shows a moving average value signal.

  In the demodulator 100A, the modulation method is GMSK, and the inner product value signal of the burst signal and the burst signal after 2T delay output from the adder 14 is as shown in FIG. 7A, for example. The absolute value signal of the inner product value output from the absolute value calculation unit 15 is as shown in FIG. As shown in FIG. 7C, the moving average value signal of the absolute value of the inner product value output from the moving average value calculation unit 16 is arranged with a plurality of maximum values, each representing the timing of symbol point extraction. Yes.

  As described above, according to the demodulator 100A, intersymbol interference of a burst signal whose communication method is GSM (modulation method is GMSK (BPSK)) can be removed, and the symbol timing of the burst signal can be easily reproduced. In addition, since the demodulation (decoding) process can be performed after the symbol point is determined, the circuit scale can be reduced.

(Second Embodiment)
A second embodiment according to the present invention will be described with reference to FIGS. Since demodulator 200 according to the present embodiment has the same components as demodulator 100 and 100A, the same reference numerals are given to the same parts of demodulator 200 as demodulator 100 and 100A, and the demodulator mainly. Parts different from 100 and 100A will be described.

  First, the device configuration of the present embodiment will be described with reference to FIG. FIG. 8 shows the internal configuration of the demodulation device 200 of the present embodiment.

  The demodulating apparatus 200 according to the present embodiment is an apparatus that receives and demodulates a signal whose communication method is GSM or EDGE. The GSM modulation method is GMSK (BPSK), and the EDGE modulation method is 8PSK.

  As shown in FIG. 8, the demodulator 200 includes equalizing filters 11a and 11b, an inner product value calculation unit 50, an absolute value calculation unit 15, a moving average value calculation unit 16, a maximum value detection unit 17A, a symbol point The extraction units 18 a and 18 b, the phase detection unit 19, the modulation scheme determination unit 21, the symbol reverse rotation unit 22, and the demodulation unit 23 are configured. The inner product value calculation unit 50 includes 8T delay units 24a and 24b as first and second delay units, multipliers 13a and 13b, and an adder 14.

  As shown in FIG. 2, the moving average value calculation unit 16 includes T delay units 1611 to 161n (n: an integer of 1 or more) and adders 1621 to 162n.

  A GSM or EDGE burst signal including data modulated by the BPSK or 8PSK modulation scheme is transmitted by a transmission device (not shown), and the demodulation device 200 receives the transmitted burst signal. Specifically, the transmitted burst signal is received by an antenna (not shown) of the demodulator 200, and the received signal is converted to IF by a tuner (not shown). The IF-converted received signal is converted into a digital signal by an A / D converter (not shown), and the digital signal is divided into an I component and a Q component by an IQ signal divider (not shown).

  The inner product value calculation unit 50 calculates the inner product value of the received signal of the burst signal and the received signal of the burst signal after 8T delay. 8T is eight times the symbol time T.

  The 8T delay units 24a and 24b give an 8T delay to the I and Q components of the received signals input from the equalizing filters 11a and 11b, respectively, and output the delayed signals. The multipliers 13a and 13b respectively receive the I component and the Q component of the received signal input from the equalizing filters 11a and 11b, and the I component and the Q component of the received signal after 8T delay input from the 8T delay units 24a and 24b. And the multiplication value signal is output.

  The maximum value detection unit 17A acquires the timing of the maximum value of the portion corresponding to the training sequence in the burst signal in the moving average value signal input from the moving average value calculation unit 16, and outputs it as a timing signal for symbol point extraction To do.

  The phase detection unit 19 detects and outputs the phase of the symbol point input from the symbol point extraction units 18a and 18b. The modulation method determination unit 21 determines the modulation method (GMSK (BPSK) or 8PSK) based on the phase of the symbol point input from the phase detection unit 19, and outputs a modulation method signal indicating the modulation method.

  The symbol reverse rotation unit 22 reversely rotates the phase of the symbol point of the reception signal input from the phase detection unit 19 by an amount corresponding to the modulation scheme of the modulation scheme signal input from the modulation scheme determination unit 21. The demodulator 23 demodulates (decodes) the signal of the symbol point after the reverse rotation input from the symbol reverse rotation unit 22 based on the modulation system of the modulation system signal input from the modulation system determination unit 21 to generate a data signal To get.

  Next, an 8PSK burst signal will be described with reference to FIGS. 3B and 4C. The GMSK (BPSK) burst signal is as described above with reference to FIGS. 3A, 4A, and 4B. FIG. 3B shows an 8PSK constellation. FIG. 4C shows an 8PSK training sequence pattern.

As shown in FIG. 3 (b), when the modulation method is 8PSK, data on the I axis (d _3i , d _{3i + 1} , d _{3i + 2} ) = (1, 1, 1), (0, 1, 1), (0, 1, 0), (0, 0, 0), (0, 0, 1), (1, 0, 1), (1, 0, 0), (1 , 1, 0), (1, 1, 1) symbol points are assigned. Each symbol point indicates the phase of the start point of the signal (symbol).

  On the transmitter side, the symbol points are phase-shifted (phase shifted) by a predetermined amount for each symbol in accordance with the communication method. In the case of GSM, for each symbol, the phase of the symbol point is increased by 0 by π / 2 (0, π / 2, (π / 2) × 2, (π / 2) × 3,...) Phase is rotated. . In the case of EDGE, the phase of each symbol point is increased by 0 by 3π / 8 (0, 3π / 8, (3π / 8) × 2, (3π / 8) × 3,...) Phase is rotated. .

  The format of the burst signal received and input by the demodulator 200 has a predetermined format, and is the format of the burst signal 30 as shown in FIG. As shown in FIGS. 4B and 4C, the training sequence 33 is a predetermined pattern in which values on the I axis are continuous in GMSK and 8PSK.

  Next, the operation of the demodulation device 200 will be described. First, in the demodulating device 200, the burst signal 30 transmitted from the transmitting device is received and converted into IF and digital, and the burst signal 30 is divided into I component and Q component, which are respectively applied to the equalizing filters 11a and 11b. Entered. The I component and Q component of the burst signal 30 are subjected to intersymbol interference removal by the equalizing filters 11a and 11b.

  The I and Q components of the burst signal 30 output from the equalizing filters 11a and 11b are delayed by 8T by the 8T delay units 24a and 24b, respectively. As described above, the symbol rotation amount added on the transmission side is π / 2 in GSM (GMSK) and 3π / 8 in EDGE (8PSK). For this reason, when the delay is 8T, the symbol rotation amount is 4π larger at GMSK and 3π larger at 8PSK than before the delay.

  The multipliers 13a and 13b and the adder 14 then (I component of the burst signal 30) × (I component after 8T delay of the burst signal 30) + (Q component of the burst signal 30) × (8T of the burst signal 30). Q component after delay) is calculated. That is, the inner product value of the burst signal 30 and the burst signal 30 after 8T delay is calculated. This inner product value is also expressed as | A || B | cos θ. However, | A | and | B | are the amplitudes of the burst signal 30 and the burst signal 30 after 8T delay, respectively, and are fixed values. θ is an angle between the burst signal 30 and the burst signal 30 after 8T delay.

  In the training sequence 33 of the burst signal 30, both GMSK and 8PSK have a phase of only 0 or π at the symbol point on the I axis, so cos θ = ± 1 at this symbol point. Therefore, the absolute value calculation unit 15 calculates the absolute value signal of the inner product value. That is, for GMSK and 8PSK, the timing at which the absolute value of the inner product value is maximized is the symbol point extraction timing.

  Then, the moving average value calculation unit 16 calculates a moving average value signal of the absolute value signal of the inner product value. By taking the moving average value, the absolute value signal of the inner product value becomes more accurate. In the moving average value calculation unit 16, the absolute value signal of the inner product value becomes more accurate as the number of stages (the combination of the T delay unit 161i and the adder 162i) increases.

  Then, the maximum value detector 17A detects the timing signal of the symbol point from the maximum value of the moving average signal of the absolute value of the inner product value of the portion corresponding to the training sequence 33 of the burst signal 30. The symbol point extraction units 18a and 18b extract symbol points from the I and Q components of the burst signal 30 based on the symbol point timing signal input from the maximum value detection unit 17A.

  Then, the phase detection unit 19 detects the phase of the extracted symbol point. The phase difference between consecutive symbol points in the training sequence 33 is ± π / 2 for GMSK and ± πk / 4 + π / 8 (k: integer) for 8PSK. The modulation scheme determination unit 21 determines the modulation scheme to be GMSK or 8PSK based on the phase difference between successive symbol points detected by the phase detection unit 19.

  The phase of the symbol point detected by the phase detection unit 19 is determined by the symbol reverse rotation unit 22 based on the modulation scheme determined by the modulation scheme determination unit 21. π / 2,..., 8PSK, 0, 3π / 8,.

  The reversely rotated symbol points are demodulated by the demodulation unit 23 using a demodulation method corresponding to the modulation method (GMSK or 8PSK) determined by the modulation method determination unit 21. The demodulator 23 divides the IQ plane into two regions according to the positive and negative of the I axis, or divides it into eight regions by π / 4 around the origin, and determines where the input signal is located in that region. The demodulated signal corresponding to the position of the input signal is output. Alternatively, a demodulated signal may be output depending on where in the eight regions, both GMSK (BPSK) and 8PSK. In this case, in the case of BPSK, for example, among the eight regions, a region where the I axis is positive can be set to 1, and a negative region can be set to 0. Therefore, the same circuit can be used regardless of the demodulation method corresponding to either BPSK or 8PSK. Note that there is a possibility that the phase of the signal input to the demodulator 23 is rotated. In this case, the demodulator 23 corrects the pattern by matching a known bit pattern embedded in a part of the received signal. .

  The demodulator 200 acquires the symbol point extraction timing from the training sequence 33 in the burst signal 30 and also extracts the symbol points of the tail bits 31 and 35 and the data 32 and 34 in synchronization with the acquired timing. More specifically, the demodulator 200 includes a memory (not shown) in front of the symbol point extraction units 18a and 18b, and performs symbol point extraction of the training sequence 33 of the burst signal 30 (timing signal output of the maximum value detection unit 17A). The received burst signal 30 is sequentially stored in the memory until the end. When the timing signal is output from the maximum value detection unit 17A, the symbol point extraction units 18a and 18b extract the symbol point of the burst signal stored in the memory in synchronization with the timing signal. The remaining burst signal received after the timing signal is output may be extracted without storing it in the memory.

  When burst signals are received continuously, the symbol points of the received burst signal are extracted, and the symbol points of the next and subsequent burst signals are also extracted in synchronization with the extracted timing signal. It is good.

  Here, specific examples of various signal values relating to symbol point extraction of the received burst signal will be described with reference to FIGS. FIG. 9A shows an inner product signal when the modulation method in the demodulator 200 is GMSK. FIG. 9B shows an absolute value signal when the modulation method is GMSK. FIG. 9C shows a moving average signal when the modulation method is GMSK. FIG. 10A shows an inner product signal when the modulation method in the demodulator 200 is 8PSK. FIG. 10B shows an absolute value signal when the modulation method is also 8PSK. FIG. 10C shows a moving average value signal when the modulation method is 8PSK.

  Consider the case where the modulation scheme is GMSK. In the case of GMSK, the inner product signal of the burst signal and the burst signal after 8T delay output from the adder 14 is as shown in FIG. 9A, for example. The absolute value signal of the inner product value output from the absolute value calculation unit 15 is as shown in FIG. As shown in FIG. 9C, the moving average value signal of the absolute value of the inner product value output from the moving average value calculation unit 16 is arranged with a plurality of maximum values, each representing the timing of symbol point extraction. Yes.

  Next, consider a case where the modulation method is 8PSK. In the case of 8PSK, the inner product signal of the burst signal and the burst signal delayed by 8T output from the adder 14 is as shown in FIG. 10A, for example. The absolute value signal of the inner product value output from the absolute value calculation unit 15 is as shown in FIG. Then, the moving average value signal of the absolute value of the inner product value output from the moving average value calculation unit 16 has a plurality of maximum values as shown in FIG. 10 (c), each representing the timing of symbol point extraction. Yes.

  As described above, according to the present embodiment, the symbol timing is the same regardless of which burst signal whose communication method is GSM (modulation method is GMSK (BPSK)) or EDGE (modulation method is 8PSK) is input by demodulator 200. It is possible to easily reproduce with the configuration. In addition, since the demodulation (decoding) process can be performed after the symbol point is determined, the circuit scale can be reduced.

  Further, since the moving average value calculation unit 16 calculates the moving average value of the absolute value of the inner product value, the timing reproduction of symbol point extraction can be performed more accurately.

  Further, the moving average value calculation unit 16 can be easily configured by the T delay units 1611 to 161n and the adders 1621 to 162n.

(Second modification)
With reference to FIG. 11, a second modification as a modification of the second embodiment will be described. Since the demodulator 200A of the present modification has the same components as the demodulator 200 described above, the same reference numerals are given to the same parts as those of the demodulator 200 among the parts of the demodulator 200A, and the parts that are mainly different from the demodulator 200 are mainly provided. explain.

  A demodulator 200A of this modification will be described. FIG. 11 shows the internal configuration of the demodulator 200A of this modification.

  As shown in FIG. 11, the demodulator 200A includes equalizing filters 11a and 11b, an inner product value calculating unit 50, an absolute value calculating unit 15, a moving average value calculating unit 16, a maximum value detecting unit 17A, a symbol point The extraction units 18 a and 18 b, the phase detection unit 19, the modulation scheme determination unit 21, and the demodulation unit 25 are configured.

  The demodulator 200 </ b> A does not include the symbol reverse rotation unit 22 but includes a demodulation unit 25 instead of the demodulation unit 23. The demodulator 25 demodulates (decodes) the symbol points input from the phase detector 19 in consideration of the amount of phase rotation based on the modulation scheme of the modulation scheme signal input from the modulation scheme determiner 21. Get the signal.

  In the demodulator 200A, if the phase detection resolution in the phase detector 19 is sufficient, even if the symbol reverse rotation is omitted, the demodulator 25 demodulates in consideration of the phase rotation at the time of demodulation. Demodulation can be performed as in the case of 200.

  As described above, according to the present modification, the demodulating device 200A can achieve the effects of the above-described embodiment, and can be demodulated by the demodulating unit 25 in consideration of the phase rotation of the symbol point, thereby simplifying the device configuration.

  Note that the descriptions in the above embodiments and modifications are examples of the demodulation device according to the present invention, and the present invention is not limited to this.

  For example, in each of the above embodiments and modifications, a demodulator capable of demodulating a received signal for only GSM and EDGE or GSM has been described, but the present invention is not limited to this. That is, the present invention can also be applied to other communication systems (modulation systems) that require symbol point extraction timing reproduction. In this case, the delay time for delaying the I component and Q component signals of the burst signal to obtain the inner product value is a symbol time T which is an integer multiple of π when multiplied by the symbol rotation amount of a plurality or a single communication method. The delay time multiplied by.

  Moreover, in each said embodiment and each modification, although it was set as the structure provided with the moving average value calculating part 16, it is not limited to this. The moving average value calculation unit may be configured to perform an average calculation using absolute values separated by symbol time while continuously moving the calculation range. For example, the T delay units 1611 to 161n are added to the adder 1621. It is good also as a structure provided in -162n side, and it is good also as a structure implement | achieved by a CIC (Cascaded Integrate Comb) filter.

  In addition, in the demodulating devices 100 and 100A, the symbol timing of the signal having the modulation scheme GMSK is reproduced. However, the present invention is not limited to this, and the symbol timing of the signal of another modulation scheme is reproduced. Also good. For example, in the demodulating devices 100 and 100A, the 2T delay units 12a and 12b may be changed to 8T delay units to reproduce the symbol timing of a signal whose modulation scheme is 8PSK.

  In addition, the detailed configuration and detailed operation of the demodulator in each of the above embodiments and modifications can be changed as appropriate without departing from the spirit of the present invention.

It is a block diagram which shows the internal structure of the demodulation apparatus 100 of 1st Embodiment which concerns on this invention. 3 is a block diagram showing an internal configuration of a moving average value calculation unit 16. FIG. (A) is a figure which shows the constellation of a BPSK system. (B) is a diagram showing an 8PSK constellation. (A) is a figure which shows the structure of the format format of the burst signal 30. FIG. (B) is a figure which shows the pattern of the training sequence of a BPSK system. (C) is a figure which shows the pattern of the training sequence of 8PSK system. (A) is a figure which shows the inner product value signal in the demodulator 100. FIG. (B) is a figure which similarly shows an absolute value signal. (C) is a figure which similarly shows a moving average value signal. It is a block diagram which shows the internal structure of 100 A of demodulation apparatuses of a 1st modification. (A) is a figure which shows the inner product value signal in 100 A of demodulation apparatuses. (B) is a figure which similarly shows an absolute value signal. (C) is a figure which similarly shows a moving average value signal. It is a block diagram which shows the internal structure of the demodulation apparatus 200 of 2nd Embodiment which concerns on this invention. (A) is a figure which shows the inner product value signal in case the modulation system in the demodulator 200 is GMSK. (B) is a figure which shows an absolute value signal in case a modulation system is GMSK similarly. (C) is a figure which shows a moving average value signal in case the modulation system is GMSK similarly. (A) is a figure which shows the inner product value signal in case the modulation system in the demodulator 200 is 8PSK. (B) is a figure which shows an absolute value signal in case a modulation system is also 8PSK. (C) is a figure which shows a moving average value signal in case a modulation system is also 8PSK. It is a block diagram which shows the internal structure of 200 A of demodulation apparatuses of a 2nd modification.

Explanation of symbols

100, 100A, 200, 200A Demodulator 11a, 11b Equalize filter 40, 50 Inner product value calculator 12a, 12b 2T delay unit 13a, 13b Multiplier 14 Adder 15 Absolute value calculator 16 Moving average value calculator 1611-161n T Delay unit 1621 to 162n Adder 17, 17A Maximum value detection unit 18a, 18b Symbol point extraction unit 19 Phase detection unit 20, 23, 25 Demodulation unit 21 Modulation method determination unit 22 Symbol reverse rotation unit 24a, 24b 8T delay unit

Claims (9)

A burst signal divided into an I component and a Q component by a predetermined modulation method is delayed by a delay time obtained by multiplying the symbol time by a value that is an integral multiple of π when multiplied by the symbol rotation amount of the predetermined modulation method. An inner product value calculation unit that calculates an inner product value of the divided burst signal and the delayed burst signal and outputs the inner product value signal;
An absolute value calculation unit that calculates an absolute value of the inner product value signal and outputs the absolute value signal;
A maximum value detecting unit for detecting a maximum value of the absolute value signal and outputting it as a symbol timing signal;
A first symbol point extraction unit that extracts a symbol point of the I component signal based on the symbol timing signal;
A second symbol point extracting unit for extracting a symbol point of the Q component signal based on the symbol timing signal;
A phase detector for detecting the phase of the extracted symbol points;
A demodulator that demodulates the signal at the symbol point from which the phase has been detected by reverse rotation based on the predetermined modulation method; A first equalizing filter for removing intersymbol interference of the I component of the burst signal divided and input into the I component and the Q component of the predetermined communication method;
A second equalizing filter for removing intersymbol interference of the Q component of the divided burst signal,
The inner product value calculation unit is configured to delay the I- and Q-component signals from which the inter-symbol interference has been removed by the delay time, and to remove the inter-symbol interference from the burst signal and the delayed burst. The inner product value with the signal is calculated and output as an inner product value signal,
The first symbol point extraction unit extracts a symbol point of an I component signal from which the inter-symbol interference is removed based on the symbol timing signal,
2. The demodulator according to claim 1, wherein the second symbol point extraction unit extracts a symbol point of a Q component signal from which the inter-symbol interference is removed based on the symbol timing signal. The inner product value calculation unit includes:
A first delay unit that delays the I component signal by the delay time;
A second delay unit that delays the Q component signal by the delay time;
A first multiplier that multiplies the I-component signal from which the inter-symbol interference has been removed and the time-delayed I-component signal and outputs the result as a first multiplied signal;
A second multiplier that multiplies the Q-component signal from which the intersymbol interference has been removed and the time-delayed Q-component signal and outputs the result as a second multiplied value signal;
The demodulation apparatus according to claim 1, further comprising: a first adder that adds the first and second multiplication value signals and outputs the result as the inner product value signal. A first equalizing filter that removes intersymbol interference of the I component of the burst signal that is divided and input into a plurality of I and Q components of different modulation schemes;
A second equalizing filter for removing intersymbol interference of the Q component of the divided burst signal;
The I- and Q-component training sequence signals from which the inter-symbol interference has been removed are delayed by a delay time obtained by multiplying the symbol time by a value that is an integral multiple of π when multiplied by the symbol rotation amount of the different modulation method. An inner product value computing unit that computes an inner product value of the burst signal from which the inter-symbol interference has been removed and the delayed burst signal and outputs the inner product value signal;
An absolute value calculation unit that calculates an absolute value of the inner product value signal and outputs the absolute value signal;
A maximum value detecting unit for detecting a maximum value of the absolute value signal and outputting it as a symbol timing signal;
A first symbol point extraction unit that extracts a symbol point of an I-component signal from which the inter-symbol interference is removed based on the symbol timing signal;
A second symbol point extraction unit that extracts a symbol point of a Q-component signal from which the inter-symbol interference is removed based on the symbol timing signal;
A phase detector for detecting the phase of the extracted symbol points;
A modulation scheme determination unit that determines a modulation scheme based on the phase of the detected symbol point;
And a demodulator that demodulates the signal of the symbol point from which the phase has been detected based on the determined modulation method. The inner product value calculation unit includes:
A first delay unit that delays the I-component signal from which the intersymbol interference is removed by the delay time;
A second delay unit that delays the signal of the Q component from which the intersymbol interference is removed by the delay time;
A first multiplier that multiplies the I-component signal from which the inter-symbol interference has been removed and the time-delayed I-component signal and outputs the result as a first multiplied value signal;
A second multiplier that multiplies the Q-component signal from which the intersymbol interference has been removed and the time-delayed Q-component signal and outputs the result as a second multiplied value signal;
The demodulator according to claim 4, further comprising: a first adder that adds the first and second multiplication value signals and outputs the result as the inner product value signal. A symbol reverse rotation unit configured to reversely rotate the symbol point from which the phase is detected based on the determined modulation method;
6. The demodulator according to claim 4, wherein the demodulator demodulates the signal at the reversely rotated symbol point based on the determined modulation scheme.   5. The demodulator demodulates a signal based on the determined modulation scheme, taking into account the phase rotation added on the transmission side, on the symbol point where the phase is detected. Or 5. The demodulator according to 5. A moving average value calculating unit that calculates a moving average value using the absolute value signal separated by a symbol time and outputs it as a moving average value signal while continuously moving the calculation range,
The demodulator according to any one of claims 1 to 7, wherein the maximum value detection unit detects a maximum value of the moving average value signal and outputs the maximum value as a symbol timing signal. The moving average value calculator is
At least one stage of a set of a third delay unit that delays the absolute value signal by a symbol time and a second adder that adds the absolute value signal and the absolute value signal delayed by the symbol time is provided. The demodulator according to claim 8.

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