JP4801054B2 - Circuit update system - Google Patents

Abstract

An information processing apparatus includes a reconfigurable unit in which a circuit is reconfigured. A generation unit generates design data for the circuit configured by the reconfigurable unit and reduces the amount of design data to be held by a design data storage unit.

Description

  The present invention relates to a technique for updating a circuit mounted in a device.

When distributing content over a network or distributing content recorded on a recording medium, the content is generally encrypted and distributed to prevent unauthorized use of the content and to protect the copyright of the content. Or distributed.
The device that plays the content performs decryption processing to decrypt the encrypted content, but the encryption method in the device is implemented in hardware from the viewpoint of the required processing speed and tamper resistance. There are many.
Here, there is a demand to update the encryption method implemented in hardware to a new encryption method, but in recent years, reconfigurations such as FPGA (Field Programmable Gate Array) and PLA (Programmable Logic Array) It has become possible to reconfigure the circuit and update the encryption method by using a device capable of the above (see Patent Document 1).
In Patent Document 2, a database that stores an algorithm file for updating a circuit is held inside the device, the algorithm file is acquired from the database according to an instruction from the outside, and the mounted circuit is Techniques for updating are disclosed.
Japanese Patent Laid-Open No. 10-320191 JP-A-10-55135

However, the above-described conventional technique for maintaining a database in a device is useful for updating a circuit, but in order to effectively use the storage capacity of the device. There is a desire to reduce the amount of data in the database.
Therefore, the present invention has been made in order to meet the above-mentioned demand, and circuit update capable of updating the circuit mounted on the device while reducing the data amount of the database as compared with the prior art. The purpose is to provide a system.

  In order to achieve the above object, the present invention is an information processing apparatus comprising a plurality of logical blocks, and reconfiguring a circuit by changing the logic of each logical block and changing the connection between the logical blocks. First design data indicating reconfigurable means capable of configuring and logic of a logic block indicating a first circuit currently configured in the reconfigurable means and connection between the logic blocks are received from the reconfigurable means. Extracting means for extracting, and output means for outputting the second design data indicating the logic of the logic block indicating the second circuit and the connection between the logic blocks to the reconfigurable means, the reconfigurable means comprising: The second circuit is reconfigured based on the second design data.

The above-mentioned “reconfigurable means” corresponds to the reconfigurable unit of each embodiment described below. The “extraction means” has the function of the extraction unit of each embodiment. The “output unit” is responsible for the function of the update unit of each embodiment.
According to the above configuration, the first design data can be extracted by the extraction unit. Therefore, the information processing apparatus can be configured as long as the reconfigurable unit implements the first circuit based on the first design data. It is not necessary to hold the first design data in the inside. Therefore, the storage capacity in the device can be saved and the storage capacity can be used effectively.

  Here, when the second design data is output to the reconfigurable means by the output means, the design data storage means stores the design data storage means that stores the second design data. The means may comprise a deleting means for deleting the second design data, and a writing means for writing the first design data extracted by the extracting means into the design data storage means.

The above-mentioned “design data storage means” has the function of the design data storage unit of each of the following embodiments. The “deleting unit” and “writing unit” have the functions of the design data storage unit of each embodiment.
According to this configuration, when the second design data is output to the reconfigurable means by the output means, the second design data is deleted from the design data storage means, so that the design data stored in the design data storage means The amount of data can be reduced. In addition, the first design data is written to the design data storage means by the writing means. By providing the extraction means, the design data corresponding to the circuit mounted by the reconfigurable means is the design data storage means. However, the amount of data in the design data storage means is reduced as compared with the prior art in which all design data must be held in the design data storage means.

Here, the information processing apparatus includes an encryption unit that encrypts the first design data extracted by the extraction unit, and the writing unit stores the encrypted first design data in the design You may comprise so that it may write in a data storage means.
The above-mentioned “encryption means” has the function of the encryption units of the following embodiments.
Further, the second design data stored in the design data storage means is encrypted, and the information processing apparatus includes decryption means for decrypting the encrypted second design data, and the output The means may be configured to output the second design data decoded by the decoding means to the reconfigurable means.

The above-described “decoding unit” has the function of the decoding unit according to the following embodiment.
According to this configuration, the first design data and the second design data stored in the design data storage unit are encrypted, the design data storage unit is accessed from the outside, and the first design data and the second design data are stored. Even if it is leaked, it can be prevented from being used illegally. In addition, since the decoding means is provided, the decoded first design data and second design data can be used for circuit reconfiguration in the reconfigurable means.

  Here, the information processing apparatus includes key information storage means for securely storing key information corresponding to each design data, and the encryption means receives the first design data from the key information storage means. Corresponding first key information is read, the first design data is encrypted based on the read first key information, and the decryption means receives a second corresponding to the second design data from the key information storage means. Key information may be read, and the second design data may be decrypted based on the read second key information.

In the following embodiments, the above-mentioned “key information storage unit” has the function of the key storage unit.
According to this configuration, the key information used in the encryption unit and the decryption unit is unique for each design data, and the safety is improved as compared with the case where the key information is encrypted with the same key information. Furthermore, each key information is securely stored in the key information storage means, and even when the design data storage means is accessed from the outside and the first and second design data are leaked, acquisition of the key information is not possible. It is difficult to prevent unauthorized use of the first and second design data.

Here, the information processing apparatus further includes key information generation means for generating the key information corresponding to each design data, and the key information generated by the key information generation means is stored in the key information storage means. You may comprise so that it may write.
According to this configuration, since the key information is generated inside the information processing apparatus, it is possible to prevent the key information from leaking outside.

  Here, the information processing apparatus further includes an internal state holding unit that holds an internal state indicating a position of a logical block used in the configuration of the first circuit in the reconfigurable unit, and the internal state holding unit Design data of a circuit that achieves a second function different from the first function achieved by the first circuit, and the first design data extracted by the extraction means. Optimization means for generating the second design data so that the reconfigurable means can be optimized from the third design data, and the output means is the optimization means generated by the optimization means. The second design data may be output to the reconfigurable means.

Further, the internal state holding means includes the position of the logic block used in the circuit configuration that achieves the first function and the logic block used in the circuit configuration that achieves the second function. New internal information indicating the position may be generated and held.
According to this configuration, the reconfigurable means of the information processing apparatus achieves the first and second functions instead of replacing the first circuit that achieves the first function with the second circuit that has a different function. A new second circuit can be reconfigured. Further, since the internal state holding means holds the state information, the circuit can be reconfigured so that the logical block of the reconfigurable means is optimized.

Even in this case, the design data (that is, the first design data and the second design data) whose circuit configuration is realized by the reconfigurable means need not be stored in the design data storage means. Thus, the data amount of the design data storage means can be reduced.
In addition, when the circuit that achieves the first function and the second function is configured by reconfigurable means, the internal state holding means holds information indicating the position of the logical block corresponding to each function. Thus, the extraction unit can also individually extract design data corresponding to the first function and design data corresponding to the second function.

Here, the information processing apparatus further includes an internal state holding unit that holds an internal state indicating a position of a logical block used in the configuration of the first circuit in the reconfigurable unit, and the extraction unit includes The first design data may be selectively extracted from the reconfigurable means based on the internal state held by the internal state holding means.
According to this configuration, the extracting unit can efficiently perform the extraction process by referring to the internal state when extracting the first design data from the reconfigurable unit.

  Here, the information processing apparatus is connected to an external device via a network, and further, the internal state held in the internal state holding unit and the first design data extracted by the extracting unit And transmission means for transmitting third design data, which is design data of a circuit that achieves a function different from that of the first circuit, to the external device, and the reconfigurable means can be optimized from the external device. It may be configured to include receiving means for receiving the second design data.

  According to this configuration, the reconfigurable means of the information processing apparatus achieves the first and second functions instead of replacing the first circuit that achieves the first function with the second circuit that has a different function. A new second circuit can be reconfigured. Further, since the internal state holding means holds the state information, the circuit can be reconfigured so that the logical block of the reconfigurable means is optimized.

Further, by requesting an external device to generate new design data, the processing amount of the information processing apparatus can be reduced.
Here, the first circuit configured in the reconfigurable means based on the first design data achieves a first function, and the information processing apparatus is configured to extract the first information extracted by the extracting means. From the design data and third design data that is design data for configuring a third circuit that achieves a second function different from the first function, the first function that achieves the first and second functions. You may comprise so that the design data conversion means which produces | generates the said 2nd design data for comprising 2 circuits may be provided.

  According to this configuration, the reconfigurable means of the information processing apparatus achieves the first and second functions instead of replacing the first circuit that achieves the first function with the second circuit that has a different function. A new second circuit can be reconfigured. Even in this case, the design data (that is, the first design data and the second design data) whose circuit configuration is realized by the reconfigurable means need not be stored in the design data storage means. Thus, the data amount of the design data storage means can be reduced.

  Here, the information processing apparatus further includes medium input / output means for inputting / outputting information to / from an externally connected recording medium, and the output means is a recording medium on which the second design data is recorded. From the medium input / output means, the second data is acquired and output to the reconfigurable means, and the writing means sends the second data to the recording medium via the medium input / output means. One design data may be written.

  According to this configuration, when the second design data is output to the reconfigurable means by the output means, the second design data is deleted from the recording medium, thereby reducing the data amount of the design data recorded on the recording medium. Can do. In addition, the first design data is written to the recording medium by the writing means. Since the information processing apparatus includes the extracting means, the design data corresponding to the circuit mounted by the reconfigurable means can be recorded. There is no need to record on the medium.

Here, the information processing apparatus includes an encryption unit that encrypts the first design data extracted by the extraction unit, and the writing unit stores the encrypted first design data in the recording You may comprise so that it may write in a medium.
In addition, the second design data stored in the recording medium is encrypted, and the information processing apparatus includes a decryption unit that decrypts the encrypted second design data, and the output unit includes The second design data decoded by the decoding unit may be acquired and output to the reconfigurable unit.

  According to this configuration, the first design data and the second design data recorded on the recording medium are encrypted, the recording medium is accessed by an unauthorized user, and the first design data and the second design data are leaked. Even in this case, illegal use can be prevented. In addition, since the decoding means is provided, the decoded first design data and second design data can be used for circuit reconfiguration in the reconfigurable means.

1. First Embodiment An information processing apparatus 10 will be described as a first embodiment of the present invention.
The information processing apparatus 10 includes a device that can reconfigure a circuit based on design data, and updates the circuit as required.
<Configuration>
FIG. 1 is a functional block diagram functionally showing the configuration of the information processing apparatus 10.

As shown in the figure, the information processing apparatus 10 includes a reconfigurable unit 101, a design data storage unit 102, an extraction unit 103, a key storage unit 104, an encryption unit 105, a decryption unit 106, and an update unit 107. The
Specifically, the information processing apparatus 10 is a computer system including a microprocessor, a ROM, a RAM, a hard disk unit, and the like, and when the microprocessor executes a computer program stored in the RAM or the hard disk unit, Achieve that function.

Below, each component of the information processing apparatus 10 is demonstrated.
(1) Reconfigurable unit 101
FIG. 2 is a diagram illustrating an outline of the reconfigurable unit 101.
The reconfigurable unit 101 includes a logical block LB1 (121), a logical block LB2 (122), a logical block LB3 (123), a logical block LB4 (124), a logical block LB5 (125), a logical block LB6 (126), a logical block The block LB7 (127), the logical block LB8 (128), the logical block LB9 (129), 16 switch matrices 131 to 146, and a wiring group that connects each logical block and each switch matrix.

FIG. 3 is a diagram showing the inside of the logical block LB1 (121). The logical blocks LB2 (122) to LB9 (129) have the same configuration.
The logical block LB1 (121) includes a lookup table (hereinafter referred to as “LUT”) 151, an LUT 152, an LUT 153, a flip-flop 154, and a flip-flop 155. The LUT 151 and the LUT 153 have a configuration of 4 inputs and 1 output, and the LUT 152 has a configuration of 3 inputs and 1 output. However, this is an example, and the configuration is not necessarily limited to this configuration. Each logical block is specifically composed of a small SRAM.

FIG. 4A is a diagram illustrating the configuration of the switch matrix 131. The switch matrices 132 to 146 have the same configuration.
The switch matrix 131 includes transistor switch groups 161, 162, 163, and 164 that are arranged at the intersections of the vertical wiring channel and the horizontal wiring channel that constitute the wiring group.

FIG. 4B is a diagram illustrating the configuration of the transistor switch group 161. The transistor switch groups 162 to 164 have the same configuration.
The transistor switch group 161 includes six transistor switches 171 to 176, and each transistor switch is set to ON or OFF using an SRAM. Here, in this specification, a bit string including LUT setting values of each logical block and information indicating ON / OFF of each transistor switch is referred to as design data.

  When the design data is input by the updating unit 107, the reconfigurable unit 101 changes various setting values of each LUT and ON / OFF setting of the transistor switch based on the input design data. Configure or reconfigure the circuit. Note that the circuit configuration and reconfiguration in the reconfigurable unit 101 can be realized by a known technique, and thus detailed description thereof is omitted.

(2) Design data storage unit 102
The design data storage unit 102 has a function of storing and managing a design data table.
FIG. 5 is a diagram illustrating a data configuration of a design data table 200 that is an example of a design data table. As shown in the figure, the design data table 200 includes a plurality of design data information 201, 202,..., 203, 204, 205,..., And each design data information includes a design data ID and encrypted design data. Composed.

The design data ID is an identifier for uniquely identifying design data and encrypted design data generated by encrypting the design data.
The encrypted design data is the encrypted data generated by applying the encryption algorithm E to the design data identified by the associated design data ID using the key data unique to the design data as the encryption key. is there. An example of the encryption algorithm E is DES (Data Encryption Standard). In this specification, for example, design data with a design data ID “A” is described as “ARC_A”, design data with a design data ID “B” is described as “ARC_B”, and the like. Also, the encrypted design data generated by encrypting the design data ARC_A is described as “Enc_ARC_A”, the encrypted design data generated by encrypting the design data “ARC_B” is described as “Enc_ARC_B”, and the like.

  The design data information 201 includes a design data ID “A” and encrypted design data “Enc_ARC_A”. The encrypted design data “Enc_ARC_A” is encrypted data generated by encrypting the design data “ARC_A”. The design data “ARC_A” is data necessary for reconfiguring the circuit in the reconfigurable unit 101. Specifically, as described above, the setting of each LUT in the reconfigurable unit 101 is performed. It is a bit string indicating a value and ON / OFF of each transistor switch.

  The design data storage unit 102 reads the encrypted data when the decryption unit 106 that has received an instruction from the update unit 107 reads certain encrypted design data for circuit reconfiguration by the reconfigurable unit 101. The design data information including the design data is deleted from the design data table. When the design data storage unit 102 receives the encrypted design data and the design data ID from the encryption unit 105 that has received the design data extracted by the extraction unit 103, the design data storage unit 102 receives the encrypted design data and the design data ID. Is generated, and the design data information is stored in the design data table.

Below, it demonstrates concretely using FIG.5 and FIG.6.
When the design data storage unit 102 stores the design data table 200 shown in FIG. 5 and the encrypted design data “Enc_ARC_A” is read, the design data information 201 is deleted from the design data table 200, The design data table 210 is as shown in FIG. When the encrypted design data “Enc_ARC_V” is received from the encryption unit 105, the design data information 206 including the design data ID “V” and the encrypted design data “Enc_ARC_V” is generated and stored in the design data table 210. .

(3) Extraction unit 103
The extraction unit 103 has a function of extracting design data from the circuit configured by the reconfigurable unit 101 when receiving a circuit update request via an input unit such as an input device (not shown).
Specifically, the extraction unit 103 extracts an LUT from each logical block of the reconfigurable unit 101, and further extracts information indicating ON / OFF of each transistor switch from each switch matrix. The extraction unit 103 outputs the design data extracted from the reconfigurable unit 101 to the encryption unit 105 together with the design data ID of the design data. It is assumed that the extraction unit 103 already knows the design data ID of the design data extracted from the reconfigurable unit 101.

Details of the design data extraction method will be described later using the flowchart shown in FIG.
(4) Key storage unit 104
The key storage unit 104 stores a key table 300 shown in FIG. As shown in the figure, the key table 300 includes a plurality of pieces of key information 301, 302,..., 303,..., And each key information is configured by associating a design data ID with key data.

  As a specific example, the key information 303 includes a design data ID “V” and key data “K_V”. This indicates that the key data used for encryption of the design data “ARC_V” identified by the design data ID “V” and decryption of the encrypted design data “Ecn_ARC_V” is “K_V”. The key data “K_V” is, for example, 64-bit data used as a DES encryption / decryption key.

Note that the key storage unit 104 in this specification is tamper resistant. The tamper resistant mounting method is not particularly limited.
(5) Encryption unit 105
The encryption unit 105 has an encryption function for converting plaintext into ciphertext.
More specifically, when receiving the design data and the design data ID from the extraction unit 103, the encryption unit 105 reads out key data corresponding to the received design data ID from the key storage unit 104. The encryption unit 105 uses the read key data as an encryption key, encrypts the design data by applying an encryption algorithm E, and generates encrypted design data. The encryption unit 105 outputs the generated encrypted design data to the design data storage unit 102 together with the design data ID.

  As an example, consider a case where the encryption unit 105 receives the design data “ARC_V” and the design data ID “V” from the extraction unit 103. The encryption unit 105 specifies key information 303 including the received design data ID “V” from the key table 300 stored in the key storage unit 104. Next, the encryption unit 105 reads key data “K_V” from the key information 303. The encryption unit 105 uses the key data “K_V” as an encryption key, encrypts “ARC_V”, and generates “Enc_ARC_V”.

(6) Decoding unit 106
The decryption unit 106 has a decryption function for converting ciphertext into plaintext.
More specifically, when receiving a decryption request including a design data ID from the update unit 107, the decryption unit 106 reads out key data corresponding to the received design data ID from the key storage unit 104. Further, the decryption unit 106 reads out the encrypted design data corresponding to the received design data ID from the design data storage unit 102. The decryption unit 106 uses the read key data as a decryption key, decrypts the encrypted design data by applying a decryption algorithm D, and generates design data. The decoding unit 106 outputs the generated design data to the update unit 107. The decryption algorithm D is an algorithm for converting the ciphertext encrypted by the encryption algorithm E into plaintext.

  As an example, consider a case where the decoding unit 106 receives the design data ID “A” from the update unit 107. The decryption unit 106 identifies key information 301 including the received design data ID “A” from the key table 300 stored in the key storage unit 104. Next, the decryption unit 106 reads key data “K_A” from the key information 301. Using the key data “K_A” as a decryption key, the decryption unit 106 decrypts “Enc_ARC_A” to generate “ARC_A”.

(7) Update unit 107
The update unit 107 has a function of outputting new circuit design data to the reconfigurable unit 101 when a circuit update request is received via an input unit such as an input device (not shown).
Specifically, when receiving the update request including the design data ID, the update unit 107 instructs the decryption unit 106 to decrypt the encrypted design data identified by the received design data ID. The update unit 107 receives the design data decoded by the decoding unit 106, and outputs the received design data to the reconfigurable unit 101.

As an example, when receiving the design data ID identified by the design data “A”, the updating unit 107 outputs the design data ID “A” to the decoding unit 106. Further, the updating unit 107 receives the design data “ARC_A” from the decoding unit 106 and outputs the received design data “ARC_A” to the reconfigurable unit 101.
<Operation>
Here, the operation of the information processing apparatus 10 will be described using the flowcharts shown in FIGS. 8 and 9.
(1) Operation of the information processing apparatus 10 First, a circuit update request is generated (step S101), and the extraction unit 103 and the update unit 107 accept the circuit update request. Specifically, the extraction unit 103 and the update unit 107 accept a circuit update request via an input unit such as an input device. Here, it is assumed that the update unit 107 receives the design data ID together with the circuit update request via the input unit.

Receiving the circuit update request including the design data ID, the update unit 107 notifies the decryption unit 106 of the design data ID and instructs the decryption of the encrypted design data identified by the design data ID.
Upon receiving the instruction from the updating unit 107, the decrypting unit 106 reads out the encrypted design data identified by the design data ID from the design data storage unit 102 (step S102). Next, the decryption unit 106 reads key data associated with the design data ID from the key storage unit 104 (step S103).

The design data storage unit 102 deletes the design data information including the encrypted design data read in step S102 from the design data table (step S104).
Next, the decryption unit 106 decrypts the design data by applying the decryption algorithm D to the encrypted design data read in step S102, using the key data read in step S103 as a decryption key (step S105). The decoding unit 106 outputs the decoded design data to the update unit 107.

When receiving the design data from the decoding unit 106, the update unit 107 transfers the received design data to the reconfigurable unit 101 (step S106). Here, the reconfigurable unit 101 may be configured to have a memory for temporarily storing design data transferred from the update unit 107.
Next, the extraction unit 103 performs a process of extracting design data of a circuit currently configured in the reconfigurable unit 101 (step S107). Details of the design data extraction process will be described later.

The extraction unit 103 outputs the extracted design data to the encryption unit 105. The encryption unit 105 receives design data from the extraction unit 103 (step S108), and further receives key data associated with the design data ID for identifying the design data received in step S108 from the key storage unit 104. Read (step S109).
The encryption unit 105 generates encrypted design data by applying the encryption algorithm E to the design data received in step S108, using the key data read in step S109 as an encryption key (step S110). The encryption unit 105 outputs the generated encrypted design data and design data ID to the design data storage unit 102. The design data storage unit 102 generates design data information in which the received encrypted design data and the design data ID are associated with each other, and writes the generated design data information in the design data table (step S111).

Next, the reconfigurable unit 101 reconfigures the circuit by setting the value of each SRAM based on the design data received in step S106 (step S112).
Note that the above steps are not necessarily processed in this order. For example, the transfer processing in step S106 may be performed after the design data extraction processing (step S107).

(2) Operation of Design Data Extraction Processing by Extraction Unit 103 FIG. 9 is a flowchart showing the operation of design data extraction processing by the extraction unit 103. The operation shown here is the details of step S107 in FIG.
The extraction unit 103 repeats Steps S1001 to S1003 for each of the logical blocks LB1 (121) to LB9 (129) included in the reconfigurable unit 101 (Step S1001).

In step S1002, the extraction unit 103 extracts an LUT value from the logical block (step S1002). After extracting the LUT for all the logical blocks, the extraction unit 103 ends the repetition (step S1003).
Next, the extraction unit 103 repeats Steps S1004 to S1010 for each of the switch matrices 131 to 146 included in the reconfigurable unit 101 (Step S1004).

Next, the extraction unit 103 repeats Steps S1005 to S1009 for each transistor switch group for all transistor switch groups included in each switch matrix (Step S1005).
Next, the extraction unit 103 repeats steps S1006 to S1008 for all transistor switches included in each transistor switch group (step S1006).

In step S1006, the extraction unit 103 extracts a memory value indicating ON / OFF of the transistor switch (step S1007).
When the extraction unit 103 extracts the memory values indicating ON / OFF for all the transistor switches, the extraction unit 103 ends the repetition for each transistor switch (step S1008). Next, when the process of step S1007 is finished for all the transistor switch groups, the repetition for each transistor switch group is finished (step S1009). Next, when the process of step S1007 is finished for all switch matrices, the repetition for each switch matrix is finished (step S1010).
2. Second Embodiment Here, an information processing apparatus 10a will be described as a second embodiment of the present invention. The information processing apparatus 10a includes a device capable of reconfiguring a circuit based on design data, as with the information processing apparatus 10 according to the first embodiment. The information processing apparatus 10a is a function that the information processing apparatus 10 has. In addition, it has a function of optimizing a circuit composed of reconfigurable devices.
<Configuration>
FIG. 10 is a functional block diagram showing a functional configuration of the information processing apparatus 10a.

  As shown in the figure, the information processing apparatus 10a includes a reconfigurable unit 101a, a design data storage unit 102a, an extraction unit 103a, a key storage unit 104a, an encryption unit 105a, a decryption unit 106a, an update unit 107a, and an internal state storage. Unit 108a and optimization unit 109a. The difference from the information processing apparatus 10 is that an internal state storage unit 108a and an optimization unit 109a are provided.

Specifically, the information processing apparatus 10a is a computer system including a microprocessor, a ROM, a RAM, a hard disk unit, and the like, and when the microprocessor executes a computer program stored in the RAM or the hard disk unit, Achieve that function.
The reconfigurable unit 101a, the design data storage unit 102a, the extraction unit 103a, the key storage unit 104a, the encryption unit 105a, the decryption unit 106a, and the update unit 107a are reconfigurable components that are components of the information processing apparatus 10. Unit 101, design data storage unit 102, extraction unit 103, key storage unit 104, encryption unit 105, decryption unit 106, and update unit 107. The internal state storage unit 108a and the optimization unit 109a, which are components unique to the processing apparatus 10a, will be described.
(1) Internal state storage unit 108a
The internal state storage unit 108a has a function of storing the internal state of the reconfigurable unit 101a.

Specifically, the internal state storage unit 108a stores state information indicating which of the plurality of logical blocks included in the reconfigurable unit 101a is used for circuit configuration. .
FIG. 11 is a diagram illustrating a data configuration of state information 400 which is an example of state information. As shown in the figure, the status information 400 is configured by associating logical blocks LB1 and LB2 with a design data ID “A”. This indicates that the logical block LB1 and the logical block LB2 in the reconfigurable unit 101a are configured based on design data whose design data ID is “A”.

Further, when the circuit configuration in the reconfigurable unit 101a is updated, the internal state storage unit 108a generates new state information, and replaces the state information stored so far with the new circuit configuration. The state information to be stored is stored internally.
The internal state storage unit 108a may be configured to generate new state information based on information received from the optimization unit 109a when new design data is generated in the optimization unit 109a.

For example, the state information 410 shown in FIG. 12 is different from the state information 400 of FIG. 11 in that the logical blocks LB1 and LB4 are associated with the design data ID “A”, and the logical blocks LB2, LB3, LB5, LB6 and the design data ID “B” are associated with each other. This is because the logical blocks LB1 and LB4 in the reconfigurable unit 101a are configured based on design data whose design data ID is “A”, and the logical blocks LB2, LB3, LB5, and LB6 are designed. It shows that the circuit is configured based on design data whose data ID is “B”.
(2) Optimization unit 109a
The optimization unit 109a has a function of generating design data such that two or more circuits newly configured by the reconfigurable unit 101a have an optimal arrangement.

  Specifically, the optimization unit 109a receives a circuit update request including one or more design data IDs from input means such as an input device. When receiving the circuit update request, the optimization unit 109a instructs the decoding unit 106a to decode the decoded data identified by the received one or more design data IDs. The optimization unit 109a receives one or more design data decoded by the decoding unit 106a.

In addition, the optimization unit 109a receives the design data extracted by the extraction unit 103a. The optimization unit 109a further reads out the state information stored in the internal state storage unit 108a.
The optimizing unit 109a uses the two or more design data received from the extracting unit 103a and the decoding unit 106a and the read state information so that the logical block utilization efficiency in the reconfigurable unit 101a is the highest. Design data for arranging the above circuits is generated.

As an example, the optimization unit 109a receives design data identified by the design data ID “A” from the extraction unit 103a, receives design data identified by the design data ID “B” from the decoding unit 106a, Consider a case where the state information 400 (see FIG. 11) is read from the state storage unit 108a.
Here, it is assumed that the optimization unit 109a already knows the arrangement of each logical block of the reconfigurable unit 101a. Specifically, the arrangement of each logical block is the arrangement order of the logical blocks shown in FIG. 2, that is, the position of each logical block in the reconfigurable section 101a. Furthermore, it is assumed that the optimization unit 109a also knows the number of logical blocks to be used for the circuit configuration of each design data. This may be described in the design data.

  The optimization unit 109a can recognize from the state information 400 that the unused logical blocks are LB3 to LB9. Here, assuming that four logical blocks are necessary for the configuration of the design data identified by the design data ID “B”, the optimization unit 109a uses the unused LB3 to LB9 effectively. For example, the design data identified by the design data ID “A” that has been configured by using the logic blocks LB1 and LB2 is realized by using the logic blocks LB1 and LB4, and the design data ID “B”. The identified design data is realized using logical blocks LB2, LB3, LB5, and LB6.

At this time, the unused logical blocks are LB7, LB8, and LB9, and the reconfigurable unit 101a can further configure a new circuit using the three consecutive logical blocks. .
<Operation>
Here, the operation of the information processing apparatus 10a will be described using the flowchart shown in FIG.

First, a circuit update request is generated (step S201), and the extraction unit 103a and the optimization unit 109a accept the circuit update request. Specifically, the extraction unit 103a and the optimization unit 109a accept a circuit update request via an input unit such as an input device. Here, the optimization unit 109a accepts the input of the design data ID together with the circuit update request.
The optimization unit 109a that has received the circuit update request reads the state information from the internal state storage unit 108a (step S202). The optimization unit 109a outputs the design data ID to the decoding unit 106a, and instructs the decoding unit 106a to decode the design data identified by the design data ID.

The decryption unit 106a reads out the encrypted design data identified by the design data ID from the design data storage unit 102a (step S203). Next, the decryption unit 106a reads key data associated with the design data ID from the key storage unit 104a (step S204).
The design data storage unit 102a deletes the design data information including the encrypted design data read in step S203 from the design data table (step S205).

  Next, the decryption unit 106a decrypts the design data by applying the decryption algorithm D to the encrypted design data read in step S203, using the key data read in step S204 as a decryption key (step S206). The decoding unit 106a outputs the decoded design data to the optimization unit 109a, and the optimization unit 109a receives the design data (step S207).

  Subsequently, the extraction unit 103a performs a process of extracting design data of a circuit currently configured inside the reconfigurable unit 101a (step S208). The details of the design data extraction process are the same as those in the first embodiment. The extraction unit 103a outputs the extracted design data to the optimization unit 109a, and the optimization unit 109a receives the design data (step S209).

Next, the optimizing unit 109a uses the state information read out in step S202, the design data received in step S207, the design data received in step S209, and the arrangement of known logical blocks in the reconfigurable unit 101a. New design data for effectively using the block is generated (step S210).
The update unit 107a receives new design data from the optimization unit 109a, and transfers the received design data to the reconfigurable unit 101 (step S211).

The reconfigurable unit 101a reconfigures the circuit by setting the value of each SRAM based on the newly received design data (step S212). Next, the internal state storage unit 108a generates state information indicating the state of the reconfigurable unit 101a whose circuit has been reconfigured (step S213), and updates the state information.
3. Third Embodiment A circuit update system 1 will be described as a third embodiment of the present invention.
<Configuration>
FIG. 14 is a diagram illustrating a configuration of the circuit update system 1. As shown in the figure, the circuit update system 1 includes an information processing apparatus 10b and a design data conversion apparatus 20, and the information processing apparatus 10b and the design data conversion apparatus 20 are connected via a network 30. .

As shown in FIG. 14, the information processing apparatus 10b includes a reconfigurable unit 101b, a design data storage unit 102b, an extraction unit 103b, a key storage unit 104b, an encryption unit 105b, a decryption unit 106b, an update unit 107b, and an internal state storage. Unit 108a and transmission / reception unit 110b. The design data conversion apparatus 20 includes a transmission / reception unit 501 and an optimization unit 502.
That is, in the circuit update system 1 according to the third embodiment, the optimization unit 109a of the information processing apparatus 10a according to the second embodiment exists in the design data conversion apparatus 20 that is an external apparatus via the network 30. It has a configuration.

The transmission / reception unit 110b and the transmission / reception unit 501 are both network connection units and have a function of transmitting / receiving information to / from each other via the network 30.
The optimization unit 502 of the design data conversion apparatus 20 has the same function as the optimization unit 109a of the second embodiment.
The information processing apparatus 10b and the design data conversion apparatus 20 are specifically computer systems including a microprocessor, a ROM, a RAM, a hard disk unit, etc., and a computer program stored in the RAM or the hard disk unit. Each device achieves its function by being executed by the microprocessor.
<Operation>
Here, the operation of the circuit update system 1 will be described using the flowchart shown in FIG.

  First, a circuit update request is generated (step S301), and the extraction unit 103b and the update unit 107b accept a circuit update request. Specifically, the extraction unit 103a and the optimization unit 109a accept a circuit update request via an input unit such as an input device. Here, the update unit 107b accepts an input of a design data ID together with a circuit update request. The update unit 107b that has received the circuit update request including the design data ID notifies the decryption unit 106b of the design data ID and instructs the decryption of the encrypted design data identified by the design data ID.

The decrypting unit 106b that has received the instruction from the updating unit 107b reads out the encrypted design data identified by the design data ID from the design data storage unit 102b (step S302). Next, the decryption unit 106b reads the key data associated with the design data ID from the key storage unit 104b (step S303).
The design data storage unit 102b deletes the design data information including the encrypted design data read in step S302 from the design data table (step S304).

  Next, the decryption unit 106b decrypts the design data by applying the decryption algorithm D to the encrypted design data read in step S302, using the key data read in step S303 as a decryption key (step S305). The decryption unit 106b outputs the decrypted design data to the update unit 107b. The update unit 107b that has received the design data outputs the design data to the transmission / reception unit 110b.

Next, the extraction unit 103b performs a process of extracting design data of a circuit currently configured in the reconfigurable unit 101b (step S306). The extraction unit 103b outputs the extracted design data to the transmission / reception unit 110b.
The transmission / reception unit 110b that has received the design data from the extraction unit 103b and the update unit 107b reads state information from the internal state storage unit 108b (step S307).

The transmission / reception unit 110b transmits the design data received from the extraction unit 103b, the design data received from the update unit 107b, and the state information to the design data conversion device 20 via the network 30, and the transmission / reception unit of the design data conversion device 20 501 receives design data and state information (step S308).
The optimization unit 502 of the design data conversion apparatus 20 uses each logical block in the reconfigurable unit 101b of the information processing apparatus 10b based on the arrangement of two or more pieces of design data, status information, and known logical blocks received in step S308. New design data is generated for effectively using (Step S309).

The optimization unit 502 transmits the generated new design data to the information processing apparatus 10b via the transmission / reception unit 501 and the network 30, and the transmission / reception unit 110b of the information processing apparatus 10b receives the design data (step S310). .
The transmission / reception unit 110b outputs the received new design data to the update unit 107b, and the update unit 107b receives the new design data and transfers the received design data to the reconfigurable unit 101b.

The reconfigurable unit 101b reconfigures the circuit by setting the value of each SRAM based on the received design data (step S311).
Subsequently, the internal state storage unit 108b generates state information indicating the state of the reconfigurable unit 101b whose circuit has been reconfigured (step S312), and updates the state information.
4). Other Modifications Although the present invention has been described based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and the following cases are included in the present invention. .
(1) The reconfigurable unit in the above embodiment is not limited to a device having a specific configuration such as FPGA or PLD. Thus, the logical block of the above embodiment has a configuration realized by an LUT. However, the logical block in the present invention is not limited to the case realized by an LUT, and an ALU, a logical operation unit, a shift control unit, and a data control unit. , Flip-flops, etc., or a combination thereof.
(2) A configuration in which the function of the design data storage unit in the above embodiment is substituted for an external recording medium is also included in the present invention.

  In this case, the information processing apparatus includes a medium input / output unit that inputs and outputs information with an external recording medium. The information processing apparatus writes the design data encrypted by the encryption unit to the recording medium via the medium input / output unit while the recording medium is mounted on the medium input / output unit. The information processing apparatus reads the encrypted design data stored in the recording medium via the medium input / output unit, and outputs the read encrypted design data to the decryption unit.

With this configuration, the memory procedure of the information processing apparatus itself can be saved, and the memory capacity can be effectively used.
(3) The internal state holding unit in the above embodiment has a configuration for holding the state information in which the logic block used in the circuit configuration is associated with the design data ID. Of course, the information may be any information that can be used for optimization by the optimization unit, such as position information of logical blocks that are not used in the circuit configuration.
(4) The information processing apparatus of the above embodiment has a configuration in which key data unique to each design data is held in the key storage unit, but key information used for design data encryption / decryption in the present invention. Is not limited to the configuration previously stored in the key storage unit.

For example, each time design data encryption / decryption processing is executed, a random number generator may be generated using a random number generator, and the random number sequence may be used as key information to execute encryption / decryption processing. Further, the random number sequence generated here may be stored in the key storage unit in association with the design data ID.
In this way, by managing the design data ID and the key information used for encryption in association with each other, it is possible to easily select the key information used at the time of decryption.

Further, when the same key is used for decryption and encryption, there is an effect that key management becomes easy.
Also, by providing a function for generating a key, a different key can be used for each encryption, and a higher level of design data protection can be realized.
The design data decrypted by the decryption unit is mounted as a circuit in the reconfigurable unit, and the design data is further extracted from the circuit by the extraction unit, and is encrypted again by the encryption unit. Encryption may be performed using the same key information as the key information (random number sequence) used at the time of decryption, or different key information may be separately generated and encrypted.
(5) The information processing apparatus of the present invention refers to the state information held by the internal state holding unit, and does not extract all design data from the reconfigurable unit, but selectively selects the design data. May be configured to be extracted.

For example, when the internal state holding unit stores the state information 410 illustrated in FIG. 12, the extraction unit refers to the state information 410, and the design data ID is “A” from the logical blocks LB1 and LB4. Extract data only. Alternatively, the extraction unit may be configured to extract only design data whose design data ID is “B” from the logical blocks LB2, LB3, LB5, and LB6.
(6) The information processing apparatus according to the present invention may include a circuit deletion unit that deletes a circuit realized by the reconfigurable unit. Specifically, after the extraction unit reads the design data of the circuit realized by the reconfigurable unit, the circuit deleting unit is configured to delete the circuit realized by the reconfigurable unit. Also good.

By including such a circuit deletion unit and deleting a circuit that does not require the circuit deletion unit, the reconfigurable unit can be used efficiently.
(7) In the information processing apparatus according to the present invention, when the extraction unit reads out the circuit realized by the reconfigurable unit as design data, the extraction unit requests, for example, an apparatus that requested extraction (circuit reconfiguration), Alternatively, the configuration may be such that the user is authenticated, and whether or not the design data is extracted is determined based on the result of the authentication process.

An example of the authentication process here is challenge-response authentication using a public key cryptosystem.
Even when a request for transmitting the extracted design data from the information processing device is accepted, the device or user who requested the transmission is authenticated, and the design data is transmitted to the outside based on the result of the authentication process. It may be configured to determine whether or not to execute.

Further, the process of writing the encrypted design data to the external recording medium may be similarly executed by determining whether or not to write the encrypted design data based on the result of the authentication process.
(8) In the above embodiment, the information processing apparatus 10b is configured to transmit the design data extracted by the extraction unit as it is via the network 30 when transmitting the design data to the external design data conversion apparatus 20. However, the present invention is not limited to the configuration. For example, a configuration in which part or all of the design data is encrypted and the encrypted design data is transmitted to the design data conversion apparatus 20 is also included in the present invention.

In this case, the design data conversion apparatus 20 may be configured such that the optimization unit 502 executes the conversion process based on the design data partially or entirely encrypted and the internal state.
As a specific example, it is assumed that only the position of the circuit in the reconfigurable part is adjusted while keeping the design data secret.
(9) The design data storage unit provided in the information processing apparatus according to the present invention may be a memory such as a general RAM accessible from the outside. By realizing with a general RAM or the like, it is possible to increase the capacity of the design data storage unit relatively inexpensively.

Further, the design data storage unit may be a memory existing inside an integrated circuit where access is restricted.
(10) The optimization unit in the above embodiment has a configuration that optimizes the arrangement when two or more circuits are configured in the reconfigurable unit, but the present invention replaces the optimization unit, A configuration may be provided that includes conversion means for converting design data indicating two or more circuits into new design data.

  For example, when the first circuit that achieves the first function is realized in the reconfigurable unit, the extraction unit extracts the first design data from the first circuit. On the other hand, the decoding unit decodes second design data, which is design data for configuring the second circuit that achieves the second function. The conversion means may be configured to generate third design data for configuring a third circuit having both the first function and the second function.

Further, the conversion means does not simply generate the third design data for configuring the third circuit having both the first and second functions, but incorporates the second function into the first function, It may be configured to generate third design data for configuring a third circuit that achieves a new function that performs a simple process.
(11) In the reconfigurable section in the above embodiment, for example, a configuration in which a decryption circuit for decrypting encrypted content may be implemented.

Since the decoding circuit implemented in the reconfigurable unit is different for each algorithm, the decoding process corresponding to various algorithms can be realized by updating the decoding circuit.
However, the present invention is not limited in any way to the function achieved by the circuit implemented in the reconfigurable unit, and any circuit may be configured in the reconfigurable unit.
(12) The present invention may be the method described above. Further, the present invention may be a computer program that realizes these methods by a computer, or may be a digital signal composed of the computer program.

  The present invention also provides a computer-readable recording medium such as a flexible disk, hard disk, CD-ROM, MO, DVD, DVD-ROM, DVD-RAM, BD (Blu-ray Disc). ), Recorded in a semiconductor memory or the like. Further, the present invention may be the computer program or the digital signal recorded on these recording media.

In the present invention, the computer program or the digital signal may be transmitted via an electric communication line, a wireless or wired communication line, a network represented by the Internet, or the like.
The present invention may be a computer system including a microprocessor and a memory, wherein the memory stores the computer program, and the microprocessor operates according to the computer program.

In addition, the program or the digital signal is recorded on the recording medium and transferred, or the program or the digital signal is transferred via the network or the like, and is executed by another independent computer system. It is good.
(13) The present invention is also applicable to a case where some or all of the functional blocks of the information processing apparatuses 10, 10a, and 10b and the design data conversion apparatus 20 in the above embodiment are realized as an LSI that is an integrated circuit. included. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them. The name used here is LSI, but it may also be called IC, system LSI, super LSI, or ultra LSI depending on the degree of integration.

Further, the method of circuit integration is not limited to LSI, and may be realized with a dedicated circuit. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI or a reconfigurable processor that can reconfigure the connection and setting of circuit cells inside the LSI may be used.
Furthermore, if integrated circuit technology comes out to replace LSI's as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to carry out function block integration using this technology. Biotechnology can be applied as a possibility.
(14) A configuration in which the embodiment and the modification examples are combined is also included in the present invention.

  The present invention can be used in a management and continuous manner, for example, in an industry that manufactures and sells equipment capable of updating an encryption algorithm.

It is a functional block diagram which shows the functional structure of the information processing apparatus 10 which is the 1st Embodiment of this invention. 3 is a diagram showing an outline of a reconfigurable unit 101. FIG. It is a figure which shows the outline | summary of logical block LB1 (121). (A) It is a figure which shows the outline | summary of the switch matrix 131. FIG. (B) It is a figure which shows the internal structure of a transistor switch group. 4 is a diagram showing a data configuration of a design data table 200. FIG. It is a figure which shows the data structure of the design data table. 3 is a diagram showing a data configuration of a key table 300. FIG. 3 is a flowchart illustrating an overall operation of the information processing apparatus 10. 5 is a flowchart illustrating an operation of design data extraction processing by an extraction unit 103. It is a functional block diagram which shows the functional structure of the information processing apparatus 10a which is the 2nd Embodiment of this invention. It is a figure which shows the data structure of the status information 400 memorize | stored in the internal state memory | storage part 108a. It is a figure which shows the data structure of the status information 410 memorize | stored in the internal state memory | storage part 108a. It is a flowchart which shows the whole operation | movement of the information processing apparatus 10a. It is a figure which shows the structure of the circuit update system 1 which is the 3rd Embodiment of this invention. 3 is a flowchart showing the overall operation of the circuit update system 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit update system 10 Information processing apparatus 10a Information processing apparatus 10b Information processing apparatus 20 Design data conversion apparatus 30 Network 101 Reconfigurable part 101a Reconfigurable part 101b Reconfigurable part 102 Design data storage part 102a Design data storage part 102b Design Data storage unit 103 Extraction unit 103a Extraction unit 103b Extraction unit 104 Key storage unit 104a Key storage unit 104b Key storage unit 105 Encryption unit 105a Encryption unit 105b Encryption unit 106 Decryption unit 106a Decryption unit 106b Decryption unit 107 Update unit 107a Update Unit 107b update unit 108a internal state storage unit 108b internal state storage unit 109a optimization unit 110a transmission / reception unit 110b transmission / reception unit
131-146 Switch matrix 151-153 LUT
154, 155 Flip-flop 161-164 Transistor switch group 171-176 Transistor switch 501 Transmission / reception unit 502 Optimization unit

Claims (16)

Reconfigurable means including a plurality of logic blocks, and capable of reconfiguring a circuit by changing the logic of each logic block and changing the connection between each logic block;
Extracting means for the shown to design data and connection between logical and logical block with logical block showing the circuits that are currently configured to extract from the reconfigurable device in the reconfigurable section,
Design data storage means for storing design data indicating logic of logic blocks indicating circuits and connections between the logic blocks;
Upon receiving an instruction to update the circuit configured in the reconfigurable means, the design data of the first circuit currently configured in the reconfigurable means is currently configured in the reconfigurable means from the extraction means. The design data of the second circuit that is not obtained is acquired from the design data storage means, and the circuit configured in the reconfigurable means is updated using the design data of the first circuit and the design data of the second circuit, An information processing apparatus comprising: an updating unit that deletes design data of the second circuit from the design data storage unit when updating of the circuit is completed . The update means further includes the reconfigurable means without using the design data of the first circuit when receiving an instruction to update the circuit configured in the reconfigurable means to the second circuit. The write circuit according to claim 1, further comprising: a writing unit that updates a configured circuit and writes the design data of the first circuit into the design data storage unit after the design data of the second circuit is deleted. The information processing apparatus described. The information processing apparatus includes:
Encryption means for encrypting design data of the first circuit extracted by the extraction means;
The information processing apparatus according to claim 2, wherein the writing unit writes the encrypted design data of the first circuit into the design data storage unit. The design data of the second circuit stored in the design data storage means is encrypted,
The information processing apparatus includes:
Decryption means for decrypting the encrypted design data of the second circuit ,
The information processing apparatus according to claim 3, wherein the updating unit updates a circuit configured in the reconfigurable unit by using design data of the second circuit decoded by the decoding unit. The information processing apparatus includes:
Key information storage means for securely storing key information corresponding to each design data,
The encryption unit reads first key information corresponding to the design data of the first circuit from the key information storage unit, and encrypts the design data of the first circuit based on the read first key information. ,
The decryption means reads out second key information corresponding to the design data of the second circuit from the key information storage means, and decrypts the design data of the second circuit based on the read second key information. The information processing apparatus according to claim 4. The information processing apparatus further includes:
Key information generating means for generating the key information corresponding to each design data,
The information processing apparatus according to claim 5, wherein the key information generated by the key information generation unit is written in the key information storage unit. The information processing apparatus further includes:
Internal state holding means for holding an internal state indicating a position of a logic block used in the configuration of the first circuit in the reconfigurable means;
The internal state held by the internal state holding unit, the design data of the first circuit extracted by the extraction unit, and a second function different from the first function achieved by the first circuit are achieved. And optimization means for generating design data for the third circuit so that the reconfigurable means can be optimized from the design data for the second circuit .
The information processing apparatus according to claim 1, wherein the updating unit updates a circuit configured in the reconfigurable unit using design data of the third circuit generated by the optimization unit. . The internal state holding means includes a position of a logic block used in the configuration of a circuit that achieves the first function, and a position of a logic block used in the configuration of a circuit that achieves the second function. The information processing apparatus according to claim 7, wherein new internal information that indicates is generated and held. The information processing apparatus further includes:
An internal state holding means for holding an internal state indicating a position of a logic block used in the configuration of the first circuit in the reconfigurable means;
The extraction unit selectively extracts design data of the first circuit from the reconfigurable unit based on the internal state held by the internal state holding unit. The information processing apparatus described. The information processing apparatus is connected to an external device via a network, and
The internal state held in the internal state holding unit, the design data of the first circuit extracted by the extraction unit, and the design data of the second circuit that achieves a function different from the first circuit. Transmitting means for transmitting to the external device;
Receiving means for receiving design data of the third circuit from the external device so that the reconfigurable means can be optimized ;
The information processing apparatus according to claim 9, wherein the updating unit updates a circuit configured in the reconfigurable unit using the received design data of the third circuit . Before Symbol The first circuit, to achieve the first function,
The information processing apparatus includes:
The first and second functions are achieved from the design data of the first circuit extracted by the extracting means and the design data of the second circuit that achieves a second function different from the first function. Design data conversion means for generating design data for configuring the third circuit to be provided ,
The information processing apparatus according to claim 1 , wherein the updating unit updates a circuit configured in the reconfigurable unit using design data of the third circuit . The information processing apparatus according to any one of claims 1 to 6, wherein the design data storage unit is configured as a recording medium that is removable from the information processing apparatus. An information processing apparatus including a plurality of logical blocks, and comprising: reconfigurable means capable of reconfiguring a circuit by changing the logic of each logical block and changing connections between the logical blocks; and design data storage means A processing method used,
The design data storage means stores design data indicating logic of logic blocks indicating circuits and connections between the logic blocks,
The processing method is:
An extraction step of the shows to design data and connection between logical and logical block with logical block showing the circuits that are currently configured to extract from the reconfigurable device in the reconfigurable section,
Upon receiving an instruction to update the circuit configured in the reconfigurable means, the design data of the first circuit currently configured in the reconfigurable means is currently configured in the reconfigurable means from the extraction means. The design data of the second circuit that is not obtained is acquired from the design data storage means, and the circuit configured in the reconfigurable means is updated using the design data of the first circuit and the design data of the second circuit, A processing method comprising: an update step of deleting design data of the second circuit from the design data storage means when the update of the circuit is completed . An information processing apparatus including a plurality of logical blocks, and comprising: reconfigurable means capable of reconfiguring a circuit by changing the logic of each logical block and changing connections between the logical blocks; and design data storage means A computer program used,
The design data storage means stores design data indicating logic of logic blocks indicating circuits and connections between the logic blocks,
The computer program is
An extraction step of the shows to design data and connection between logical and logical block with logical block showing the circuits that are currently configured to extract from the reconfigurable device in the reconfigurable section,
Upon receiving an instruction to update the circuit configured in the reconfigurable means, the design data of the first circuit currently configured in the reconfigurable means is currently configured in the reconfigurable means from the extraction means. The design data of the second circuit that is not obtained is acquired from the design data storage means, and the circuit configured in the reconfigurable means is updated using the design data of the first circuit and the design data of the second circuit, A computer program comprising: an update step of deleting design data of the second circuit from the design data storage means when the update of the circuit is completed . The computer program, a computer program according to claim 1 4, characterized in that it is recorded in a computer-readable recording medium. Reconfigurable means including a plurality of logic blocks, and capable of reconfiguring a circuit by changing the logic of each logic block and changing the connection between each logic block;
Extracting means for the shown to design data and connection between logical and logical block with logical block showing the circuits that are currently configured to extract from the reconfigurable device in the reconfigurable section,
Design data storage means for storing design data indicating logic of logic blocks indicating circuits and connections between the logic blocks;
Upon receiving an instruction to update the circuit configured in the reconfigurable means, the design data of the first circuit currently configured in the reconfigurable means is currently configured in the reconfigurable means from the extraction means. The design data of the second circuit that is not obtained is acquired from the design data storage means, and the circuit configured in the reconfigurable means is updated using the design data of the first circuit and the design data of the second circuit, An integrated circuit comprising: update means for deleting design data of the second circuit from the design data storage means when update of the circuit is completed.

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