JP4799637B2 - Low density parity check code decoding apparatus and method - Google Patents

Description

  The present invention relates to a low-density parity check (LDPC) code decoding apparatus and method, and more particularly, to improve processing throughput without reducing quality.

A Belief Propagation (BP) algorithm is known as a decoding algorithm in an LDPC code (see Non-Patent Document 1). The BP algorithm is a probability propagation algorithm that updates the reliability by repeating the row processing shown in equations (1) to (3) and the column processing shown in equation (4).

Here, i is the number of decoding iterations, Z ⁱ n is the a posteriori log likelihood ratio (a posteriori LLR) after performing the decoding process ⁱ times at the n th bit, F n is the channel value, and R ⁱ mn is m rows. This is a row processing result after i-th decoding processing for the n-th bit (initial value Z ⁰ n = Fn, R ⁰ mn = 0).

  In the decoding method to which the BP algorithm is applied, as shown in the above equation, the posterior LLR is updated every decoding iteration.

  On the other hand, the Turbo Decoding Message Passing (TDMP) algorithm shown in Non-Patent Document 2 processes i in the above-described equations (1) to (4) for the m-th row instead of the decoding iteration number. This is an algorithm for processing as time (cycle). That is, the posterior LLR is updated for each row process. Since the TDMP algorithm has excellent convergence characteristics, it is known to obtain the same error characteristics with a smaller number of iterations than the BP algorithm.

R. G. Gallager, “Low-Density Parity-Check Codes”, IRE Trans. Info. Theory, vol. IT-8, pp. 21-28, 1962 M.M. M.M. Mansour and N.M. R. Shanbhag, “High Throughput LDPC Decoder,” IEEE Trans. VLSI Systems, vol. 11, no. 6, Dec. 2003

  However, in the TDMP algorithm, when row processing is performed, the row processing cannot be performed until processing of rows and columns including the same bit node as the bit node included in the target row is completed.

  Also, in the TDMP algorithm, the decoding process is executed for the set number of repetitions, and the decoding process is terminated. However, when there are almost no errors from the beginning, the decoding process of a predetermined number of repetitions may be wasted.

  Furthermore, when performing error detection, it is necessary to stop the decoding process once and perform error detection.

For this reason, there is a problem that the decoding process is delayed by the error detection processing time, and the error detection process cannot be performed frequently.

  Therefore, a low density parity check (LDPC) code decoding apparatus and method that can improve processing throughput without reducing quality is desired.

In order to solve such a problem, the low-density parity check code decoding device according to the first aspect of the present invention includes (1) decoding processing means for executing decoding processing, and (2) data to be decoded by applying the same check matrix. Priority information holding means for holding priority information assigned to each decoding block, and (3) the decoding processing based on the priority information assigned to a plurality of decoding blocks used for decoding processing. The means has processing block determination means for determining a decoding block for decoding processing, and performs decoding processing of a plurality of decoding blocks in parallel .

The low density parity check code decoding method according to the second aspect of the present invention comprises: (0) decoding processing means, priority information holding means, and processing decoding block determination means; (1) the decoding processing means executes decoding processing; (2) The priority information holding means holds priority information given to each decoding block , which is a cluster of data to be decoded by applying the same check matrix , and (3) the processing decoding The block determination means determines a decoding block to be decoded by the decoding processing means based on the priority information given to the plurality of decoding blocks to be subjected to the decoding processing , and (4) performs the decoding processing of the plurality of decoding blocks in parallel. It is characterized by being executed.

  According to the low density parity check code decoding apparatus and method of the present invention, it is possible to improve the processing throughput without reducing the quality.

It is a block diagram which shows the whole structure of the LDPC code decoding apparatus which concerns on embodiment. It is a block diagram which shows the detailed structure of the decoding process control part of embodiment. It is a flowchart which shows the process of the decoding process monitoring part of embodiment. It is explanatory drawing which shows the example of the wait cycle defined about the example of the check matrix of embodiment, and the check matrix. It is a timing chart which shows the decoding block and row | line | column of the process start for demonstrating the effect of embodiment.

(A) Main Embodiment Hereinafter, an embodiment of a low density parity check (LDPC) code decoding apparatus and method according to the present invention will be described in detail with reference to the drawings.

(A-1) Configuration of Embodiment FIG. 1 is a block diagram showing an overall configuration of an LDPC code decoding apparatus according to the embodiment, and FIG. 2 is a block diagram showing a detailed configuration of a decoding processing control unit in FIG. is there.

  1, an LDPC code decoding apparatus 1 according to an embodiment includes a decoder input interface unit (decoder input IF) 10, an Fn storage memory 11, a decoding process control unit 12, a selector 13, a row processing circuit 14, and a first buffer. 15, adder 16, Zn storage memory 17, second buffer 18, Rmn storage memory 19, third buffer 20, subtractor 21, hard decision unit 22, parity decision unit 23, hard decision data storage memory 24, and decoding A decoder output interface unit (decoder output IF) 25 is provided.

  The decoder input interface unit 10 takes in the data (communication channel value) of each decoding block and the decoding information about each decoding block, gives the channel value to the Fn storage memory 11, and gives the decoding information to the decoding processing control unit 12. It is.

  Here, the decoding block is a cluster (data to be decoded) of data to be decoded by applying the same check matrix. That is, the LDPC code decoding apparatus 1 of this embodiment can perform decoding on a plurality of decoding blocks in parallel in a time division manner. Decoding information includes (a) check matrix information, (b) maximum number of decoding repetitions, (c) priority information, and (d) parity monitoring cycle. The parity check matrix information is information on a parity check matrix related to the decoded block. The maximum number of decoding repetitions is the upper limit number of repetitions for repeating the decoding process. The priority information is information on the priority for decoding processing between decoding blocks. The parity monitoring cycle is a preset value that is compared with the number of consecutive times that the parity check result for the processed row is OK, and the decoding process is performed when the number of OK consecutive times becomes the parity monitoring cycle. It is used to terminate.

  The Fn storage memory 11 stores a channel value given from the outside via the decoder input interface unit 10, and stores the channel value Fn stored under the control of the decoding processing control unit 12. Is supplied to the selector 13.

  The decoding process control unit 12 has a function of determining a block and a row to be decoded and has a detailed configuration as shown in FIG. The detailed configuration of the decoding process control unit 12 will be described later.

  The selector 13 selects the data (communication channel value) read from the Fn storage memory 11 or the output data of the subtraction unit 21 under the control of the decoding processing control unit 12, and the row processing circuit 14 and the first buffer 15. It is something to give to. When the selector 13 selects the data (communication path value) read from the Fn storage memory 11, the above-described equation (1) is calculated first (i-1 = 0), the processing target row, etc. This is a case where the communication path value Fn is transferred to the first buffer 15.

  The row processing circuit 14 performs the operation of the above-described equation (2). In the case of this embodiment, there is no feature in the calculation method of matrix processing, and the detailed description thereof is omitted. The calculation of the expression (3) necessary for the calculation of the expression (2) may be executed using a lookup table or the like. Further, instead of the expression (2) itself, an approximation expression of the expression (2) may be calculated. The row processing result Rmn by the row processing circuit 14 is given to the adder 16 and the Rmn storage memory 19.

  The first buffer 15 buffers the communication path value Fn necessary for the calculation of the above-described equation (4), and adjusts the timing at which the communication path value Fn is given to the adding unit 16.

  The adding unit 16 includes a plurality of adders, and adds the row processing result Rmn from the row processing circuit 14 and the communication path value Fn buffered by the first buffer 15. That is, the adding unit 16 executes the above-described equation (4). The column processing result Zn obtained by the adding unit 16 is given to the Zn storage memory 17 and the hard decision unit 22.

  The Zn storage memory 17 stores the column processing result Zn from the adding unit 16 in the area of the address given from the decoding processing control unit 12. The Zn storage memory 17 reads the column processing result Zn from the area of the address output from the second buffer 18 and gives it to the subtractor 21 as a subtracted input.

  The second buffer 18 buffers the write address to the Zn storage memory 17 to adjust the timing, and gives the buffered address to the Zn storage memory 17, the parity determination unit 23, and the hard decision data storage memory 24. It is.

  The Rmn storage memory 19 stores the row processing result Rmn from the row processing circuit 14 in the area of the address given from the decoding processing control unit 12. The Rmn storage memory 19 reads the row processing result Rmn from the area of the address output from the third buffer 20 and gives it to the subtractor 21 as a subtraction input.

  The third buffer 20 buffers the write address to the Rmn storage memory 19 to adjust the timing, and gives the buffered address to the Rmn storage memory 19.

  The subtracting unit 21 includes a plurality of subtracters, and subtracts the row processing result Rmn read from the Rmn storage memory 19 from the column processing result Zn read from the Zn storage memory 17 and selects it by the selector 13. It is given as input. That is, the subtracting unit 21 performs the calculation of the above-described equation (1).

  The hard decision unit 22 performs a hard decision according to the equation (5) to be described later on the column processing result Zn output from the adder 16, and the obtained hard decision data is converted to the parity decision unit 23 and the hard decision data. This is given to the judgment data storage memory 24.

  The parity determination unit 23 performs error detection (parity determination) for each repetition of the decoding process based on the hard determination data from the hard determination unit 22 and the address output from the second buffer 18. As will be described later, the address output from the second buffer 18 is formed by the decoding processing control unit 12 also using the decoding block to be checked and the check matrix information. Error information), and error detection can be performed. The parity determination unit 23 gives the parity determination result and the parity check block number to the decoding process control unit 12. Here, the parity determination unit 23 holds information (for example, table information) for converting the address output from the second buffer 18 into a parity check block number, thereby generating a parity check block number. To do. Note that the decoding process control unit 12 may have a function of converting an address into a parity check block number.

The LDPC code uses a check matrix H and a decoding result X ^ = (x ^ ₁ , ..., x ^ _n , ..., x ^ _N ) obtained by performing a hard decision as shown in Equation (5), and HX = By determining whether or not it is 0, error detection is possible. That is, even if the decoding process with the maximum number of iterations is not performed, error detection is performed on a row that has been processed for each decoding iteration, and if the error detection result is OK for a predetermined number of times, the decoding process is performed. It may be terminated. In this embodiment, in view of such a point, error detection (parity determination) is performed on a processed row every time decoding processing is repeated, and the decoding processing control unit 11 side performs maximum error detection based on the parity determination result. It is decided to determine whether or not to end the decoding process before repeating the decoding process of the number of repetitions.

  The hard decision data storage memory 24 stores the hard decision data from the hard decision unit 22 in the area of the address output from the second buffer 18.

  The decoder output interface unit (decoder output IF) 25 reads hard decision data stored in the hard decision data storage memory 24 as decoded data when a decoding end notification is given from the decoding process control unit 12. Output.

  In the case of this embodiment, decoding can be performed in parallel on a plurality of decoding blocks in a time-sharing manner, so that the Fn storage memory 11, the Zn storage memory 17, the Rmn storage memory 19, and the hard decision data storage memory 24. Are selected to have such a capacity that data of a plurality of decoded blocks can be stored simultaneously.

  As described above, the decoding process control unit 12 having a function of determining a block and a row to be decoded has a detailed configuration as shown in FIG.

  In FIG. 2, the decoding process control unit 12 includes decoding information storage units 30-0 to 30- (B-1) for each decoding block (Code Block), and decoding process monitoring units 31-0 to 31- (for each decoding block. B-1), a scheduler 32 and an address generation unit 33. In FIG. 2, only the decoding block # 0 shows the decoding information storage unit (30-0) and the decoding process monitoring unit (31-0).

  Each decoding information storage unit 30 (30-0 to 30- (B-1)) is supplied from the outside via the decoder input interface unit 10, and the parity monitoring cycle, maximum decoding repetition number, priority of the decoding block This is a part for storing degree information and check matrix information.

  Each decoding process monitoring unit 31 (31-0 to 31- (B-1)) monitors the timing of executing the decoding process of the decoding block, or determines the end of the decoding process. Each decoding process monitoring unit 31 (31-0 to 31- (B-1)) is functionally connected to the parity counter 40 (40-0 to 40-) with respect to the decoding process monitoring unit 31-0 as shown in FIG. (B-1)), a decoding repetition counter 41 (41-0 to 41- (B-1)), a row counter 42 (42-0 to 42- (B-1)), a wait cycle operation unit 43 (43-). 0-43- (B-1)) and Wait counter 44 (44-0-44- (B-1)). The function of the decryption process monitoring unit 31 will be described in detail in the section on operation description.

  The scheduler 32 generates a schedule of decoding processing in units of rows based on information from the decoding processing monitoring units 31-0 to 31- (B-1) of all the decoding blocks. The decoding block number (block number), row number, and check matrix information to be executed are given to the address generation unit 33, and a selector control signal for the selector 13 shown in FIG. 1 is also formed. At present, the numbers of the decoding blocks to be subjected to the decoding process are fed back to the decoding process monitoring units 31-0 to 31- (B-1) of all the decoding blocks.

  The address generation unit 33 generates memory addresses for the Fn storage memory 11, the Zn storage memory 17, and the Rmn storage memory 19 of FIG. 1 described above based on the block number, row number, and parity check matrix information given from the scheduler 32. Is.

(A-2) Operation of Embodiment Next, the operation (LDPC code decoding method of the embodiment) of the LDPC code decoding apparatus 1 of the embodiment having the configuration shown in FIGS. 1 and 2 described above will be described.

The data (communication channel value) of each decoding block given from the outside is written to the Fn storage memory 11 via the decoder input interface unit 10 and is input in parallel with the data (communication channel value). information, decoding information storage unit 30 of the corresponding decoded block of the decoding processing control unit 12; the (30-0~30- (B-1) optionally in the following description by omitting the branch numbers of the code) Written.

  Each decoding process monitoring unit 31 in the decoding process control unit 12 starts a series of processes shown in FIG. 3 after the decoding information is written in the corresponding decoding information storage unit 30. For example, the processing shown in FIG. 3 is started every review unit time (hereinafter referred to as a cycle). Further, for example, although the signal lines are not shown, all the decoding information storage units that require decoding processing at the time when the decoding information is set synchronize the processing shown in FIG. 3 under the control of the scheduler 32. And execute. FIG. 3 is a flowchart showing the process of each decoding process monitoring unit 31. Note that the cycle corresponds to a period in which “i” in each equation is updated in the above-described TDMP algorithm.

  When the process shown in FIG. 3 is started, the decoding process monitoring unit 31 determines whether or not to start the decoding process for the decoding block (step 100).

  In the case of starting from now, the decoding process monitoring unit 31 resets all the built-in counters (parity counter 40, decoding repetition counter 41, row counter 42, and wait counter 44) (step 101).

  On the other hand, when the decoding process has already been started for the decoding block, the decoding process monitoring unit 31 performs decoding of the row processed in the previous cycle based on the block number given from the scheduler 32. It is determined whether or not the block is the decoding block (step 102).

  If the row of the decoding block has been processed in the previous cycle, the decoding processing monitoring unit 31 counts up the row counter 42 (step 103), and then the count value of the row counter 42 is the number of rows of the check matrix. Is determined (step 104).

  Here, the count value of the row counter 42 represents the row in the decoding block to be decoded next, and the count value “0” represents the first row. Matching the number of rows in the matrix means that it is immediately after the row processing of the last row is finished. When the count value of the row counter 42 matches the number of rows in the parity check matrix, the decoding process monitoring unit 31 counts up the decoding repetition counter 41 and resets the row counter 42 (the value “ 0 ") (step 105). The decoding repetition counter 41 counts how many times the decoding process has been repeated.

  When the count value of the row counter 42 counted up in step 103 does not match the number of rows in the check matrix, or after the count up of the decoding repetition counter 41 or the reset of the row counter 42 is performed, the decoding process monitoring unit 31 The check matrix information stored in the decoded information storage unit 30 is read, the wait cycle is calculated by the wait cycle calculation unit 44, and the value of the obtained wait cycle is loaded into the wait counter 44 (step 106).

  The wait cycle calculation unit 44 may be configured by hardware, or may be provided as a subroutine.

  When row processing is performed, processing of the target row cannot be performed until processing of a row and a column including the same bit node as the bit node included in the target row is completed. The wait cycle is the number of cycles until the processing target row indicated by the count value of the row counter 42 can start processing. The wait cycle calculation unit 44 calculates a wait cycle according to the position of the bit node in the processing target row of the check matrix and the position of the bit node in another row on the column of the bit node.

  FIG. 4 shows an example of a parity check matrix (FIG. 4A) and a Wait cycle (FIG. 4B) for each row in the parity check matrix. In FIG. 4, L is the number of cycles in which row processing and column processing for one row are completed. As L, for example, 6 cycles can be applied.

  In the first row (row number is “0”), there are bit nodes in the 6th, 15th and 23rd columns. In these columns, the bit nodes are in the 15th, 8th and 13th rows, respectively. Node exists.

Even when the 15th row is a processing target row, the processing of that row ends after L cycles after becoming the processing target. For this reason, after the 16th to 18th rows are processed, even if the first row having a bit node in the same column becomes the processed row, the processing of the first row cannot be started immediately. -3 Cannot start without waiting for cycle ("3" is a cycle related to the 16th to 18th lines).

  The row having the bit node in the same column as the 15th column of the first row is the eighth row, and there is a period sufficiently longer than the L cycle before the processing target row changes from the eighth row to the first row. Therefore, it is not necessary to consider the Wait cycle in this column, and the same applies to the 23rd column of the first row.

  When the second row becomes the processing target row (row number is “1”), the first row starts processing after waiting for the Wait cycle, so the 17th and 9th rows having bit nodes in the same column The processing of the 14th and 14th lines has been completed, and the Wait cycle is “0”. The same applies to the third to sixth lines.

  In the seventh row (row number is “6”), bit nodes exist in the 10th and 14th columns, and in these columns, bit nodes exist in the 17th and 6th rows, respectively. Even when the sixth row is a processing target row, since the processing of that row ends after L cycles after the processing target row, even if the seventh row having a bit node in the same column becomes the processing target row, The process on the seventh line cannot be started immediately, and cannot be started without waiting for the L cycle.

  Similarly, the wait cycles for the eighth and subsequent rows are determined by calculation. As a result, when the wait cycles for each row are tabulated, the result is as shown in FIG.

  As long as the Wait cycle calculation unit 44 can calculate the Wait cycle as shown in FIG. 4B, the internal configuration and processing method are not limited. For example, it recognizes the positions of all the bit nodes in the processing target row, and then recognizes a row having a bit node in the same column as the column of each bit node, and has recently become a processing target in the recognition row. Recognize the line. Then, it is determined whether the difference in the number of lines between the recognized line and the relevant line is less than or equal to the required cycle L. If the required cycle is not less than L, “0” is set. Search whether there is a wait cycle other than “0” in the previous row up to row L, and remove the wait cycle of the previous row from the required cycle L as the wait cycle To do.

  If the decoding block that has been subjected to the row processing in the previous cycle of step 102 described above is a negative result as a result of determination as to whether or not the decoding block is the decoding block, the decoding processing monitoring unit 31 counts the count value of the wait counter 44. Whether or not is 0 is determined (step 107). If not 0, the decoding process monitoring unit 31 counts down the wait counter 44 (step 108).

  When the operations of the row counter 42, the decoding repetition counter 41, and the wait counter 44 are finished (steps 102 to 108), the decoding process monitoring unit 31 indicates that the parity check block number that has arrived from the parity determination unit 23 in FIG. It is determined whether or not a block is instructed (step 109). If the parity check block number does not arrive, the same processing is performed as when the arrived parity check block number does not indicate the decoding block.

  When the decoding block is instructed, the decoding process monitoring unit 31 further determines whether the parity determination result that has arrived together with the parity check block number is OK (the above-mentioned HX = 0 is OK). (Step 110), if it is OK, the parity counter 40 is counted up (step 111), and if it is NG, the parity counter 40 is reset (step 112).

  When the decoding process has just started and various counters are reset (step 101), or when the parity check block number that has arrived does not indicate the decoding block (negative result at step 109), When the operation is finished (steps 111 and 112), the decoding process monitoring unit 31 determines whether or not the count value of the parity counter 40 is smaller than the parity monitoring cycle stored in the decoding information storage unit 30 ( Step 113). If the count value of the parity counter 40 is smaller than the parity monitoring cycle, it is determined whether or not the count value of the decoding repetition counter 41 is smaller than the maximum number of decoding repetitions stored in the decoding information storage unit 30 (step 114). . The determination processing in these steps 113 and 114 is determination as to whether or not to end the decoding processing.

  When the count value of the parity counter 40 reaches the parity monitoring cycle, or when the count value of the decoding repetition counter 41 reaches the maximum number of decoding repetitions, the decoding process monitoring unit 31 performs the decoder output interface unit 25 of FIG. In response to this, a decoding completion notification specifying the decoding block is sent (step 115), and the decoding process flag is set to “0” (“1” indicates that the decoding process is continuing) (step 116). The series of processes shown in FIG.

  If the condition for terminating the decryption process is not satisfied, the decryption process monitoring unit 31 determines whether or not the count value of the wait counter 44 is 0 (step 117). If the count value of the wait counter 44 is other than 0 (in other words, the state in which the decoding process must be waited), the decoding process monitoring unit 31 sets the decoding process flag to “0” (step 116). Then, the series of processes shown in FIG.

  On the other hand, when the count value of the wait counter 44 is 0, the decoding process monitoring unit 31 sets the decoding process flag to “1” (step 118), generates a signal to be given to the scheduler 32, and outputs the signal to the scheduler 32. (Step 119), the series of processing shown in FIG.

  The signal given to the scheduler 32 includes priority information and check matrix information (only processing target row information) stored in the decoding information storage unit 30, a count value (processing row number) of the row counter 42, and decoding A processing flag and a selector control signal. The selector control signal is a control signal based on the count value of the decoding repetition counter 41 so that the output of the Fn storage memory 11 is selected at the time of the first decoding process of the processing target row.

  Even when the decoding process flag is set to “0” (step 116), the decoding process monitoring unit 31 may provide the scheduler 32 with a signal to that effect.

  In the scheduler 32, the decoding process flag and priority information output from the decoding process monitoring units 31-0 to 31- (B-1) are viewed, and the highest priority is selected from among the decoding process flags “1”. A decoding block having a high value is selected. Then, the scheduler 32 gives the decoding block number (block number), the row number, and the check matrix information for executing the decoding process at the present time (current cycle) to the address generation unit 33 and the selector 13 of FIG. Is supplied with the selector control signal given to the decoded block as it is. At this time, the number of the decoding block for executing the decoding process is also given to the decoding process monitoring units 31-0 to 31- (B-1) of all the decoding blocks.

  Note that the scheduler 32 may predetermine not only the current cycle but also a decoding block and a row number to be processed in a future cycle.

In the address generation unit 33, based on the information output from the scheduler 32, addresses to be given to the various memories 11, 17 and 19 are generated and given to the corresponding memories 11, 17 and 19, and each of the memories 11, 17 and 19 From 19, data necessary for input of the row processing to be processed in the decoding block to be processed is read.

The output data from the subtractor 21 that executes the calculation of the above-described equation (1) by the selector 13 according to the selector control signal from the scheduler 32 basically becomes the input data Lmn to the row processing circuit 14. Since the data read from the Fn storage memory 11 is input data Lmn to row processing circuit 14, the initial value of Ru is used as a posteriori log likelihood ratio Zn.

  In addition, data necessary for the calculation of equation (4) is also read from the Fn storage memory 11 and stored in the first buffer 15.

  The row processing circuit 14 performs the operation of the above-described expression (2), and the row processing circuit 14 outputs the row processing result Rmn after M (≦ L) cycles. The row processing result Rmn updated in this way is stored in the Rmn storage memory 19. The adding unit 16 adds the updated row processing result Rmn and the data Fn read from the Fn storage memory 11 whose timing is adjusted via the first buffer 15 (that is, the expression (4)). And the updated posterior log likelihood ratio Zn is stored in the Zn storage memory 17.

  The posterior log-likelihood ratio Zn and the row processing result Rmn stored in the Zn storage memory 17 and the Rmn storage memory 19 are delayed from the time of writing by the functions of the corresponding second buffer 18 and third buffer 20. This is output and used for the calculation of equation (1) by the subtracting unit 21.

The hard decision unit 22 stores the result of the hard decision on the posterior log likelihood ratio Zn in the hard decision data storage memory 24, and the parity decision unit 23 performs a parity check using the obtained hard decision data. The parity determination result is output to the decoding process control unit 12. The parity determination result is used as described with reference to FIG.

  In the decoder output interface unit 24, when the decoding end notification output as described above is given from the decoding processing control unit 12, the decoding result (decoded data) for the decoding block related to the decoding end notification. Is read from the hard decision data storage memory 24 and output.

  Although not explicitly shown in FIG. 1, information about which decoding block is associated with the decoded data may be given, and an output line from the decoder output interface unit 24 may be used for each decoding block. An output line may be provided and output to the corresponding output line.

Such a modification is the same for the decoder input interface unit 10.

  FIGS. 5B and 5C are timing charts showing decoding blocks and rows to be processed determined by the decoding processing control unit 12 for each cycle, and FIG. 5B is used for decoding processing. FIG. 5C shows the case where there are only two decoding blocks # 0 and # 2, and FIG. 5C shows that the decoding block # 0 is the decoding block # 0. The case where priority is higher than 2 is shown. For reference, FIG. 5A shows a case where the decoding block is only # 0 and the Wait cycle is fixed (see Non-Patent Document 2).

  FIG. 5 shows a case where the check matrix of the decoding block # 0 is shown in FIG. 4A, and the required cycle L of decoding processing for one row is 6 cycles.

  As shown in FIG. 5 (A), when the Wait cycle is fixed to the required cycle L (= 6) of the decoding process, a wait time of L (= 6) cycles is always required every 6 rows. A wait time of 6 × 3 = 18 cycles is generated for the decoding process.

  On the other hand, when the Wait cycle is obtained by calculation (therefore, the Wait cycle is variable), and when the Wait block elapses, the decoding block can be executed. In the case shown in B), the overall wait time (the number of wait cycles) can be reduced as compared to the case of FIG. 5A.

For example, a wait time of 6 cycles before the processing of the 7th row is performed, and a wait time before the processing of the 13th row and the 1st row is 3 cycles, which is 6 + 3 × 2 for one decoding process. As shown in FIG. 5A, the wait time can be shortened by 6 cycles.

  Furthermore, if processing is performed while scheduling a plurality of decoding blocks, the wait time in the decoding process of a certain decoding block can be allocated to the decoding process of another decoding block, and the processing unit that executes the decoding process Throughput can be improved. For example, as shown in FIG. 5C, the decoding process of the decoding block # 2 can be performed during the Wait time when the decoding process of the decoding block # 0 cannot be performed.

(A-3) Effect of Embodiment According to the above-described embodiment, the Wait time (Wait cycle) is set so that processing can be executed immediately when decoding processing can be performed on the processing target row according to the configuration of the check matrix. Therefore, it is possible to prevent a meaningless wait time such as waiting for the process even though the decoding process is possible, and the throughput of the decoding process can be improved.

  In addition, according to the above-described embodiment, the decoding process of a plurality of decoding blocks is adjusted by the scheduler so that they can be processed in parallel in a time-sharing manner. Also in this aspect, the throughput of the decoding process can be improved.

  Furthermore, according to the above embodiment, error detection is performed for each decoding iteration, and when the detection result is OK for a predetermined number of times, the decoding processing is terminated without repeating the decoding processing for the maximum number of iterations. As a result, the processing can be sent to processing of other decoding blocks by the amount corresponding to the reduction in the number of decoding processing, and the throughput of the decoding processing can be improved in this aspect as well.

(B) Other Embodiments In the above embodiment, the execution configuration of the decoding process is the one shown in FIG. 1, but the present invention provides a row (or a combination of a block and a row) for the decoding process. The determination method is not limited to that shown in FIG. 1. For example, a part of the configuration (for example, a storage memory) may be a multi-side configuration.

  In the above embodiment, the decoding information is input from the outside. However, a plurality of types of decoding information may be set in advance in the decoding processing control unit and selected.

  Furthermore, in the above-described embodiment, what is obtained by calculating the Wait cycle as shown in FIG. 4B each time is shown. However, as with the inspection information, it is input to the decoding processing control unit from the outside. Also good.

  In the above embodiment, an LDPC code decoding apparatus that can handle a plurality of decoding blocks has been described. However, the present invention can also be applied to an LDPC code decoding apparatus that can handle only one decoding block. In this case, the scheduler in FIG. 2 may be omitted.

  Further, in the above embodiment, the scheduler shows that the scheduler always determines the decoding block to be subjected to the decoding process according to the priority information unless it is in the Wait state. However, the priority of the selected decoding block is lowered by one step and the next cycle is decoded. The method for selecting between a plurality of decoded blocks, such as used for determining a block, is not limited to that in the above embodiment.

  Note that the row processing calculation unit may be capable of executing the calculation of the approximate expression (2). As an arithmetic configuration of such an approximate expression, for example, a document ““ Near optimal universal belief propagation based decoding of low-density parity check codes, ”IEEE Trans. Commun. , Vol. 50, pp. 406-414, Mar. 2002 ".

  DESCRIPTION OF SYMBOLS 1 ... LDPC code decoding apparatus, 12 ... Decoding process control part, 23 ... Parity determination part, 30-0-30- (B-1) ... Decoding information storage part, 31-0-31- (B-1) ... Decoding Process monitoring unit, 32... Scheduler, 33... Address generation unit.

Claims (6)

A decode processing means for executing decrypt processing,
Priority information holding means for holding priority information assigned to each decoding block , which is a cluster of data to be decoded by applying the same check matrix ;
Based on the priority information attached to a plurality of decoded blocks to be subjected to decoding processing, possess a processing decoded block determination means for determining a decoded block in which the decoding means is decoding,
A low-density parity check code decoding device, wherein a plurality of decoding blocks are decoded in parallel . The decoding processing means applies an algorithm for updating a decoding result for each row processing,
Each decoding block, which is determined from information of a check matrix for a low-density parity check code to be decoded, holds time information from which the target row can start processing after the row before the target row starts decoding processing Processing waiting information holding means for each,
It further comprises start instruction postponing means for each decoding block that waits at least for the time information held by the processing waiting information holding means and instructs the decoding processing means to start decoding processing of the target row. ,
The processing decoding block determining means determines a decoding block to be decoded by the decoding processing means based on priority information from among the decoding blocks sent out by the start instruction postponing means. Item 2. The low density parity check code decoding device according to Item 1. Each time the decoding processing unit repeats the decoding process, the parity check is performed on the row that has been processed, and the error-free continuous number measuring unit that measures the number of consecutive times that the parity check result is OK;
The low-density parity check code decoding apparatus according to claim 1, further comprising: an end instruction unit that ends the decoding process when the continuous number reaches a preset value. Decrypt processing means includes a priority information holding means and the processing decoding block decision unit,
The decoding processing means executes a decoding process,
The priority information holding means holds the priority information given to each decoding block , which is a cluster of data to be decoded by applying the same check matrix ,
The processing decoding block determining means determines a decoding block to be decoded by the decoding processing means based on priority information given to a plurality of decoding blocks to be subjected to decoding processing ,
A low-density parity check code decoding method, wherein decoding processing of a plurality of decoding blocks is executed in parallel . The decoding processing means applies an algorithm for updating a decoding result for each row processing,
Further comprising processing waiting information holding means for each decoding block and start instruction postponing means for each decoding block,
Each processing waiting information holding means can start processing of a target row after the row preceding the target row starts decoding processing, which is determined from the check matrix information for the low-density parity check code to be decoded. Keeps time information,
Each of the start instruction postponing means waits at least for the time information held by the corresponding processing waiting information holding means, and instructs the decoding processing means to start decoding processing of the target row,
The processing decoding block determining means determines a decoding block to be decoded by the decoding processing means based on priority information from among the decoding blocks sent out by the start instruction postponing means. Item 5. The low-density parity check code decoding method according to Item 4. It further has error-free continuous frequency measurement means and end instruction means,
The error-free continuous number of times measurement means performs a parity check on the row processed each time the decoding processing means repeats the decoding process, and measures the number of times that the parity check result is OK,
The low-density parity check code decoding method according to claim 4 or 5, wherein the termination instruction means terminates the decoding process when the number of consecutive times reaches a preset value.

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