JP4788004B2 - Information processing apparatus, PCI bus control method, and PCI bus control program - Google Patents

Description

  The present invention relates to an information processing apparatus including a PCI bus, and in particular, an information processing apparatus, a PCI bus control method, and a method for improving the efficiency of connection between a plurality of peripheral devices (PCI devices) having different operation clock frequencies and the PCI bus, And a PCI bus control program.

With the improvement in performance of information processing apparatuses such as personal computers, there is an increasing demand for connecting various peripheral devices (devices) to the information processing apparatus. For this reason, the information processing apparatus is provided with a transfer circuit (referred to as a “bus”) for data input / output that can be commonly used by a plurality of peripheral devices.
In this case, when connecting peripheral devices having the same operation clock frequency, they may be connected to the same bus (for example, ISA bus, PCI bus, etc.), but in order to connect a plurality of peripheral devices having different operation clock frequencies. Required a plurality of “buses” corresponding to the operating clock frequency.

Here, as a specific example, a configuration including a plurality of buses for a PCI (Peripheral Component Interconnect) bus, which is a typical example of a bus provided in a conventional information processing apparatus, will be described (see FIG. 7).
As shown in FIG. 7, in this specific example, a processor 110 and a system bus 120 connected to the processor 110, a PCI host bridge 130 for connecting the system bus 120 and the PCI bus (A) 140, and a PCI-PCI. The bridge 150 is connected under the PCI bus A140, and the PCI bus (B) 160 is provided.

  In the configuration shown in FIG. 7, when operating peripheral devices (hereinafter referred to as “PCI devices”) 170 and 180 that operate at different PCI clocks, the PCI bus A 140 is 66, for example. A method is adopted in which PCI devices having different PCI clocks such as 66 [MHz] and 33 [MHz] are operated by using the PCI bus B 160 for 33 [MHz] for [MHz].

  In addition, a configuration in which a plurality of PCI buses operating with different clocks are provided, and these PCI buses are connected to and switched to the system bus via a single PCI host bridge, eliminating the need for a PCI-PCI bridge (patented) Document 1) or a method in which two PCI buses having different clock frequencies are provided via a bus switch in a slot for connecting a PCI device, and each PCI bus is connected to and switched to a system bus via a single PCI host bridge. (Patent Document 2) is conventionally known.

JP 2000-082035 A JP 2001-043179 A

  However, in the example shown in FIG. 7 described above, it is necessary to always mount the PCI-PCI bridge 150. Further, the bridge circuit 150 has a disadvantage that the cost is high because the circuit configuration is complicated. Further, in the example of FIG. 7, since two PCI buses are required, there is a disadvantage that the circuit scale becomes large.

In addition, the contents disclosed in Patent Documents 1 and 2 are the same in that a plurality of PCI buses are prepared, so that the circuit scale increases due to a bus control circuit, a bus switch, and the like. I had a problem.
As described above, in the conventional method, when PCI devices having different operation clocks are connected to and mounted on the PCI bus of the information processing apparatus, a plurality of PCI buses are required even if the PCI-PCI bridge is not used. Met. For this reason, a bus control circuit and a bus switch are required for each PCI bus, so that the circuit scale has always been increased.

(Object of invention)
In view of the above problems, the present invention has an object to provide an information processing apparatus, a PCI bus control method, and a PCI bus control program that configure a PCI bus in a minimum unit and simplify the system configuration. And

In order to achieve the above object, an information processing apparatus according to the present invention includes a system bus to which a processor and a memory are connected, and a PCI bus connected to the system bus via a PCI host bridge. At least two PCI devices having different frequencies connected to the bus, and a PCI which is provided in the PCI host bridge and outputs a bus clock having a frequency corresponding to each PCI device as an operation clock for the PCI bus And a frequency control means for determining whether the operating clock output from the PCI clock control unit has a frequency corresponding to one of the PCI devices or the other PCI device . Further, between the PCI host bridge described above and each of the PCI devices, the bus on the side of the PCI device that is determined not to correspond to the operation clock by the frequency determination means in the PCI device according to an external command. A request signal masking means for masking the request signal is provided. The processor controls the PCI clock to output a bus clock having a frequency corresponding to the PCI device when a bus use request signal is output to the PCI device masked by the request signal masking unit. It has a corresponding bus clock output command function for commanding the unit.

In order to achieve the above object, a PCI bus control method according to the present invention includes a system bus to which a processor and a memory are connected , and a PCI bus connected to the system bus via a PCI host bridge. At least two PCI devices having different frequencies connected to the bus, and a PCI clock control unit that is provided in the PCI host bridge and outputs a bus clock having a frequency corresponding to each PCI device as an operation clock for the PCI bus. The frequency determination processing means provided in advance determines whether the operation clock output from the PCI clock control unit has a frequency corresponding to one or the other PCI device. Between the PCI host bridge and each PCI device. A request signal masking step in which a request signal masking means provided in advance masks a bus use request signal for a PCI device which is determined not to correspond to the operation clock in the frequency determination step among the PCI devices according to the command; When a bus use request signal for the PCI device masked in the request signal mask processing step is output, a bus clock output of a processor provided in advance is output so that a bus clock having a frequency corresponding to the PCI device is output. And a clock switching step in which the command function commands the PCI clock control unit .

In order to achieve the above object, a PCI bus control program according to the present invention includes a system bus to which a processor and a memory are connected , and a PCI bus connected to the system bus via a PCI host bridge. At least two PCI devices having different frequencies connected to the bus, and a PCI clock control unit that is provided in the PCI host bridge and outputs a bus clock having a frequency corresponding to each PCI device as an operation clock for the PCI bus. And determining whether the operating clock output from the PCI clock control unit has a frequency corresponding to one of the PCI devices or the other PCI device. Frequency judgment function, PCI host bridge and each PCI device In addition, a request signal mask function that masks a bus use request signal applied to a PCI device that is determined not to support an operation clock by a frequency determination function among PCI devices according to an external command, and a request signal mask processing function A clock switching function that instructs the PCI clock controller to output a bus clock having a frequency corresponding to the PCI device when a bus use request signal is output to the PCI device masked with Features.

  Since the present invention is configured as described above and PCI devices having different operation clocks on the same PCI bus can be connected and controlled to be switched, the system configuration is greatly simplified, and the PCI bus clock frequency is set to the operation clock at the same time. Since the request signal masking means selectively masks the bus use request signal when the bus use request signal is output from another PCI device that is not set to the frequency, the burden on the processor is greatly reduced. It is possible to provide an unprecedented excellent information processing apparatus, PCI bus control method, and PCI bus control program that can perform information processing of the entire system even more quickly.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
Here, in the present embodiment, the basic configuration of the information processing apparatus will be described first, and then the specific contents will be described sequentially.

First, FIG. 1 shows a block diagram of an information processing apparatus according to the present embodiment. In FIG. 1, the information processing apparatus includes a system bus 20 to which a processor 10 and a memory 15 are connected, and a PCI bus 60 connected to the system bus 20 via a PCI host bridge 30. The PCI bus 60 is connected to at least two PCI devices 70 and 80 having different frequencies and the other.
Here, in the present embodiment, one PCI device 70 has a function that operates at 33 [MHz], and the other PCI device 80 has a function that operates at 66 [MHz].

The PCI host bridge 30 is equipped with a PCI clock control unit 35 that outputs a bus clock having a frequency of 33 [MHz] or 66 [MHz] corresponding to each of the PCI devices 70 and 80 described above as an operation clock for the PCI bus. ing.
In addition to the PCI bus 60, a bus use request signal for one of the PCI devices 70 and 80 is sent between the PCI host bridge 30 and the PCI devices 70 and 80 in response to an external command. A REQ mask part (request signal masking means) 50 for masking is interposed.

  In the present embodiment, the frequency determination means for determining whether the operation clock output from the PCI clock control unit 35 is a frequency corresponding to the PCI device 70 or 80 of the one or the other. 11 is attached to the system bus 20. Here, the frequency determination unit 11 may be configured to be realized by, for example, the processor 10 executing the frequency determination program 15A stored in advance in the memory 15 described above.

Here, the REQ mask unit (request signal mask means) 50 receives the bus use request signals from 70 and 80 from one or the other PCI device described above, and operates on the PCI bus 60 by the frequency determination means 11. For example, when it is determined that the clock frequency is a frequency corresponding to one PCI device 70 (or 80), a bus use request signal from the other PCI device 80 (or 70) is selected based on the determination result. A selective masking function is provided for masking.
When the clock frequency of the PCI bus is switched, the bus use request signal REQ # _IN from the PCI device to be masked passes without being masked until now by the command “MASK REQ” from the processor 10. It has the function of being switched to the signal that has been made.

  Further, in the present embodiment, when a bus use request signal is output from the other PCI device 80 (or 70) masked by the REQ mask unit 50, a REQ for holding and setting the bus use request signal is set. A monitoring unit (monitoring means) 40 is provided. That is, the system bus 20 includes a REQ monitoring unit (monitoring unit) 40 that monitors whether or not the bus use request signals are transmitted from the two PCI devices 70 and 80 and transmits the monitoring information to the processor 10. It is attached.

Further, the processor 10 described above determines whether or not the bus use request signal held in the REQ monitoring unit (monitoring means) 40 is the same signal as the bus use request signal applied to the one PCI device. A switching command transmission function 10a for transmitting a frequency switching command to the PCI clock control unit 35 described above when it is determined that the bus use request signal is held is provided.
The PCI clock control unit 35 operates based on a command from the processor 10 and sets the frequency of the operation clock in the PCI bus 60 to the clock frequency corresponding to the other PCI device 80 (or 70) related to the bus use request signal. A clock switching control function 35a for switching to is provided.

Here, a specific example of the above-described REQ mask section (request signal mask means) 50 will be described.
As shown in FIG. 1, a REQ mask circuit 50A for the PCI device 70 and a REQ mask circuit 50B for the PCI device 80 are provided. Both the REQ mask circuits 50A and 50B are composed of the same constituent members.
As will be described later, the REQ mask circuits 50A and 50B are each constituted by the logic of a D-type flip-flop 54 and a logical OR circuit 52, and individually and quickly respond to the bus use request signal from each PCI device 70 or 80. In other words, each PCI device described above has one circuit (see FIG. 3).

  The REQ monitoring unit (monitoring means) 40 has a function of latching the masked bus use request signal and a memory (REQ monitoring table) 45 for holding the latched use request signal. The processor 10 is configured to periodically fetch the stored contents from the memory 45 in accordance with its own operation timing.

Hereinafter, this will be described in more detail.
The PCI bus 60 described above is a bus that allows PCI signals conforming to the PCI bus specification for connecting and mounting PCI devices 70 and 80 having different operation clock frequencies.
The PCI host bridge 30 has a function of performing information transfer between the system bus 20 and the PCI bus 60 and bus control of the PCI bus 60. The bus control for the PCI bus 60 performs contention control (arbitration) of the bus use request signal REQ # _OUT from the PCI device 70 or 80, which is an output signal from the REQ mask unit 50, and avoids the collision. This control is executed in accordance with the PCI bus specification.

  Here, a bus use request signal from a PCI device having an operation clock different from the bus clock frequency in operation is masked in the REQ mask unit 50 and is not output to the PCI host bridge 30 as will be described later. . Therefore, the contention control in this case is between PCI devices having the same operation clock frequency.

  The PCI clock control unit 35 supplies and switches two bus clocks (for example, 33 [MHz] and 66 [MHz]) supplied to the PCI bus 60 as described above. The bus clock switching control is based on a command from the processor 10. The trigger for the switching control is the bus clock frequency currently being operated by monitoring the REQ monitoring table 45 provided in the REQ monitoring unit 40 by the processor 10. This is a case where a bus use request signal is issued from a PCI device having a different operation clock frequency.

The REQ monitoring unit 40 latches the state of each use request signal (REQ # 1 signal, REQ # 2 signal) of the PCI devices 70 and 80, and stores the state as a REQ monitoring table 45 on a storage circuit included in the REQ monitoring unit 40. And hold.
The REQ monitoring table 45 is configured to be monitored from the processor 10. That is, the processor 10 cooperates with the monitoring program on the memory 15 to send a bus use request signal from a PCI device masked by the REQ mask unit 50 in the REQ monitoring table 45 and prohibited from using the bus. A state is detected, and a bus clock switching command is sent to the PCI clock control unit 35 when it becomes valid.

The REQ mask unit 50 receives only a bus use request signal from the PCI device 70 or 80 having the same operation clock as the PCI bus clock frequency in operation, and outputs it to the PCI host bridge 30 according to a command from the processor 10. The bus use request signal from the PCI device of the operation clock is configured to be masked.
Then, when the clock frequency of the PCI bus is switched, the bus use request signal REQ # _IN from the PCI device to be masked has been passed without being masked until now according to a command from the processor 10. It has a function that can be switched to.

  Next, prior to description of a specific configuration and operation of the REQ mask unit 50, basic operation contents of the bus control of the PCI bus 60 in the present embodiment (details will be described later).

  As shown in FIG. 2, first, the processor 10 determines the clock frequency of the PCI bus 60 that is currently operating (frequency determination step: first step). Next, the REQ mask unit 50 receives the information on the clock frequency being operated from the processor 10, and the bus use request from the PCI device (for example, the PCI device 70) operating at the current clock frequency of the PCI bus 60 is the PCI. The PCI host bridge 30 selectively transmits a bus use request signal from another PCI device (for example, PCI device 80) which is sent to the host bridge 30 and does not use the currently operating PCI bus clock frequency as the operating clock frequency. 30 is not sent out (request signal masking process: second step).

  Subsequently, the bus use request signal selectively masked by the cooperation of the processor 10 and the REQ monitoring table 45 of the REQ monitoring unit 40 is monitored (monitoring step: third step). When the activation of the bus use request signal in the monitoring process is detected, that is, the bus use request signal held in the REQ monitoring unit 40 is the bus use request signal related to the operation clock frequency in the PCI bus 60. If it is determined that the signals are different (request signal activation detection step: fourth step), a clock switching command is issued from the processor 10 based on the bus use request signal, and the PCI clock control unit In 35, the PCI bus clock frequency is switched (clock switching step: fifth step).

  By this clock switching, as described above, the processor 10 that has determined the clock frequency in the frequency determination step sends the clock frequency information to the REQ mask unit 50 and sets the REQ mask unit 50 to mask the PCI device opposite to the current one. Since the operation is performed, the PCI device that has been restrained from using the bus until now obtains the right to use the bus, and the PCI device that has the right to use the bus switches so that the use of the bus can be restrained.

Here, the basic control operation contents related to the bus control of the PCI bus 60 described above may be programmed and executed by the processor 10 described above.
The program of the content of the control operation relating to the bus control of the PCI bus 60 may be specified in the following form, for example.

  That is, the frequency determination function for determining which PCI device 70 or 80 is the frequency of the PCI bus operation clock output from the PCI host bridge 30 to the PCI bus 60. When a bus use request signal is output from another PCI device 80 or 70 that does not use the bus clock frequency of the PCI bus 60 as an operation clock frequency, the REQ mask unit 50 equipped with the bus use request signal in advance is selectively used. Request signal holding that allows masking and allows the monitoring means 40 provided in advance in the system bus 20 to capture and hold the bus use request signal for the other PCI device 80 or 70 that has been masked. The bus use request signal held by the permissible function and the monitoring means 40 is A request signal determination function for determining whether or not the signal is different from the bus use request signal related to the operation clock frequency in the CI bus 60, and the bus use request signal held in the monitoring means 40 is an operation in the PCI bus 60. The processor 10 described above has a switching command transmission function that issues a PCI bus operation clock switching command to the PCI host bridge 30 when it is determined that the signal is different from the bus use request signal related to the clock frequency. Program it to run.

Next, a specific example of the configuration of the REQ mask unit 50 will be described in detail with reference to FIGS. 1 and 3 described above.
As shown in FIG. 1, the REQ mask unit 50 includes two REQ mask circuits 50A and 50B corresponding to the above-described one and other two PCI devices 70 and 80, respectively.
Here, FIG. 1 illustrates the case where the REQ mask unit 50 includes two REQ mask circuits 50A and 50B. However, when there are three or more PCI devices, the REQ mask circuits corresponding to the number of the REQ mask circuits 50A and 50B are provided. It is prepared for.
As shown in FIG. 3A, one REQ mask circuit 50A corresponding to one PCI device 70 described above is configured to include a D-type flip-flop 54 and the logic of an OR circuit 52 that is a logical sum. Yes. The other REQ mask circuit 50B is similarly configured.

  FIGS. 3B and 3C show a truth table of the D-type flip-flop 54 and a truth table of the OR circuit 52 in order to clarify the operation of the REQ mask unit 50A (or 50B). .

Here, the control signals related to the REQ mask unit 50 will be described in detail.
First, as an input signal to the OR circuit 52, there is a bus use request signal REQ # _IN from the PCI device. As input signals to the D-type flip-flop 54, there are a mask request signal signal MASK_REQ from the processor 10 and a PCI bus clock signal PCICLK_IN.

  Further, the output signal from the REQ mask unit 50 includes REQ # _OUT as a bus use request signal to the PCI host bridge 30, and the OR signal 52 is output from the output terminal D of the D-type flip-flop 54. As an input signal, there is an internal signal MASK_EN. This internal signal MASK_EN is a control signal for controlling the validity / invalidity of the mask. When this signal is valid, the use request signal “REQ # _OUT” to the PCI host bridge 30 is not valid.

  A signal with # in the signal display here indicates negative logic, and indicates that it is valid when the signal is “0” and invalid when it is “1”. A signal without # indicates positive logic, indicating that it is invalid when the signal is “0” and valid when it is “1”.

Hereinafter, the overall operation of the REQ mask circuit 50A of the REQ mask unit 50 will be described with reference to FIGS.
Here, FIG. 4 shows a timing chart of signal control of the REQ mask circuit 50A. As shown in FIG. 4, the signal control of the REQ mask circuit 50A will be described in the order of mask operation timing, mask operation state, and mask release timing.

<Mask operation timing>
At timing 4-1 (mask timing) in FIG. 4, the signal REQ # _OUT, which is the output signal of the REQ mask circuit 50A, is “1”, and this signal REQ # _OUT is applied to the terminal EN of the flip-flop 54. As added, the flip-flop 54 is enabled.

  For this reason, when the mask request signal MASK_REQ from the processor 10 becomes valid by the input signal to the input terminal D of the flip-flop 54, the internal signal MASK_EN which is a signal from the output terminal Q of the flip-flop 54 becomes valid. Whether the bus use request signal REQ # _IN from the PCI device 70 input to the logical OR circuit 52 is “0” or “1”, the output signal from the output terminal X of the logical OR circuit 52 The mask is applied and becomes “1”.

<Mask operation state>
Since the internal signal MASK_EN is valid at the timing 4-2 (mask state) in the figure, the bus use request signal REQ # _IN from the PCI device 70 input to the OR circuit 52 becomes valid. However, since the signal REQ # _OUT that is the output signal of the REQ mask circuit 50A is not valid, the bus use request signal REQ # _IN is in a masked state.

<Mask release timing>
At 4-3 (mask release timing) in the figure, the mask request signal MASK_REQ from the processor 10 becomes invalid, and the internal signal MASK_EN becomes invalid. Therefore, the valid state of the bus use request signal REQ # _IN from the PCI device 70 input to the OR circuit 52 is output from the output signal REQ # _OUT of the REQ mask circuit 50A, and the mask state is changed. Canceled.

<Unmasking>
At timing 4-4 (during mask release) in the figure, since the internal signal MASK_EN is invalid, this state is changed together with the state change of the bus use request signal REQ # _IN from the PCI device 70 input to the OR circuit 52. The output signal REQ # _OUT of the REQ mask circuit 50A also changes. That is, the bus use request signal REQ # _IN is reflected in the output signal REQ # _OUT without being masked.

Next, the operation of the mask request signal MASK_REQ from the processor 10 described above that is executed when the bus use request signal REQ # from the PCI device 70 is valid will be described with reference to FIG.
Before the timing 5-1 in FIG. 5, since the mask is released, the use request signal REQ # _IN from the PCI device and the output signal REQ # _OUT from the REQ mask circuit 50A both change, and FIG. 5-1 is a state in which the use request signal REQ # _IN from the PCI device and the output signal REQ # _OUT of the REQ mask circuit 50A are both valid. At this time, the operation when the mask request signal MASK_REQ from the processor 10 becomes valid is as follows.

When the output signal REQ # _OUT of the REQ mask circuit 50A is valid, that is, is “0” because it is negative logic, the terminal EN of the flip-flop 54 becomes “0”, and the operation of the flip-flop 54 is invalid. It is in a state. For this reason, even if the mask request signal MASK_REQ from the processor 10 becomes valid, the internal signal MASK_EN does not become valid.
Therefore, the bus use request signal REQ # _IN is not masked and becomes the output signal REQ # _OUT of the REQ mask circuit 50A.

Thereafter, when the bus use request signal REQ # _IN becomes invalid, that is, “1” at the timing 5-2 in FIG. 5, the terminal EN of the flip-flop 54 becomes valid, and the flip-flop 54 becomes operable. . As a result, the mask signal MASK_REQ from the processor 10 becomes valid, and the internal signal MASK_EN becomes valid.
Therefore, the bus use request signal REQ # _IN is masked.

By using the REQ mask circuit 50A that operates as described above, even when the bus use request signal REQ # is valid, a malfunction in the mask operation can be avoided and the bus clock frequency can be switched appropriately.
These operations are similarly performed when the bus use request signal REQ # from the PCI device 80 is input to the REQ mask circuit 50B.

(Description of bus control operation)
Next, a PCI bus control operation of the information processing apparatus, particularly, an operation when PCI devices having different operation clock frequencies are connected (mounted) on the same PCI bus will be described.

Prior to the description of this operation, the basic operation of a PCI device on a general PCI clock having a single clock frequency will be described.
For example, in the case of the well-known example shown in FIG. 7 described above, when the PCI device 170 operates as a master (also referred to as “initiator”) having the initiative of information transfer operation, the PCI device 170 transmits a use request signal (REQ #). First, a use request (request) for the PCI bus A 140 is made to the PCI host bridge 130. Next, when receiving a valid use request signal, the PCI host bridge 130 grants the PCI device 170 permission to use the PCI bus A 140 based on the use permission signal (GNT #). Accordingly, the PCI device 170 that has obtained permission to use the PCI bus A140 can start access using the PCI bus A140.

In the case of the information processing apparatus according to the present embodiment (see FIG. 1), in addition to the operation of FIG. 7 described above, the bus clock frequency of the PCI bus 60 and the operable clock frequency of the PCI devices 70 and 80 are matched. It has configuration and operation.
The specific contents will be described below with reference to FIG.

  Here, as a specific example, regarding the switching control operation when the PCI device 70 (33 [MHz] operating device) becomes the master, the PCI bus clock frequency at that time is 33 [MHz] and 66 [MHz]. This will be explained separately for each case.

<When the clock frequency of the PCI bus 60 is 33 [MHz]>
The current PCI bus clock frequency is determined by the processor 10 (step S100, frequency determination step). If the PCI bus clock frequency is 33 [MHz], the REQ mask unit 50 determines that the frequency of the PCI bus clock frequency is 33 according to the instruction of the processor 10. The use request signal (REQ # _1) from the PCI device 70 of [MHz] is released from the mask, and the use request signal (REQ # _2) from the PCI device 80 of 66 [MHz] is put into a masked state (step S102, Request signal mask process).

As a result, access from the PCI device 70 at 33 [MHz] is permitted, and access from the PCI device 80 at 66 [MHz] is not permitted.
In this case, since the use request signal (REQ # _1) from the PCI device 70 has been unmasked, the PCI host bridge 30 is notified. Therefore, the PCI device 70 can access the PCI bus 60 according to a normal PCI procedure without any problem.

<When the clock frequency of the PCI bus 60 is 66 [MHz]>
The PCI bus clock frequency is determined by the processor 10 (step S100, frequency determination step). As a result, when the PCI bus clock frequency is 66 [MHz], the REQ mask unit 50 is set to 33 [ The use request signal REQ # _1 from the PCI device 70 of [MHz] is put into a masked state, and the use request signal REQ # _2 from the PCI device 80 of 66 [MHz] is unmasked (step S202, request signal mask process). .

  This is because since the PCI bus clock frequency is 66 [MHz], only the PCI device 80 of 66 [MHz] can be granted access permission. In this state, since the use request signal REQ # _1 from the PCI device 70 is masked by the REQ mask unit 50, it is not notified to the PCI host bridge, and the 33 [MHz] PCI device 70 remains unchanged. Will not be able to receive access permission for the PCI bus 60 forever.

  In order to avoid this, the REQ monitoring unit 40 monitors the state of the use request signal (REQ # _1). That is, the processor 10 monitors the REQ monitoring table provided in the REQ monitoring unit 40, and when the column of the use request signal REQ # _1 in the table becomes “0”, the use request signal REQ that has been in the masked state. It is determined that # _1 has become valid (step S203, monitoring process).

  When determining this state, the processor 10 controls the PCI clock control unit 35 to change the PCI bus clock frequency to 33 [MHz], which is the clock frequency of the PCI device 70 sending the use request signal REQ # _1. (Step S204, clock switching step).

Next, the processor 10 determines the PCI bus clock frequency of this change, and determines the frequency as 33 [MHz] (step S100, frequency determination step).
Then, the processor 10 controls the REQ mask unit 50 to cancel the masking of the use request signal REQ # _1 from the 33 [MHz] PCI device 70 and to use the 66 [MHz] PCI device 80. The signal REQ # _2 is set to a mask state (step S102, request signal mask process). As a result, the state of the use request signal REQ # _1 is notified from the PCI device 70 to the PCI host bridge 30, and access is possible according to a normal PCI procedure.

  In the REQ monitoring unit 40, the state of the use request signal REQ # _2 from the PCI device 80 of 66 [MHz] is latched and stored in the REQ monitoring table. The processor 10 continues to monitor the column of the use request signal REQ # _2 in this table (step S103, monitoring process).

  The above processing is the same when the use of the PCI bus 60 is requested from the PCI device 80 of 66 [MHz], and operates according to the flowchart shown in FIG.

When the PCI host bridge 30 operates as a master, the processor 10 knows the PCI device to be accessed from now on, so that the operation clock frequency of the PCI device is also known. Since it can be accessed after changing to the frequency, there is no particular inconvenience.
Here, each operation content of the bus control in the PCI bus 60 described above may be configured to be programmed and executed by the processor 10 described above.

  For convenience of explanation, the description has been made on the assumption that there are two PCI devices having different operation clock frequencies. However, the circuit of FIG. 2 which is a constituent unit of the REQ mask unit 50 is provided by the number of PCI devices (REQ mask). Further, two or more PCI devices having different speeds are controlled by increasing the number of bus use request signals from the PCI devices that are latched by the REQ monitoring unit 40 and stored in the monitoring cable. It is also possible.

  As described above, according to the information processing apparatus according to the present embodiment, it is possible to connect and mount PCI devices having different operation clock frequencies on a single PCI bus by including a mask unit and a monitoring unit with a simple circuit configuration. Therefore, even when equipped with a plurality of PCI devices, they can be arranged in parallel on a single PCI bus without using a plurality of PCI buses, which simplifies the system configuration and makes it economical. There is an unprecedented advantage that flexibility and convenience in use can be improved.

  The present invention can be applied to all information processing apparatuses that require a plurality of buses equivalent to the PCI bus connected to the system bus, and is a versatile invention.

It is a block diagram which shows the information processing apparatus which concerns on one Embodiment of this invention. 3 is a flowchart illustrating a PCI bus control operation according to the information processing apparatus disclosed in FIG. 1. FIG. 3A is a diagram illustrating an example of a REQ mask unit according to the information processing apparatus disclosed in FIG. 1. FIG. 3A illustrates a mask circuit that constitutes a part of the REQ mask unit, and FIGS. A truth table of a D flip-flop and a truth table of an OR circuit for clarifying the operation of the REQ mask circuit are shown. 3 is a timing chart illustrating a signal control state of a REQ mask unit according to the information processing apparatus disclosed in FIG. 1. 6 is a timing chart of signal control (when REQ # _IN is valid) of a REQ mask unit according to the information processing apparatus disclosed in FIG. 1; 3 is a flowchart showing a bus clock frequency switching operation in the information processing apparatus disclosed in FIG. 1. It is a block diagram which shows the example of 1 structure of the information processing apparatus in a known example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Processor 10a Switching command transmission function 11 Frequency determination means 15 Memory 15A Frequency determination program 15B Monitoring program 20 System bus 30 PCI host bridge 35 PCI clock control part 35a Clock switching function 40 REQ monitoring part (monitoring means)
45 REQ monitoring table 50 REQ mask section (request signal mask means)
52 OR circuit (logical OR)
54 D-type flip-flop 60 PCI bus 70 PCI device (for 33 [MHz] clock)
80 PCI devices (for 66 [MHz] clock)

Claims (6)

A system bus to which a processor and a memory are connected, and a PCI bus connected to the system bus via a PCI host bridge;
At least two PCI devices having different frequencies connected to the PCI bus and the other PCI devices, and a bus clock having a frequency corresponding to each PCI device provided in the PCI host bridge are output as operation clocks for the PCI bus. In an information processing apparatus comprising a PCI clock control unit
A frequency determination means for determining whether the operation clock output from the PCI clock control unit is a frequency corresponding to the one or the other PCI device;
Between the PCI host bridge and each PCI device, the bus used by the PCI device which is determined not to correspond to the operation clock by the frequency determination means among the PCI devices according to an external command While interposing a request signal masking means for masking the request signal,
The processor outputs a bus clock having a frequency corresponding to the PCI device to the PCI clock control unit when a bus use request signal applied to the PCI device masked by the request signal masking unit is output. An information processing apparatus having a corresponding bus clock output command function for commanding. The information processing apparatus according to claim 1 ,
The request signal masking means is a bus use request from the other PCI device based on the determination signal when the frequency determination means determines that the operation clock has a frequency corresponding to the one PCI device. A selective mask function for selectively masking signals is provided.
When a bus use request signal is output from the other PCI device masked by the request signal masking means, a monitoring means is provided for holding and setting the monitoring use state.
The processor determines whether or not the bus use request signal held in the monitoring unit is the same signal as the bus use request signal applied to the one PCI device, and different bus use request signals are held. A switching command transmission function for transmitting a frequency switching command to the PCI clock control unit when it is determined,
The PCI clock control unit has a clock switching control function that operates based on a command from the processor and switches a frequency of an operation clock in the PCI bus to a clock frequency corresponding to another PCI device related to the bus use request signal. An information processing apparatus characterized by In the information processing apparatus according to claim 1 or 2,
The request signal masking means constitutes one circuit by a D-type flip-flop and a logical OR logic, and has one circuit for each PCI device corresponding to the bus use request signal from each PCI device. An information processing apparatus characterized by that. In the information processing apparatus according to claim 1 or 2,
An information processing apparatus characterized in that the monitoring means includes a circuit that latches a bus use request signal masked by the request signal mask means and a memory that holds the bus use request signal. A system bus to which a processor and a memory are connected, and a PCI bus connected to the system bus via a PCI host bridge;
At least two PCI devices having different frequencies connected to the PCI bus and the other PCI devices, and a bus clock having a frequency corresponding to each PCI device provided in the PCI host bridge are output as operation clocks for the PCI bus. An information processing apparatus comprising a PCI clock control unit,
A frequency determination step in which a frequency determination processing unit provided in advance determines whether the operation clock output from the PCI clock control unit has a frequency corresponding to one of the PCI devices or the other PCI device;
Between the PCI host bridge and each PCI device, the bus used by the PCI device which is determined not to correspond to the operation clock in the frequency determination step among the PCI devices according to an external command A request signal masking step in which a request signal mask means provided in advance masks the request signal;
Corresponding bus of the processor provided in advance so as to output a bus clock having a frequency corresponding to the PCI device when a bus use request signal related to the PCI device masked in the request signal masking process is output. A clock switching step in which a clock output command function commands the PCI clock control unit;
A PCI bus control method comprising: A system bus to which a processor and a memory are connected, and a PCI bus connected to the system bus via a PCI host bridge;
At least two PCI devices having different frequencies connected to the PCI bus and the other PCI devices, and a bus clock having a frequency corresponding to each PCI device provided in the PCI host bridge are output as operation clocks for the PCI bus. An information processing apparatus comprising a PCI clock control unit,
In the computer provided in the information processing apparatus,
A frequency determination function for determining whether the operation clock output from the PCI clock control unit has a frequency corresponding to the PCI device of the one or the other;
Between the PCI host bridge and each PCI device, a bus is applied to a PCI device that is determined not to support the operation clock by the frequency determination processing function among the PCI devices according to an external command. A request signal mask function for masking the use request signal;
A clock for instructing the PCI clock controller to output a bus clock having a frequency corresponding to the PCI device when a bus use request signal is output to the PCI device masked by the request signal mask processing function. Switching function and
A PCI bus control program characterized in that is executed.

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