JP4771303B2 - Integrated circuit for motor drive - Google Patents

Description

  The present invention relates to an integrated circuit for driving a motor.

  A motor drive circuit that controls the drive of the motor includes an output transistor that supplies current to the coil, and a control circuit that controls the operation of each output transistor. In addition, as an output transistor, an output transistor on the power source side (hereinafter referred to as a source side transistor) that discharges current to a motor driving coil, and a ground side output transistor (hereinafter referred to as a sink side transistor) that sucks current from the driving coil have.

For example, in the case of a motor drive circuit of a brushless motor of single-phase full-wave drive, it has an output transistor that constitutes an H-bridge and a control circuit that controls the operation of each output transistor.
FIG. 5 is a diagram for explaining a case where the output is an H-bridge.

  At one end of the drive coil L (hereinafter referred to as X point), a PNP type bipolar transistor (hereinafter referred to as PNP transistor) T1 which is a source side transistor and an NPN type bipolar transistor (hereinafter referred to as NPN transistor) which is a sink side transistor T4 is connected. The other end (hereinafter referred to as Y point) of the drive coil L is connected to a PNP transistor T2 that is a source side transistor and an NPN transistor T4 that is a sink side transistor.

  Note that an NPN transistor can be used as the source-side transistor, but in this case, the source-side transistor cannot be turned on with a control voltage equal to or lower than the power supply voltage VCC. Therefore, it is necessary to generate a control voltage higher than the power supply voltage VCC by providing a booster circuit or the like.

The control circuit 500 controls on / off of the PNP transistor T1, the PNP transistor T2, the NPN transistor T3, and the NPN transistor T4.
When the PNP transistor T1 and the NPN transistor T4 are turned on according to the instruction from the control circuit 500, the path of the power supply voltage VCC → PNP transistor T1 → drive coil L → NPN transistor T4 → ground GND shown by the solid line in FIG. Current flows. On the other hand, when the PNP transistor T2 and the NPN transistor T4 are turned on, the current in the path of the power supply voltage VCC → PNP transistor T2 → drive coil L → NPN transistor T3 → ground GND flows. In this way, the motor is driven by controlling the on / off of the source side transistor and the sink side transistor to switch the current flowing through the drive coil L.

  It is also possible to use MOSFETs as the source side transistor and the sink side transistor.

  As one of motor driving methods, PWM control (Pulse Width Modulation) is known. In the PWM control, for example, when the PNP transistor T1 and the NPN transistor T4 are turned on in FIG. 5 and the current in the solid line flows, the PNP transistor T1 is intermittently turned on while the NPN transistor T4 is on. . At this time, when the PNP transistor T1 is turned off, the drive coil L tries to continue the current flow in the same direction, so that the drive coil L → NPN transistor T4 → ground GND → regenerative diode D3 → drive coil shown by the broken line in FIG. The regenerative current of the L path flows.

  Similarly, the PNP transistor T2 is intermittently turned on while the NPN transistor T3 is on. In this case, a regenerative current in the direction opposite to the broken line flows.

  Thus, in the PWM control, the current flowing through the drive coil L can be controlled by the on / off duty of the source-side transistor during the period when the sink-side transistor is on.

As described above, the source-side transistor and the sink-side transistor can be integrated on a chip, for example.
JP 2001-16086 A

  An integrated circuit for driving a motor (hereinafter referred to as an IC) and external components are mounted on the same substrate. However, the area of the mounting base is also decreasing with the miniaturization of the motor. For example, in the case of a small fan motor, an IC or an external component must be mounted on a small-sized donut-type substrate.

  FIG. 4 is a diagram for explaining a donut-type substrate used for a fan motor. A donut-shaped substrate 404 having a diameter of 40 mm, for example, is provided around the rotation axis of the fan 402. The IC for driving the motor and the external parts are mounted on the donut-type substrate 404. Therefore, when mounting on such a small substrate, it is required that the number of components is small and the package size is small.

  Further, since there is a possibility that the IC is destroyed by heat generated by the current flowing through the output transistor, it is required that the heat generated in the IC is small.

  Furthermore, in order to increase the drive capability of the motor, the output transistor connected to the drive coil has low saturation voltage (low on-resistance) characteristics that do not reduce the voltage applied to the drive coil, and is low in cost. Is required.

  Here, in the case where an H-bridge motor drive circuit is integrated, if four output transistors are built in the IC, the number of parts is reduced, but the amount of heat generated in the IC is increased. Further, since the performance of the built-in output transistor is limited, the driving capability of the motor is limited. If the package is enlarged, the performance of the output transistor can be improved by increasing the size of the output transistor, but it is difficult to mount it on a small, for example, donut-type substrate 404.

  If four output transistors are externally attached, a transistor can be selected according to the motor capability. Further, since the IC and the output transistor can be distributed and arranged, the heat generation can be distributed to each output transistor. However, since all output transistors are externally attached, the number of parts increases, and it becomes difficult to mount on a donut-type substrate. Further, since all output transistors are discrete transistors, there is a problem that the cost is increased.

  As described above, when the four output transistors are built in and when the four output transistors are externally attached, the conditions for the number of parts and the heat generation amount cannot be satisfied simultaneously.

  Therefore, the present invention provides an integrated circuit for driving a motor that can improve the problem of the number of parts and the amount of heat generated when four output transistors are built in and when four output transistors are externally attached. The purpose is to do.

Incidentally, in order to satisfy the above-mentioned conditions, a configuration in which a part of the output transistor is built in the IC and a part is externally attached is conceivable.
For example, when the source transistor of the H-bridge is externally attached and the sink-side transistor is built in the IC, when 4 output transistors are built in, the advantages of each of the 4 output transistors are externally satisfied to some extent. It becomes possible.

  However, in this case, for example, when PWM control is performed, a regenerative current of a path indicated by a broken line in FIG. 5 flows in the IC. As the regenerative current flows, the voltage at the point X becomes lower than the ground GND by the forward voltage VF of the diode D3. When this path is taken into the IC, a parasitic current (negative current) flows in the IC, and there is a possibility that a malfunction such as fluctuation of the power supply voltage VCC may occur.

  Therefore, when the sink side transistor is built in the IC and the source side transistor is externally attached, it is necessary to add a countermeasure circuit against negative current to the IC or to devise a layout. As described above, when the sink-side transistor is built in the IC, there is a possibility that it is affected by a negative current that causes a malfunction of the IC.

  A main invention for solving the above-described problems is that a plurality of first terminals to which a driving coil is connected, a plurality of source-side transistors that discharge current to the driving coil through the plurality of first terminals, and the driving A plurality of second terminals to which control electrodes of a plurality of external sink-side transistors for sucking current from the coil are connected; and a plurality of source-side transistors and a plurality of sink-sides for supplying currents in different directions to the drive coil And a control circuit for selectively operating the transistor.

  According to the present invention, it is possible to effectively solve the problems of the number of parts and the amount of heat generation.

  At least the following matters will become apparent from the description of this specification and the accompanying drawings.

=== Overall structure ===
The motor driving integrated circuit according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing an outline of an integrated circuit for driving a motor according to the present invention.

  The motor driving integrated circuit 100 of the present invention includes a reference voltage generating circuit 102, a constant voltage generating circuit 104, a Hall amplifier 106, a current limiting circuit 108, a control circuit 110, delay circuits 112 and 114, an oscillation circuit 116, a pre-driver 118, 120, PNP transistors 122 and 126, NPN transistors 124 and 128, VCC terminal ("first power supply terminal"), VM terminal ("second power supply terminal"), VREG terminal, HB terminal, IN1 terminal, IN2 terminal, GND terminal , OUT1 terminal, OUT2 terminal, PRE1 terminal, PRE2 terminal, and two power supply lines.

  The power supply line connected to the VCC terminal is referred to as a VCC line (“first power supply line”), and the power supply line connected to the VM terminal is referred to as a VM line (“second power supply line”).

  The power supply voltage VCC from the power supply 200 is applied to the VCC terminal via a power supply reverse connection prevention diode 204. A non-grounded electrode of a voltage stabilizing capacitor 202 for maintaining the power supply voltage VCC stably is connected between the power supply 200 and the anode of the diode 204.

The VM terminal is connected to an electrode on the non-ground side of the voltage stabilizing capacitor 206.
The VM terminal is externally connected to the VCC terminal via an external resistor Rf (“heat radiation resistor”) for supplying current from the VCC line to the VM line.

  The reference voltage generation circuit 102 is connected to the VCC line, and generates a reference voltage VREF (hereinafter, simply referred to as VREF) of 1.25 volts, for example, from the power supply voltage VCC. Then, the reference voltage generation circuit 102 outputs VREF to the hall element 210 via the current limiting circuit 108 and the HB terminal.

  The reference voltage generation circuit 102 can be configured with a band gap type reference voltage circuit. By using the band gap type reference voltage, it is possible to obtain VREF which is not affected by temperature change. Note that VREF may be generated from a power supply other than the power supply voltage VCC.

  The constant voltage generation circuit 104 is connected to the VCC line, and generates a regulated voltage VREG of 6 volts, for example (hereinafter simply referred to as VREG), from the power supply voltage VCC. Then, the constant voltage generation circuit 104 outputs VREG to the hall amplifier 106 and the current limiting circuit 108. VREG is applied to the non-grounded electrode of the voltage stabilizing capacitor 208 via the VREG terminal.

  A sine wave generated according to the rotational position of the rotor is applied from the Hall element 210 to the non-inverting input terminal (+ terminal) of the Hall amplifier 106 via the IN1 terminal. Further, a sine wave having a phase opposite to that of the sine wave applied to the + terminal is applied to the inverting input terminal (− terminal) of the Hall amplifier 106 via the IN2 terminal from the Hall element 210. The hall amplifier 106 amplifies the input signal until the logic processing can be performed by the control circuit 110 at the subsequent stage, and outputs the amplified signal to the control circuit 110.

The oscillation circuit 116 generates a reference frequency for performing PWM control and outputs the reference frequency to the control circuit 110.
The control circuit 110 generates a signal for turning on / off the PNP transistor 122 and the N-channel MOSFET (hereinafter referred to as NMOS) 214 based on the output of the Hall amplifier 106, the output of the oscillation circuit 116, and the output of the current limiting circuit 108. Output to the delay circuit 112. The control circuit 110 also outputs a signal for turning on / off the PNP transistor 126 and the NMOS 212 to the delay circuit 114 based on the output of the Hall amplifier 106, the output of the oscillation circuit 116, and the output of the current limiting circuit 108.

  The delay circuits 112 and 114 appropriately delay the output of the control circuit 110 and output it to each output transistor. Thereby, the through current due to the source-side transistor and the sink-side transistor connected to the same side of the drive coil 216 being simultaneously turned on does not flow. Note that each of the delay circuit 112 and the delay circuit 114 separately outputs signals to the source-side transistor and the sink-side transistor.

  The PNP transistor 122 (“first transistor”) and the NPN transistor 124 (“second transistor”) are in an inverted Darlington connection. The emitter of the PNP transistor 122 is connected to the VCC line, and the base is connected to the delay circuit 112. The collector of the NPN transistor 124 is connected to the VM line, and the emitter of the NPN transistor 124 is connected to the OUT1 terminal.

  The OUT1 terminal is externally connected to one end of the drive coil 216 and the drain of the NMOS 212. Note that the source of the NMOS 212 is grounded.

  The PNP transistor 126 and the NPN transistor 128 are connected by inverted Darlington. The emitter of the PNP transistor 126 is connected to the VCC line, and the base is connected to the delay circuit 114. The collector of the NPN transistor 128 is connected to the VM line, and the emitter of the NPN transistor 128 is connected to the OUT2 terminal.

  The OUT2 terminal is externally connected to the other end of the drive coil 216 and the drain of the NMOS 214. Note that the source of the NMOS 214 is grounded.

  The pre-driver 118 amplifies the output of the delay circuit 114 and outputs it to the PRE1 terminal. The PRE1 terminal is connected to the gate of the NMOS 212.

  The pre-driver 120 amplifies the output of the delay circuit 112 and outputs it to the PRE2 terminal. The PRE2 terminal is connected to the gate of the NMOS 214.

  The current limiting circuit 108 is connected to the VCC line and the VM line, and when the voltage generated in the resistor Rf becomes larger than a predetermined limit voltage, the control circuit 110 outputs a signal VOUT for turning off the source side transistor. Output to.

=== Configuration of Current Limiting Circuit ===
The configuration of the current limiting circuit 108 will be described with reference to FIG. FIG. 2 is a circuit diagram showing an example of the configuration of the current limiting circuit 108.

  The current limiting circuit 108 includes constant current circuits I1, I2, I3, I4, I5, I6, PNP transistors Q5, Q6, Q9, Q10, NPN transistors Q1, Q2, Q3, Q4, Q7, Q8, Q11, Q12, Q13. , Capacitor C1 and resistor R1.

  The NPN transistor Q1 and the NPN transistor Q2 are Darlington connected. The base of the NPN transistor Q1 is connected to the VM line, and the collector is connected to the VCC line. The collector of NPN transistor Q2 is connected to the collector of PNP transistor Q5, and the emitter is connected to constant current circuit I1.

The NPN transistor Q4 and the NPN transistor Q3 are Darlington connected. The base (hereinafter referred to as point a) of the NPN transistor Q4 is connected to the VCC line via the resistor R1, and the collector is connected to the VCC line. The NPN transistor Q3 has a collector connected to the VCC line and an emitter connected to the constant current circuit I1.
The constant current circuit I1 generates a constant current I1.
The constant current circuit I2 is connected to the point a and the ground GND, and generates a constant current I2.

  The PNP transistor Q5 is diode-connected, and the PNP transistor Q5 and the PNP transistor Q6 constitute a current mirror circuit. The emitters of PNP transistor Q5 and PNP transistor Q6 are both connected to the VCC line, and the collector of PNP transistor Q6 is connected to the collector of NPN transistor Q7.

  The NPN transistor Q7 is diode-connected, and the NPN transistor Q7 and the PNP transistor Q8 constitute a current mirror circuit. The emitters of NPN transistor Q7 and NPN transistor Q8 are both grounded GND, and the collector of NPN transistor Q8 is connected to the non-grounded electrode (hereinafter referred to as point b) of capacitor C1.

The constant current circuit I3 generates a constant current I3 from VREG and supplies it to the point b.
The constant current circuit I4 generates a constant current I4 from VREG.
The emitter of the PNP transistor Q9 is connected to the constant current circuit I4, and the collector is grounded. The base of the PNP transistor Q9 is connected to the point b.
The emitter of the PNP transistor Q10 is connected to the constant current circuit I4, and the collector is connected to the collector of the NPN transistor Q11. VREF is applied to the base of the PNP transistor Q10.

The constant current circuit I5 generates a constant current I5 from VREG.
The NPN transistor Q11 is diode-connected, and the NPN transistor Q11 and the NPN transistor Q12 constitute a current mirror circuit. The collectors of NPN transistor Q11 and NPN transistor Q12 are both grounded, and the collector of NPN transistor Q12 is connected to the constant current circuit I5 and the base of NPN transistor Q13.

The constant current circuit I6 generates a constant current I6 from VREG.
The NPN transistor Q13 has an emitter connected to the ground GND and a collector connected to the constant current circuit I6. Further, the collector of the NPN transistor Q13 becomes the output VOUT of the current limiting circuit.

=== Operation of Current Limiting Circuit ===
Next, the operation of the current limiting circuit 108 will be described. The resistance values of the resistors R1 and Rf are R1 and Rf, respectively. The voltage at point a is Va, and the voltage on the VM line is VM.

When the constant current I2 flows through the resistor R1, Va becomes VCC− (I2 × R1).
On the other hand, NPN transistors 124 and 128 and NMOSs 212 and 214 constituting the H bridge in FIG. 1 are connected between the VM terminal and the ground GND. Therefore, as will be described later, all of the current flowing through the drive coil 216 flows through the resistor Rf. At this time, if the current flowing through the resistor Rf is IO, VM becomes VCC− (IO × Rf).
It is assumed that the values of constant current I2 and resistor R1 are set so that Va is equal to VM when IO × Rf becomes the limit voltage.

≪Va <VM≫ (IO × Rf is smaller than the limit voltage)
The NPN transistor Q1 is turned on and the NPN transistor Q4 is turned off. When the NPN transistor Q1 is turned on, the NPN transistor Q2 is turned on and an attempt is made to flow the collector current of the PNP transistor Q5. Therefore, both the PNP transistor Q5 and the PNP transistor Q6 constituting the current mirror circuit are turned on. When the transistor size ratios of the PNP transistor Q5 and the PNP transistor Q6 are equal, the PNP transistor Q6 tries to flow a collector current that is equal to the collector current of the PNP transistor Q5.

  Then, when the collector current of the PNP transistor Q6 is supplied to the collector of the NPN transistor Q7, both the NPN transistor Q7 and the NPN transistor Q8 constituting the current mirror circuit are turned on. When the transistor size ratio between the NPN transistor Q7 and the NPN transistor Q8 is equal, the NPN transistor Q8 tries to flow a collector current that is equal to the collector current of the NPN transistor Q7. Therefore, the voltage at the point b (hereinafter referred to as Vb) decreases and becomes lower than VREF.

  Since VREF> Vb, the NPN transistor Q9 is turned on and the NPN transistor Q10 is turned off. When the NPN transistor Q10 is turned off, no current is supplied to the collector of the NPN transistor Q11, and both the NPN transistor Q11 and the NPN transistor Q12 constituting the current mirror circuit are turned off.

The NPN transistor Q13 is turned on when the constant current I5 is supplied to the base, and the constant current I6 flows as the collector current.
Therefore, VOUT becomes low level (hereinafter referred to as “L”).

<< In case of Va> VM >> (IO × Rf is larger than the limit voltage)
The NPN transistor Q4 is turned on and the NPN transistor Q1 is turned off. Since the NPN transistor Q1 is off, the NPN transistor Q2 is also off. Therefore, both the PNP transistor Q5 and the PNP transistor Q6 constituting the current mirror circuit are turned off.

  Further, since the PNP transistor Q6 is off, no current is supplied to the collector of the NPN transistor Q7, and both the NPN transistor Q7 and the NPN transistor Q8 constituting the current mirror circuit are also turned off. Therefore, the capacitor C1 is charged with the constant current I3, and the voltage at the point b (hereinafter referred to as Vb) becomes higher than VREF.

Since VREF <Vb, the NPN transistor Q9 is turned off and the NPN transistor Q10 is turned on. Since the current is supplied to the collector of the NPN transistor Q11 when the NPN transistor Q10 is turned on, both the NPN transistor Q11 and the NPN transistor Q12 constituting the current mirror circuit are turned on. Assuming that the transistor size ratio between the NPN transistor Q11 and the NPN transistor Q12 is equal, the NPN transistor Q12 attempts to flow a collector current that is equal to the collector current of the NPN transistor Q11. Therefore, no current is supplied to the base of the NPN transistor Q13, and the NPN transistor Q13 is turned off.
Therefore, VOUT becomes high level (hereinafter referred to as “H”) by the constant current I6.

  This VOUT is output to the control circuit 110. The control circuit 110 stops the supply of the drive current to the drive coil 216 by turning off the source-side transistor when VOUT becomes “H”.

=== Operation of Motor Driven Integrated Circuit ===
Next, the operation of the motor driving integrated circuit according to the present invention will be described with reference to FIGS. FIG. 3 is a diagram for explaining the operation of the output transistor.

  A sine wave corresponding to the rotational position of the rotor and a sine wave having a phase opposite to that of the sine wave are output from the Hall element 210 to the Hall amplifier 106 in accordance with the change of the magnetic pole when the motor rotates. This sine wave is amplified by the hall amplifier 106 until logic processing is possible in the control circuit 110 at the subsequent stage.

  The control circuit 110 performs logic processing based on the output from the hall amplifier 106. Then, the PNP transistors 122 and 126 and the NMOSs 212 and 214 are selectively turned on / off through the delay circuits 112 and 114, the pre-drivers 118 and 120, and the PRE1 terminal and the PRE2 terminal.

  When the PNP transistor 122 and the NMOS 214 are turned on and the PNP transistor 126 and the NMOS 212 are turned off, the VCC terminal → resistor Rf → VM terminal → NPN transistor 124 → OUT1 terminal → drive coil 216 → OUT2 terminal shown by the solid line in FIG. → NMOS 214 → Ground current GND flows.

  On the other hand, when the PNP transistor 126 and the NMOS 212 are turned on and the PNP transistor 122 and the NMOS 214 are turned off, the VCC terminal → the resistor Rf → the VM terminal → the NPN transistor 128 → the OUT2 terminal → the drive coil 216 shown by the one-dot chain line in FIG. → OUT1 terminal → NMOS 212 → Ground GND current flows.

  The motor is driven by switching the current flowing through the drive coil 216 in this way. In addition, a current flows through the resistor Rf regardless of the current path.

  Here, when the collector-emitter voltage of the PNP transistor 122 is VCE2, the collector-emitter voltage of the NPN transistor 124 is VCE1, and the base-emitter voltage is VBE1, the PNP transistor 122 and the NPN transistor 124 are turned on. The voltage applied to the OUT1 terminal is VCC− (VCE2 + VBE1).

  When the voltage drop due to the resistor Rf is VR, the voltage at the OUT1 terminal due to the flow of the solid line path is VCC− (VR + VCE1).

  Therefore, if (VCE2 + VBE1)> (VR + VCE1) is satisfied, even if the resistor Rf is connected between the VCC terminal and the VM terminal, the voltage applied to the OUT1 terminal does not change. Furthermore, in the motor drive integrated circuit of the present invention, since the resistor Rf is connected between the VCC terminal and the VM terminal outside the IC, heat generation can be dispersed inside the IC and outside the IC. As the source side transistor, for example, a Darlington connection transistor may be used. Even in this case, the heat generation can be dispersed by externally connecting the resistor Rf between the VCC terminal and the VM terminal.

  In the motor driving integrated circuit according to the present invention, since the NMOSs 212 and 214 of the sink side transistors are externally attached, the heat generation in the IC can be further reduced.

  Further, the control circuit 110 intermittently turns on the other source side transistor during the period when one sink side transistor of the drive coil 216 is on based on the PWM control reference frequency output from the oscillation circuit 116. PWM control is performed.

  Further, the control circuit 110 stops the supply of the drive current by turning off the source-side transistor when “H” VOUT is output from the current limiting circuit 108.

  When performing PWM control or current limiting, for example, the PNP transistor 122 and the NPN transistor 124 are turned off in a state where the current of the solid line in FIG. 3 is flowing.

  If the current of the path of the solid line in FIG. 3 is flowing and the NPN transistor 124 is turned off, the coil L tries to continue to flow the current in the same direction, so that the drive coil 216 → OUT2 terminal indicated by the broken line in FIG. → NMOS 214 → Ground GND → Parallel diode (not shown) of NMOS 212 → OUT1 terminal → Regenerative current of the path of the drive coil 216 flows.

  In the MOSFET, a parasitic diode is formed between the drain and the source in the process.

  As the regenerative current flows, the voltage at the OUT1 terminal becomes lower than the ground GND by the forward voltage of the parasitic diode of the NMOS 212. However, in the motor drive integrated circuit of the present invention, since the path of the regenerative current is provided outside the IC, it is not affected by the negative current flowing or can be minimized. Therefore, it is not necessary to provide a countermeasure circuit for negative current in the IC and to devise a layout.

=== Other Embodiments ===
The motor driving integrated circuit of the present invention can also be applied to a three-phase motor. In the three-phase motor, a source-side transistor and a sink-side transistor are connected to each phase drive coil. In the case of a three-phase motor, a three-phase source-side transistor is built in the IC, and a three-phase sink-side transistor is externally attached.
Also in the case of a three-phase motor, the source side transistor of each phase is composed of an inverted Darlington-connected bipolar transistor connected to the VCC line and the VM line, and a resistor Rf is connected between the VCC line and the VM line. be able to.

When PWM control is performed on a three-phase motor, for example, by intermittently turning on / off the source-side transistor of another phase during a period when the sink-side transistor of a certain phase is on, between the sink-side transistors. Regenerate current.
In addition, when the current is limited, the source side transistor is turned off.
As described above, in the three-phase motor, the number of parts and the amount of heat generation can be improved by externally attaching the sink side transistor as in the case of the single-phase motor.

  As described above, the integrated circuit for driving the motor according to the present invention includes the source side transistor in the IC and the sink side transistor externally. The problem of the number of parts and the amount of heat generation can be improved, and for example, mounting on the donut-shaped substrate 404 is possible. Since the sink-side transistor is externally attached, it is not affected by the negative current generated by the regenerative current flowing between the sink-side transistors or can be minimized. Therefore, it is not necessary to provide a negative current countermeasure circuit or to devise a layout.

  Further, by making the source side transistor a Darlington connection, the resistor Rf can be externally connected between the VCC line and the VM line, and heat generation can be dispersed outside the IC. In particular, when the source side transistors are the inverted Darlington-connected PNP transistor 122 and NPN transistor 124, and the PNP transistor 126 and the NPN transistor 128, on / off control can be performed with a low control voltage, and hfe Can be increased.

  In addition, when the resistor Rf is connected between the VCC line and the VM line where the voltage drop VR in the resistor Rf satisfies (VCE2 + VBE1)> (VR + VCE1), the voltage applied to the coil 216 does not decrease, and the voltage in the IC is reduced. Heat generation can be reduced.

  Furthermore, by using the resistor Rf as the voltage detection resistor of the current limiting circuit 108, the heat generation in the IC can be reduced without increasing the number of components.

  In addition, the motor driving integrated circuit that performs PWM control for regenerating current between the sink-side transistors can be effectively unaffected by negative current.

  By using the external NMOS 212 and NMOS 214 as the sink side transistors, low saturation voltage (low on-resistance) and low cost can be achieved.

  As described above, the present embodiment has been specifically described based on the embodiment. However, the present embodiment is not limited to this, and various modifications can be made without departing from the scope of the present embodiment.

1 is a circuit diagram showing a configuration of an integrated circuit for driving a motor according to an embodiment of the present invention. It is a circuit diagram which shows the structure of a current limiting circuit. It is a figure for demonstrating the operation | movement in an output transistor. It is a figure for demonstrating a donut type | mold base | substrate. It is a figure for demonstrating the case where an output is an H bridge.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Motor drive integrated circuit 102 Reference voltage generation circuit 104 Constant voltage generation circuit 106 Hall amplifier 108 Current limiting circuit 110 Control circuit 112,114 Delay circuit 116 Transmission circuit 118,120 Pre-driver 122,126 PNP transistor 124,128,130 NPN Transistor 200 VCC power supply 202, 206, 208 Capacitor 210 Hall element 212, 214 N-type MOSFET
216 Driving coil Rf Sensing resistance

Claims (7)

A plurality of first terminals to which the drive coil is connected;
A plurality of source side transistors for discharging current to the drive coil via the plurality of first terminals;
A plurality of second terminals to which control electrodes of a plurality of external sink-side transistors that draw current from the drive coil are connected;
To provide different directions of current to the driving coil, and a control circuit for the plurality of source-side transistor and the plurality of external sink side transistor selectively operated,
Motor driving integrated circuit, wherein the kite comprising a. A plurality of first terminals to which the drive coil is connected;
A plurality of source side transistors each comprising a first transistor and a second transistor connected in Darlington, and discharging current to the drive coil via the plurality of first terminals;
A plurality of second terminals to which control electrodes of a plurality of external sink-side transistors that draw current from the drive coil are connected;
A control circuit for selectively operating the plurality of source-side transistors and the plurality of external sink-side transistors to supply currents in different directions to the drive coil;
A first power line connected to the first transistor;
A second power line connected to the second transistor and having a voltage value lower than the voltage value of the first power line;
A first power supply terminal connected to the first power supply line and connected to one end of a heat radiation resistor connected externally;
A second power supply terminal connected to the second power supply line and connected to the other end of the heat radiation resistor;
Features and to makes the chromophore at the distal end over data driving integrated circuit further comprising a. Said first transistor 及 beauty said second transistor, a motor driving integrated circuit according to claim 2, characterized in that the inverted Darlington connection. Resistance of the heat dissipation resistor, claim 2 also characterized in that the voltage between the first transistor and the second transistor is a larger value than the voltage between the radiating resistor and the second transistor 4 is an integrated circuit for driving a motor according to 3; It detects that voltage generated in the discharge thermal resistance exceeds a predetermined voltage, a current limit circuit, which outputs a signal for stopping the operation of the source side transistor,
The control circuit includes:
Based on the signal output from the current limiting circuit stops the operation of the source side transistor, that the motor driving integrated circuit according to any one of claims 2 to 4, characterized in. The control circuit includes:
6. The integrated circuit for driving a motor according to claim 1, wherein the selected source-side transistor is intermittently operated while the selected external sink-side transistor is operating. . The external sink side transistor is an N-channel MOSFET.
The motor drive integrated circuit according to claim 1, wherein the motor drive integrated circuit is according to claim 1.

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