JP4766026B2 - Electronic device and method for canceling firewall of electronic device - Google Patents

Abstract

[Object] To increase the usability for users without decreasing the security level. [Solving Means] A personal computer (PC) 10 is connected to a television receiver (TV) 30 using an HDMI cable 1. When a video signal is transmitted from the PC 10 to the TV 30, a TMDS channel in the HDMI cable 1 is used. A high-speed data line that performs bi-directional communication using predetermined lines of the HDMI cable 1 (e.g., a reserve line and an HPD line) is provided. In PC 10, a firewall is set. When, for example, being connected to the PC 10, the TV 30 transmits a firewall turn-off command to the PC 10. Alternatively, when, for example, performing data transmission using the high-speed data line provided between the TV 30 and the PC 10, the TV 30 transmits a firewall turn-off command to the PC 10. The security level and connectivity can be maintained without troublesome setting performed by the user and, therefore, the usability for users can be increased.

Description

  The present invention relates to an electronic device and a method for canceling a firewall of the electronic device.

  Specifically, the present invention relates to an electronic device having a communication unit that performs bidirectional communication using a predetermined line of a transmission path for receiving a baseband video signal from an external device, and canceling a firewall for the communication unit By providing a command transmission unit that transmits commands to external devices, it is related to electronic devices, etc. that ensure connectivity with external devices without compromising the security of external devices and improve user convenience. is there.

  The present invention also relates to an electronic device including a communication unit that performs bidirectional communication using a predetermined line of a transmission path for transmitting a baseband video signal to an external device, and a firewall release command is issued from the external device. When received, the firewall for the external device is canceled, and when the firewall release termination command is received from the external device, the firewall release for the external device is canceled to improve the connectivity with the external device without compromising security. The present invention relates to an electronic device that is ensured and improved in user-friendliness.

  Conventionally, for example, an electronic device such as a television receiver is connected to a personal computer. When high-speed data transmission / reception is performed between a personal computer and a television receiver, etc. via an Ethernet connection, the connectivity is significantly degraded due to the security firewall generally set in the personal computer. In many cases, high-speed data transfer was hindered.

  Further, when priority is given to the connectivity and the firewall of the personal computer is completely canceled, there is a risk that the security level is significantly lowered on the personal computer side.

  In order to solve these problems, when sending high-speed data, it is necessary to manually release the appropriate and minimum firewall, send and receive high-speed data while ensuring security, and then release the release. It was necessary for a person with some knowledge and experience to perform this method. However, this method lacks versatility and is very difficult to use for general users.

In recent years, for example, digital video signals, that is, non-video signals, from personal computers, DVD (Digital Versatile Disc) recorders, set-top boxes, and other AV sources (Audio Visual source) to TV receivers, projectors, and other displays. As a communication interface for transmitting a compressed (baseband) video signal and a digital audio signal accompanying the video signal at high speed, HDMI (High Definition Multimedia Interface) is becoming widespread. For example, Patent Document 1 describes the details of the HDMI standard.
WO2002 / 078336

  As described above, for example, in an AV system in which an electronic device such as a television receiver is connected to a personal computer, when high-speed data is transmitted and received between the personal computer and the television receiver or the like by an Ether connection, Due to the firewall set in the computer, the connectivity was remarkably poor, and there were many cases where it was difficult to transfer data at high speed.

  An object of the present invention is to ensure connectivity and improve user convenience without compromising security.

The concept of this invention is
A signal receiving unit that receives a video signal from an external device via a transmission path using a plurality of channels and a differential signal;
A communication unit that performs bidirectional communication using a predetermined line constituting the transmission path;
An electronic apparatus comprising: a command transmission unit that transmits a firewall cancellation command for requesting cancellation of a firewall for the communication unit to the external device.

  In this invention, in addition to a signal receiving unit that receives a video signal via a transmission line by a differential signal using a plurality of channels, a communication unit that performs bidirectional communication using a predetermined line constituting the transmission line is provided. Provided, and data transmission is performed between the communication unit and an external device. For example, the predetermined lines are a reserved line and an HPD line that constitute an HDMI cable.

  The external device is provided with a command transmission unit that transmits a firewall cancellation command for requesting the communication unit to cancel the firewall. For example, the firewall release command is performed using the control data line of the transmission path.

  In the present invention, for example, a connection detection unit that detects that the external device is connected via the transmission path is provided, and the command transmission unit is externally connected when the connection detection unit detects that the external device is connected to the external device. A firewall release command may be transmitted to the device. In this case, when the external device is connected via the transmission path, the firewall is released from the communication unit and the connectivity is ensured in the external device, so that the data can be transmitted by the communication unit.

  Further, in the present invention, for example, when the power transmission operation is performed, the command transmission unit further transmits, to the external device, a firewall release end command that requests the communication unit to end the release of the firewall. May be. In this case, the release of the firewall for the communication unit in the external device is stopped, and security is ensured.

  In the present invention, the command transmission unit transmits a firewall release command to the external device when data transmission is performed using the communication unit, and when the data transmission is completed, the command transmission unit transmits a firewall for the communication unit to the external device. It is also possible to transmit a firewall release end command for requesting the end of release. In this case, when data transmission is performed in the communication unit, the firewall for the communication unit in the external device is released and the connectivity is ensured, so that data transmission with the external device is possible.

The concept of the present invention is
A signal transmission unit that transmits the video signal to the external device via a transmission path using a differential signal in a plurality of channels;
A communication unit that performs bidirectional communication using a predetermined line constituting the transmission path;
A firewall setting section for setting a firewall;
A command receiving unit for receiving commands from the external device,
The firewall setting section
When the firewall receiving command is received by the command receiving unit, the firewall for the external device is released, and when the firewall releasing end command is received by the command receiving unit, canceling the firewall releasing for the external device is stopped. It is in electronic equipment that is characterized by

  In the present invention, bidirectional communication is performed using a predetermined line constituting the transmission path, in addition to the signal transmission unit that transmits the video signal to the external device via the transmission path as a differential signal using a plurality of channels. The communication part which performs is provided. For example, the predetermined lines are a reserved line and an HPD line that constitute an HDMI cable.

  This communication unit enables data transmission with an external device. When the firewall release command is received, the firewall for the external device is released, and when the firewall release end command is received, the firewall release for the external device is stopped.

  In this case, since the firewall for the external device is released and the connectivity is ensured from the reception of the firewall release command until the reception of the firewall release end command, data between the external device and the external device is secured by the communication unit. Transmission is possible.

  In the present invention, for example, a connection detection unit that detects whether or not an external device is connected via a transmission path is provided, and the firewall setting unit detects connection in a state where the firewall for the external device is released. When the unit detects that the external device is not connected, the cancellation of the firewall for the external device may be stopped. In this case, when the connection to the external device is disconnected without performing the termination operation when the firewall for the external device is released, the firewall release for the external device is automatically canceled. Is called.

  According to the present invention, there is provided an electronic device having a communication unit that performs two-way communication using a predetermined line of a transmission path for receiving a baseband video signal from an external device, and a firewall release command for the communication unit Can be transmitted to the external device, ensuring connectivity with the external device without impairing the security of the external device, and improving the usability of the user.

  According to the invention, there is provided an electronic device including a communication unit that performs bidirectional communication using a predetermined line of a transmission path for transmitting a baseband video signal to an external device, and the firewall is released from the external device. When the command is received, the firewall for the external device is canceled, and when the firewall release termination command is received from the external device, the firewall cancellation for the external device is canceled. Connectivity can be ensured and user convenience can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration example of an AV (Audio Visual) system 5 as an embodiment.

  The AV system 5 includes a personal computer (PC) 10 as a source device and a television receiver (TV) 30 as a sink device. The personal computer 10 and the television receiver 30 are connected via the HDMI cable 1.

  The personal computer 10 is provided with an HDMI terminal 11 to which an HDMI transmission unit (HDMITX) 12 and a high-speed data line interface 12A are connected. The television receiver 30 is provided with an HDMI terminal 31 to which an HDMI receiving unit (HDMI RX) 32 and a high-speed data line interface 32A are connected. One end of the HDMI cable 1 is connected to the HDMI terminal 11 of the personal computer 10, and the other end of the HDMI cable 1 is connected to the HDMI terminal 31 of the television receiver 30.

  In the AV system 5 shown in FIG. 1, the personal computer 10 can transmit a baseband video signal to the television receiver 30 using an HDMI TMDS (Transition Minimized Differential Signaling) channel. In this case, the baseband video signal is supplied from the HDMI transmission unit 12 of the personal computer 10 to the HDMI reception unit 32 of the television receiver 30 via the HDMI cable 1.

  In the AV system 5 shown in FIG. 1, data can be transmitted and received between the personal computer 10 and the television receiver 30 using an Ethernet IP packet using a high-speed data line. In this case, data is transmitted / received via the HDMI cable 1 between the high-speed data line interface 12A of the personal computer 10 and the high-speed data line interface 32A of the television receiver 30.

  In the personal computer 10, a firewall is set. However, as described above, for the television receiver 30 connected using the HDMI cable 30, the firewall is canceled if necessary, and a high-speed data line is set. It is possible to transmit data using. Details of the firewall release sequence will be described later.

  FIG. 2 shows a configuration example of the personal computer 10.

  The personal computer 10 includes an HDMI terminal 11, an HDMI transmission unit 12, a high-speed data line interface 12A, a CPU (Central Processing Unit) 13, a ROM (Read Only Memory) 14, a RAM (Random Access Memory) 15, A bus 16, an input / output interface 17, an input unit 18, an output unit 19, a storage unit 20, a drive 21, an Ethernet interface (Ethernet I / F) 22, and a network terminal 23 are provided. “Ethernet” and “Ethernet” are registered trademarks.

  In the personal computer 10, the CPU 13, ROM 14, and RAM 15 are connected to each other by a bus 16. An input / output interface 17 is further connected to the bus 16. An input unit 18, an output unit 19, a storage unit 20, a drive 21, and an HDMI transmission unit (HDMI TX) 12 are connected to the input / output interface 17.

  The input unit 18 includes a keyboard, a mouse, a microphone, and the like. The output unit 19 includes a display, a speaker, and the like. The storage unit 20 includes an HDD (Hard Disk Drive), a nonvolatile memory, and the like. The drive 21 drives a removable medium such as a magnetic disk, an optical disk, a magneto-optical disk, or a memory card.

  An Ethernet interface 22 is connected to the bus 16. A network terminal 23 and a high-speed data line interface 12A are connected to the Ethernet interface 22. The high-speed data line interface 12A is a bidirectional communication interface using a predetermined line (in this embodiment, a reserved line and an HPD line) constituting the HDMI cable 1. Details of the high-speed data line interface 12A will be described later.

  In the personal computer 10 configured as shown in FIG. 2, for example, the CPU 13 loads a program stored in the storage unit 20 to the RAM 15 via the input / output interface 17 and the bus 16 and executes the program. A series of processing described later is performed.

  FIG. 3 shows a configuration example of the television receiver 30. The television receiver 30 includes an HDMI terminal 31, an HDMI receiving unit 32, a high-speed data line interface 32A, an antenna terminal 37, a digital tuner 38, a demultiplexer 39, an MPEG (Moving Picture Expert Group) decoder 40, Video / graphic processing circuit 41, panel driving circuit 42, display panel 43, audio signal processing circuit 44, audio amplification circuit 45, speaker 46, DTCP (Digital Transmission Content Protection) circuit 47, internal bus 50, a CPU 51, a flash ROM 52, a DRAM 53, an Ethernet interface (Ethernet I / F) 54, a network terminal 55, a remote control receiver 56, and a remote control transmitter 57.

  The antenna terminal 37 is a terminal for inputting a television broadcast signal received by a receiving antenna (not shown). The digital tuner 38 processes the television broadcast signal input to the antenna terminal 37 and outputs a predetermined transport stream corresponding to the user's selected channel. The demultiplexer 39 extracts a partial TS (Transport Stream) (a TS packet of video data and a TS packet of audio data) corresponding to the user's selected channel from the transport stream obtained by the digital tuner 38.

  Further, the demultiplexer 39 extracts PSI / SI (Program Specific Information / Service Information) from the transport stream obtained by the digital tuner 38 and outputs it to the CPU 51. A plurality of channels are multiplexed in the transport stream obtained by the digital tuner 38. The process of extracting a partial TS of an arbitrary channel from the transport stream by the demultiplexer 39 can be performed by obtaining the packet ID (PID) information of the arbitrary channel from PSI / SI (PAT / PMT). .

  The MPEG decoder 40 performs a decoding process on a video PES (Packetized Elementary Stream) packet composed of TS packets of video data obtained by the demultiplexer 39 to obtain video data. Also, the MPEG decoder 40 obtains audio data by performing a decoding process on the audio PES packet constituted by the audio data TS packet obtained by the demultiplexer 39. The MPEG decoder 40 decodes the video and audio PES packets obtained by decoding by the DTCP circuit 47 as necessary to obtain video data and audio data.

  The video / graphic processing circuit 41 performs multi-screen processing, graphics data superimposition processing, and the like on the video data obtained by the MPEG decoder 40 as necessary. The panel drive circuit 42 drives the display panel 43 based on the video data output from the video / graphic processing circuit 41. The display panel 43 includes, for example, an LCD (Liquid Crystal Display), a PDP (Plasma Display Panel), or the like. The audio signal processing circuit 44 performs necessary processing such as D / A conversion on the audio data obtained by the MPEG decoder 40. The audio amplifier circuit 45 amplifies the audio signal output from the audio signal processing circuit 44 and supplies it to the speaker 46.

  The DTCP circuit 47 encrypts the partial TS extracted by the demultiplexer 39 as necessary. The DTCP circuit 47 decrypts the encrypted data supplied from the network terminal 55 or the high-speed data line interface 32A to the Ethernet interface 54.

  The CPU 51 controls the operation of each part of the television receiver 30. The flash ROM 52 stores control software and data. The DRAM 53 constitutes a work area for the CPU 51. The CPU 51 develops software and data read from the flash ROM 52 on the DRAM 53 and activates the software to control each unit of the television receiver 30. The remote control receiving unit 56 receives a remote control signal (remote control code) transmitted from the remote control transmitter 57 and supplies it to the CPU 51. The CPU 51, flash ROM 52, DRAM 53 and Ethernet interface 54 are connected to the internal bus 50.

  The HDMI receiving unit (HDMI sink) 32 receives baseband video (image) and audio data supplied to the HDMI terminal 31 by communication conforming to HDMI. Details of the HDMI receiving unit 32 will be described later. The high-speed data line interface 32A is a bidirectional communication interface using a predetermined line (in this embodiment, a reserved line and an HPD line) constituting an HDMI cable. Details of the high-speed data line interface 32A will be described later.

  The operation of the television receiver 30 shown in FIG. 3 will be briefly described.

  A television broadcast signal input to the antenna terminal 37 is supplied to the digital tuner 38. The digital tuner 38 processes the television broadcast signal, outputs a predetermined transport stream corresponding to the user's selected channel, and supplies the predetermined transport stream to the demultiplexer 39. In the demultiplexer 39, a partial TS (video data TS packet, audio data TS packet) corresponding to the user's selected channel is extracted from the transport stream, and the partial TS is supplied to the MPEG decoder 40.

  In the MPEG decoder 40, video data is obtained by performing a decoding process on a video PES packet composed of TS packets of video data. The video data is supplied to the panel drive circuit 42 after being subjected to multi-screen processing, graphics data superimposition processing, and the like in the video / graphic processing circuit 41 as necessary. Therefore, an image corresponding to the user's selected channel is displayed on the display panel 43.

  In the MPEG decoder 40, audio data is obtained by performing a decoding process on an audio PES packet constituted by TS packets of audio data. The audio data is subjected to necessary processing such as D / A conversion by the audio signal processing circuit 44, further amplified by the audio amplification circuit 45, and then supplied to the speaker 46. Therefore, sound corresponding to the user's selected channel is output from the speaker 46.

  At the time of receiving a television broadcast signal, when the partial TS extracted by the demultiplexer 39 is sent to a network or a high-speed data line constituted by a predetermined line of an HDMI cable described later, the partial TS is a DTCP circuit 47. After being encrypted, the data is supplied to the network terminal 55 or the high-speed data line interface 32A via the Ethernet interface 54.

  The remote control receiver 56 receives the remote control code (remote control signal) transmitted from the remote control transmitter 57 and supplies the remote control code to the CPU 51. The CPU 51 controls each part of the television receiver 30 based on the remote control code.

  The encrypted partial TS supplied from the network terminal 55 to the Ethernet interface 54 or supplied from the HDMI terminal 31 to the Ethernet interface 54 via the high-speed data line interface 32A is decrypted by the DTCP circuit 47. After being converted, it is supplied to the MPEG decoder 40. Thereafter, the operation is the same as that when receiving the television broadcast signal described above, an image is displayed on the display panel 43, and sound is output from the speaker 46.

  Also, the HDMI receiving unit 32 acquires video (image) data and audio data input to the HDMI terminal 31 through the HDMI cable. The video data and audio data are supplied to the video / graphic processing circuit 41 and the audio signal processing circuit 44, respectively. Thereafter, the operation is the same as that when receiving the television broadcast signal described above, an image is displayed on the display panel 43, and sound is output from the speaker 46.

  FIG. 4 shows a configuration example of the HDMI transmission unit (HDMI source) 12 of the personal computer 10 and the HDMI reception unit (HDMI sink) 32 of the television receiver 30 in the AV system 5 of FIG.

  The HDMI source 12 is an effective image section (hereinafter also referred to as an active video section as appropriate) that is a section obtained by removing a horizontal blanking section and a vertical blanking section from a section from one vertical synchronization signal to the next vertical synchronization signal. , The differential signal corresponding to the pixel data of the uncompressed image for one screen is transmitted to the HDMI sink 32 in one direction through a plurality of channels, and at least the image in the horizontal blanking interval or the vertical blanking interval A differential signal corresponding to audio data, control data, and other auxiliary data accompanying the data is transmitted to the HDMI sink 32 in one direction through a plurality of channels.

  That is, the HDMI source 12 has a transmitter 81. The transmitter 81 converts, for example, pixel data of an uncompressed image into a corresponding differential signal, and is connected via the HDMI cable 1 through three TMDS channels # 0, # 1, and # 2 that are a plurality of channels. Serial transmission in one direction to the HDMI sink 32.

  The transmitter 81 converts audio data accompanying uncompressed images, further necessary control data and other auxiliary data, etc. into corresponding differential signals, and converts them into three TMDS channels # 0, # 1, #. 2 is serially transmitted in one direction to the HDMI sink 32 connected via the HDMI cable 1.

  Further, the transmitter 81 transmits a pixel clock synchronized with the pixel data transmitted through the three TMDS channels # 0, # 1, and # 2 to the HDMI sink 32 connected via the HDMI cable 1 using the TMDS clock channel. To do. Here, in one TMDS channel #i (i = 0, 1, 2), 10-bit pixel data is transmitted during one pixel clock.

  The HDMI sink 32 receives a differential signal corresponding to pixel data transmitted in one direction from the HDMI source 12 through a plurality of channels in the active video section, and in the horizontal blanking section or the vertical blanking section. The differential signals corresponding to the audio data and the control data transmitted in one direction from the HDMI source 12 are received through a plurality of channels.

  That is, the HDMI sink 32 has a receiver 82. The receiver 82 is transmitted in one direction from the HDMI source 12 connected via the HDMI cable 1 through the TMDS channels # 0, # 1, and # 2, and the differential signal corresponding to the pixel data and the audio data Similarly, the differential signal corresponding to the control data is received in synchronization with the pixel clock transmitted from the HDMI source 12 through the TMDS clock channel.

  In the transmission channel of the HDMI system including the HDMI source 12 and the HDMI sink 32, pixel data and audio data are serially transmitted in one direction from the HDMI source 12 to the HDMI sink 32 in synchronization with the pixel clock. In addition to the three TMDS channels # 0 to # 2 as the transmission channels of TM4 and the TMDS clock channel as the transmission channel for transmitting the pixel clock, there are transmission channels called the DDC (Display Data Channel) 83 and the CEC line 84 .

  The DDC 83 is composed of two signal lines (not shown) included in the HDMI cable 1, and the HDMI source 12 receives E-EDID (Enhanced Extended Display Identification Data) from the HDMI sink 32 connected via the HDMI cable 1. Used for reading.

  That is, in addition to the HDMI receiver 81, the HDMI sink 32 has an EDID ROM (Read Only Memory) 85 that stores E-EDID, which is performance information related to its performance (Configuration / capability). The HDMI source 12 reads the E-EDID of the HDMI sink 32 from the HDMI sink 32 connected via the HDMI cable 1 via the DDC 83, and sets the performance of the HDMI sink 32 based on the E-EDID. That is, for example, an image format (profile) supported by the electronic device having the HDMI sink 32, for example, RGB, YCbCr4: 4: 4, YCbCr4: 2: 2, etc. is recognized.

  The CEC line 84 includes one signal line (not shown) included in the HDMI cable 1 and is used for bidirectional communication of control data between the HDMI source 12 and the HDMI sink 32. The CEC line 84 constitutes a control data line.

  Further, the HDMI cable 1 includes a line 86 connected to a pin called HPD (Hot Plug Detect). The source device can detect the connection of the sink device using the line 86. The HDMI cable 1 also includes a line 87 that is used to supply power from the source device to the sink device. Further, the HDMI cable 1 includes a reserved line 88.

  Here, FIG. 5 simply shows the peripheral circuits of the power supply terminal (+ 5V power terminal) and the HPD (Hot Plug Detect) terminal in the personal computer 10 as the source device and the television receiver 30 as the sink device. Show.

  The personal computer 10 includes a power supply unit 201 that generates + 5V power and supplies it to the above-described power supply terminal (+ 5V power terminal), and an HPD circuit 202 connected to the HPD terminal. The HPD terminal of the personal computer 10 is grounded through a pull-down resistor 203 of 47 kΩ, for example.

  On the other hand, the television receiver 30 includes an HPD circuit 204 connected to the HPD terminal. In the television receiver 30, the EDID ROM 85 is supplied with power for reading from a power terminal (+ 5V power terminal). In the television receiver 30, a 1 kΩ resistor 205 defined by the standard is connected between the power supply terminal (+5 V power terminal) and the HPD terminal.

  In such a configuration, when the personal computer 10 and the television receiver 30 are connected by the HDMI cable 1, + 5V power from the power supply unit 201 supplied to the power supply terminal (+ 5V power terminal) of the television receiver 10. As a result, the potential of the HPD terminal of the television receiver 30 is increased. Therefore, the HPD circuit 204 of the television receiver 30 can detect that the personal computer 10 is connected to the TV receiver 30 via the HDMI cable 1. At this time, the potential of the HPD terminal of the personal computer 10 also increases. Therefore, the HPD circuit 202 of the personal computer 10 can detect that the television receiver 30 is connected to the personal computer 10 via the HDMI cable 1.

  Further, in this state, for example, when the HDMI cable 1 is disconnected from the television receiver 30, the potentials of the HPD terminal of the television receiver 30 and the HPD terminal of the personal computer 10 both become low, and the HPD circuit of the television receiver 30. 204 and the HPD circuit 202 of the personal computer 10 can detect the disconnection.

  FIG. 6 shows a configuration example of the HDMI transmitter 81 and the HDMI receiver 82 of FIG.

  The transmitter 81 includes three encoders / serializers 81A, 81B, and 81C corresponding to the three TMDS channels # 0, # 1, and # 2, respectively. Each of the encoders / serializers 81A, 81B, and 81C encodes the image data, auxiliary data, and control data supplied thereto, converts the parallel data into serial data, and transmits the data by a differential signal. Here, when the image data has, for example, three components of R (red), G (green), and B (blue), the B component (B component) is supplied to the encoder / serializer 81A, and the G component (G component) is The encoder / serializer 81B is supplied, and the R component (R component) is supplied to the encoder / serializer 81C.

  The auxiliary data includes, for example, audio data and control packets. The control packets are supplied to, for example, the encoder / serializer 81A, and the audio data is supplied to the encoder / serializers 81B and 81C.

  Further, the control data includes a 1-bit vertical synchronization signal (VSYNC), a 1-bit horizontal synchronization signal (HSYNC), and 1-bit control bits CTL0, CTL1, CTL2, and CTL3. The vertical synchronization signal and the horizontal synchronization signal are supplied to the encoder / serializer 81A. The control bits CTL0 and CTL1 are supplied to the encoder / serializer 81B, and the control bits CTL2 and CTL3 are supplied to the encoder / serializer 81C.

  The encoder / serializer 81A transmits the B component of the image data, the vertical synchronization signal and the horizontal synchronization signal, and auxiliary data supplied thereto in a time division manner. That is, the encoder / serializer 81A converts the B component of the image data supplied thereto into 8-bit parallel data that is a fixed number of bits. Further, the encoder / serializer 81A encodes the parallel data, converts it into serial data, and transmits it through the TMDS channel # 0.

  The encoder / serializer 81A encodes the 2-bit parallel data of the vertical synchronization signal and horizontal synchronization signal supplied thereto, converts the data into serial data, and transmits the serial data through the TMDS channel # 0. Furthermore, the encoder / serializer 81A converts the auxiliary data supplied thereto into parallel data in units of 4 bits. Then, the encoder / serializer 81A encodes the parallel data, converts it into serial data, and transmits it through the TMDS channel # 0.

  The encoder / serializer 81B transmits the G component of the image data, control bits CTL0 and CTL1, and auxiliary data supplied thereto in a time division manner. That is, the encoder / serializer 81B sets the G component of the image data supplied thereto as parallel data in units of 8 bits, which is a fixed number of bits. Further, the encoder / serializer 81B encodes the parallel data, converts it into serial data, and transmits it through the TMDS channel # 1.

  The encoder / serializer 81B encodes the 2-bit parallel data of the control bits CTL0 and CTL1 supplied thereto, converts the data into serial data, and transmits the serial data through the TMDS channel # 1. Furthermore, the encoder / serializer 81B converts the auxiliary data supplied thereto into parallel data in units of 4 bits. Then, the encoder / serializer 81B encodes the parallel data, converts it into serial data, and transmits it through the TMDS channel # 1.

  The encoder / serializer 81C transmits the R component of the image data, control bits CTL2 and CTL3, and auxiliary data supplied thereto in a time division manner. That is, the encoder / serializer 81C sets the R component of the image data supplied thereto as parallel data in units of 8 bits, which is a fixed number of bits. Further, the encoder / serializer 81C encodes the parallel data, converts it into serial data, and transmits it through the TMDS channel # 2.

  The encoder / serializer 81C encodes 2-bit parallel data of the control bits CTL2 and CTL3 supplied thereto, converts the data into serial data, and transmits the serial data through the TMDS channel # 2. Furthermore, the encoder / serializer 81C converts the auxiliary data supplied thereto into parallel data in units of 4 bits. Then, the encoder / serializer 81C encodes the parallel data, converts it into serial data, and transmits it through the TMDS channel # 2.

  The receiver 82 includes three recovery / decoders 82A, 82B, and 82C corresponding to the three TMDS channels # 0, # 1, and # 2, respectively. Then, each of the recovery / decoders 82A, 82B, and 82C receives image data, auxiliary data, and control data transmitted as differential signals through the TMDS channels # 0, # 1, and # 2. Further, each of the recovery / decoders 82A, 82B, and 82C converts the image data, auxiliary data, and control data from serial data to parallel data, and further decodes and outputs them.

  That is, the recovery / decoder 82A receives the B component of the image data, the vertical synchronization signal, the horizontal synchronization signal, and the auxiliary data that are transmitted as differential signals through the TMDS channel # 0. Then, the recovery / decoder 82A converts the B component of the image data, the vertical synchronization signal, the horizontal synchronization signal, and the auxiliary data from serial data to parallel data, and decodes and outputs them.

  The recovery / decoder 82B receives the G component of the image data, the control bits CTL0 and CTL1, and the auxiliary data transmitted by the differential signal through the TMDS channel # 1. Then, the recovery / decoder 82B converts the G component of the image data, the control bits CTL0 and CTL1, and the auxiliary data from serial data to parallel data, and decodes and outputs them.

  The recovery / decoder 82C receives the R component of the image data, the control bits CTL2 and CTL3, and the auxiliary data transmitted by the differential signal through the TMDS channel # 2. Then, the recovery / decoder 82C converts the R component of the image data, the control bits CTL2 and CTL3, and the auxiliary data from serial data to parallel data, and decodes and outputs them.

  FIG. 7 shows an example of a transmission section (period) in which various types of transmission data are transmitted through the three TMDS channels # 0, # 1, and # 2 of HDMI. Note that FIG. 7 shows sections of various transmission data when a progressive image of 720 × 480 pixels in width × length is transmitted in TMDS channels # 0, # 1, # 2.

  A video field (Video Field) in which transmission data is transmitted through the three TMDS channels # 0, # 1, and # 2 of HDMI includes a video data period (VideoData period) and a data island period ( There are three types of sections: Data Island period) and Control period.

  Here, the video field period is a period from the rising edge (active edge) of a certain vertical synchronizing signal to the rising edge of the next vertical synchronizing signal, and includes a horizontal blanking period (horizontal blanking) and a vertical blanking period (vertical blanking). In addition, the video field period is divided into an active video period (Active Video) that is a period excluding the horizontal blanking period and the vertical blanking period.

  The video data section is assigned to the active video section. In this video data section, data of effective pixels (Active pixels) corresponding to 720 pixels × 480 lines constituting uncompressed image data for one screen is transmitted.

  The data island period and the control period are assigned to the horizontal blanking period and the vertical blanking period. In the data island section and the control section, auxiliary data (Auxiliary data) is transmitted.

  That is, the data island period is assigned to a part of the horizontal blanking period and the vertical blanking period. In this data island period, for example, audio data packets, which are data not related to control, of auxiliary data are transmitted.

  The control period is allocated to other parts of the horizontal blanking period and the vertical blanking period. In this control period, for example, vertical synchronization signals, horizontal synchronization signals, control packets, and the like, which are data related to control, of auxiliary data are transmitted.

  Here, in the current HDMI, the frequency of the pixel clock transmitted through the TMDS clock channel is, for example, 165 MHz, and in this case, the transmission rate in the data island period is about 500 Mbps.

  FIG. 8 shows a pin arrangement of the HDMI terminals 11 and 31. This pin arrangement is called type A (type-A).

  Two lines, which are differential lines through which TMDS Data # i + and TMDS Data # i−, which are differential signals of TMDS channel #i, are transmitted are pins to which TMDS Data # i + is assigned (the pin number is 1). , 4, 7) and pins assigned with TMDS Data # i− (pin numbers 3, 6, 9).

  A CEC line 84 through which a CEC signal as control data is transmitted is connected to a pin having a pin number of 13, and a pin having a pin number of 14 is a reserved pin. Further, a line through which an SDA (Serial Data) signal such as E-EDID is transmitted is connected to a pin having a pin number of 16, and an SCL (Serial Clock) signal which is a clock signal used for synchronization when the SDA signal is transmitted and received. Is transmitted to a pin having a pin number of 15. The above-described DDC 83 includes a line for transmitting the SDA signal and a line for transmitting the SCL signal.

  Further, as described above, the line 86 for the source device to detect the connection of the sink device is connected to the pin having the pin number 19. Further, as described above, the line 87 for supplying power is connected to a pin having a pin number of 18.

  FIG. 9 shows a configuration example of the high-speed data line interface 12A of the personal computer 10 and the high-speed data line interface 32A of the television receiver 30 in the AV system 5 of FIG. These interfaces 12A and 32A constitute a communication unit that performs LAN (Local Area Network) communication. This communication unit is a pair of differential lines among a plurality of lines constituting the HDMI cable 1, and in this embodiment, a reserved line (Ether-line) corresponding to a vacant (Reserve) pin (14 pins) , And an HPD line (Ether + line) corresponding to the HPD pin (19 pin).

  The personal computer 10 includes a LAN signal transmission circuit 411, a termination resistor 412, AC coupling capacitors 413 and 414, a LAN signal reception circuit 415, a subtraction circuit 416, a pull-up resistor 421, a resistor 422 and a capacitor 423 constituting a low-pass filter, and a comparator. 424, a pull-down resistor 431, a resistor 432 and a capacitor 433 forming a low-pass filter, and a comparator 434. Here, the high-speed data line interface 12A includes a LAN signal transmission circuit 411, a termination resistor 412, AC coupling capacitors 413 and 414, a LAN signal reception circuit 415, and a subtraction circuit 416.

  A series circuit of a pull-up resistor 421, an AC coupling capacitor 413, a termination resistor 412, an AC coupling capacitor 414, and a pull-down resistor 431 is connected between the power supply line (+5.0 V) and the ground line. A connection point P1 between the AC coupling capacitor 413 and the termination resistor 412 is connected to the positive output side of the LAN signal transmission circuit 411 and to the positive input side of the LAN signal reception circuit 415. The connection point P2 between the AC coupling capacitor 414 and the termination resistor 412 is connected to the negative output side of the LAN signal transmission circuit 411 and to the negative input side of the LAN signal reception circuit 415. A transmission signal (transmission data) SG411 is supplied to the input side of the LAN signal transmission circuit 411.

  The output signal SG412 of the LAN signal receiving circuit 415 is supplied to the positive side terminal of the subtraction circuit 416, and the transmission signal (transmission data) SG411 is supplied to the negative side terminal of the subtraction circuit 416. In the subtracting circuit 416, the transmission signal SG411 is subtracted from the output signal SG412 of the LAN signal receiving circuit 415 to obtain a reception signal (reception data) SG413.

  In addition, a connection point Q1 between the pull-up resistor 421 and the AC coupling capacitor 413 is connected to the ground line through a series circuit of the resistor 422 and the capacitor 423. The output signal of the low-pass filter obtained at the connection point between the resistor 422 and the capacitor 423 is supplied to one input terminal of the comparator 424. In the comparator 424, the output signal of the low-pass filter is compared with a reference voltage Vref1 (+ 3.75V) supplied to the other input terminal. The output signal SG414 of the comparator 424 is supplied to the CPU 13.

  Further, a connection point Q2 between the AC coupling capacitor 414 and the pull-down resistor 431 is connected to the ground line via a series circuit of the resistor 432 and the capacitor 433. The output signal of the low-pass filter obtained at the connection point between the resistor 432 and the capacitor 433 is supplied to one input terminal of the comparator 434. In the comparator 434, the output signal of the low-pass filter is compared with a reference voltage Vref2 (+1.4 V) supplied to the other input terminal. An output signal SG415 of the comparator 434 is supplied to the CPU 13.

  The television receiver 30 includes a LAN signal transmission circuit 441, a termination resistor 442, AC coupling capacitors 443 and 444, a LAN signal reception circuit 445, a subtraction circuit 446, a pull-down resistor 451, a resistor 452 and a capacitor 453 constituting a low-pass filter, and a comparator. 454, a choke coil 461, a resistor 462, and a resistor 463. Here, the high-speed data line interface 32A includes a LAN signal transmission circuit 441, a termination resistor 442, AC coupling capacitors 443 and 444, a LAN signal reception circuit 445, and a subtraction circuit 446.

  A series circuit of a resistor 462 and a resistor 463 is connected between the power supply line (+5.0 V) and the ground line. A series circuit of a choke coil 461, an AC coupling capacitor 444, a termination resistor 442, an AC coupling capacitor 443, and a pull-down resistor 451 is connected between the connection point of the resistors 462 and 463 and the ground line. The

  A connection point P3 between the AC coupling capacitor 443 and the termination resistor 442 is connected to the positive output side of the LAN signal transmission circuit 441 and to the positive input side of the LAN signal reception circuit 445. A connection point P4 between the AC coupling capacitor 444 and the termination resistor 442 is connected to the negative output side of the LAN signal transmission circuit 441 and to the negative input side of the LAN signal reception circuit 445. A transmission signal (transmission data) SG417 is supplied to the input side of the LAN signal transmission circuit 441.

  The output signal SG418 of the LAN signal receiving circuit 445 is supplied to the positive terminal of the subtracting circuit 446, and the transmission signal SG417 is supplied to the negative terminal of the subtracting circuit 446. In the subtracting circuit 446, the transmission signal SG417 is subtracted from the output signal SG418 of the LAN signal receiving circuit 445 to obtain a reception signal (reception data) SG419.

  The connection point Q3 between the pull-down resistor 451 and the AC coupling capacitor 443 is connected to the ground line via a series circuit of the resistor 452 and the capacitor 453. The output signal of the low-pass filter obtained at the connection point between the resistor 452 and the capacitor 453 is supplied to one input terminal of the comparator 454. In this comparator 454, the output signal of the low-pass filter is compared with a reference voltage Vref3 (+1.25 V) supplied to the other input terminal. The output signal SG416 of the comparator 454 is supplied to the CPU 51.

  The reserved line 501 and the HPD line 502 included in the HDMI cable 1 constitute a differential twisted pair. The source side end 511 of the reserved line 501 is connected to the 14th pin of the HDMI terminal 11, and the sink side end 521 of the reserved line 501 is connected to the 14th pin of the HDMI terminal 31. The source side end 512 of the HPD line 502 is connected to the 19th pin of the HDMI terminal 11, and the sink side end 522 of the HPD line 502 is connected to the 19th pin of the HDMI terminal 31.

  In the personal computer 10, the connection point Q1 between the pull-up resistor 421 and the AC coupling capacitor 413 described above is connected to the 14th pin of the HDMI terminal 11, and the connection point between the pull-down resistor 431 and the AC coupling capacitor 414 described above. Q2 is connected to the 19th pin of the HDMI terminal 11. On the other hand, in the television receiver 30, the connection point Q3 between the pull-down resistor 451 and the AC coupling capacitor 443 is connected to the 14th pin of the HDMI terminal 31, and the choke coil 461 and the AC coupling capacitor 444 are connected to each other. The connection point Q4 is connected to the 19th pin of the HDMI terminal 31.

  Next, the operation of LAN communication by the high-speed data line interfaces 12A and 32A configured as described above will be described.

  In the personal computer 10, the transmission signal (transmission data) SG411 is supplied to the input side of the LAN signal transmission circuit 411, and the differential signal (positive output signal, negative output signal) corresponding to the transmission signal SG411 from the LAN signal transmission circuit 411. Is output. The differential signal output from the LAN signal transmission circuit 411 is supplied to the connection points P1 and P2, and is transmitted to the television receiver 30 through a pair of lines (reserved line 501 and HPD line 502) of the HDMI cable 1. Is done.

  In the television receiver 30, a transmission signal (transmission data) SG 417 is supplied to the input side of the LAN signal transmission circuit 441, and a differential signal (positive output signal, negative signal) corresponding to the transmission signal SG 417 is transmitted from the LAN signal transmission circuit 441. Output signal) is output. The differential signal output from the LAN signal transmission circuit 441 is supplied to the connection points P3 and P4, and is transmitted to the personal computer 10 through a pair of lines (the reserve line 501 and the HPD line 502) of the HDMI cable 1. The

  Further, in the personal computer 10, since the input side of the LAN signal receiving circuit 415 is connected to the connection points P1 and P2, the output signal SG412 of the LAN signal receiving circuit 415 is output from the LAN signal transmitting circuit 411. An addition signal of the transmission signal corresponding to the differential signal (current signal) and the reception signal corresponding to the differential signal transmitted from the television receiver 30 as described above is obtained. In the subtracting circuit 416, the transmission signal SG411 is subtracted from the output signal SG412 of the LAN signal receiving circuit 415. Therefore, the output signal SG413 of the subtraction circuit 416 corresponds to the transmission signal (transmission data) SG417 of the television receiver 30.

  In the television receiver 30, the input side of the LAN signal receiving circuit 445 is connected to the connection points P 3 and P 4, so that it is output from the LAN signal transmitting circuit 441 as the output signal SG 418 of the LAN signal receiving circuit 445. As described above, an addition signal of the transmission signal corresponding to the differential signal (current signal) and the reception signal corresponding to the differential signal transmitted from the personal computer 10 is obtained. In the subtracting circuit 446, the transmission signal SG417 is subtracted from the output signal SG418 of the LAN signal receiving circuit 445. Therefore, the output signal SG419 of the subtracting circuit 446 corresponds to the transmission signal (transmission data) SG411 of the personal computer 10.

  In this manner, bidirectional LAN communication can be performed between the high-speed data line interface 12A of the personal computer 10 and the high-speed data line interface 32A of the television receiver 30.

  According to the configuration example shown in FIG. 9, a single HDMI cable 1 is used to transfer video and audio data, exchange and connection device information exchange and authentication, communication of device control data, and LAN communication. Since the interface connection state is notified by the DC bias potential of at least one of the transmission lines, the SCL line and the SDA line are physically used for LAN communication. Spatial separation can be performed. As a result, a circuit for LAN communication can be formed by the division regardless of the electrical specifications defined for DDC, and stable and reliable LAN communication can be realized at low cost.

  In FIG. 9, the HPD line 502 transmits to the personal computer 10 that the HDMI cable 1 is connected to the television receiver 30 at a DC bias level in addition to the LAN communication described above. That is, the resistors 462 and 463 and the choke coil 461 in the television receiver 30 connect the HPD line 502 to about 4 V via the 19th pin of the HDMI terminal 31 when the HDMI cable 1 is connected to the television receiver 30. Bias. The personal computer 10 extracts the DC bias of the HPD line 502 with a low-pass filter composed of a resistor 432 and a capacitor 433, and compares it with a reference voltage Vref2 (for example, 1.4 V) by a comparator 434.

  The 19-pin voltage of the HDMI terminal 11 is lower than the reference voltage Vref2 because the pull-down resistor 431 exists when the HDMI cable 1 is not connected to the television receiver 30. Conversely, the HDMI cable 1 is connected to the television receiver 30. Is higher than the reference voltage Vref2. Therefore, the output signal SG415 of the comparator 434 is at a high level when the HDMI cable 1 is connected to the television receiver 30, and is at a low level otherwise. Thus, the CPU 13 of the personal computer 10 can recognize whether the HDMI cable 1 is connected to the television receiver 30 based on the output signal SG415 of the comparator 434.

  In FIG. 9, whether the devices connected to both ends of the HDMI cable 1 with the DC bias potential of the reserved line 501 are devices capable of LAN communication (hereinafter referred to as “e-HDMI compatible devices”), It has a function of mutually recognizing whether it is a device incapable of communication (hereinafter, “e-HDMI non-compliant device”).

  As described above, the personal computer 10 pulls up the reserve line 501 with the resistor 421 (+5 V), and the television receiver 30 pulls down the reserve line 501 with the resistor 451. The resistors 421 and 451 do not exist in an e-HDMI non-compliant device.

  As described above, the personal computer 10 uses the comparator 424 to compare the DC potential of the reserved line 501 that has passed through the low-pass filter including the resistor 422 and the capacitor 423 with the reference voltage Vref1. When the television receiver 30 is an e-HDMI compatible device and has a pull-down resistor 451, the voltage of the reserved line 501 is 2.5V. However, when the television receiver 30 is an e-HDMI non-compliant device and does not have the pull-down resistor 451, the voltage of the reserved line 501 becomes 5V due to the presence of the pull-up resistor 421.

  Therefore, the reference voltage Vref1 is set to 3.75 V, for example, so that the output signal SG414 of the comparator 424 is at a low level when the television receiver 30 is an e-HDMI compatible device, and is at a high level otherwise. Become. Thereby, the CPU 13 of the personal computer 10 can recognize whether or not the television receiver 30 is an e-HDMI compatible device based on the output signal SG414 of the comparator 424.

  Similarly, as described above, the television receiver 30 uses the comparator 454 to compare the DC potential of the reserved line 501 that has passed through the low-pass filter including the resistor 452 and the capacitor 453 with the reference voltage Vref3. When the personal computer 10 is an e-HDMI compatible device and has a pull-up resistor 421, the voltage of the reserved line 501 is 2.5V. However, when the personal computer 10 is an e-HDMI non-compliant device and does not have the pull-up resistor 421, the voltage of the reserved line 501 becomes 0 V due to the presence of the pull-down resistor 451.

  Therefore, when the reference voltage Vref3 is set to 1.25 V, for example, the output signal SG416 of the comparator 454 is at a high level when the personal computer 10 is an e-HDMI compatible device, and is at a low level otherwise. . Thereby, the CPU 51 of the television receiver 30 can recognize whether or not the personal computer 10 is an e-HDMI compatible device based on the output signal SG416 of the comparator 454.

  Next, an example of a firewall release sequence for the television receiver 30 of the personal computer 10 will be described with reference to FIG. For command abbreviations, “Open RQ” indicates “Open Request”, “Open Res” indicates “Open Response”, “Close RQ” indicates “Close Request”, and “Close Res” indicates “ "Close Response" indicates "IP_AD" indicates "IP Address". This command abbreviation is the same in FIG.

  (A) When the personal computer 10 and the television receiver 30 are connected via the HDMI cable 1, a power of +5 V from the power terminal (+5 V Power terminal) of the personal computer 10 is connected via the HDMI cable 1 to the television receiver 30. To the power supply terminal (+ 5V Power terminal) (see FIG. 5). (B) Thereby, the HPD terminal of the television receiver 30 and the HPD terminal of the personal computer 10 become approximately +5 V, and it is detected that the television receiver 30 and the personal computer 10 are connected by the HDMI cable 1.

  (C) The CPU 51 of the television receiver 30 transmits a CEC Firewall release command to the personal computer 10 using the CEC line of the HDMI cable 1. Here, as the command system, for example, as shown in FIG. 11, a Vender <Maker> specific OP code in the Vender Specific command is used. This command includes the IP address (IP AD) of the television receiver 30 and the port number (Port #) for requesting release in the data portion.

  (D) The CPU 13 of the personal computer 10 receives the CEC Firewall release command from the television receiver 30 and performs appropriate Firewall open processing. That is, the CPU 13 cancels the access restriction for the IP address included in the CEC Firewall cancel command, and releases the port (port) of the port number included in the command. (E) The personal computer 10 transmits a CEC release response command to the television receiver 30 using the CEC line of the HDMI cable 1 after the Firewallopen process is completed.

  (F) The CPU 51 of the television receiver 30 receives the CEC release response command from the personal computer 10 and recognizes that transmission on the high-speed data line (Ether Line) is possible. (G) Thereafter, If necessary, data transmission is performed using a high-speed data line.

  Thereafter, when the personal computer 10 is turned on (including the standby state) and the power switch of the television receiver 30 is pressed to start the power-off process, (h) the CPU 51 of the television receiver 30 Then, the CEC Firewall release end command is transmitted to the personal computer 10 using the CEC line of the HDMI cable 1.

  (I) The CPU 13 of the personal computer 10 receives the CEC Firewall release end command from the television receiver 30 and (j) immediately transmits a CEC release end response command to the television receiver 30. (K) The CPU 51 of the television receiver 30 receives the CEC cancellation end response command from the personal computer 10 and ends the firewall cancellation sequence. The television receiver 30 enters a substantial power-off process after completing the firewall release sequence in this way.

  (M) The CPU 13 of the personal computer 10 performs Firewall close processing for canceling the firewall release after a sufficient time has elapsed for the television receiver 30 to receive the CEC release end response command. In this Firewall close process, the opening of the port for which the firewall has been canceled is stopped, and the access restriction for the IP address that has become accessible is resumed.

  According to the firewall release sequence shown in FIG. 10, the firewall for the television receiver 30 in the personal computer 10 is automatically set when the television receiver 30 is connected to the personal computer 10 via the HDMI cable 1. The connection is secured by being released, and data transmission using the high-speed data line from the television receiver 30 to the personal computer 10 becomes possible. Further, according to the firewall release sequence shown in FIG. 10, when a power-off operation is performed in the television receiver 30 in a state where the firewall for the television receiver 30 in the personal computer 10 is released, Canceling is automatically canceled.

  Next, with reference to FIG. 12, another example of the firewall cancellation sequence for the television receiver 30 of the personal computer 10 will be described.

  (A) When the personal computer 10 and the television receiver 30 are connected via the HDMI cable 1, a power of +5 V from the power terminal (+5 V Power terminal) of the personal computer 10 is connected via the HDMI cable 1 to the television receiver 30. To the power supply terminal (+ 5V Power terminal) (see FIG. 5). (B) Thereby, the HPD terminal of the television receiver 30 and the HPD terminal of the personal computer 10 become approximately +5 V, and it is detected that the television receiver 30 and the personal computer 10 are connected by the HDMI cable 1.

  (C) When there is a request for data transmission through a high-speed data line (Ether Line), (d) the CPU 51 of the television receiver 30 sends a CEC Firewall release command to the personal computer 10 using the CEC line of the HDMI cable 1. Send. This command includes the IP address (IP AD) of the television receiver 30 and the port number (Port #) for requesting release in the data portion.

  (E) The CPU 13 of the personal computer 10 receives the CEC Firewall release command from the television receiver 30 and performs appropriate Firewall open processing. That is, the CPU 13 cancels the access restriction for the IP address included in the CEC Firewall cancel command, and releases the port (port) of the port number included in the command. (F) The personal computer 10 then transmits a CEC release response command to the television receiver 30 using the CEC line of the HDMI cable 1 after the Firewallopen process is completed.

  (G) The CPU 51 of the television receiver 30 receives the CEC cancellation response command from the personal computer 10, recognizes that transmission on the high-speed data line (Ether Line) is possible, and (h) high-speed data. Data transmission is performed using a line.

  (I) When data transmission is completed, (j) the CPU 51 of the television receiver 30 transmits a CEC Firewall release termination command to the personal computer 10 using the CEC line of the HDMI cable 1.

  (K) The CPU 13 of the personal computer 10 receives the CEC Firewall release end command from the television receiver 30 and (m) immediately transmits a CEC release end response command to the television receiver 30. (N) The CPU 51 of the television receiver 30 receives the CEC cancellation end response command from the personal computer 10 and ends the firewall cancellation sequence.

  (P) The CPU 13 of the personal computer 10 performs Firewall close processing for canceling the firewall release after a sufficient time has elapsed for the television receiver 30 to receive the CEC release end response command. In this Firewall close process, the opening of the port for which the firewall has been canceled is stopped, and the access restriction for the IP address that has become accessible is resumed.

  According to the firewall release sequence shown in FIG. 12, when there is a request for data transmission using a high-speed data line, the firewall for the television receiver 30 in the personal computer 10 is automatically released, and the high-speed data line is used. Data transmission is possible. Further, according to the firewall cancellation sequence shown in FIG. 12, when the data transmission by the high-speed data line is completed, the cancellation of the firewall for the television receiver 30 in the personal computer 10 is automatically stopped.

  In the firewall cancellation sequence shown in FIG. 12, the CEC Firewall cancellation command transmission sequence starts from the television receiver 30 side (see FIG. 12D). However, the CEC Firewall release command transmission sequence can be started from the personal computer 10 side.

  When there is a request for data transmission through the high-speed data line, the CPU 13 of the personal computer 10 transmits a CEC Firewall release command to the television receiver 30 with an IP address and a port number of Null. The CPU 51 of the television receiver 30 that has received this CEC Firewall cancel command enters the IP address and port number necessary for the CEC Firewall cancel command and returns them to the personal computer 10. The subsequent steps are the same as the sequence shown in FIG.

  Further, when starting the transmission sequence of the CEC Firewall cancellation command from the personal computer 10 side in this way, instead of transmitting the CEC Firewall cancellation command with the IP address and port number being Null, the CPU 13 of the personal computer 10 does not transmit the CEC Firewall cancellation command. In addition, a command that instructs to start the transmission sequence of the CEC Firewall release command, for example, CEC [open sequence start] Command may be transmitted.

  As described above, according to the firewall release sequence shown in FIGS. 10 and 12, the personal computer 10 automatically sends a CEC Firewall release command to the personal computer 10 so that an appropriate firewall can be automatically set. The release is performed, security and connectivity can be ensured without complicated settings by the user, and the usability of the user is improved.

  Further, according to the firewall release sequence shown in FIGS. 10 and 12, when the television receiver 30 is connected to the personal computer 10 via the HDMI cable 1, or when there is a request for data transmission through a high-speed data line. The firewall for the television receiver 30 in the personal computer 10 is automatically released, and the firewall can be released in a timely manner at an appropriate time.

  Although not in the firewall release sequence shown in FIGS. 10 and 12, the firewall close process is not normally performed in the state where the firewall for the television receiver 30 is released in the personal computer 10. When the connection between the personal computer 10 and the television receiver 30 is disconnected, the personal computer 10 can know that the connection has been disconnected by HPD detection. The personal computer 10 performs Firewall close processing when it is detected that the connection with the television receiver 30 has been disconnected.

  Further, in the above description, the firewall cancellation setting has been shown to perform both port setting and IP address setting. However, the cancellation setting such as only the port setting or only the IP address setting is performed as necessary. You may adjust. Further, the television receiver 30 may change the port number for requesting cancellation of the firewall to an appropriate number for each communication in order to increase security.

  Further, in the description of the firewall release sequence shown in FIGS. 10 and 12, the case where the IP address and the port number are included in the data part of the CEC Firewall release command has been described. In order to increase the security of the release data sent from the television receiver 30 to the personal computer 10 via the CEC line, the following operation may be added.

  (1) In addition to the IP address and port number, a MAC address or the like may be added to the data transmitted by CEC, or the combination thereof may be changed.

  (2) Since the information on the CEC line is transmitted to all connected to the television receiver 30, it is necessary to be cautious when transmitting the release data. Therefore, the following operations may be added to increase security (to prevent impersonation and schemes).

(A) Only the firewall release signal is valid.
(B) Encrypt the release data to be sent.
(C) After the Ether connection is established, the port transfer data to another port is sent quickly on the ether line, and the stream transmission is mainly performed at that portion. That is, the port setting in CEC is used for introduction to Ether.
(D) Port change and release are not performed on the CEC line, but are performed with DTCP-IP applied on the ether line.
(E) The above (a) to (d) are used in combination.

  In the AV system 5 shown in FIG. 1, a communication unit that performs bidirectional communication is configured using a reserved line (Ether-line) and an HPD line (Ether + line) of the HDMI cable 1. The configuration of the communication unit that performs bidirectional communication (see FIG. 9) is not limited to this. Other configuration examples will be described below. In the following example, the personal computer 10 is described as a source device, and the television receiver 30 is described as a sink device.

  FIG. 13 shows an example in which IP communication is performed by a half-duplex communication method using the CEC line 84 and the reserved line 88. In FIG. 13, portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The high-speed data line interface 12A of the source device includes a conversion unit 131, a decoding unit 132, a switch 133, a switching control unit 121, and a timing control unit 122. The conversion unit 131 is supplied with Tx data that is data transmitted from the source device to the sink device by bidirectional IP communication between the source device and the sink device.

  The conversion unit 131 is configured by, for example, a differential amplifier, and converts the supplied Tx data into a differential signal composed of two partial signals. In addition, the conversion unit 131 transmits the differential signal obtained by the conversion to the sink device via the CEC line 84 and the reserved line 88. That is, the converting unit 131 is a CEC line 84, more specifically a signal line provided in the source device, that is one of the partial signals constituting the differential signal obtained by the conversion, and the CEC line 84 of the HDMI cable 1 The other partial signal constituting the differential signal is supplied to the switch 133 via the signal line connected to the reserve line 88, more specifically, a signal line provided in the source device, and the HDMI cable 1 The signal line connected to the reserve line 88 and the reserve line 88 are supplied to the sink device.

  The decoding unit 132 is configured by, for example, a differential amplifier, and its input terminal is connected to the CEC line 84 and the reserved line 88. Based on the control of the timing control unit 122, the decoding unit 132 transmits the differential signal transmitted from the sink device via the CEC line 84 and the reserved line 88, that is, the partial signal on the CEC line 84 and the reserved line 88. A differential signal composed of partial signals is received, decoded into Rx data which is the original data, and output. Here, the Rx data is data transmitted from the sink device to the source device by bidirectional IP communication between the source device and the sink device.

  The switch 133 is supplied with a partial signal constituting a differential signal corresponding to the CEC signal from the control unit (CPU) of the source device or the Tx data from the conversion unit 131 at the timing of transmitting the data. At the reception timing, a CEC signal from the sink device or a partial signal constituting a differential signal corresponding to the Rx data from the sink device is supplied. Based on the control from the switching control unit 121, the switch 133 is a CEC signal from the control unit (CPU), a CEC signal from the sink device, or a partial signal constituting a differential signal corresponding to Tx data, or Rx Select and output a partial signal constituting a differential signal corresponding to data.

  That is, the switch 133 selects either the CEC signal supplied from the control unit (CPU) or the partial signal supplied from the conversion unit 131 at the timing when the source device transmits data to the sink device. The selected CEC signal or partial signal is transmitted to the sink device via the CEC line 84.

  The switch 133 is a portion of the differential signal corresponding to the CEC signal transmitted from the sink device via the CEC line 84 or the Rx data at the timing when the source device receives the data transmitted from the sink device. The signal is received, and the received CEC signal or partial signal is supplied to the control unit (CPU) or the decoding unit 132.

  The switching control unit 121 controls the switch 133 to switch the switch 133 so that one of the signals supplied to the switch 133 is selected. The timing control unit 122 controls the reception timing of the differential signal by the decoding unit 132.

  Further, the high-speed data line interface 32A of the sink device includes a conversion unit 134, a decoding unit 136, a switch 135, a switching control unit 124, and a timing control unit 123. The conversion unit 134 is configured by, for example, a differential amplifier, and Rx data is supplied to the conversion unit 134. Based on the control of the timing control unit 123, the conversion unit 134 converts the supplied Rx data into a differential signal composed of two partial signals, and the differential signal obtained by the conversion is converted into a CEC line 84 and a reserved line 88. To the source device via

  That is, the conversion unit 134 is a signal line provided in the CEC line 84, more specifically, a sink device, for one partial signal constituting the differential signal obtained by the conversion, and the CEC line 84 of the HDMI cable 1. The other partial signal constituting the differential signal is supplied to the switch 135 via the signal line connected to the reserve line 88, more specifically, a signal line provided in the sink device, and the HDMI cable 1 The signal line connected to the reserve line 88 and the reserve line 88 are supplied to the source device.

  The switch 135 is supplied with a partial signal constituting a differential signal corresponding to the CEC signal from the source device or the Tx data from the source device at the timing of receiving data, and at the timing of transmitting the data, the conversion unit A partial signal constituting a differential signal corresponding to the Rx data from 134 or a CEC signal from the control unit (CPU) of the sink device is supplied. Based on the control from the switching control unit 124, the switch 135 is a CEC signal from the source device, a CEC signal from the control unit (CPU), or a partial signal constituting a differential signal corresponding to Tx data, or Rx Select and output a partial signal constituting a differential signal corresponding to data.

  That is, the switch 135 selects either the CEC signal supplied from the control unit (CPU) of the sink device or the partial signal supplied from the conversion unit 134 at the timing when the sink device transmits data to the source device. The selected CEC signal or partial signal is transmitted to the source device via the CEC line 84.

  The switch 135 is a portion of the differential signal corresponding to the CEC signal transmitted from the source device via the CEC line 84 or the Tx data at the timing at which the sink device receives the data transmitted from the source device. The signal is received, and the received CEC signal or partial signal is supplied to the control unit (CPU) or the decoding unit 136.

  The decoding unit 136 is configured by, for example, a differential amplifier, and its input terminal is connected to the CEC line 84 and the reserved line 88. The decoding unit 136 receives a differential signal transmitted from the source device via the CEC line 84 and the reserved line 88, that is, a differential signal composed of a partial signal on the CEC line 84 and a partial signal on the reserved line 88. The original data is decoded into Tx data and output.

  The switching control unit 124 controls the switch 135 to switch the switch 135 so that one of the signals supplied to the switch 135 is selected. The timing control unit 123 controls the transmission timing of the differential signal by the conversion unit 134.

  FIG. 14 shows a full-duplex communication IP using a CEC line 84 and a reserved line 88, a signal line (SDA line) for transmitting an SDA signal, and a signal line (SCL line) for transmitting an SCL signal. It is an example which performs communication. In FIG. 14, portions corresponding to those in FIG. 13 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The high-speed data line interface 12A of the source device includes a conversion unit 131, a switch 133, a switch 181, a switch 182, a decoding unit 183, a switching control unit 121, and a switching control unit 171.

  The switch 181 is supplied with the SDA signal from the control unit (CPU) of the source device at the timing of data transmission, and is converted into the SDA signal from the sink device or the Rx data from the sink device at the timing of data reception. A partial signal constituting a corresponding differential signal is supplied. The switch 181 selects a partial signal constituting a differential signal corresponding to the SDA signal from the control unit (CPU), the SDA signal from the sink device, or the Rx data based on the control from the switching control unit 171. Output.

  That is, the switch 181 receives the SDA signal transmitted from the sink device via the SDA line 191 that is a signal line to which the SDA signal is transmitted, or the timing at which the source device receives data transmitted from the sink device, or A partial signal of the differential signal corresponding to the Rx data is received, and the received SDA signal or partial signal is supplied to the control unit (CPU) or the decoding unit 183.

  The switch 181 transmits the SDA signal supplied from the control unit (CPU) to the sink device via the SDA line 191 at the timing when the source device transmits data to the sink device, or Also do not send.

  The switch 182 is supplied with an SCL signal from the control unit (CPU) of the source device at the timing of transmitting data, and forms a differential signal corresponding to the Rx data from the sink device at the timing of receiving data. A partial signal is supplied. The switch 182 selects and outputs either the SCL signal or the partial signal constituting the differential signal corresponding to the Rx data based on the control from the switching control unit 171.

  That is, the switch 182 receives Rx data transmitted from the sink device via the SCL line 192, which is a signal line to which the SCL signal is transmitted, at a timing when the source device receives data transmitted from the sink device. A corresponding partial signal of the differential signal is received, and the received partial signal is supplied to the decoding unit 183 or nothing is received.

  The switch 182 transmits the SCL signal supplied from the control unit (CPU) of the source device to the sink device via the SCL line 192 at the timing when the source device transmits data to the sink device, or what Also do not send.

  The decoding unit 183 is configured by, for example, a differential amplifier, and its input terminal is connected to the SDA line 191 and the SCL line 192. The decoding unit 183 receives a differential signal transmitted from the sink device via the SDA line 191 and the SCL line 192, that is, a differential signal composed of a partial signal on the SDA line 191 and a partial signal on the SCL line 192. , The original data is decoded into Rx data and output.

  The switching control unit 171 controls the switch 181 and the switch 182 to switch the switch 181 and the switch 182 so that one of the supplied signals is selected for each of the switch 181 and the switch 182.

  The high-speed data line interface 32A constituting the sink device includes a conversion unit 184, a switch 135, a switch 185, a switch 186, a decoding unit 136, a switching control unit 172, and a switching control unit 124.

  The conversion unit 184 is configured by, for example, a differential amplifier, and Rx data is supplied to the conversion unit 184. The converter 184 converts the supplied Rx data into a differential signal composed of two partial signals, and transmits the differential signal obtained by the conversion to the source device via the SDA line 191 and the SCL line 192. That is, the conversion unit 184 transmits one partial signal constituting the differential signal obtained by the conversion to the source device via the switch 185, and transmits the other partial signal constituting the differential signal via the switch 186. Send to source device.

  The switch 185 is supplied with the partial signal constituting the differential signal corresponding to the Rx data from the conversion unit 184 or the SDA signal from the control unit (CPU) of the sink device at the data transmission timing. At the reception timing, the SDA signal from the source device is supplied. The switch 185 selects the SDA signal from the control unit (CPU), the SDA signal from the source device, or the partial signal constituting the differential signal corresponding to the Rx data based on the control from the switching control unit 172. Output.

  That is, the switch 185 receives the SDA signal transmitted from the source device via the SDA line 191 at the timing when the sink device receives the data transmitted from the source device, and the received SDA signal is transmitted to the control unit ( CPU) or receive nothing.

  In addition, the switch 185 sends the SDA signal supplied from the control unit (CPU) or the partial signal supplied from the conversion unit 184 to the source via the SDA line 191 at the timing when the sink device transmits data to the source device. Send to device.

  The switch 186 is supplied with the partial signal constituting the differential signal corresponding to the Rx data from the conversion unit 184 at the timing of transmitting data, and is supplied with the SCL signal from the source device at the timing of receiving data. Is done. The switch 186 selects and outputs either a partial signal constituting a differential signal corresponding to the Rx data or an SCL signal based on the control from the switching control unit 172.

  That is, the switch 186 receives the SCL signal transmitted from the source device via the SCL line 192 at the timing at which the sink device receives data transmitted from the source device, and the received SCL signal is transmitted to the control unit ( CPU) or receive nothing.

  In addition, the switch 186 transmits the partial signal supplied from the conversion unit 184 to the source device via the SCL line 192 or transmits nothing at the timing when the sink device transmits data to the source device.

  The switching control unit 172 controls the switch 185 and the switch 186, and switches the switch 185 and the switch 186 so that one of the supplied signals is selected for each of the switch 185 and the switch 186.

  By the way, when the source device and the sink device perform IP communication, whether half-duplex communication or full-duplex communication is possible depends on the configuration of the source device and the sink device. Therefore, the source device refers to the E-EDID received from the sink device and determines whether to perform half-duplex communication, full-duplex communication, or bidirectional communication by exchanging CEC signals. Do.

  The E-EDID received by the source device includes, for example, a basic block and an extended block as shown in FIG.

  At the beginning of the basic block of E-EDID, data defined by the E-EDID1.3 standard represented by “E-EDID1.3 Basic Structure” is arranged, and subsequently represented by “Preferred timing”. Timing information for maintaining compatibility with the conventional EDID and timing information different from “Preferred timing” for maintaining compatibility with the conventional EDID represented by “2nd timing” are arranged.

  The basic block includes information indicating the name of the display device represented by “Monitor NAME” following “2nd timing”, and aspect ratios represented by “Monitor Range Limits” of 4: 3 and 16 : Information indicating the number of displayable pixels in the case of 9 is arranged in order.

  On the other hand, information about the left and right speakers represented by “Speaker Allocation” is arranged at the head of the extension block, and subsequently, the displayable image size, frame rate, and interlace represented by “VIDEO SHORT”. Information indicating whether the image is progressive or progressive, data in which information such as an aspect ratio is described, audio audio codec format represented by “AUDIO SHORT”, sampling frequency, cutoff band, codec bit number, etc. Data in which information is described, and information on left and right speakers represented by “Speaker Allocation” are arranged in order.

  In addition, the extension block maintains compatibility with the conventional EDID represented by “3rd timing”, the data defined uniquely for each manufacturer represented by “Vender Specific” following “Speaker Allocation”. Timing information for maintaining compatibility with the conventional EDID represented by “4th timing” is arranged.

  Furthermore, the data represented by “Vender Specific” has a data structure shown in FIG. That is, the data represented by “Vender Specific” is provided with 0th to Nth blocks which are 1-byte blocks.

  In the 0th block arranged at the head of the data represented by “Vender Specific”, a header indicating a data area of data “Vender Specific” (“Vender-Specific tag code (= 3)”) and “Vendor Specific” Information indicating the length of the data “Vender Specific” represented by “Length (= N)” is arranged.

  In the first to third blocks, information indicating the number “0x000C03” registered for HDMI (R) represented by “24-bit IEEE Registration Identifier (0x000C03) LSB first” is arranged. Further, in the fourth block and the fifth block, information indicating the physical address of the 24-bit sink device represented by “A”, “B”, “C”, and “D” is arranged.

  The sixth block is represented by a flag indicating a function supported by the sink device represented by “Supports-AI”, “DC-48 bit”, “DC-36 bit”, and “DC-30 bit”. Each of the information specifying the number of bits per pixel, a flag indicating whether the sink device supports transmission of a YCbCr4: 4: 4 image, represented by “DC-Y444”, and “DVI-Dual A flag indicating whether the sink device corresponds to dual DVI (Digital Visual Interface) is arranged.

  In the seventh block, information indicating the maximum frequency of the TMDS pixel clock represented by “Max-TMDS-Clock” is arranged. Further, the eighth block includes a flag indicating the presence / absence of video and audio delay information represented by “Latency”, and a full-duplex flag representing whether full-duplex communication is possible represented by “Full Duplex”. And a half-duplex flag indicating whether or not half-duplex communication represented by “Half Duplex” is possible.

  Here, for example, the full-duplex flag that is set (for example, set to “1”) has a function in which the sink device performs full-duplex communication, that is, the configuration shown in FIG. The full-duplex flag that is reset (for example, set to “0”) indicates that the sink device does not have a function of performing full-duplex communication.

  Similarly, the half-duplex flag that is set (for example, set to “1”) has a function for the sink device to perform half-duplex communication, that is, the configuration shown in FIG. The half-duplex flag that is reset (for example, set to “0”) indicates that the sink device does not have a function of performing half-duplex communication.

  Also, progressive video delay time data represented by “Video Latency” is arranged in the ninth block of data represented by “Vender Specific”, and “Audio Latency” is represented by the tenth block. The audio delay time data associated with the progressive video is arranged. Furthermore, in the eleventh block, delay time data of an interlaced video represented by “Interlaced Video Latency” is arranged, and in the twelfth block, an interlaced video represented by “Interlaced Audio Latency” is attached. Audio delay time data is arranged.

  The source device performs half-duplex communication, full-duplex communication, or CEC signal based on the full-duplex flag and half-duplex flag included in the E-EDID received from the sink device. It is determined whether to perform bidirectional communication by sending and receiving, and bidirectional communication with the sink device is performed according to the determination result.

  For example, when the source device has the configuration shown in FIG. 13, the source device can perform half-duplex communication with the sink device shown in FIG. 13, but with the sink device shown in FIG. Half-duplex communication is not possible. Therefore, the source device starts communication processing when the source device is turned on, and performs bidirectional communication according to the function of the sink device connected to the source device.

  Hereinafter, communication processing by the source device shown in FIG. 13 will be described with reference to the flowchart of FIG.

  In step S11, the source device determines whether a new electronic device is connected to the source device. For example, the source device determines whether or not a new electronic device (sink device) is connected based on the magnitude of the voltage added to a pin called Hot Plug Detect to which the HPD line 86 is connected. .

  If it is determined in step S11 that a new electronic device is not connected, communication is not performed, and the communication process ends. On the other hand, if it is determined in step S11 that a new electronic device has been connected, in step S12, the switching control unit 121 controls the switch 133, and at the time of data transmission, the control unit (CPU) of the source device. The switch 133 is switched so that the CEC signal from the sink device is selected at the time of data reception.

  In step S <b> 13, the source device receives the E-EDID transmitted from the sink device via the DDC 83. That is, when the sink device detects the connection of the source device, the sink device reads the E-EDID from the EDID ROM 85 and transmits the read E-EDID to the source device via the DDC 83, so the source device has been transmitted from the sink device. Receive E-EDID.

  In step S14, the source device determines whether half-duplex communication with the sink device is possible. That is, the source device refers to the E-EDID received from the sink device and determines whether or not the half duplex flag “Half Duplex” in FIG. 16 is set. For example, the half duplex flag is set. The source device determines that bidirectional IP communication using the half-duplex communication method, that is, half-duplex communication is possible.

  If it is determined in step S14 that half-duplex communication is possible, in step S15, the source device uses the CEC line 84 and the reserved line 88 as channel information indicating channels used for bidirectional communication. A signal indicating that IP communication is performed by the duplex communication method is transmitted to the sink device via the switch 133 and the CEC line 84.

  That is, when the half-duplex flag is set, it can be seen that the source device has the configuration shown in FIG. 13 as the sink device and can perform half-duplex communication using the CEC line 84 and the reserved line 88. Therefore, the channel information is transmitted to the sink device to notify that half duplex communication is to be performed.

  In step S16, the switching control unit 121 controls the switch 133 so that a differential signal corresponding to the Tx data from the conversion unit 131 is selected at the time of data transmission and corresponds to the Rx data from the sink device at the time of data reception. The switch 133 is switched so that the differential signal to be selected is selected.

  In step S17, each unit of the source device performs bidirectional IP communication with the sink device using the half-duplex communication method, and the communication process ends. That is, at the time of data transmission, the conversion unit 131 converts the Tx data supplied from the control unit (CPU) into a differential signal and converts one of the partial signals constituting the differential signal obtained by the conversion. The signal is supplied to the switch 133 and the other partial signal is transmitted to the sink device via the reserved line 88. The switch 133 transmits the partial signal supplied from the conversion unit 131 to the sink device via the CEC line 84. Thereby, a differential signal corresponding to the Tx data is transmitted from the source device to the sink device.

  At the time of data reception, the decoding unit 132 receives a differential signal corresponding to Rx data transmitted from the sink device. That is, the switch 133 receives the partial signal of the differential signal corresponding to the Rx data transmitted from the sink device via the CEC line 84 and supplies the received partial signal to the decoding unit 132. Based on the control of the timing control unit 122, the decoding unit 132 converts the partial signal supplied from the switch 133 and the partial signal supplied from the sink device via the reserve line 88 into the original data. The data is decoded into certain Rx data and output to the control unit (CPU).

  Thereby, the source device exchanges various data such as control data, pixel data, and audio data with the sink device.

  If it is determined in step S14 that half-duplex communication is not possible, in step S18, the source device performs bidirectional communication with the sink device by transmitting and receiving CEC signals, and communication processing is performed. finish.

  That is, at the time of data transmission, the source device transmits a CEC signal to the sink device via the switch 133 and the CEC line 84, and at the time of data reception, the source device passes through the switch 133 and the CEC line 84. By receiving the CEC signal transmitted from the sink device, control data is exchanged with the sink device.

  In this way, the source device refers to the half-duplex flag, and performs half-duplex communication using the sink device capable of half-duplex communication, the CEC line 84, and the reserved line 88.

  As described above, the switch 133 is switched to select the data to be transmitted and the data to be received, and perform the half-duplex communication using the CEC line 84 and the reserve line, that is, the IP communication by the half-duplex communication method. Thus, high-speed bidirectional communication can be performed while maintaining compatibility with the conventional HDMI.

  Similarly to the source device, the sink device also starts communication processing when the power is turned on, and performs bidirectional communication with the source device.

  Hereinafter, communication processing by the sink device shown in FIG. 13 will be described with reference to the flowchart of FIG.

  In step S41, the sink device determines whether a new electronic device (source device) is connected to the sink device. For example, the sink device determines whether a new electronic device is connected based on the magnitude of the voltage added to a pin called Hot Plug Detect to which the HPD line 86 is connected.

  If it is determined in step S41 that a new electronic device is not connected, communication is not performed, and the communication process ends. On the other hand, if it is determined in step S41 that a new electronic device has been connected, in step S42, the switching control unit 124 controls the switch 135, and at the time of data transmission, the control unit (CPU of the sink device). The switch 135 is switched so that the CEC signal from the source device is selected when data is received.

  In step S43, the sink device reads the E-EDID from the EDIDROM 85, and transmits the read E-EDID to the source device via the DDC 83.

  In step S44, the sink device determines whether or not the channel information transmitted from the source device has been received.

  That is, channel information indicating a bidirectional communication channel is transmitted from the source device according to the functions of the source device and the sink device. For example, when the source device is configured as shown in FIG. 13, half-duplex communication using the CEC line 84 and the reserved line 88 is possible between the source device and the sink device. Therefore, channel information indicating that IP communication using the CEC line 84 and the reserved line 88 is performed is transmitted from the source device to the sink device. The sink device receives the channel information transmitted from the source device via the switch 135 and the CEC line 84, and determines that the channel information has been received.

  On the other hand, if the source device does not have a half-duplex communication function, channel information is not transmitted from the source device to the sink device, so the sink device has not received the channel information. Is determined.

  If it is determined in step S44 that the channel information has been received, the process proceeds to step S45, where the switching control unit 124 controls the switch 135, and the difference corresponding to the Rx data from the conversion unit 134 at the time of data transmission. The moving signal is selected, and the switch 135 is switched so that the differential signal corresponding to the Tx data from the source device is selected when the data is received.

  In step S46, the sink device performs bidirectional IP communication with the source device using the half-duplex communication method, and the communication process ends. That is, at the time of data transmission, the conversion unit 134 converts the Rx data supplied from the control unit (CPU) of the sink device into a differential signal based on the control of the timing control unit 123, and is obtained by the conversion. One of the partial signals constituting the differential signal is supplied to the switch 135, and the other partial signal is transmitted to the source device via the reserved line 88. The switch 135 transmits the partial signal supplied from the conversion unit 134 to the source device via the CEC line 84. As a result, a differential signal corresponding to the Rx data is transmitted from the sink device to the source device.

  At the time of data reception, the decoding unit 136 receives a differential signal corresponding to Tx data transmitted from the source device. That is, the switch 135 receives a partial signal of a differential signal corresponding to Tx data transmitted from the source device via the CEC line 84 and supplies the received partial signal to the decoding unit 136. The decoding unit 136 decodes the differential signal including the partial signal supplied from the switch 135 and the partial signal supplied from the source device via the reserved line 88 into Tx data that is the original data, and the control unit (CPU ).

  Accordingly, the sink device exchanges various data such as control data, pixel data, and audio data with the source device.

  If it is determined in step S44 that the channel information has not been received, the sink device performs bidirectional communication with the source device by transmitting and receiving the CEC signal in step S47, and the communication processing ends. To do.

  That is, at the time of data transmission, the sink device transmits a CEC signal to the source device via the switch 135 and the CEC line 84, and at the time of data reception, the sink device passes through the switch 135 and the CEC line 84. By receiving the CEC signal transmitted from the source device, control data is exchanged with the source device.

  In this way, when receiving the channel information, the sink device performs half-duplex communication with the sink device using the CEC line 84 and the reserved line 88.

  In this way, the sink device switches the switch 135 to select the data to be transmitted and the data to be received, and performs half-duplex communication with the source device using the CEC line 84 and the reserved line 88. High-speed bidirectional communication can be performed while maintaining compatibility.

  When the source device has the configuration shown in FIG. 14, the source device has a function for the sink device to perform full-duplex communication based on the full-duplex flag included in the E-EDID in the communication process. And bidirectional communication according to the determination result is performed.

  The communication process by the source device shown in FIG. 14 will be described below with reference to the flowchart of FIG.

  In step S <b> 71, the source device determines whether a new electronic device is connected to the source device. If it is determined in step S71 that a new electronic device is not connected, communication is not performed, and the communication process ends.

  On the other hand, when it is determined in step S71 that a new electronic device has been connected, in step S72, the switching control unit 171 controls the switch 181 and the switch 182, and the data is transmitted by the switch 181. The SDA signal from the control unit (CPU) of the source device is selected, the SCL signal from the control unit (CPU) of the source device is selected by the switch 182, and the SDA from the sink device is received by the switch 181 when data is received. Switch 181 and switch 182 are switched so that the signal is selected.

  In step S73, the switching control unit 121 controls the switch 133 to select the CEC signal from the control unit (CPU) of the source device at the time of data transmission and to select the CEC signal from the sink device at the time of data reception. Thus, the switch 133 is switched.

  In step S74, the source device receives the E-EDID transmitted from the sink device via the SDA line 191 of the DDC 83. That is, when the sink device detects the connection of the source device, the sink device reads the E-EDID from the EDIDROM 85 and transmits the read E-EDID to the source device via the SDA line 191 of the DDC 83. The transmitted E-EDID is received.

  In step S75, the source device determines whether full-duplex communication with the sink device is possible. That is, the source device refers to the E-EDID received from the sink device and determines whether or not the full-duplex flag “Full Duplex” in FIG. 16 is set. For example, the full-duplex flag is set. The source device determines that bidirectional IP communication using the full-duplex communication method, that is, full-duplex communication is possible.

  If it is determined in step S75 that full-duplex communication is possible, in step S76, the switching control unit 171 controls the switch 181 and the switch 182, and at the time of data reception, the Rx data from the sink device is converted. The switches 181 and 182 are switched so that the corresponding differential signal is selected.

  That is, the switching control unit 171 receives the partial signal transmitted via the SDA line 191 among the partial signals constituting the differential signal corresponding to the Rx data transmitted from the sink device at the time of data reception. Is switched by the switch 181 and the switch 181 and the switch 182 are switched so that the partial signal transmitted via the SCL line 192 is selected by the switch 182.

  Since the SDA line 191 and the SCL line 192 constituting the DDC 83 are not used after the E-EDID is transmitted from the sink device to the source device, that is, transmission / reception of the SDA signal and the SCL signal via the SDA line 191 and the SCL line 192. Therefore, the switch 181 and the switch 182 are switched, and the SDA line 191 and the SCL line 192 can be used as a transmission path for Rx data by full-duplex communication.

  In step S77, the source device performs IP communication by the full-duplex communication method using the CEC line 84 and the reserved line 88, and the SDA line 191 and the SCL line 192 as channel information indicating a bidirectional communication channel. A signal to that effect is transmitted to the sink device via the switch 133 and the CEC line 84.

  That is, when the full-duplex flag is set, the source device has the configuration shown in FIG. 14 as the sink device, and the source device uses the CEC line 84 and the reserve line 88, and the SDA line 191 and the SCL line 192. Since it can be seen that duplex communication is possible, channel information is transmitted to the sink device to notify that full duplex communication is to be performed.

  In step S78, the switching control unit 121 controls the switch 133 to switch the switch 133 so that a differential signal corresponding to the Tx data from the conversion unit 131 is selected at the time of data transmission. That is, the switching control unit 121 switches the switch 133 so that the partial signal of the differential signal corresponding to the Tx data supplied from the conversion unit 131 to the switch 133 is selected.

  In step S79, the source device performs bidirectional IP communication with the sink device using the full-duplex communication method, and the communication process ends. That is, at the time of data transmission, the conversion unit 131 converts the Tx data supplied from the control unit (CPU) of the source device into a differential signal, and among the partial signals constituting the differential signal obtained by the conversion Is supplied to the switch 133, and the other partial signal is transmitted to the sink device via the reserved line 88. The switch 133 transmits the partial signal supplied from the conversion unit 131 to the sink device via the CEC line 84. As a result, a differential signal corresponding to the Tx data is transmitted from the source device to the sink device.

  At the time of data reception, the decoding unit 183 receives a differential signal corresponding to Rx data transmitted from the sink device. That is, the switch 181 receives the partial signal of the differential signal corresponding to the Rx data transmitted from the sink device via the SDA line 191 and supplies the received partial signal to the decoding unit 183. The switch 182 receives the other partial signal of the differential signal corresponding to the Rx data transmitted from the sink device via the SCL line 192, and supplies the received partial signal to the decoding unit 183. The decoding unit 183 decodes the differential signal composed of the partial signals supplied from the switch 181 and the switch 182 to Rx data that is the original data, and outputs it to the control unit (CPU).

  Thereby, the source device exchanges various data such as control data, pixel data, and audio data with the sink device.

  If it is determined in step S75 that full-duplex communication is not possible, in step S80, the source device performs bidirectional communication with the sink device by transmitting and receiving the CEC signal, and the communication process ends. To do.

  That is, at the time of data transmission, the source device transmits a CEC signal to the sink device via the switch 133 and the CEC line 84, and at the time of data reception, the source device passes through the switch 133 and the CEC line 84. By receiving the CEC signal transmitted from the sink device, control data is exchanged with the sink device.

  In this way, the source device refers to the full-duplex flag, uses the sink device capable of full-duplex communication, the CEC line 84 and the reserved line 88, and the full-duplex using the SDA line 191 and the SCL line 192. Communicate.

  In this way, the switch 133, the switch 181, and the switch 182 are switched to select the data to be transmitted and the data to be received, and the sink device, the CEC line 84 and the reserve line 88, and the SDA line 191 and the SCL line 192 are used. By performing full-duplex communication, high-speed bidirectional communication can be performed while maintaining compatibility with conventional HDMI.

  Further, even when the sink device has the configuration shown in FIG. 14, the sink device performs communication processing in the same way as in the sink device shown in FIG. 13, and performs bidirectional communication with the source device. Do.

  Hereinafter, communication processing by the sink device shown in FIG. 14 will be described with reference to the flowchart of FIG.

  In step S111, the sink device determines whether a new electronic device (source device) is connected to the sink device. If it is determined in step S111 that a new electronic device is not connected, communication is not performed, and the communication process ends.

  On the other hand, when it is determined in step S111 that a new electronic device has been connected, in step S112, the switching control unit 172 controls the switch 185 and the switch 186, and the data is transmitted by the switch 185. The SDA signal from the control unit (CPU) of the sink device is selected, and when the data is received, the SDA signal from the source device is selected by the switch 185, and the SCL signal from the source device is selected by the switch 186. Then, the switch 185 and the switch 186 are switched.

  In step S113, the switching control unit 124 controls the switch 135 so that the CEC signal from the control unit (CPU) of the sink device is selected at the time of data transmission, and the CEC signal from the source device is selected at the time of data reception. Then, the switch 135 is switched.

  In step S <b> 114, the sink device reads E-EDID from the EDIDROM 85 and transmits the read E-EDID to the source device via the switch 185 and the SDA line 191 of the DDC 83.

  In step S115, the sink device determines whether channel information transmitted from the source device has been received.

  That is, channel information indicating a bidirectional communication channel is transmitted from the source device according to the functions of the source device and the sink device. For example, when the source device is configured as shown in FIG. 13, since the source device and the sink device can perform full duplex communication, the CEC line 84 and the reserved line 88 from the source device to the sink device, Since channel information indicating that IP communication is performed by the full-duplex communication method using the SDA line 191 and the SCL line 192 is transmitted, the sink device is transmitted from the source device via the switch 135 and the CEC line 84. It is determined that the channel information has been received.

  On the other hand, when the source device does not have a function of performing full-duplex communication, channel information is not transmitted from the source device to the sink device, so the sink device has not received the channel information. Is determined.

  If it is determined in step S115 that channel information has been received, the process proceeds to step S116, and the switching control unit 172 controls the switch 185 and the switch 186, and converts the Rx data from the conversion unit 184 into data at the time of data transmission. Switch 185 and switch 186 are switched so that the corresponding differential signal is selected.

  In step S117, the switching control unit 124 controls the switch 135, and switches the switch 135 so that a differential signal corresponding to Tx data from the source device is selected when data is received.

  In step S118, the sink device performs bidirectional IP communication with the source device using the full-duplex communication method, and the communication process ends. That is, at the time of data transmission, the conversion unit 184 converts the Rx data supplied from the control unit (CPU) of the sink device into a differential signal, and among the partial signals constituting the differential signal obtained by the conversion Is supplied to the switch 185, and the other partial signal is supplied to the switch 186. The switch 185 and the switch 186 transmit the partial signal supplied from the conversion unit 184 to the source device via the SDA line 191 and the SCL line 192. As a result, a differential signal corresponding to the Rx data is transmitted from the sink device to the source device.

  At the time of data reception, the decoding unit 136 receives a differential signal corresponding to Tx data transmitted from the source device. That is, the switch 135 receives a partial signal of a differential signal corresponding to Tx data transmitted from the source device via the CEC line 84 and supplies the received partial signal to the decoding unit 136. The decoding unit 136 decodes the differential signal including the partial signal supplied from the switch 135 and the partial signal supplied from the source device via the reserved line 88 into Tx data that is the original data, and the control unit (CPU ).

  Accordingly, the sink device exchanges various data such as control data, pixel data, and audio data with the source device.

  If it is determined in step S115 that channel information has not been received, in step S119, the sink device performs bidirectional communication with the source device by transmitting and receiving the CEC signal, and the communication processing ends. To do.

  In this way, when the sink device receives the channel information, the sink device performs full-duplex communication with the sink device using the CEC line 84 and the reserved line 88, and the SDA line 191 and the SCL line 192.

  In this manner, the sink device switches the switch 135, the switch 185, and the switch 186 to select the data to be transmitted and the data to be received, and the source device, the CEC line 84 and the reserved line 88, and the SDA line 191 and the SCL line 192 are selected. By performing full-duplex communication using, high-speed bidirectional communication can be performed while maintaining compatibility with conventional HDMI.

  In the example of FIG. 14, the source device is configured such that the conversion unit 131 is connected to the CEC line 84 and the reserve line 88, and the decoding unit 183 is connected to the SDA line 191 and the SCL line 192. The decoding unit 183 may be connected to the line 84 and the reserved line 88, and the conversion unit 131 may be connected to the SDA line 191 and the SCL line 192.

  In such a case, the switch 181 and the switch 182 are connected to the CEC line 84 and the reserve line 88 and connected to the decoding unit 183, and the switch 133 is connected to the SDA line 191 and connected to the conversion unit 131.

  Similarly, the sink device of FIG. 14 may be configured such that the conversion unit 184 is connected to the CEC line 84 and the reserve line 88, and the decoding unit 136 is connected to the SDA line 191 and the SCL line 192. In such a case, the switch 185 and the switch 186 are connected to the CEC line 84 and the reserve line 88 and connected to the conversion unit 184, and the switch 135 is connected to the SDA line 191 and connected to the decoding unit 136.

  Further, in FIG. 13, the CEC line 84 and the reserved line 88 may be the SDA line 191 and the SCL line 192. That is, the source device conversion unit 131 and decoding unit 132, and the sink device conversion unit 134 and decoding unit 136 are connected to the SDA line 191 and SCL line 192, and the source device and the sink device are in a half-duplex communication system. You may make it perform IP communication. Further, in this case, the connection of the electronic device may be detected using the reserved line 88.

  Furthermore, each of the source device and the sink device may have both a function of performing half duplex communication and a function of performing full duplex communication. In such a case, the source device and the sink device can perform IP communication using the half-duplex communication method or the full-duplex communication method according to the function of the connected electronic device.

  When each of the source device and the sink device has both a function of performing half-duplex communication and a function of performing full-duplex communication, the source device and the sink device are configured as illustrated in FIG. 21, for example. In FIG. 21, parts corresponding to those in FIG. 13 or FIG. 14 are denoted by the same reference numerals, and description thereof is omitted as appropriate.

  The high-speed data line interface 12A of the source device includes a conversion unit 131, a decoding unit 132, a switch 133, a switch 181, a switch 182, a decoding unit 183, a switching control unit 121, a timing control unit 122, and a switching control unit 171. Yes. That is, the high-speed data line interface 12A in the source device in FIG. 21 is configured such that the timing control unit 122 and the decoding unit 132 in FIG. 13 are further provided in the high-speed data line interface 12A in the source device shown in FIG. Yes.

  21 includes a conversion unit 134, a switch 135, a decoding unit 136, a conversion unit 184, a switch 185, a switch 186, a timing control unit 123, a switching control unit 124, and a switching control. Part 172. That is, the sink device of FIG. 21 is configured such that the timing device 123 and the converter 134 of FIG. 13 are further provided in the sink device shown in FIG.

  Next, communication processing by the source device and the sink device in FIG. 21 will be described.

  First, communication processing by the source device of FIG. 21 will be described with reference to the flowchart of FIG. Note that the processes in steps S151 through S154 are the same as the processes in steps S71 through S74 in FIG.

  In step S155, the source device determines whether full-duplex communication with the sink device is possible. That is, the source device refers to the E-EDID received from the sink device and determines whether or not the full-duplex flag “Full Duplex” in FIG. 16 is set.

  If it is determined in step S155 that full-duplex communication is possible, that is, if the sink device shown in FIG. 21 or FIG. 14 is connected to the source device, in step S156, the switching control unit 171 The switches 181 and 182 are controlled to switch the switches 181 and 182 so that a differential signal corresponding to the Rx data from the sink device is selected when data is received.

  On the other hand, if it is determined in step S155 that full-duplex communication is not possible, in step S157, the source device determines whether half-duplex communication is possible. That is, the source device refers to the received E-EDID and determines whether or not the half-duplex flag “Half Duplex” in FIG. 16 is set. In other words, the source device determines whether or not the sink device shown in FIG. 13 is connected to the source device.

  If it is determined in step S157 that half-duplex communication is possible, or if switch 181 and switch 182 are switched in step S156, in step S158, the source device transmits channel information to switch 133 and CEC. The data is transmitted to the sink device via the line 84.

  Here, if it is determined in step S155 that full-duplex communication is possible, the sink device has a function of performing full-duplex communication. Therefore, the source device uses the CEC line as channel information. 84, the reserve line 88, and a signal indicating that IP communication is performed using the SDA line 191 and the SCL line 192 are transmitted to the sink device via the switch 133 and the CEC line 84.

  If it is determined in step S157 that half-duplex communication is possible, the sink device does not have a function to perform full-duplex communication, but has a function to perform half-duplex communication. Therefore, the source device transmits a signal indicating that IP communication using the CEC line 84 and the reserved line 88 is performed as channel information to the sink device via the switch 133 and the CEC line 84.

  In step S159, the switching control unit 121 controls the switch 133 so that a differential signal corresponding to the Tx data from the conversion unit 131 is selected at the time of data transmission, and is transmitted from the sink device at the time of data reception. The switch 133 is switched so that the differential signal corresponding to the Rx data is selected. When the source device and the sink device perform full-duplex communication, the differential signal corresponding to the Rx data is received from the sink device via the CEC line 84 and the reserve line 88 when receiving data at the source device. Since no signal is transmitted, the differential signal corresponding to the Rx data is not supplied to the decoding unit 132.

  In step S160, the source device performs bidirectional IP communication with the sink device, and the communication process ends.

  That is, when the source device performs full-duplex communication with the sink device and when half-duplex communication is performed, the conversion unit 131 transmits Tx data supplied from the control unit (CPU) of the source device when transmitting data. Is converted into a differential signal, one of the partial signals constituting the differential signal obtained by the conversion is transmitted to the sink device via the switch 133 and the CEC line 84, and the other partial signal is transmitted to the reserve line 88. To the sink device.

  When the source device performs full-duplex communication with the sink device, at the time of data reception, the decoding unit 183 receives a differential signal corresponding to the Rx data transmitted from the sink device, and receives the received differential signal. The signal is decoded into the original data Rx data and output to the control unit (CPU).

  On the other hand, when the source device performs half-duplex communication with the sink device, at the time of data reception, the decoding unit 132 converts the Rx data transmitted from the sink device to the Rx data transmitted under the control of the timing control unit 122. A corresponding differential signal is received, the received differential signal is decoded into Rx data which is the original data, and output to the control unit (CPU).

  Thereby, the source device exchanges various data such as control data, pixel data, and audio data with the sink device.

  If it is determined in step S157 that half-duplex communication is not possible, the source device performs bidirectional communication with the sink device by transmitting and receiving the CEC signal via the CEC line 84 in step S161. The communication process ends.

  In this way, the source device refers to the full-duplex flag and the half-duplex flag, and performs full-duplex communication or half-duplex communication according to the function of the sink device that is the communication partner.

  In this way, the switch 133, the switch 181, and the switch 182 are switched to select the data to be transmitted and the data to be received according to the function of the sink device that is the communication partner, and full duplex communication or half duplex communication is performed. By performing the above, it is possible to select a more optimal communication method and perform high-speed bidirectional communication while maintaining compatibility with the conventional HDMI.

  Next, communication processing by the sink device of FIG. 21 will be described with reference to the flowchart of FIG. Note that the processes in steps S191 through S194 are the same as the processes in steps S111 through S114 in FIG.

  In step S195, the sink device receives the channel information transmitted from the source device via the switch 135 and the CEC line 84. If the source device connected to the sink device does not have a function to perform full-duplex communication or half-duplex communication, channel information is transmitted from the source device to the sink device. Therefore, the sink device does not receive channel information.

  In step S196, the sink device determines whether to perform full-duplex communication based on the received channel information. For example, when the sink device receives channel information indicating that IP communication using the CEC line 84 and the reserved line 88 and the SDA line 191 and the SCL line 192 is performed, the sink device determines that full-duplex communication is performed.

  If it is determined in step S196 that full-duplex communication is to be performed, in step S197, the switching control unit 172 controls the switch 185 and the switch 186, and corresponds to the Rx data from the conversion unit 184 at the time of data transmission. Switch 185 and switch 186 are switched so that the differential signal is selected.

  If it is determined in step S196 that full-duplex communication is not performed, in step S198, the sink device determines whether to perform half-duplex communication based on the received channel information. For example, when the sink device receives channel information indicating that IP communication using the CEC line 84 and the reserved line 88 is performed, the sink device determines to perform half-duplex communication.

  If it is determined in step S198 that half-duplex communication is to be performed or if the switch 185 and the switch 186 are switched in step S197, the switching control unit 124 controls the switch 135 in step S199 to transmit data. At the time, the switch 135 is switched so that the differential signal corresponding to the Rx data from the conversion unit 134 is selected, and the differential signal corresponding to the Tx data from the source device is selected when the data is received.

  When the source device and the sink device perform full-duplex communication, the differential signal corresponding to the Rx data is not transmitted from the conversion unit 134 to the transmitter 81 when transmitting data in the sink device. A differential signal corresponding to the Rx data is not supplied.

  In step S200, the sink device performs bidirectional IP communication with the source device, and the communication process ends.

  That is, when the sink device performs full-duplex communication with the source device, at the time of data transmission, the conversion unit 184 converts the Rx data supplied from the control unit (CPU) of the sink device into a differential signal, and performs conversion. One of the partial signals constituting the differential signal obtained by the above is transmitted to the source device via the switch 185 and the SDA line 191, and the other partial signal is transmitted to the source device via the switch 186 and the SCL line 192. Send.

  When the sink device performs half-duplex communication with the source device, the conversion unit 134 converts the Rx data supplied from the control unit (CPU) of the sink device into a differential signal and converts the data at the time of data transmission. One of the partial signals constituting the differential signal obtained by the above is transmitted to the transmitter 81 via the switch 135 and the CEC line 84, and the other partial signal is transmitted to the source device via the reserved line 88.

  Further, when the sink device performs full-duplex communication and half-duplex communication with the source device, the decoding unit 136 at the time of data reception receives the differential corresponding to the Tx data transmitted from the source device. A signal is received, the received differential signal is decoded into Tx data which is the original data, and output to the control unit (CPU).

  If it is determined in step S198 that half-duplex communication is not performed, that is, for example, channel information has not been transmitted, in step S201, the sink device transmits / receives the CEC signal to transmit the source device. And the communication processing ends.

  In this way, the sink device performs full-duplex communication or half-duplex communication according to the received channel information, that is, according to the function of the source device that is the communication partner.

  In this way, the switch 135, the switch 185, and the switch 186 are switched to select the data to be transmitted and the data to be received in accordance with the function of the source device that is the communication partner, and full-duplex communication or half-duplex communication is selected. By performing the above, it is possible to select a more optimal communication method and perform high-speed bidirectional communication while maintaining compatibility with the conventional HDMI (R).

  Further, the CEC line 84 and the reserve line 88 which are differentially twisted pair connected and shielded and grounded to the ground line, and the SDA line 191 and SCL line 192 which are differentially twisted pair connected and shielded and grounded to the ground line. By connecting the source device and the sink device with the HDMI cable 1 including the above, it is possible to maintain both the compatibility with the conventional HDMI cable and the high speed by the half-duplex communication method or the full-duplex communication method. IP communication can be performed.

  Next, the series of processes described above can be performed by dedicated hardware or by software. When a series of processing is performed by software, a program constituting the software is installed in, for example, a microcomputer that controls the source device and the sink device.

  FIG. 24 shows an example of the configuration of an embodiment of a computer in which a program for executing the series of processes described above is installed.

  The program can be recorded in advance in an EEPROM (Electrically Erasable Programmable Read-only Memory) 305 or a ROM 303 as a recording medium built in the computer.

  Alternatively, the program is temporarily or permanently stored on a removable recording medium such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, or a semiconductor memory. Can be stored (recorded). Such a removable recording medium can be provided as so-called package software.

  The program is installed on the computer from the above-described removable recording medium, transferred from the download site to the computer via a digital satellite broadcasting satellite, or via a network such as a LAN or the Internet. The program transferred to the computer by wire can be received by the input / output interface 306 and installed in the built-in EEPROM 305.

  The computer incorporates a CPU (Central Processing Unit) 302. An input / output interface 306 is connected to the CPU 302 via the bus 301, and the CPU 302 loads a program stored in a ROM (Read Only Memory) 303 or an EEPROM 305 to a RAM (Random Access Memory) 304. And execute. Thereby, the CPU 302 performs processing according to the flowchart described above or processing performed by the configuration of the block diagram described above.

  Here, in this specification, the processing steps for describing a program for causing a computer to perform various types of processing do not necessarily have to be processed in time series according to the order described in the flowchart, but in parallel or individually. This includes processing to be executed (for example, parallel processing or processing by an object). Further, the program may be processed by a single computer, or may be processed in a distributed manner by a plurality of computers.

  Although the configuration example shown in FIG. 9 described above can form a circuit for LAN communication regardless of the electrical specifications defined for DDC, FIG. 25 shows another configuration example having the same effect. Show.

  In this example, in an interface for performing video and audio data transmission, connection device information exchange and authentication, device control data communication and LAN communication with a single cable, LAN communication is simply performed via two pairs of differential transmission paths. The communication is performed in the direction communication, and the connection state of the interface is notified by the DC bias potential of at least one of the transmission lines. Further, at least two transmission lines are time-shared with the LAN communication in the connected device information It is used for communication of exchange and authentication.

  The source device includes a LAN signal transmission circuit 611, termination resistors 612 and 613, AC coupling capacitors 614 to 617, a LAN signal reception circuit 618, an inverter 620, a resistor 621, a resistor 622 and a capacitor 623 forming a low pulse filter, and a comparator 624. , Pull-down resistor 631, resistor 632 and capacitor 633 forming a low-pass filter, comparator 634, NOR gate 640, analog switches 641 to 644, inverter 645, analog switches 646 and 747, DDC transceivers 651 and 652, and pull-up resistor 653 , 654.

  The sink device 602 includes a LAN signal transmission circuit 661, termination resistors 662 and 663, AC coupling capacitors 664 to 667, a LAN signal reception circuit 668, a pull-down resistor 671, a resistor 672 and a capacitor 673 forming a low pulse filter, and a comparator. 674, choke coil 681, resistors 682 and 683 connected in series between the power supply potential and the reference potential, analog switches 691 to 694, inverter 695, analog switches 696 and 697, DDC transceivers 701 and 702, and pull-up resistors 703 and 704 have.

  The HDMI cable 1 includes a differential transmission path composed of a reserved line 801 and an SCL line 803, a differential transmission path composed of an SDA line 804 and an HPD line 802, their source side terminals 811 and 814, and a sink. Side terminals 821 to 824 are formed.

  The reserved line 801 and the SCL line 803, and the SDA line 804 and the HPD line 802 are connected as a differential twisted pair.

  In the source device, the terminals 811 and 813 are connected to the transmission circuit 611 and the termination resistor 612 that transmit the LAN transmission signal SG611 to the sink via the AC coupling capacitors 614 and 605 and the analog switches 641 and 642, respectively. Terminals 814 and 812 are connected to a receiving circuit 618 that receives a LAN signal from the sink device and a terminating resistor 613 via AC coupling capacitors 616 and 617 and analog switches 643 and 644.

  In the sink device, the terminals 821 to 824 are connected to the transmission circuit 661 and the reception circuit 668 and the termination resistors 662 and 663 via the AC coupling capacitors 664, 665, 666, and 667 and the analog switches 691 to 694, respectively. The analog switches 641 to 644 and 691 to 694 are turned on when LAN communication is performed, and are opened when DDC communication is performed.

  The source device connects terminal 813 and terminal 814 to DDC transceivers 651 and 652 and pull-up resistors 653 and 654 via another analog switch 646 and 647.

  The sink device connects the terminals 823 and 824 to the DDC transceivers 701 and 702 and the pull-up resistor 703 via the analog switches 696 and 697. The analog switches 646 and 647 are turned on when DDC communication is performed, and are opened when LAN communication is performed.

  The recognition mechanism of the e-HDMI compatible device by the potential of the reserved line 801 is basically the same as the example shown in FIG. 9 except that the resistor 62 of the source device 601 is driven by the inverter 620.

  When the input of the inverter 620 is HIGH, the resistor 621 becomes a pull-down resistor, so that when viewed from the sink device, it becomes the same 0V state as when an e-HDMI non-compliant device is connected. As a result, the signal SG623 indicating the e-HDMI correspondence identification result of the sink device becomes LOW, the analog switches 691 to 694 controlled by the signal SG623 are opened, and the analog switch controlled by the signal obtained by inverting the signal SG623 by the inverter 695 696 and 697 are conductive. As a result, the sink device 602 is in a state where the SCL line 803 and the SDA line 804 are disconnected from the LAN transceiver and connected to the DDC transceiver.

  On the other hand, in the source device, the input of the inverter 620 is also input to the NOR gate 640, and its output SG614 is set to LOW. The analog switches 641 to 644 controlled by the output signal SG614 of the NOR gate 640 are opened, and the analog switches 646 and 647 controlled by a signal obtained by inverting the signal SG614 by the inverter 645 are turned on. As a result, the source device 601 is also in a state where the SCL line 803 and the SDA line 804 are disconnected from the LAN transceiver and connected to the DDC transceiver.

  Conversely, when the input of the inverter 620 is LOW, both the source device and the sink device are disconnected from the DDC transceiver and connected to the LAN transceiver in the SCL line 803 and SDA line 804.

  Circuits 631 to 634 and 681 to 683 for confirming connection by the DC bias potential of the HPD line 802 have the same function as the example shown in FIG. That is, the HPD line 802 transmits to the source device that the cable 1 is connected to the sink device at the DC bias level in addition to the above-described LAN communication. Resistors 682 and 683 and the choke coil 681 in the sink device bias the HPD line 802 to about 4 V via the terminal 822 when the cable 1 is connected to the sink device.

  The source device extracts the DC bias of the HPD line 802 by a low-pass filter composed of a resistor 632 and a capacitor 633, and compares it with a reference potential Vref2 (for example, 1.4 V) by a comparator 634. If the cable 1 is not connected to the sink device, the potential of the terminal 812 is lower than the reference potential Vref2 by the pull-down resistor 631, and is higher if it is connected. Therefore, if the output signal SG613 of the comparator 634 is HIGH, it indicates that the cable 1 and the sink device are connected. On the other hand, if the output signal SG613 of the comparator 634 is LOW, it indicates that the cable 1 and the sink device are not connected.

  As described above, according to the configuration example shown in FIG. 25, LAN communication is performed in an interface for performing video and audio data transmission, connection device information exchange and authentication, device control data communication, and LAN communication using a single cable. It is performed by unidirectional communication via two pairs of differential transmission lines, and has a configuration in which the connection state of the interface is notified by at least one DC bias potential of the transmission lines, and at least two transmission lines are connected to the LAN. Since communication is used for the exchange of connected device information and authentication communication in a time-sharing manner, time-sharing is divided into a time zone in which the SCL line and SDA line are connected to the LAN communication circuit with a switch and a time zone in which the DDC circuit is connected. This division can form a circuit for LAN communication regardless of the electrical specifications defined for DDC. , Stable and reliable LAN communication can be realized at low cost.

  Note that SDA and SCL are pull-downs with H being 1.5 KΩ pull-up and L being low impedance, and CEC is also performing pull-down communication with H being 27 KΩ pull-up and L being low impedance. Maintaining these functions in order to have compatibility with existing HDMI may make it difficult to share the functions of a LAN that performs high-speed data communication that requires matching termination of transmission line terminations.

  9 and 25 can avoid such a problem. That is, the configuration example of FIG. 9 is configured to perform full-duplex communication by one-way bidirectional communication with the reserved line and the HPD line as a differential pair while avoiding the use of the SDA, SCL, and CEC lines. In the configuration example of FIG. 25, two pairs of full-duplex communications are performed in which two pairs of differential pairs are formed by the HPD line and the SDA line, and the SCL line and the reserve line, and each one-way communication is performed. .

  26A to 26E show bidirectional communication waveforms in the configuration example of FIG. 9 or FIG.

  26A shows the signal waveform sent from the source device, FIG. 26B shows the signal waveform received by the sink device, FIG. 26C shows the signal waveform passing through the cable, and FIG. 26D shows the source waveform. FIG. 26E shows the signal received by the device and the signal waveform sent from the source device. As is clear from FIG. 26, according to the configuration example of FIG. 9 or FIG. 25, good bidirectional communication can be realized.

  In the above-described embodiment, the transmission path for connecting the personal computer (source device) and the television receiver (sink device) has been described on the premise of the HDMI standard interface. However, other similar transmission standards may be used. Applicable. Further, although the personal computer 10 is used as the source device and the television receiver 30 is used as the sink device, the present invention can be similarly applied to an AV system configured using other electronic devices. .

  In the above embodiment, bidirectional IP communication is performed between the source device and the sink device. However, bidirectional communication can be performed using a protocol other than IP. Further, in the above-described embodiment, an example in which electronic devices are connected by an HDMI cable has been described. However, the present invention can be similarly applied to a device in which electronic devices are connected wirelessly.

  The present invention can ensure connectivity and improve the user-friendliness without sacrificing security, and can be applied to, for example, an AV system in which a television receiver and a personal computer are connected by an HDMI cable.

1 is a block diagram showing a configuration example of an AV system as an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration example of a personal computer (source device) configuring an AV system. It is a block diagram which shows the structural example of the television receiver (sink apparatus) which comprises AV system. It is a block diagram which shows the structural example of an HDMI transmission part (HDMI source) and an HDMI receiving part (HDMI sink). It is a figure which shows simply the peripheral circuit of the power supply terminal (+ 5V power terminal) and the HPD (Hot Plug Detect) terminal in the personal computer as the source device and the television receiver as the sink device. It is a block diagram which shows the structural example of an HDMI transmitter and an HDMI receiver. It is a figure which shows the structure of TMDS transmission data. It is a figure which shows the pin arrangement (type A) of an HDMI terminal. It is a connection diagram which shows the structural example of the high-speed data line interface of a personal computer and a television receiver. It is a figure which shows an example of the cancellation | release sequence of the firewall with respect to the television receiver of a personal computer. It is a figure which shows the command system of CEC. It is a figure which shows the other example of the cancellation | release sequence of the firewall with respect to the television receiver of a personal computer. FIG. 10 is a connection diagram illustrating another configuration example of a high-speed data line interface of a personal computer and a television receiver. FIG. 10 is a connection diagram illustrating still another configuration example of the high-speed data line interface of the personal computer and the television receiver. It is a figure which shows the structure of E-EDID which a source device receives. It is a figure which shows an E-EDID Vendor Specific Data Block structure. It is a flowchart for demonstrating the communication process by a source device. It is a flowchart for demonstrating the communication process by a sink device. It is a flowchart for demonstrating the communication process by a source device. It is a flowchart for demonstrating the communication process by a sink device. FIG. 10 is a connection diagram illustrating another configuration example of a high-speed data line interface of a personal computer and a television receiver. It is a flowchart for demonstrating the communication process by a source device. It is a flowchart for demonstrating the communication process by a sink device. It is a block diagram which shows the structural example of the computer to which this invention is applied. FIG. 10 is a connection diagram illustrating still another configuration example of the high-speed data line interface of the personal computer and the television receiver. It is a figure which shows a bidirectional | two-way communication waveform.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... HDMI cable, 5 ... AV system, 10 ... Personal computer, 11 ... HDMI terminal, 12 ... HDMI transmission part, 12A ... High-speed data line interface, 13 ... CPU , 22 ... Ethernet interface, 30 ... TV receiver, 31 ... HDMI terminal, 32 ... HDMI receiver, 32A ... high-speed data line interface, 42 ... display panel, 51 ... CPU, 54 ... Ethernet interface

Claims (12)

A signal receiving unit that receives a video signal from an external device via a transmission path using a plurality of channels and a differential signal;
A communication unit that performs bidirectional communication using a predetermined line constituting the transmission path;
An electronic apparatus comprising: a command transmission unit that transmits a firewall cancellation command for requesting cancellation of a firewall for the communication unit to the external device. The electronic device according to claim 1, wherein the predetermined line is a reserved line and an HPD line constituting an HDMI cable. A connection detection unit that detects that the external device is connected via the transmission path,
The command transmitter
The electronic device according to claim 1, wherein when the connection detection unit detects that the connection is connected to the external device, the firewall release command is transmitted to the external device. The command transmission unit further includes:
The electronic device according to claim 3, wherein when a power-off operation is performed, a firewall release end command is transmitted to the external device for requesting completion of firewall release for the communication unit. The command transmitter
When performing data transmission using the communication unit, send the firewall release command to the external device,
2. The electronic device according to claim 1, wherein when the data transmission is finished, a firewall release end command is transmitted to the external device for requesting the end of the release of the firewall for the communication unit. A signal receiving unit that receives a video signal from an external device via a transmission path using a plurality of channels and a differential signal;
A firewall cancellation method for an electronic device comprising a communication unit that performs bidirectional communication using a predetermined line constituting the transmission path,
A firewall release method for an electronic device, characterized in that, when connected to the external device via the transmission line, a firewall release command for requesting the communication unit to release the firewall is transmitted to the external device. . The method for canceling a firewall of an electronic device according to claim 6, wherein the predetermined lines are a reserved line and an HPD line constituting an HDMI cable. A signal receiving unit that receives a video signal from an external device via a transmission path using a plurality of channels and a differential signal;
A firewall cancellation method for an electronic device comprising a communication unit that performs bidirectional communication using a predetermined line constituting the transmission path,
When performing data transmission using the communication unit, a firewall cancellation command for requesting cancellation of the firewall for the communication unit is transmitted to the external device. The method for canceling a firewall of an electronic device according to claim 8, wherein the predetermined lines are a reserved line and an HPD line constituting an HDMI cable. A signal transmission unit that transmits the video signal to the external device via a transmission path using a differential signal in a plurality of channels;
A communication unit that performs bidirectional communication using a predetermined line constituting the transmission path;
A firewall setting section for setting a firewall;
A command receiving unit for receiving commands from the external device,
The firewall setting section
When the command receiving unit receives a firewall release command, it releases the firewall for the external device, and when the command receiving unit receives a firewall release end command, it cancels the firewall for the external device. Electronic equipment characterized by discontinuation. The electronic device according to claim 10, wherein the predetermined line is a reserved line and an HPD line constituting an HDMI cable. A connection detection unit for detecting whether or not the external device is connected via the transmission line;
The firewall setting unit cancels the firewall for the external device when the connection detection unit detects that the external device is not connected while the firewall for the external device is cancelled. The electronic device according to claim 10, wherein the electronic device is stopped.

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