JP4764086B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device that controls a threshold voltage of a MIS (Metal Insulated Semiconductor) transistor, and more particularly to a semiconductor integrated circuit device capable of substrate voltage control in a low power supply voltage operation for a miniaturized MIS transistor.

  In recent years, a method for reducing a power supply voltage is known as an effective method for reducing power consumption of a semiconductor integrated circuit. However, by lowering the power supply voltage, the influence of fluctuations in the threshold voltage of the MIS transistor or MOS (Metal Oxide Semiconductor) transistor on the operation speed of the semiconductor integrated circuit has increased.

In order to solve this problem, conventionally, a circuit technique for reducing variation in threshold voltage has been developed. For example, as shown in FIG. 12, a stable potential generated by two NchMOS transistors M _1n and M _2n operated in the subthreshold region is applied to the gate of a leakage current detecting NchMOS transistor _MLn , and the transistor M _The following operation is performed using a leakage current detection circuit in which a constant current source is connected to the drain of _Ln and a substrate bias circuit. First, when the threshold voltage is lower than the target value, the leak current increases from the target value, so that the detected leak current becomes larger than the set value. As a result, the substrate bias circuit is activated, the substrate bias is deepened, and the threshold voltage is corrected to be high. On the contrary, when the threshold voltage is higher than the target value, the leak current decreases from the target value, so that the detected leak current becomes smaller than the set value. As a result, the substrate bias circuit makes the substrate bias shallow, and the threshold voltage is corrected to be low (see Patent Document 1).

Further, as shown in FIG. 13, on the semiconductor substrate, the integrated circuit body 16B, the monitor means 15B for monitoring the drain current of at least one of the plurality of NchMOS transistors, and the semiconductor so that the drain current is constant. A substrate voltage adjusting means 14B for controlling the substrate voltage BN of the substrate is provided, the drain of the Nch MOS transistor 11B is connected to the constant current source 12B, the source is connected to the ground potential _VSS terminal, and the gate is set to an arbitrary voltage 17B. Then, the voltage value of the reference input IN1 of the comparison unit 13B is set to the power supply voltage value. The measured input IN2 of the comparison unit 13B is connected to the drain of the MOS transistor 11B (see Patent Document 2).

Further, in Patent Document 2, as shown in FIG. 14, an integrated circuit body 16A on a semiconductor substrate, a monitor means 15A for monitoring at least one drain current of a plurality of PchMOS transistors, and a constant drain current are provided. As shown, the substrate voltage adjusting means 14A for controlling the substrate voltage BP of the semiconductor substrate is provided, and the monitoring means is a constant current source 12A and a monitoring PchMOS transistor 11A formed on the same substrate as the plurality of PchMOS transistors. The source potential of the monitor PchMOS transistor is compared with a predetermined reference potential in a state where the drains of the plurality of PchMOS transistors or the drains of the NchMOS transistors of the integrated circuit body are connected to the ground potential _VSS terminal. The comparison means 13A is provided and the comparison result is obtained. This is fed back to the substrate voltage of the monitor PchMOS transistor (see Patent Document 2).

Further, as shown in FIG. 15, the monitoring means for monitoring the drain potential of the NchMOS transistor having the gate and drain connected to the constant current source, and the substrate for controlling the substrate voltage Vbn of the semiconductor substrate so that the drain potential is constant. A voltage adjusting unit is provided, and the drain of the NchMOS transistor is connected to one of the comparison units, and the other is connected to a reference potential Vgsn (constant potential). Then, the output of the comparison unit is input to the substrate voltage adjusting means, and the substrate voltage Vbn is generated from the substrate voltage adjusting means (see Non-Patent Document 1).
JP-A-9-130232 JP 2004-165649 A Sumita, M. etc., “Mixed Body Bias Techniques With Fixed Vt and Ids Generation Circuits” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO.1, JANUARY 2005

  However, such a conventional semiconductor integrated circuit device has the following three problems. First, as the first problem, the methods disclosed in Patent Document 1 and Patent Document 2 are both methods for detecting the fluctuation of the drain potential of the leakage current detection NchMOS transistor, and therefore, the fluctuation of the drain potential is detected from the initial potential. Therefore, there is a problem that a change in leak current cannot be detected unless there is a drain potential fluctuation until the reference potential exceeds the reference potential. For this reason, there is a limit to improvement in detection sensitivity and response of leak current detection.

As a second problem, in the substrate voltage control of the PchMOS transistor disclosed in Patent Document 2, the drain of the monitoring PchMOSFET and the drains of a plurality of PchMOSFETs or NchMOSFETs in the integrated circuit body are connected to the ground potential V. There is a limitation of connecting to the _SS terminal. For this reason, there exists a fault that there exists restrictions on circuit designs, such as a circuit connection restriction.

  Further, as a third problem, in the methods of Patent Document 2 and Non-Patent Document 1, since a comparator using a comparator or an operational amplifier is used, a DC offset error of the comparator becomes a threshold voltage setting value error. That is.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor integrated circuit device capable of improving the detection sensitivity of a leakage current detection circuit and improving the response.

  Another object of the present invention is to provide a semiconductor integrated circuit device that can cancel the DC offset error of the comparator and improve the accuracy of controlling the substrate voltage.

  (1) A semiconductor integrated circuit device of the present invention includes an internal circuit having a plurality of MIS transistors on a semiconductor substrate, and a substrate voltage for supplying a substrate voltage to the internal circuit to control a threshold voltage of the MIS transistor of the internal circuit. A leakage current in which a power supply voltage of an arbitrary potential is supplied to a control block and a drain, a source is connected to a constant current source, an arbitrary stable potential is applied to a gate, and a substrate voltage is controlled by the substrate voltage control block A leakage current detection circuit comprising a detection MIS transistor and a comparator that compares a source potential of the leakage current detection MIS transistor with a predetermined reference potential; and the substrate voltage control block includes: A substrate voltage is generated based on the comparison result, and the generated substrate voltage is determined based on the substrate of the leak current detection MIS transistor and the internal voltage. A configuration to be applied to the substrate of the MIS transistor in the circuit.

(2) A semiconductor integrated circuit device according to the present invention includes an internal circuit having a plurality of MIS transistors on a semiconductor substrate, and a substrate voltage for supplying a substrate voltage to the internal circuit to control a threshold voltage of the MIS transistor of the internal circuit. The control block and the drain are supplied with the high potential side power supply voltage V _DD , the source is connected to the constant current source, the gate is applied with an arbitrary stable potential, and the substrate voltage is controlled by the substrate voltage control block A leakage current detection circuit comprising: a current detection NchMIS transistor; and a comparator that compares a source potential of the leakage current detection NchMIS transistor with a predetermined reference potential; and the substrate voltage control block includes the comparator The substrate voltage is generated based on the comparison result of the leakage current detection NchMIS transistor. The structure is applied to the substrate of the star and the substrate of the Nch MIS transistor of the internal circuit.

(3) A semiconductor integrated circuit device according to the present invention includes an internal circuit having a plurality of MIS transistors on a semiconductor substrate, and a substrate voltage for supplying a substrate voltage to the internal circuit and controlling a threshold voltage of the MIS transistor of the internal circuit. a control block, and supplies the low potential side power supply voltage V _SS to the drain, a source connected to a constant current source, is applied to any stable potential to the gate, leakage substrate voltage is controlled by the substrate voltage control block A leakage current detection circuit comprising: a current detection PchMIS transistor; and a comparator that compares a source potential of the leakage current detection PchMIS transistor with a predetermined reference potential; and the substrate voltage control block includes the comparator The substrate voltage is generated on the basis of the comparison result, and the generated substrate voltage is converted into the leakage current detection PchMIS transistor. It is applied to the substrate of the star and the substrate of the PchMIS transistor of the internal circuit, and the sources of the plurality of PchMOS transistors of the internal circuit are connected to the high potential side power supply voltage V _DD terminal.

  (4) Further, when the first and second input terminals of the comparator, a switch provided between the source and reference potential terminal of the leak current detection MIS transistor, and the internal circuit are not operating, the leak By switching between the source and reference potential terminal of the current detection MIS transistor and each input terminal of the comparator by the switch, the substrate voltage adjustment is performed twice, and the average of the respective substrate voltage setting values is taken, and the internal circuit It is more preferable to provide an input data correction unit that corrects a DC offset of the comparator by generating a substrate voltage based on the averaged substrate voltage setting value during the normal operation.

(5) A semiconductor integrated circuit device according to the present invention includes an internal circuit having a plurality of MIS transistors on a semiconductor substrate, and a substrate voltage for supplying a substrate voltage to the internal circuit and controlling a threshold voltage of the MIS transistor of the internal circuit. a control block, and supplies the low potential side power supply voltage V _SS to the source, a gate connected to the drain in connection with and a constant current source, and the leakage current detection NchMIS transistor substrate voltage is controlled by the substrate voltage control block, A leakage current detection circuit comprising a comparator for comparing a drain potential of the leakage current detection NchMIS transistor with a predetermined reference potential; and the substrate voltage control block is based on a comparison result of the comparator. Generating a substrate voltage, and using the generated substrate voltage as a substrate of the leakage current detection NchMIS transistor; Applied to the substrate of the Nch MIS transistor of the internal circuit, the first and second input terminals of the comparator, a switch installed between the drain and reference potential terminal of the leak current detection Nch MIS transistor, and the internal circuit operate When the switch is not switched, the substrate voltage is adjusted twice by switching the drain and reference potential terminals of the leakage current detection NchMIS transistor and the input terminals of the comparator with the switch, and the average of the respective substrate voltage setting values And an input data correction means for correcting a DC offset of the comparator by generating a substrate voltage based on the averaged substrate voltage setting value during normal operation of the internal circuit.

(6) A semiconductor integrated circuit device according to the present invention includes an internal circuit having a plurality of MIS transistors on a semiconductor substrate, and a substrate voltage for supplying a substrate voltage to the internal circuit and controlling a threshold voltage of the MIS transistor of the internal circuit. A leakage current detection PchMIS transistor that supplies a high-potential-side power supply voltage V _DD to a source, connects a gate and a drain and is connected to a constant current source, and a substrate voltage is controlled by the substrate voltage control block; A leakage current detection circuit comprising a comparator for comparing a drain potential of the leakage current detection PchMIS transistor with a predetermined reference potential, and the substrate voltage control block is based on a comparison result of the comparator. Generating a substrate voltage, and using the generated substrate voltage as a substrate of the leakage current detection PchMIS transistor; Applied to the substrate of the PchMIS transistor of the internal circuit, the first and second input terminals of the comparator, the switch installed between the drain and reference potential terminal of the leak current detection PchMIS transistor, and the internal circuit operate When not being performed, substrate voltage adjustment is performed twice by switching between the drain and reference potential terminal of the leakage current detection PchMIS transistor and each input terminal of the comparator by the switch, and the average of the respective substrate voltage setting values And an input data correction means for correcting a DC offset of the comparator by generating a substrate voltage based on the averaged substrate voltage setting value during normal operation of the internal circuit.

  According to the present invention, in the leak current detection circuit of the semiconductor integrated circuit device that controls the threshold voltage of the transistor, it is possible to improve the detection sensitivity and the response of the detection potential of the leak current detection MIS transistor. Further, the DC offset of the comparator can be canceled by switching between the potential detection node of the leak current detection MIS transistor and the reference potential terminal and the input terminal of the comparator.

  Hereinafter, embodiments of the present invention using MOS transistors, which are typical examples of MIS transistors, will be described in detail with reference to the drawings.

(Principle explanation)
First, the basic principle of the present invention will be described.

The semiconductor integrated circuit device for controlling the threshold voltage of the MOS transistor according to the present invention includes a leakage current detection circuit, a substrate voltage control block, and an internal circuit. The leakage current detection circuit has the following circuit configuration. First, in order to solve the first problem, the high-potential side power supply voltage V _DD is supplied to the drain, the source is connected to the constant current source, the arbitrary stable potential V _ref1 is applied to the gate, and the substrate voltage is A leakage current detection NchMOS transistor T _n1 controlled by the voltage control block is formed. Next, the source of the NchMOS transistor T _n1 is connected to the input terminal IN1 of the comparator using a comparator or an operational amplifier, and the low-potential-side power supply voltage _VSS is applied as a reference potential to the input terminal IN2 of the comparator. In the internal _{circuit, V SS} terminal is connected to a source of a plurality of NchMOS transistors. The output of the comparator is inputted to substrate voltage control block, the source potential detecting a small change in either V _SS larger or smaller than, controlling the substrate voltage of the NchMOS transistor leakage current detection NchMOS transistor T _n1 and the internal circuit To do.

As a result, the detection sensitivity and response of the detection potential of leakage current detection NchMOS transistor _{T n1} is improved.

In order to solve the second problem in the substrate voltage control of the PchMOS transistor disclosed in Patent Document 2, the low potential side power supply voltage _VSS is supplied to the drain, the source is connected to the constant current source, and the gate is connected to the gate. _{Applies an} arbitrary stable potential V _ref2 to form a leakage current detection PchMOS transistor T _p1 whose substrate voltage is controlled by the substrate voltage control block. Next, the source of the PchMOS transistor T _p1 is connected to the input terminal IN1 of the comparator, and V _DD is applied as a reference potential to the input terminal IN2 of the comparator. Above is the same as the conventional example, in the conventional example, and the drain of the leakage current detection PchMOS transistor _{T p1,} to connect to both _{V SS} terminal and a drain, a plurality of PchMOS transistors or NchMOS transistors of the internal circuit compared, in this embodiment, connect only the drain of the leakage current detection PchMOS transistor _{T p1} to _{V SS} terminal, the internal circuit is different that connects the source of the plurality of PchMOS transistors to _{V DD} terminal.

Furthermore, in order to solve the third problem, in the semiconductor integrated circuit device for controlling the threshold voltage of the NchMOS transistor shown in Patent Document 2, the input terminals IN1, IN2 of the comparator, the source of the NchMOS transistor _Tn1 , and A switch is provided between the _VSS terminals. First, when the internal circuit is not operating, the source of NchMOS transistor _{T n1} connected to _IN1, adjusting the substrate voltage of leakage current detection NchMOS transistor by connecting the _{V SS} terminal IN2, the substrate voltage setting value Input to the register 1 inside the controller. Then, by switching the switch, the source of NchMOS transistor _{T n1} connected to _IN2, by connecting the _{V SS} terminal IN1 to adjust the substrate voltage of leakage current detection NchMOS transistor. In this case, it is necessary to consider the polarity of the substrate voltage. The substrate voltage setting value obtained in this way is input to the register 2 in the controller. Next, the respective substrate voltage setting values stored in the register 1 and the register 2 are averaged, stored in the register 3, and the substrate voltage of the internal circuit is set by the substrate voltage setting value of the register 3 during the normal operation of the internal circuit. Try to control. Thereby, DC offset of a comparator can be canceled and the precision which controls a substrate voltage can be improved. This can be similarly applied to the substrate voltage control circuit of the Pch MOS transistor.

Switch In the semiconductor integrated circuit device for controlling the threshold voltage of the NchMOS transistor shown in Non-Patent Document 1, the respective input terminals IN1, IN2 of the comparator, between the drain of the NchMOS transistor _{T n1} and reference potential _{V ref3} terminal Is provided. First, when the internal circuit is not operating, the drain of the NchMOS transistor _{T n1} connected to IN1, adjusting the substrate voltage of the drain voltage detection NchMOS transistor connected to reference potential _{V ref3} terminal IN2, the substrate voltage setting The value is input to the register 1 in the controller. Then, by switching the switch to connect the drain of the NchMOS transistor _{T n1} to IN2, to adjust the substrate voltage of the drain voltage detection NchMOS transistor connected to reference potential _{V ref3} terminal IN1. In this case, it is necessary to consider the polarity of the substrate voltage. The substrate voltage setting value obtained in this way is input to the register 2 in the controller. Next, the respective substrate voltage setting values stored in the register 1 and the register 2 are averaged, stored in the register 3, and the substrate voltage of the internal circuit is set by the substrate voltage setting value of the register 3 during the normal operation of the internal circuit. Try to control. Thereby, DC offset of a comparator can be canceled and the precision which controls a substrate voltage can be improved. This can be similarly applied to the substrate voltage control circuit of the Pch MOS transistor.

(Embodiment 1)
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit device according to the first embodiment of the present invention based on the above basic concept. The present embodiment is an example applied to a semiconductor integrated circuit device including a leakage current detection circuit of an Nch MOS transistor, a substrate voltage control block, and an internal circuit.

  In FIG. 1, a semiconductor integrated circuit device 100 includes an NchMOS transistor leakage current detection circuit 110, a substrate voltage control block 120 for performing substrate voltage control, and an internal circuit 130 having a plurality of MOS transistors on a semiconductor substrate. The semiconductor integrated circuit device 100 controls the threshold voltage of the Nch MOS transistor that constitutes the internal circuit 130.

In the leakage current detection circuit 110, the drain is connected to the V _DD terminal, the source is connected to a constant current source, an arbitrary stable potential V _ref1 is applied to the gate, and the substrate voltage is controlled by the substrate voltage control block 120. leakage current detection NchMOS transistor _{T n1,} connect the source of the NchMOS transistor _{T n1} to one input terminal IN1, the comparator COMP1 which is applied to _{V SS} as a reference potential to the other input terminal IN2, the leakage current detection NchMOS transistor And a constant current source 111 for supplying a constant current to T _n1 .

The constant current source 111 has a PchMOS transistor T _p1 having a source connected to the V _DD terminal and a gate connected to the V _SS terminal, a gate and a drain connected to the drain of T _p1 , and a source connected to the V _SS2 terminal. configure the NchMOS transistor _{T n3} a current mirror circuit composed of NchMOS transistor _{T n2} whose source is connected to _{V SS2} terminal.

The comparator COMP1 includes a comparator and an operational amplifier, and outputs −1 (low level) if the source potential of the leakage current detection NchMOS transistor T _n1 is higher than the reference potential V _SS , and +1 (high level) if low. ) Is output. The output signal of the comparator COMP1 is input to an up / down counter 121 (described later) in the controller 127. When the value is -1, a down-count is performed, and when the value is +1, an up-count is performed. Then, the count value is stored in the register 1. As another method, an adder / subtracter can be used.

V _SS2 , which is lower than V _DD and V _SS , is applied as a power supply voltage to the comparator COMP1. Here the internal circuit _{130, V SS} terminal is connected to a source of a plurality of NchMOS transistors. The output of the comparator COMP1 is input to the substrate voltage control block 120.

There are two types of substrate voltage control block 120, an analog circuit and a digital circuit. Here, an example of a digital circuit will be described. In this example, the substrate voltage control block 120 includes an up / down counter 121, a register 122 (register 1), a substrate voltage setting upper limit register 123, a substrate voltage setting lower limit register 124, a comparison circuit 125, and a register 126 (register 2). The controller 127 includes a DA converter 128 that receives a digital value from the controller 127 and generates a substrate voltage. The controller 127 performs control to change the substrate voltage applied to the substrate of the leakage current detection NchMOS transistor _{Tn1 and} the substrate of the NchMOS transistor of the internal circuit 130 by changing the count value of the up / down counter based on the output of the comparator COMP1. Do. The DA converter 128 DA-converts the digital value from the controller 127 and generates a substrate voltage.

The substrate voltage generated by the DA converter 128 of the substrate voltage control block 120 is applied to the substrate of the leakage current detection NchMOS transistor T _n1 of the leakage current detection circuit 110 and the substrate of the NchMOS transistor of the internal circuit 130.

  The internal circuit 130 may be any circuit as long as the threshold voltage of the internal NchMOS transistor is controlled by the semiconductor integrated circuit device 100. Here, the PchMOS transistor and the NchMOS transistor are connected in series and the gate is shared. Take a CMOS (Complementary MOS) circuit as an example.

The leakage current detection NchMOS transistor T _n1 may be disposed on the same substrate as the NchMOS transistor of the internal circuit 130, or may be disposed on another substrate and electrically connected.

The upper limit of the output of substrate voltage control block 120 is equal to or greater than _{V SS} of the internal circuit 130, the lower limit is less than _{V SS} of the internal circuit 130. The substrate voltage setting upper limit value and the substrate voltage setting lower limit value are stored in the registers 123 and 124 inside the controller 127, and the comparison circuit 125 compares with the value of the register 1, and the value of the register 1 indicates the substrate voltage setting upper limit value. When it exceeds, the substrate voltage setting upper limit value is output, and when the value of register 1 exceeds the substrate voltage setting lower limit value, the substrate voltage setting lower limit value is output, and the value of register 1 is the substrate voltage setting lower limit value and the substrate voltage. If it is between the set upper limit values, the value of register 1 is output. Then, the output comparison result is stored in the register 2. That is, the value of the register 2 does not exceed the upper limit and lower limit of the substrate voltage setting value.

The value of the register 2 is input from the controller 127 to the DA converter 128, and the substrate voltage corresponding to the register 2 is applied from the DA converter 128 to the substrate of the leakage current detection NchMOS transistor _{Tn1 and} the substrate of the NchMOS transistor of the internal circuit 130. Is done. Alternatively, the output of the DA converter 128 is passed through, for example, a buffer using an operational amplifier (an impedance conversion circuit in which the output of the DA converter is connected to the + input terminal of the operational amplifier and the −input terminal and the output terminal of the operational amplifier are connected). A substrate voltage can also be generated.

  Hereinafter, the substrate voltage control operation of the semiconductor integrated circuit device 100 configured as described above will be described.

First, before starting the substrate voltage control operation, the count value of the up / down counter 121 and the values of the registers 122 and 126 (registers 1 and 2) are reset to zero (0), or the value measured last time is set. . The source potential of leakage current detection NchMOS transistor _{T n1} is higher than _{V SS} that is the reference potential, comparator COMP1 -1 outputs (low level), the up-down counter 121 counts down the count value register 1 is stored. The comparison circuit 125 compares the substrate voltage setting upper limit value or lower limit value with each other and stores the comparison result in the register 2. Then, the DA converter 128 outputs a substrate voltage corresponding to the value of the register 2, and lowers (increases) the substrate voltage of the leak current detection NchMOS transistor T _n1 . As a result, the threshold voltage of leakage current detection NchMOS transistor _{T n1} becomes large, NchMOS transistor _{T n1} source potential is lowered.

Conversely, the source potential of leakage current detection NchMOS transistor _{T n1} is lower than the reference potential _{V SS,} comparator COMP1 outputs + 1 (high level), the up-down counter 121 counts up the count value Is stored in the register 1. The comparison circuit 125 compares the substrate voltage setting upper limit value or lower limit value with each other and stores the comparison result in the register 2. Then, DA converter 128, and outputs a corresponding substrate voltage of the register 2 value (shallow) raising the substrate voltage of leakage current detection NchMOS transistor _{T n1.} As a result, decreases the threshold voltage of leakage current detection NchMOS transistor _{T n1,} NchMOS transistor _{T n1} source potential is raised.

By repeating the above operation, the source potential of the leak current detection NchMOS transistor T _n1 finally converges to be the same potential as V _SS .

  The lower limit of the output of the substrate voltage control block 120 is preferably set to a voltage in a range where no GIDL (Gate-Induced Drain Leakage) effect occurs in the Nch MOS transistor. The GIDL effect is an effect that the subthreshold current increases when a back bias, which is a negative voltage, is excessively applied to the substrate. The upper limit of the output of the substrate voltage control block 120 is preferably set to a voltage in a range where the MOS transistor does not exhibit bipolar characteristics. If a forward bias, which is a positive voltage, is applied to the substrate too much, the MOS transistor exhibits bipolar characteristics, the feedback gain of the threshold control circuit becomes very large, and the feedback system oscillates. It is.

As described above, in the leakage current detection circuit 110, the drain is connected to the V _DD terminal, the source is connected to the constant current source, an arbitrary stable potential V _ref1 is applied to the gate, and the substrate voltage is controlled by the substrate voltage. A source follower circuit constituted by a leakage current detection NchMOS transistor T _n1 controlled by a block is used. Therefore, since a very slight change (threshold level voltage fluctuation) appearing in the source potential is compared and detected by the comparator COMP1, the leakage current is compared with the conventional method for detecting the fluctuation of the drain potential of the leakage current detection NchMOS transistor. detection sensitivity and response of the detection potential of the detection NchMOS transistor _{T n1} is remarkably improved. Thereby, the substrate voltage of the MOS transistor of the internal circuit 130 can be appropriately controlled, and the threshold voltage control in the low power supply voltage operation becomes possible.

For the control operation, it can either be performed a threshold voltage control operation described above normally performed when the internal circuit 130 is not operating, when the source potential of leakage current detection NchMOS transistor T _n1 becomes the same potential as V _SS operation Can also be stopped.

(Embodiment 2)
The second embodiment is an example applied to a leakage current detection circuit using a leakage current detection PchMOS transistor.

  FIG. 2 is a diagram showing the configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention. The present embodiment is an example applied to a semiconductor integrated circuit device including a leakage current detection circuit of a PchMOS transistor, a substrate voltage control block, and an internal circuit. The same components as those in FIG. 1 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  2, the semiconductor integrated circuit device 200 includes a leak current detection circuit 210 of a PchMOS transistor, a substrate voltage control block 120, and an internal circuit 130. The semiconductor integrated circuit device 200 includes a PchMOS transistor that constitutes the internal circuit 130. To control the threshold voltage.

The leak current detection circuit 210 has a drain connected to the _VSS terminal, a source connected to a constant current source, an arbitrary stable potential V _ref2 applied to the gate, and a substrate voltage controlled by the substrate voltage control block. a current detection PchMOS transistor _{T p1,} and one connected to the source of the PchMOS transistor _{T p1} to the input terminal IN1, the comparator COMP2 of applying _{V DD} as a reference potential to the other input terminal IN2, the leakage current detection PchMOS transistor T and a constant current source 211 for supplying a constant current to _p1 .

The constant current source 211 has a source connected to _{V SS} terminal, the NchMOS transistor _{T n1} connected gate to _{V DD} terminal, a gate and a drain connected to the drain of _{T n1,} a source connected to _{V DD2} terminal configure the PchMOS transistor _{T p3} a current mirror circuit composed of PchMOS transistor _{T p2} whose source is connected to _{V DD2} terminal.

The comparator COMP2 is composed of a comparator and an operational amplifier, and outputs −1 (low level) if the source potential of the leakage current detection PchMOS transistor T _p1 is higher than the reference potential V _DD , and +1 (high level) if it is lower. ) Is output. The output signal of the comparator COMP2 is input to the up / down counter 121 in the controller 127. When the value is -1, down-counting is performed, and when the number is +1, up-counting is performed. Then, the count value is stored in the register 1. As another method, an adder / subtracter can be used.

V _DD2 and V _SS that are higher than V _DD are applied as power supply voltages to the comparator COMP2. In this embodiment, unlike the conventional example, connecting a drain of a plurality of PchMOS transistors or NchMOS transistors of the internal circuit 130 instead of connecting to the _{V SS terminal,} a _{V DD} terminal to the source of the plurality of PchMOS transistors of the internal circuit ing. The output of the comparator COMP2 is input to the substrate voltage control block.

There are two types of substrate voltage control blocks 120, an analog circuit and a digital circuit. Here, as in the first embodiment, an example of a digital input circuit will be described. The substrate voltage control block 120 includes an up / down counter 121 that performs substrate voltage control, a register 122 (register 1), a substrate voltage setting upper limit register 123, a substrate voltage setting lower limit register 124, a comparison circuit 125, and a register 126 (register 2). And a DA converter 128 that receives a digital value from the controller 127 and generates a substrate voltage. The controller 127 performs control to change the leakage current detection PchMOS transistor T _p1 substrate voltage by changing the count value of the up / down counter based on the output of the comparator COMP2. The DA converter 128 DA-converts the digital value from the controller 127 and generates a substrate voltage. Substrate voltage DA converter 128 is generated, it is applied to the substrate of the PchMOS transistor substrate and the internal circuit 130 of the leakage current detection PchMOS transistor _{T p1} of leakage current detection circuit 120.

  The internal circuit 130 may be any circuit as long as the threshold voltage of the internal PchMOS transistor is controlled by the semiconductor integrated circuit device 200, but here the PchMOS transistor and the NchMOS transistor are connected in series and the gate is shared. Take a CMOS circuit as an example.

The leakage current detection PchMOS transistor T _p1 may be disposed on the same substrate as the PchMOS transistor of the internal circuit 130, or may be disposed on another substrate and electrically connected.

The upper limit of the output of substrate voltage control block 120 is equal to or greater than _{V DD} of the internal circuit 130, the lower limit is less than _{V DD} of the internal circuit 130. The substrate voltage setting upper limit value and the substrate voltage setting lower limit value are stored in the registers 123 and 124 inside the controller 127, and the comparison circuit 125 compares with the value of the register 1, and the value of the register 1 indicates the substrate voltage setting upper limit value. When it exceeds, the substrate voltage setting upper limit value is output, and when the value of register 1 exceeds the substrate voltage setting lower limit value, the substrate voltage setting lower limit value is output, and the value of register 1 is the substrate voltage setting lower limit value and the substrate voltage. If it is between the set upper limit values, the value of register 1 is output. Then, the output comparison result is stored in the register 2. That is, the value of the register 2 does not exceed the upper limit and lower limit of the substrate voltage setting value.

Input from the controller 127 the value of the register 2 to the DA converter 128, a substrate voltage corresponding the DA converter 128 to the register 2 is applied to the substrate of the PchMOS transistor substrate and the internal circuit 130 of the leakage current detection PchMOS transistor _{T p1} Is done. As in the first embodiment, the output of the DA converter 128 is, for example, a buffer using an operational amplifier (the output of the DA converter is connected to the + input terminal of the operational amplifier, and the −input terminal and the output terminal of the operational amplifier are connected) ) To generate a substrate voltage.

  Hereinafter, the substrate voltage control operation of the semiconductor integrated circuit device 200 configured as described above will be described.

First, before starting the substrate voltage control operation, the count value of the up / down counter 121 and the values of the registers 122 and 126 (registers 1 and 2) are reset to zero (0), or the value measured last time is set. . If the source potential of the leakage current detection PchMOS transistor T _p1 is higher than the reference potential V _DD , the comparator COMP2 outputs −1 (low level), the up / down counter 121 counts down, and the count value is stored in the register. 1 is stored. The comparison circuit 125 compares the substrate voltage setting upper limit value or lower limit value with each other and stores the comparison result in the register 2. Then, DA converter 128 outputs a substrate voltage corresponding to the value of the register 2, (shallow) lowering the substrate voltage of leakage current detection PchMOS transistor _{T p1.} As a result, the threshold voltage of leakage current detection PchMOS transistor _{T p1} decreases, lowered the PchMOS transistor _{T p1} source potential.

Conversely, if the source potential of the leakage current detection PchMOS transistor T _p1 is lower than the reference potential V _DD , the comparator COMP2 outputs +1 (high level), the up / down counter counts up, and the count value is Stored in register 1. Whether the substrate voltage setting upper limit value or lower limit value is exceeded is compared, and the comparison result is stored in register 2. Then, DA converter 128, and outputs a corresponding substrate voltage of the register 2 value (deeper) raising the substrate voltage of leakage current detection PchMOS transistor _{T p1.} As a result, the threshold voltage of leakage current detection PchMOS transistor _{T p1} increases, raised the PchMOS transistor _{T p1} source potential.

By repeating the above operation, the source potential of the leakage current detection PchMOS transistor T _p1 finally converges to be the same potential as V _DD .

  The upper limit of the output of the substrate voltage control block 120 is preferably set to a voltage in a range where the GIDL effect does not occur in the Pch MOS transistor. Further, it is desirable that the lower limit of the output of the substrate voltage control block 120 be set to a voltage in a range where the PchMOS transistor does not exhibit bipolar characteristics.

As described above, according to the present embodiment, the same effect as in the first embodiment can be obtained also in the leakage current detection circuit 210 using the leakage current detection PchMOS transistor, and the detection potential of the leakage current detection PchMOS transistor T _p1 can be reduced. Detection sensitivity and response can be improved.

As for the control operation, the above-described threshold voltage control operation can be performed at all times or when the internal circuit 130 is not operating, and the operation is performed when the source potential of the leakage current detection PchMOS transistor T _p1 becomes the same potential as V _DD. Can also be stopped.

(Embodiment 3)
The third embodiment is an example in which the substrate voltages of the Pch MOS transistor and the Nch MOS transistor constituting the CMOS circuit are controlled in the internal circuit using both the semiconductor integrated circuit devices of the first embodiment and the second embodiment.

  FIG. 3 is a diagram showing a configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention. The same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  3, a semiconductor integrated circuit device 300 includes an NchMOS transistor leakage current detection circuit 110, a PchMOS transistor leakage current detection circuit 210, two sets of substrate voltage control blocks 120, and an internal circuit 130. The circuit device 300 controls the threshold voltages of the Nch MOS transistor and the Pch MOS transistor that constitute the internal circuit 130.

Thus, according to this embodiment, the same effect can be obtained even in the CMOS circuit, to improve the detection sensitivity and response of the detection potential of leakage current detection NchMOS transistor _{T n1} and leakage current detection PchMOS transistor _{T p1} Can do. Furthermore, by applying to an internal circuit using such a CMOS circuit, the threshold voltages of the Pch MOS transistor and the Nch MOS transistor can be controlled simultaneously and optimally.

(Embodiment 4)
The fourth embodiment is an example applied to a leakage current detection circuit that cancels the DC offset of the comparator.

  FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit device according to the fourth embodiment of the present invention. The present embodiment is an example applied to a semiconductor integrated circuit device including a leakage current detection circuit of an Nch MOS transistor, a substrate voltage control block, and an internal circuit. The same components as those in FIG. 1 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  4, the semiconductor integrated circuit device 400 includes an NchMOS transistor leakage current detection circuit 410, a substrate voltage control block 420 that performs substrate voltage control, and an internal circuit 130. The semiconductor integrated circuit device 400 includes the internal circuit 130. The threshold voltage of the NchMOS transistor that constitutes is controlled.

In the leakage current detection circuit 410, the drain is connected to the V _DD terminal, the source is connected to a constant current source, an arbitrary stable potential V _ref1 is applied to the gate, and the substrate voltage is controlled by the substrate voltage control block 420. leakage current detection NchMOS transistor _{T n1,} connect the source of the NchMOS transistor _{T n1} to one input terminal IN1, the comparator COMP1 which is applied to _{V SS} as a reference potential to the other input terminal IN2, each comparator COMP1 the input terminal IN1, IN2, is placed between the source and the _{V SS} terminal of NchMOS transistor _{T n1,} when the internal circuit 130 is not operating, the comparator COMP1 and the source and _{V SS} terminal of NchMOS transistor _{T n1} of each Input switching switch 41 for switching between input terminals When constituted by a constant current source 111 supplies a constant current to the leakage current detection NchMOS transistor _{T n1.}

The substrate voltage control block 420 performs control to change the substrate voltage applied to the substrate of the leakage current detection NchMOS transistor _Tn1 and the NchMOS transistor of the internal circuit 130 by comparing the output of the comparator COMP1 with a predetermined reference potential. The controller 430 to perform and the DA converter 128 which DA-converts the digital value from the controller 430 and generates a substrate voltage are provided. Further, the substrate voltage control block 420 is configured by a digital circuit because of the switching control of the input switching switch 411 and the ease of offset adjustment amount calculation control.

This embodiment, in the semiconductor integrated circuit 100 of FIG. 1 and the respective input terminals IN1, IN2 of the comparator COMP1, the switch 411 of the input switching between the source and the _{V SS} terminal of NchMOS transistor _{T n1} provided configuration It is. Further, the controller 430 of the substrate voltage control block 420 further has functions of switching control of the switch 411 for input switching and offset adjustment amount calculation control.

  FIG. 5 is a diagram showing a circuit configuration of the controller 430.

5, the controller 430 includes an inverter 431 and a selector 432, and a polarity inverter 433 for selectively inverting the polarity of the output signal of the comparator COMP1.
An input data correction unit 434 and a selector 435 that switches between the register 2 and the register 13 are configured.

  The input switching switch 411 and the polarity inverter 433 are controlled by the mode switching signal 1, and the selector 435 is controlled by the mode switching signal 2.

  The input data correction unit 434 includes an up / down counter 451 and a register 452 (register 1), a substrate voltage setting value generation unit 453 using a successive approximation method that changes by 1 LSB (least significant bit), and a substrate voltage setting upper limit value. A substrate voltage setting value upper / lower limit comparison circuit 458 including a register 454, a substrate voltage setting lower limit value register 455, a comparison circuit 456, and a register 457 (register 2), and a first substrate voltage setting value and a second substrate voltage setting value. A register 459 (register 11) and a register 460 (register 12) for temporary storage, an arithmetic circuit 461, and a register 462 (register 13) for storing an arithmetic result are configured.

  Hereinafter, the operation of the semiconductor integrated circuit device 400 configured as described above will be described. The overall operation of the substrate voltage control of the semiconductor integrated circuit device 400 is the same as that of the first embodiment.

  First, an operation for compensating for the DC offset of the comparator COMP1 in the substrate voltage control operation will be described.

  In this operation, when the internal circuit 130 is not operating, an operation for obtaining the first substrate voltage setting value (first input mode) and an operation for obtaining the second substrate voltage setting value (second input mode). ) And an operation (calculation mode) for obtaining the third substrate voltage setting value.

  The DC offset of the comparator COMP1 can be removed by applying the substrate voltage using the third substrate voltage setting value obtained in this way.

  As shown in FIG. 5, the input switching switch 411 has a function of selectively connecting the input terminals A and B to any one of the output terminals C and D.

  In the first input mode, the input switching switch 411 is connected to the A terminal and the C terminal, and connected to the B terminal and the D terminal. The selector 432 in the polarity inverter 433 is connected to the comparator COMP1. The output signal is passed as it is.

  The output signal of the comparator COMP1 is given to an up / down counter 451 that functions as the substrate voltage set value generation means 453.

  First, before starting the substrate voltage control operation, the count value of the up / down counter 451 and the value of the register 452 (register 1) are reset to zero (0) or the value measured last time is set. Next, the up / down counter 451 counts up when the output signal of the comparator COMP1 applied at this time is +1 (high level), and counts down when the output signal is -1 (low level). To store.

  The substrate voltage setting upper limit value and the substrate voltage setting lower limit value stored in the input data correction unit 434 are compared with the value of the register 1 using a comparison circuit. If the value of the register 1 exceeds the substrate voltage setting upper limit value, The board voltage setting upper limit value is output. When the value of register 1 exceeds the board voltage setting lower limit value, the board voltage setting lower limit value is output. The value of register 1 is the substrate voltage setting lower limit value and the board voltage setting upper limit value. If it is between, the value of register 1 is output. The output comparison result is stored in the register 457 (register 2).

In response to the mode switching signal 2, the value of the register 2 is input to the DA converter 128 from the input data correction unit 434 via the selector 435. As a result, the substrate voltage corresponding to the register 2 is applied from the DA converter 128 to the substrate of the leakage current detection NchMOS transistor _{Tn1 and} the substrate of the NchMOS transistor of the internal circuit 130.

That is, the source potential of leakage current detection NchMOS transistor _{T n1} is higher than the reference potential _{V SS,} comparator COMP1 outputs -1 (low level), the up-down counter counts down, the count value register 1 is stored. The comparison circuit 456 compares whether or not the substrate voltage setting upper limit value or lower limit value is exceeded, and stores the comparison result in the register 2. Then, the DA converter 128 outputs a substrate voltage corresponding to the value of the register 2, and lowers (increases) the substrate voltage of the leak current detection NchMOS transistor T _n1 . As a result, the threshold voltage of leakage current detection NchMOS transistor _{T n1} becomes large, NchMOS transistor _{T n1} source potential is lowered.

Conversely, the source potential of leakage current detection NchMOS transistor T _n1 is lower than V _SS that is the reference potential, the comparator outputs a +1 (high level), the up-down counter counts up the count value of register 1 Stored in The comparison circuit 456 compares whether or not the substrate voltage setting upper limit value or lower limit value is exceeded, and stores the comparison result in the register 2. Then, DA converter 128, and outputs a corresponding substrate voltage of the register 2 value (shallow) raising the substrate voltage of leakage current detection NchMOS transistor _{T n1.} As a result, decreases the threshold voltage of leakage current detection NchMOS transistor _{T n1,} NchMOS transistor _{T n1} source potential is raised.

  Thereafter, the same operation is performed by turning the above loop, and this operation is continued until the polarity of the output signal of the comparator COMP1 is inverted.

  That is, when the substrate voltage set value generation means 453 detects the inversion of the polarity of the output signal of the comparator COMP1, the count value at this time (this is the first substrate voltage set value) is registered in the register 459 (register 11). To hold.

  It should be noted that polarity inversion must be carefully detected in consideration of minute fluctuations in the signal voltage.

  Next, the input switching switch 411 is controlled so that the A terminal is connected to the D terminal, the B terminal is connected to the C terminal, and the second input mode is set.

  At this time, the selector 432 of the polarity inverter 433 selects the output signal of the inverter 431. That is, a signal obtained by inverting the polarity of the output signal of the comparator COMP1 is supplied to the up / down counter 451.

  In such a state, the count value of the up / down counter 451 of the substrate voltage set value generation means 453 is returned to zero (0), and the same operation as that in the first input mode is performed or obtained in the first input mode. The second substrate voltage setting value is continuously obtained from the same count value as the first substrate voltage setting value. The second substrate voltage setting value obtained as a result is stored in the register 460 (register 12).

  Then, the first and second substrate voltage setting values are taken out from the register 11 and the register 12, and the third substrate voltage setting value is calculated by taking the average value by the arithmetic circuit 461, and the third substrate voltage setting value is calculated by the register 462 (register 13 ).

  The third substrate voltage setting value is a substrate voltage setting value when the comparator COMP1 has no DC offset (that is, a substrate voltage setting value in which the DC offset of the comparator COMP1 is completely canceled).

  Therefore, during the normal operation of the internal circuit 130, the selector is controlled by the mode switching signal 2, and the substrate voltage of the internal circuit 130 is controlled by using the third substrate voltage setting value of the register 13. The offset can be canceled completely, and the accuracy of controlling the substrate voltage can be greatly improved.

Thus, according to this embodiment, the respective input terminals IN1, IN2 of the comparator COMP1, the provided switch 411 for input switching between the source and the _{V SS} terminal of NchMOS transistor _{T n1,} the internal circuit 130 when not operating, by switching between the respective input terminal of the comparator COMP1 and the source and _{V SS} terminal of NchMOS transistor _{T n1} switch 411 for input switching, perform substrate voltage regulating twice, each substrate voltage The set value is stored in the register 1 and the register 2 inside the controller 430, the average of the respective substrate voltage set values is taken and stored in the register 3, and the internal voltage 130 is stored in the register 3 during normal operation of the internal circuit 130. Since the substrate voltage of the circuit is controlled, the DC offset error of the comparator COMP1 Can be canceled and the accuracy of controlling the substrate voltage can be improved.

(Embodiment 5)
The fifth embodiment is an example in which the DC offset cancellation of the comparator is applied to a leakage current detection circuit using a leakage current detection PchMOS transistor.

  FIG. 6 is a diagram showing a configuration of a semiconductor integrated circuit device according to the fifth embodiment of the present invention. The present embodiment is an example applied to a semiconductor integrated circuit device including a leakage current detection circuit of a PchMOS transistor, a substrate voltage control block, and an internal circuit. The same components as those in FIG. 2 and FIG.

  6, the semiconductor integrated circuit device 500 includes a leakage current detection circuit 510 for a PchMOS transistor, a substrate voltage control block 420, and an internal circuit 130. The semiconductor integrated circuit device 500 includes a PchMOS transistor that constitutes the internal circuit 130. To control the threshold voltage.

The leak current detection circuit 510 has a drain connected to the _VSS terminal, a source connected to a constant current source, an arbitrary stable potential V _ref2 applied to the gate, and a substrate voltage controlled by the substrate voltage control block. Each of the current detection PchMOS transistor T _p1 , the comparator COMP2 in which the source of the PchMOS transistor T _p1 is connected to one input terminal IN1, and V _DD is applied as the reference potential to the other input terminal IN2, and the comparator COMP2 an input terminal IN1, IN2, is placed between the source and the _{V DD} terminal of PchMOS transistor _{T p1,} when the internal circuit 130 is not operating, the respective input of the comparator COMP2 to the source and _{V DD} terminal of PchMOS transistor _{T p1} An input switching switch 411 for switching between terminals; Supplying a constant current to over leakage current detection PchMOS transistor _{T p1} configured with a constant current source 211.

The substrate voltage control block 420 is configured to control the leak current detection PchMOS transistor T _p1 to change the substrate voltage by changing the count value of the up / down counter based on the output of the comparator COMP2, and the digital signal from the controller 430. A D / A converter 128 that D / A converts the value to generate a substrate voltage. Further, the substrate voltage control block 420 is configured by a digital circuit because of the switching control of the input switching switch 411 and the ease of offset adjustment amount calculation control.

  The circuit configuration of the controller 430 is the same as that shown in FIG.

  The operation principle of the semiconductor integrated circuit device 500 of the fifth embodiment and the operation principle of canceling the DC offset error of the comparator COMP2 are exactly the same as those of the fourth embodiment, except that the NchMOS transistor and the PchMOS transistor are interchanged.

  Therefore, the same effect as in the fourth embodiment can be obtained.

(Embodiment 6)
In the sixth embodiment, both the semiconductor integrated circuit devices of the fourth and fifth embodiments are used to control the substrate voltages of the Pch MOS transistor and the Nch MOS transistor constituting the CMOS circuit in the internal circuit.

  FIG. 7 is a diagram showing a configuration of a semiconductor integrated circuit device according to the sixth embodiment of the present invention. The same components as those in FIGS. 4 and 6 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  In FIG. 7, a semiconductor integrated circuit device 600 includes an NchMOS transistor leakage current detection circuit 410, a PchMOS transistor leakage current detection circuit 510, two sets of substrate voltage control blocks 420, and an internal circuit 130. The circuit device 600 controls the threshold voltages of the Nch MOS transistor and the Pch MOS transistor that constitute the internal circuit 130.

  Therefore, the present invention can be similarly applied to a CMOS circuit, and the same effects as those of the third to fifth embodiments can be obtained.

(Embodiment 7)
The seventh embodiment is an example applied to a leakage current detection circuit for canceling a DC offset of a comparator in an NchMOS transistor substrate voltage control circuit.

  FIG. 8 is a diagram showing a configuration of a semiconductor integrated circuit device according to the seventh embodiment of the present invention. The present embodiment is applied to a semiconductor integrated circuit device that controls a threshold voltage of an NchMOS transistor configured by an internal circuit, and a substrate voltage control block configured by a controller and a DA converter, and a drain potential detection circuit of the NchMOS transistor. This is an example. The same components as those in FIG. 6 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  In FIG. 8, the semiconductor integrated circuit device 700 includes an NchMOS transistor leakage current detection circuit 710, a substrate voltage control block 420, and an internal circuit 130. The semiconductor integrated circuit device 700 includes an NchMOS transistor that constitutes the internal circuit 130. To control the threshold voltage.

Leakage current detection circuit 710 is connected to the gate and drain connected to and a constant current source, a source connected to V _SS terminal, a leakage current detection NchMOS transistor T _n1 of the substrate voltage is controlled by the substrate voltage control block 420 The constant current source 711 that supplies a constant current to the leak current detection NchMOS transistor T _n1 , the drain of the NchMOS transistor T _n1 is connected to one input terminal IN1, and V _ref3 is applied as a reference potential to the other input terminal IN2. a comparator COMP1 that, the respective input terminals IN1, IN2 of the comparator COMP1, is placed between the drain of the NchMOS transistor _{T n1} and reference potential _{V ref3} terminal, when the internal circuit 130 is not operating, NchMOS transistor _{T n1} of the drain and the reference potential V _ef3 constituted a switch 712 for input switching to switch between each input terminal of the comparator COMP1 and terminal.

The constant current source 711 has a source connected to _{V SS,} and NchMOS transistor _{T n4} that a gate connected to the _{V DD,} a gate and a drain connected to the drain of _{T n4,} PchMOS transistor T having a source connected to _{V DD} constitute a _p13 and a current mirror circuit composed of PchMOS transistors _{T p12} with a source connected to _{V DD.}

The substrate voltage control block 420 controls the leakage current detection NchMOS transistor T _n1 to change the substrate voltage by changing the count value of the up / down counter based on the output of the comparator COMP1, and the digital signal from the controller 430. A D / A converter 128 that D / A converts the value to generate a substrate voltage. Further, the substrate voltage control block 420 is configured by a digital circuit because of the switching control of the input switching switch 712 and the ease of offset adjustment amount calculation control.

This embodiment, wherein the substrate voltage control circuit of the NchMOS transistor of Non-Patent Document 1, the respective input terminals IN1, IN2 of the comparator input switching between the drain of the NchMOS transistor _{T n1} and reference potential _{V ref3} terminal The switch 712 is provided.

  FIG. 9 is a diagram showing a circuit configuration of the controller 430, and the same components as those in FIG.

  In FIG. 9, the controller 430 includes an inverter 431 and a selector 432, and a polarity inverter 433 for selectively inverting the polarity of the output signal of the comparator COMP1, an input data correction unit 434, a register 2 and a register 13 And a selector 435 for switching between.

  The input switching switch 712 and the polarity inverter 433 are controlled by the mode switching signal 1, and the selector 435 is controlled by the mode switching signal 2.

  The input data correction unit 434 includes an up / down counter 451 and a register 452 (register 1), a substrate voltage setting value generation unit 453 using a successive approximation method that changes by 1 LSB, a substrate voltage setting upper limit register 454, a substrate voltage A substrate voltage setting value upper / lower limit comparison circuit 458 including a setting lower limit register 455, a comparison circuit 456, and a register 457 (register 2), and a first substrate voltage setting value and a second substrate voltage setting value are temporarily stored. And a register 459 (register 11) and a register 460 (register 12), an arithmetic circuit 461, and a register 462 (register 13) for storing an operation result.

  In the first input mode, the input switching switch 712 has an A terminal and a C terminal connected, and a B terminal and a D terminal connected, and the selector 432 in the polarity inverter 433 outputs the comparator output. Pass the signal through. The same substrate voltage control operation as in the fourth embodiment is performed, and the first substrate voltage setting value is stored in the register 11.

  In the second input mode, the input switching switch 712 has an A terminal and a D terminal connected, and a B terminal and a C terminal connected, and the selector 432 in the polarity inverter 433 has a comparator COMP1. Invert the output signal. The same substrate voltage control operation as in the fourth embodiment is performed, and the second substrate voltage setting value is stored in the register 12.

  Then, the first and second substrate voltage setting values are extracted from the register 11 and the register 12, and the third substrate voltage setting value is calculated by taking the average value by the arithmetic circuit 461, and is stored in the register 13. .

  The third substrate voltage setting value is a substrate voltage setting value when the comparator has no DC offset (that is, a substrate voltage setting value in which the DC offset of the comparator is completely canceled).

  Therefore, during normal operation of the internal circuit, the selector 435 is controlled by the mode switching signal 2 and the substrate voltage of the internal circuit 130 is controlled by using the third substrate voltage setting value of the register 13, so that the DC of the comparator COMP 1 is controlled. The offset error can be completely canceled, and the accuracy of controlling the substrate voltage can be greatly improved.

(Embodiment 8)
The eighth embodiment is an example in which the DC offset cancellation of the comparator is applied to a leakage current detection circuit using a leakage current detection PchMOS transistor.

  FIG. 10 is a diagram showing a configuration of a semiconductor integrated circuit device according to the eighth embodiment of the present invention. This embodiment is applied to a PchMOS transistor drain potential detection circuit, a substrate voltage control block composed of a controller and a DA converter, and a semiconductor integrated circuit device for controlling a threshold voltage of a PchMOS transistor composed of an internal circuit. This is an example. The same components as those in FIGS. 4 and 8 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  10, the semiconductor integrated circuit device 800 includes a leak current detection circuit 810 of a PchMOS transistor, a substrate voltage control block 420, and an internal circuit 130. The semiconductor integrated circuit device 800 includes a PchMOS transistor that forms the internal circuit 130. To control the threshold voltage.

The leakage current detection circuit 810 has a gate and a drain connected to each other, connected to a constant current source, a source connected to a V _DD terminal, and a substrate voltage controlled by a substrate voltage control block 420. The leakage current detection PchMOS transistor T _p1 The constant current source 811 that supplies a constant current to the leak current detection PchMOS transistor T _p1 , the drain of the PchMOS transistor T _p1 is connected to one input terminal IN1, and V _ref4 is applied to the other input terminal IN2 as a reference potential a comparator COMP2 that, the respective input terminals IN1, IN2 of the comparator COMP2, is placed between the drain of the PchMOS transistor _{T p1} and the reference potential _{V ref4} terminal, when the internal circuit 130 is not operating, PchMOS transistor _{T p1} of the drain and the reference voltage V _ef4 constituted a switch 812 for input switching to switch between each input terminal of the comparator COMP2 to the terminal.

The constant current source 811, a source connected to the _{V DD} terminal, the PchMOS transistor _{T p4} connected gate to _{V SS} terminal, a gate and a drain connected to the drain of _{T p4,} a source connected to _{V SS} terminal configure the NchMOS transistor _{T n13} and a current mirror circuit composed of NchMOS transistor _{T n12} having its source connected to _{V SS} terminal.

The substrate voltage control block 420 is configured to control the leak current detection PchMOS transistor T _p1 to change the substrate voltage by changing the count value of the up / down counter based on the output of the comparator COMP2, and the digital signal from the controller 430. A D / A converter 128 that D / A converts the value to generate a substrate voltage. Further, the substrate voltage control block 420 is constituted by a digital circuit because of the switching control of the input switching switch 812 and the ease of offset adjustment amount calculation control.

  The circuit configuration of the controller 430 is the same as that shown in FIG.

  The operation principle of the semiconductor integrated circuit device 800 of the eighth embodiment and the operation principle of canceling the DC offset of the comparator COMP2 are exactly the same as those of the seventh embodiment, except that the NchMOS transistor and the PchMOS transistor are interchanged.

  Therefore, the same effect as in the seventh embodiment can be obtained.

(Embodiment 9)
The ninth embodiment is an example in which the substrate voltages of the Pch MOS transistor and the Nch MOS transistor constituting the CMOS circuit are controlled in the internal circuit by using both the semiconductor integrated circuit devices of the seventh embodiment and the eighth embodiment.

  FIG. 11 is a diagram showing a configuration of a semiconductor integrated circuit device according to the ninth embodiment of the present invention. The same components as those in FIGS. 8 and 10 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  In FIG. 11, a semiconductor integrated circuit device 900 includes an NchMOS transistor leakage current detection circuit 710, a PchMOS transistor leakage current detection circuit 810, two sets of substrate voltage control blocks 420, and an internal circuit 130. The circuit device 900 controls the threshold voltages of the Nch MOS transistor and the Pch MOS transistor that constitute the internal circuit 130.

  Therefore, in the CMOS circuit, the same effects as those in the seventh and eighth embodiments can be obtained.

  The above description is an illustration of a preferred embodiment of the present invention, and the scope of the present invention is not limited to this.

  In this embodiment, the name “semiconductor integrated circuit device” is used. However, this is for convenience of explanation, and it is needless to say that the semiconductor integrated circuit, the substrate voltage control method, and the like may be used.

  Furthermore, the type, number, connection method, and the like of each circuit unit, for example, the comparison unit, etc. constituting the semiconductor integrated circuit device are not limited to the above-described embodiments.

  Each of the above embodiments can be performed for each of a plurality of circuit blocks in which the substrate is electrically separated.

  Further, the present invention can be applied not only to a MOS transistor configured on a normal silicon substrate but also to a semiconductor integrated circuit configured by a MOS transistor having an SOI (Silicon On Insulator) structure.

  The semiconductor integrated circuit device for controlling the threshold voltage of the transistor according to the present invention can improve the detection sensitivity and response of the leak current detection circuit, and can cancel the DC offset of the comparator. Therefore, it is very effective as a means for controlling variation in threshold voltage of a semiconductor integrated circuit operated with a low power supply voltage with high sensitivity, high response, and high accuracy.

The figure which shows the structure of the semiconductor integrated circuit device which concerns on Embodiment 1 of this invention. The figure which shows the structure of the semiconductor integrated circuit device which concerns on Embodiment 2 of this invention. The figure which shows the structure of the semiconductor integrated circuit device based on Embodiment 3 of this invention. The figure which shows the structure of the semiconductor integrated circuit device based on Embodiment 4 of this invention. The figure which shows the circuit structure of the controller of the said Embodiment 4. The figure which shows the structure of the semiconductor integrated circuit device based on Embodiment 5 of this invention. The figure which shows the structure of the semiconductor integrated circuit device based on Embodiment 6 of this invention. The figure which shows the structure of the semiconductor integrated circuit device based on Embodiment 7 of this invention. The figure which shows the circuit structure of the controller of the said Embodiment 7. The figure which shows the structure of the semiconductor integrated circuit device based on Embodiment 8 of this invention. The figure which shows the structure of the semiconductor integrated circuit device based on Embodiment 8 of this invention. The figure which shows the structure of the semiconductor integrated circuit device which controls the threshold voltage of the conventional NchMOS transistor The figure which shows the structure of the semiconductor integrated circuit device which controls the threshold voltage of the conventional NchMOS transistor The figure which shows the structure of the semiconductor integrated circuit device which controls the threshold voltage of the conventional PchMOS transistor The figure which shows the structure of the semiconductor integrated circuit device which controls the threshold voltage of the conventional NchMOS transistor

Explanation of symbols

100, 200, 300, 400, 500, 600, 700, 800, 900 Semiconductor integrated circuit device 111, 211, 711, 811 Constant current source 110, 210, 410, 510, 710, 810 Leakage current detection circuit 120, 420 Substrate Voltage control block 127, 430 Controller 128 DA converter 121, 451 Up / down counter 122, 452 Register (register 1)
123,454 Substrate voltage setting upper limit register 124,455 Substrate voltage setting lower limit register 125,456 Comparison circuit 126,457 Register (register 2)
130 Internal Circuit 411, 712, 812 Switch for Input Switching 431 Inverter 432, 435 Selector 433 Polarity Inverter 434 Input Data Correction Unit 453 Substrate Voltage Setting Value Generation Unit 461 Arithmetic Circuit T _n1 Leakage Current Detection NchMOS Transistor T _p1 Leakage Current Detection PchMOS transistor COMP1, COMP2 comparator

Claims (10)

An internal circuit having a plurality of MIS transistors on a semiconductor substrate;
A substrate voltage control block for supplying a substrate voltage to the internal circuit and controlling a threshold voltage of a MIS transistor of the internal circuit;
A leakage current detection MIS transistor in which a power supply voltage of an arbitrary potential is supplied to a drain, a source is connected to a constant current source, an arbitrary stable potential is applied to a gate, and a substrate voltage is controlled by the substrate voltage control block ,
A comparator that compares the source potential of the leak current detection MIS transistor with a predetermined reference potential ;
A leakage current detection circuit comprising first and second input terminals of the comparator and a switch disposed between a source and a reference potential terminal of the leakage current detection MIS transistor ;
The substrate voltage control block performs substrate voltage adjustment by switching between the source and reference potential terminal of the leak current detection MIS transistor and each input terminal of the comparator with the switch when the internal circuit is not operating. Performing twice, averaging each substrate voltage setting value, and correcting the DC offset of the comparator by generating the substrate voltage based on the average substrate voltage setting value during normal operation of the internal circuit A semiconductor integrated circuit device comprising input data correcting means for performing The input data correction means includes
When the internal circuit is not operating, the source of the leak current detection MIS transistor is connected to the first input terminal, the reference potential terminal is connected to the second input terminal, and the substrate voltage of the leak current detection MIS transistor is adjusted. Then, while inputting the substrate voltage setting value to the first register,
By switching the switch, the source of the leak current detection MIS transistor is connected to the second input terminal, the reference potential terminal is connected to the first input terminal, and the substrate voltage of the leak current detection MIS transistor is adjusted. The substrate voltage setting value is input to the second register,
The substrate voltage setting value stored in the first register and the substrate voltage setting value stored in the second register are averaged, the averaged substrate voltage setting value is stored in the third register, and the internal circuit 2. The semiconductor integrated circuit device according to claim 1 , wherein a DC offset of the comparator is corrected by generating a substrate voltage based on a substrate voltage setting value stored in the third register during normal operation. . The substrate voltage control block, the semiconductor integrated circuit device according to claim 1, characterized in that at all times the voltage adjustment operation to control the threshold voltage of the transistor of the internal circuit. The substrate voltage control block, the voltage adjustment operation to control the threshold voltage of the transistor of the internal circuit, the semiconductor integrated circuit device according to claim 1, characterized in that when the internal circuit is not operating. The substrate voltage control block includes limit means for outputting a voltage value obtained by limiting the upper limit and the lower limit of the output substrate voltage with respect to the output substrate voltage output based on the comparison result of the comparator. The semiconductor integrated circuit device according to claim 1 . The upper limit of the output voltage value of the substrate voltage control block is set to a voltage not less than the power supply voltage of the internal circuit and the leakage current detection NchMOS transistor does not exhibit bipolar characteristics, and the lower limit of the output voltage value is 2. The semiconductor integrated circuit device according to claim 1 , wherein the semiconductor integrated circuit device is set to a voltage that is equal to or lower than the power supply voltage of the internal circuit and that does not cause a GIDL effect in the leakage current detection NchMOS transistor. The lower limit of the output voltage value of the substrate voltage control block is set to a voltage equal to or lower than the power supply voltage of the internal circuit and the leakage current detection PchMOS transistor does not exhibit bipolar characteristics. The upper limit of the output voltage value is 2. The semiconductor integrated circuit device according to claim 1 , wherein the voltage is set to a voltage that is equal to or higher than the power supply voltage of the internal circuit and that does not cause a GIDL effect in the leakage current detection PchMOS transistor. The substrate voltage control block, the substrate is a semiconductor integrated circuit device according to claim 1, characterized in that it is installed in each electrically isolated plurality of functional blocks. Said MOS transistor is a semiconductor integrated circuit device according to claim 1, characterized in that the SOI structure. The internal circuit has a CMOS circuit,
The substrate voltage control block, the semiconductor integrated circuit device according to claim 1, wherein the controlling the threshold voltage of the NchMOS transistor and PchMOS transistor of the CMOS circuit.

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