JP4752279B2 - Transistor array panel - Google Patents

Description

  The present invention relates to a transistor array panel used for an active matrix drive type display panel.

  As an active matrix liquid crystal display panel, a transistor array panel in which thin film transistors, pixel electrodes and the like are patterned in an array is used. A plurality of gate lines extend in the row direction on the insulating transparent substrate of the transistor array panel, and a plurality of data lines extend in the column direction on the gate insulating film covering these gate lines. A thin film transistor is disposed at each intersection of the gate line and the data line.

  Although static electricity is generated during the manufacturing process of the transistor array panel, the technique described in Patent Document 1 has been proposed in order to prevent the transistor array panel from being destroyed by static electricity. According to Patent Document 1, the short-circuit wiring is formed so as to surround the display area with the short-circuit wiring, and the protective element which is a high resistance element is connected between the upper and lower ends of the data line and the short-circuit wiring. The protective element is also connected between the left and right ends of the gate line and the short-circuit wiring. Since the short-circuit wiring and the data line are connected via the protection element, and further, the short-circuit wiring and the gate line are connected via the protection element, the static electricity generated in the gate line and the data line is distributed to each, It is possible to prevent the transistor array from being damaged by static electricity.

  In the transistor array panel described in Patent Document 1, as shown in FIG. 13, an address terminal 422 and a data terminal 408 for inputting a drive signal from an IC chip type drive circuit for driving a liquid crystal display panel are provided. In order to provide only on the lower side of the transistor array panel 401, a lead wiring 421 having one end connected to the gate line 403 is provided on the panel, the other end of the lead wiring 421, the address terminal 422, and the data line 404. And the data terminal 408 may be connected to each other. FIG. 13 is an equivalent circuit diagram of a transistor array panel having this configuration.

According to the liquid crystal display panel constituted by such a transistor array panel 401, since the address terminal 422 and the data terminal 408 are provided only on the lower side of the transistor array panel 401, the driving circuit is provided only on the lower side of the display area. The drive circuit need not be mounted on the left and right sides of the display area of the liquid crystal display panel, so that the width of the left and right non-display areas of the display area can be reduced.
JP-A-63-85586

  By the way, in the transistor array panel 401 shown in FIG. 13, since the protective elements 409 are provided at the left and right ends of the gate line 403, a space for forming the protective elements 409 on the left and right sides of the display area is required. For this reason, the left and right non-display areas of the display area are widened.

  Accordingly, the present invention has been made to solve the above-described problems, and an object thereof is to provide a transistor array panel capable of narrowing the non-display area on the left and right end portions of the gate line. .

In order to solve the above-described problems, according to the first aspect of the present invention, a plurality of gate lines and a plurality of data lines are formed on a substrate at right angles through an insulating film, and the plurality of gate lines and the plurality of data lines are In the transistor array panel, a thin film transistor is disposed at each intersection with the data line, a gate of the thin film transistor is connected to the gate line, and one of a source and a drain of the thin film transistor is connected to the data line.
A plurality of routing lines provided in parallel to the plurality of data lines are arranged on the end side of the plurality of gate lines, and one end of the plurality of routing lines is connected to the plurality of gate lines, respectively. And a short-circuit wiring provided in parallel to the plurality of gate lines is disposed on the other end side of the plurality of routing wirings, and is connected between the short-circuit wiring and the plurality of routing wirings, respectively. A plurality of first protection elements arranged along the short-circuit wiring ,
Another short-circuit wiring provided in parallel to the plurality of gate lines is disposed on the end side of the plurality of data lines, and is connected between the another short-circuit wiring and the plurality of data lines, respectively. The plurality of second protection elements are arranged along the another short-circuit wiring .

According to the first aspect of the present invention, the shorting wiring parallel to the gate line is arranged on the other end side of the routing wiring parallel to the data line, and the other end side of each routing wiring and the shorting wiring are arranged. Since the protective elements are connected to each other and are arranged along the short-circuit wiring, the non-display area on the left and right end portions of the gate line can be narrowed. In addition, since the plurality of gate lines are connected to the short-circuit wiring via the respective routing wirings and the respective protection elements, static electricity generated in these gate lines is dispersed to each other, and the transistor array is prevented from being destroyed by static electricity. be able to. In addition, since the plurality of data lines are connected to different short-circuit wirings through the respective second protection elements, static electricity generated in these data lines is dispersed to each other, thereby preventing the transistor array from being destroyed by static electricity. be able to.

The invention according to claim 2 is the transistor array panel according to claim 1, characterized in that the further shorting lines and the short-circuit line is connected.

According to the second aspect of the present invention, since the short-circuit wiring and the other short-circuit wiring are connected, static electricity generated in the gate line and the data line is dispersed to each other, and the destruction of the transistor array due to static electricity is prevented. be able to.

  According to the present invention, the shorting wiring parallel to the gate line is arranged on the other end side of the routing wiring parallel to the data line, and between the other end side of each routing wiring and the shorting wiring. Since the protective elements are connected and these protective elements are arranged along the short-circuit wiring, the non-display area on the left and right end portions of the gate line can be narrowed.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

[First Embodiment]
FIG. 1 is an equivalent circuit diagram of a transistor array panel 1 to which the present invention is applied. As shown in FIG. 1, when the transistor array panel 1 is viewed in plan, a plurality of gate lines (scanning lines) 3 extending in the row direction and a plurality of data lines (signal lines) 4 extending in the column direction Are formed on the insulating transparent substrate 2, and the gate lines 3 and the data lines 4 are in a twisted position. Specifically, the gate line 3 and the data line 4 are insulated from each other, and the gate line 3 and the data line 4 are orthogonal to each other in plan view. A plurality of thin film transistors 5 are arranged in a matrix on the insulating transparent substrate 2, and each thin film transistor 5 is connected to the gate line 3 and the data line 4 at each intersection of the gate line 3 and the data line 4. Yes. In each surrounding region surrounded by the gate line 3 and the data line 4, a pixel electrode 6 connected to the thin film transistor 5 is arranged, and a plurality of pixel electrodes 6 are arranged in a matrix on the insulating transparent substrate 2 for display. A region is formed.

  The display area is surrounded by the short-circuit wiring 10 and the short-circuit wiring 14. The short-circuit wiring 10 has an upper side portion 11 that is parallel to the gate line 3 so as to be above the display region, and a lower side portion 12 that is parallel to the gate line 3 so as to be below the display region. And a left side portion 13 parallel to the data line 4 along the left of the display area, and is formed in an inverted U-shape. The short-circuit wiring 14 has a vertical strip 15 that is parallel to the data line 4 along the right side of the display area, and a horizontal strip that extends in the row direction from the lower end thereof and is parallel to the gate line 3. It consists of a belt part 16 and is formed in an L shape.

  The data line 4 is insulated and intersects with the lower side portion 12 of the short-circuit wiring 10, and the lower side portion 12 of the short-circuit wiring 10 crosses these data lines 4. A second protection element 7 having a high resistance characteristic or a nonlinear resistance characteristic is connected between the lower side portion 12 of the short-circuit wiring 10 and each data line 4.

  The lower end of the data line 4 is a data terminal 8, the data terminal 8 is below the lower side 12 of the short-circuit wiring 10, and the plurality of data terminals 8 are on the lower side of the insulating transparent substrate 2. It is arranged in a line along.

  The gate line 3 is insulated from the vertical strip 15 of the short-circuit wiring 14 and intersects in plan view, and the vertical strip 15 of the short-circuit wiring 14 crosses the gate line 3. The right end portion of each gate line 3 is connected to the end portion of the routing wiring 21 on the right side of the vertical strip portion 15 of the short-circuit wiring 14, and the routing wiring 21 and the gate line 3 are integrally formed. These routing wirings 21 extend in the column direction so as to be parallel to the data lines 4, and these routing wirings 21 are insulated from the horizontal band portion 16 of the shorting wiring 14 and intersect in a plan view to cause a short circuit. The horizontal band portion 16 of the wiring 14 crosses the routing wiring 21. A first protection element 9 having a high resistance characteristic or a non-linear resistance characteristic is connected between the lateral band portion 16 of the short-circuit wiring 14 and each lead wiring 21.

  The lower end portion of the routing wiring 21 is an address terminal 22, the address terminal 22 is located below the lateral band portion 16 of the short-circuit wiring 14, and these address terminals 22 extend along the lower side of the insulating transparent substrate 2. It is arranged. An IC chip type drive circuit is mounted in the area α where the data terminals 8 and the address terminals 22 are arranged, and the output terminals of the drive circuits are connected to the data terminals 8 and the address terminals 22.

  FIG. 2 is a plan view showing the lower side of the right edge portion of the transistor array panel 1. FIG. 3 is a cross-sectional view taken along the line III-III in FIG.

  Each thin film transistor 5 is configured as shown in FIG. As shown in FIG. 3, the thin film transistor 5 is formed on the gate 31 connected to the gate line 3, the semiconductor film 33 disposed opposite to the gate 31 with the gate insulating film 32 interposed therebetween, and the central portion of the semiconductor film 33. A channel protective film 34; impurity semiconductor films 35 and 36 formed on the semiconductor film 33 so as to be spaced apart from each other and disposed on both sides of the channel protective film 34 in plan view; and on one impurity semiconductor film 35 A source 37 is formed, and a drain 38 is formed on the other impurity semiconductor film 36.

  The gate 31 is made of a conductive material such as a low resistivity metal material or alloy, and more preferably has a light shielding property such as chromium, chromium alloy, aluminum, aluminum alloy or the like.

  The gate insulating film 32 is formed by depositing an insulator such as silicon oxide or silicon nitride on the entire surface of the insulating transparent substrate 2.

  The semiconductor film 33 is made of amorphous silicon or polysilicon.

  The impurity semiconductor film 35 and the impurity semiconductor film 36 are obtained by doping a semiconductor such as silicon with an impurity (for example, Ga).

  The channel protective film 34 is formed of an insulator such as silicon oxide or silicon nitride, and protects the semiconductor film 33 from the etchant when the impurity semiconductor film 35 and the impurity semiconductor film 36 are patterned.

  The source 37 and the drain 38 are made of a conductive material such as a low-resistivity metal material or alloy, and more preferably have a light-shielding property such as chromium, chromium alloy, aluminum, or aluminum alloy.

  The thin film transistor 5 is covered with an insulating film 39. The insulating film 39 is formed by depositing an insulator such as silicon oxide or silicon nitride on the entire surface, and covers the plurality of thin film transistors 5 together.

  As shown in FIGS. 1 and 2, the gates 31 of the plurality of thin film transistors 5 arranged in a line in the row direction are integrally formed with a common gate line 3. Any gate 31 and any gate line 3 are formed by patterning a conductive film (hereinafter referred to as a gate film) formed on the entire surface of the insulating transparent substrate 2. It is a thing. The short-circuit wiring 10 shown in FIG. 1 is also patterned simultaneously with the gate 31 and the gate line 3 by patterning the gate film.

  The drains 38 of the plurality of thin film transistors 5 arranged in a line in the column direction are integrally formed with the common data line 4. Any drain 38, any source 37, and any data line 4 are conductive films formed on the entire surface so as to cover the impurity semiconductor films 35 and 36 (hereinafter, this conductive film is referred to as a drain film). .) Is formed by patterning.

  As shown in FIG. 2, a protective element 7 is formed in the vicinity of the intersection between the lower side portion 12 of the short-circuit wiring 10 and each data line 4. One electrode 71 of the protection element 7 is connected to the lower side 12 of the short-circuit wiring 10 through the contact hole 45, and the other electrode 72 of the protection element 7 is integrally formed with the data line 4. A resistor 73 is connected between the electrode 71 and the electrode 72. The electrode 71 and the electrode 72 of the protection element 7 are formed simultaneously with the source 37, the drain 38 and the data line 4 by patterning the drain film, and the resistor 73 is the base of the semiconductor film 33 of the thin film transistor 5. It is formed at the same time as the semiconductor film 33 by patterning the semiconductor film on one side. These protective elements 7 are arranged along the lower side 12 of the short-circuit wiring 10 below the display area.

  The short-circuit wiring 14 shown in FIGS. 1 and 2 is formed simultaneously with the source 37, the drain 38, and the data line 4 by patterning the drain film, and the intersection of the short-circuit wiring 14 and the short-circuit wiring 10 is formed. , Contact holes 43 and 44 are formed in the gate insulating film 32, and the short-circuit wiring 14 and the short-circuit wiring 10 are connected through the contact holes 43 and 44.

  As shown in FIG. 2, a plurality of lead wirings 21 are formed on the insulating transparent substrate 2 on the right side of the vertical band portion 15 of the short-circuit wiring 14. These lead wires 21 are formed simultaneously with the gate 31 and the gate line 3 by patterning the gate film.

  FIG. 4 is a plan view showing a lower edge portion of the transistor array panel 1 which is a region below the region shown in FIG. A protective element 9 is formed in the vicinity of the intersection between the lateral band portion 16 of the short-circuit wiring 14 and each lead wiring 21. One electrode 91 of the protection element 9 is connected to the lead wiring 21 through the contact hole 46, and the other electrode 92 of the protection element 9 is integrally formed with the short-circuit wiring 14. A resistor 93 is connected between the electrode 91 and the electrode 92. The electrode 91 and the electrode 92 of the protection element 9 are formed simultaneously with the source 37, the drain 38, and the data line 4 by patterning the drain film, and the resistor 93 is the base of the semiconductor film 33 of the thin film transistor 5. It is formed at the same time as the semiconductor film 33 by patterning the semiconductor film on one side. These protective elements 9 are arranged along the horizontal band 16 of the short-circuit wiring 14 below the display area.

  As shown in FIGS. 2 and 3, a plurality of pixel electrodes 6 are arranged in a matrix on the gate insulating film 32. These pixel electrodes 6 are formed by patterning a transparent conductive film formed on the entire surface of the gate insulating film 32. The pixel electrode 6 is made of indium oxide, tin oxide, or a mixture containing at least one of them (for example, ITO, zinc-doped indium oxide, CTO). These pixel electrodes 6 are also collectively covered with an insulating film 39. In this embodiment, the source 37 is connected to the pixel electrode 6 and the drain 38 is integrally formed with the data line 4. Conversely, the drain 38 is connected to the pixel electrode 6 and the source 37 is integrated with the data line 4. It may be formed.

  As shown in FIG. 2, between adjacent gate lines 3, capacitor lines 41 extend in the row direction, and the gate lines 3 and capacitor lines 41 are alternately arranged. These capacitor lines 41 are patterned simultaneously with the gate 31 and the gate line 3 by patterning the gate film. Further, the capacitor line 41 is provided wide so as to overlap with the plurality of pixel electrodes 6 arranged in a line in the row direction, and the wide part of the capacitor line 41 and the pixel electrode 6 sandwich the gate insulating film 32. The capacitors are formed by facing each other. A contact hole 42 is formed in the gate insulating film 32 where the right end portion of the capacitor line 41 and the vertical band portion 15 of the short-circuit wiring 14 overlap, and the capacitor line 41 and the short-circuit wiring 14 are connected via the contact hole 42. ing.

  As shown in FIG. 2, a rectangular frame-shaped seal 81 is formed on the insulating film 39 so as to surround the display area. The seal 81 seals the liquid crystal sandwiched between the transistor array panel 1 and the counter substrate when the transistor array panel 1 and the counter substrate face each other. A liquid crystal display panel is formed by sealing the liquid crystal between them. Note that a color filter, a black matrix, a transparent counter electrode, an alignment film, and the like are formed on the counter substrate.

Next, a method for manufacturing the transistor array panel 1 will be described.
First, a gate film is formed on the entire surface of the insulating transparent substrate 2 by vapor deposition (sputtering, CVD, PVD, etc.), and the gate film is patterned by photolithography and etching. As a result, the plurality of gate lines 3, the gates 31 of the plurality of thin film transistors 5, the plurality of capacitor lines 41, the plurality of routing lines 21, and the short-circuit line 10 are formed simultaneously.

  Next, a gate insulating film 32 is formed on the entire surface of the insulating transparent substrate 2 by vapor deposition, and a plurality of gate lines 3, gates 31 of the plurality of thin film transistors 5, and a plurality of capacitor lines are formed by the gate insulating film 32. 41, covering the plurality of routing wirings 21 and the shorting wiring 10;

  Next, a solid semiconductor film is formed on the gate insulating film 32 by vapor deposition, and the semiconductor film is patterned by photolithography and etching. Thereby, the semiconductor films 33 of the plurality of thin film transistors 5, the resistors 93 of the plurality of protection elements 9, and the resistors 73 of the plurality of protection elements 7 are formed.

  Next, channel protective films 34 of the plurality of thin film transistors 5 are formed by sequentially performing a vapor deposition method, a photolithography method, and an etching method.

  Next, impurity semiconductor films 35 and 36 of the plurality of thin film transistors 5 are formed by sequentially performing a vapor deposition method, a photolithography method, and an etching method.

  Next, a plurality of pixel electrodes 6 are formed by sequentially performing a vapor deposition method, a photolithography method, and an etching method.

  Next, a contact hole 42 is formed in a portion of the gate insulating film 32 that overlaps the right end portion of each capacitor line 41. Further, a contact hole 44 is formed in a portion of the gate insulating film 32 that overlaps the right end portion of the upper side portion 11 of the short-circuit wiring 10, and a contact hole 43 is formed in a portion that overlaps the right end portion of the lower side portion 12 of the short-circuit wiring 10. Form. Further, the contact holes 45 are formed in the gate insulating film 32 so that the plurality of contact holes 45 are arranged along the lower side portion 12 of the short-circuit wiring 10. Further, a contact hole 46 is formed in a portion of the gate insulating film 32 that overlaps the lower end portion of each routing wiring 21.

  Next, when a drain film is formed on the entire surface of the gate insulating film 32 by vapor deposition, the drain film is filled in the contact holes 41 to 46, and then the drain film is patterned by a photolithography method and an etching method. Accordingly, the short-circuit wiring 14, the plurality of data lines 4, the drains 38 and the sources 37 of the plurality of thin film transistors 5, the electrodes 91 and 92 of the plurality of protection elements 9, and the electrodes 71 and electrodes 72 of the plurality of protection elements 7 are simultaneously connected. Form.

  Next, an insulating film 39 is formed on the entire surface of the gate insulating film 32 by vapor deposition, and the short-circuit wiring 10, the plurality of data lines 4, the drains 38 and the sources 37 of the plurality of thin film transistors 5, and the plurality of protections. The insulating film 39 covers the electrodes 91 and 92 of the element 9 and the electrodes 71 and 72 of the plurality of protective elements 7.

  Next, a contact hole is formed in a portion of the insulating film 39 that overlaps the lower end of each data line 4 to expose the data terminal 8 of each data line 4. Further, a contact hole is formed in a portion of the insulating film 39 and the gate insulating film 32 that overlaps the lower end portion of the routing wiring 21, and the address terminal 22 of each routing wiring 21 is exposed.

  If an alignment film is formed on the manufactured transistor array panel 1, the transistor array panel 1 and the counter substrate are opposed to each other, a liquid crystal is sandwiched between the transistor array panel 1 and the counter substrate, and the liquid crystal is sealed with a seal 81, A liquid crystal display panel is completed.

  According to the present embodiment, since the plurality of protection elements 9 are arranged along the horizontal band portion 16 of the short-circuit wiring 14 in the non-display region on the lower end side of the data line 4, the left and right ends of the gate line 3 are arranged. This eliminates the need for a space for providing the protective element 9 in the portion. Therefore, the non-display area on the left and right end portions of the gate line 3 can be narrowed.

  Further, the plurality of gate lines 3 are connected to the short-circuit wiring 14 via the respective lead wirings 21 and the respective protection elements 9, and the plurality of data lines 4 are connected to the short-circuit wiring via the respective second protection elements 7. 10 and the short-circuit wiring 10 and the short-circuit wiring 14 are connected to each other, so that static electricity generated in the gate line 3 and the data line 4 is dispersed to each other, thereby preventing the transistor array 1 from being destroyed by static electricity. it can.

  The size of the conventional gate lead-out wiring and protection element is a substantially rectangular shape in which the wiring pitch of the gate lead-out wiring is about 28 μm, and the area necessary for forming the protection element is about 18 μm wide and about 36 μm high. When this protective element is used, the width necessary for arranging the protective element is 18 μm in length of the short side of the protective element and 4 μm between the protective elements necessary for maintaining the characteristics of the protective element. The total is 22 μm, which is smaller than the wiring pitch of the gate routing wiring. Therefore, the protective element can be disposed between the gate routing lines without increasing the interval between the conventional gate routing lines.

[Second Embodiment]
A transistor array panel 101 according to the second embodiment will be described with reference to FIGS. FIG. 5 is an equivalent circuit diagram of the transistor array panel 101, and FIG. 6 is a plan view showing a lower edge portion of the transistor array panel 101. In the following description, for the transistor array panel 101, a lower two-digit common number is assigned to a portion corresponding to any portion of the transistor array panel 1 in the first embodiment.

  In the first embodiment, the second protection element 7 is connected between the lower side portion 12 of the short-circuit wiring 10 and the data line 4, but in the second embodiment, the second protection element 107 is It is connected between the short-circuit wiring 117 and the data line 104. The short-circuit wiring 117 extends in the row direction below the lower side portion 112 of the short-circuit wiring 110 so as to be parallel to the lower side portion 112. Further, the short-circuit wiring 117 is connected to the short-circuit wiring 110 and is integrally formed with the short-circuit wiring 110. Therefore, the short-circuit wiring 117 is formed at the same time as the gate 131 and the gate line 103 by patterning the gate film, and crosses the plurality of data lines 104.

  One electrode 171 of the protection element 107 is connected to the short-circuit wiring 117 through the contact hole 145, and the other electrode 172 of the protection element 107 is integrally formed with the data line 104. A resistor 173 is connected between the electrode 171 and the electrode 172. The electrode 171 and the electrode 172 of the protective element 7 are formed simultaneously with the source 137, the drain 138, and the data line 104 by patterning the drain film, and the resistor 173 is the base of the semiconductor film 133 of the thin film transistor 105. It is formed at the same time as the semiconductor film 133 by patterning the semiconductor film on one side. These protective elements 107 are arranged along the short-circuit wiring 117 below the display area.

  In the first embodiment, the short-circuit wiring 14 includes the vertical belt portion 15 and the horizontal belt portion 16 and is provided in an L shape. However, in the second embodiment, the short-circuit wiring 114 is the vertical belt portion. 115 and is provided in a straight line.

  In the first embodiment, the first protection element 9 is connected between the lateral band portion 16 of the short-circuit wiring 14 and the routing wiring 21, but in the second embodiment, the first protection element 109 is connected. Are connected between the lead-out wiring 121 and the short-circuit wiring 118.

  The short-circuit wiring 118 extends rightward from the right end of the short-circuit wiring 117 and is parallel to the gate line 103. The short-circuit wiring 118 is formed at the same time as the source 137, the drain 138, and the data line 104 by patterning the drain film, and traverses the plurality of routing wirings 121. In the portion where the short-circuit wiring 117 and the short-circuit wiring 118 overlap, the contact hole 147 penetrates the gate insulating film 132, and the short-circuit wiring 117 and the short-circuit wiring 118 are connected via the contact hole 147.

  One electrode 191 of the protection element 109 is connected to the lead wiring 121 through the contact hole 146, and the other electrode 192 of the protection element 109 is integrally formed with the short-circuit wiring 118. A resistor 193 is connected between the electrode 191 and the electrode 192. The electrode 191 and the electrode 192 of the protection element 109 are formed simultaneously with the source 137, the drain 138, and the data line 104 by patterning the drain film, and the resistor 193 is the base of the semiconductor film 133 of the thin film transistor 105. It is formed at the same time as the semiconductor film 133 by patterning the semiconductor film on one side. These protection elements 109 are arranged along the short-circuit wiring 118 below the display area.

  Except for the above, portions corresponding to each other are similarly provided between the transistor array panel 101 of the second embodiment and the transistor array panel 1 of the first embodiment.

  Also in this embodiment, since the plurality of protection elements 109 are arranged along the short-circuit wiring 118 in the non-display area on the lower end side of the data line 104, the protection elements 109 are provided at the left and right ends of the gate line 103. Space to provide is not necessary. Therefore, the non-display area on the left and right end sides of the gate line 103 can be narrowed.

[Third Embodiment]
A transistor array panel 201 according to the third embodiment will be described with reference to FIGS. 7 is an equivalent circuit diagram of the transistor array panel 201, and FIG. 8 is a plan view showing the lower side of the right edge of the transistor array panel 201. As shown in FIG. 9 is a cross-sectional view taken along the line IX-IX in FIG. FIG. 10 is a plan view showing a lower edge portion of the transistor array panel 201. In the following description, for the transistor array panel 201, a lower two-digit common number is assigned to a portion corresponding to any portion of the transistor array panel 1 in the first embodiment.

  In the first embodiment, all the routing wirings 21 are formed from the gate film. However, in the second embodiment, the odd-numbered gate lines 203 (hereinafter, the odd-numbered gate lines 203 are denoted by reference numerals 203a. The routing wiring 221a connected to the even-numbered gate line 203 (hereinafter, the even-numbered gate line 203 is referred to as 203b) is connected to the routing wiring 221b. Is formed from the drain film. The lower end portion of the routing wiring 221a serves as an address terminal 222a, and the lower end portion of the routing wiring 221b serves as an address terminal 222b.

  The lead wiring 221a is integrally formed with the gate line 203a. The upper end portion of the routing wiring 221b is connected to the right end portion of the gate line 203b through the contact hole 248. The routing wiring 221a and the routing wiring 221b are separate layers, and are formed in a state where the routing wiring 221a and the routing wiring 221b overlap each other in plan view. Since the routing wiring 221a and the routing wiring 221b overlap each other on the right side of the display area, the left and right width of the non-display area on the right side of the display area can be reduced.

  In the first embodiment, the short-circuit wiring 14 includes the vertical belt portion 15 and the horizontal belt portion 16 and is provided in an L shape. However, in the third embodiment, the short-circuit wiring 214 is the vertical belt portion. It consists of 215 and is provided in a straight line.

  Further, below the lower side portion 212 of the short-circuit wiring 210, the short-circuit wiring 217 extends in the row direction so as to be parallel to the lower side portion 212. The short-circuit wiring 217 is connected to the short-circuit wiring 210 and is integrally formed with the short-circuit wiring 210. Therefore, the short-circuit wiring 217 is formed simultaneously with the gate 231 and the gate line 203 by patterning the gate film, and crosses the plurality of data lines 204. The right end portion of the short-circuit wiring 217 is connected to the short-circuit wiring 218 through a contact hole 249 formed in the gate insulating film 232. The short-circuit wiring 218 is formed so as to extend rightward from the right end portion of the short-circuit wiring 217 in plan view, and is parallel to the gate line 203. The shorting wiring 218 crosses the plurality of routing wirings 221a and 221b, and the portion 218a of the shorting wiring 218 that intersects the routing wiring 221a is formed simultaneously with the source 237, the drain 238, and the data line 204 of the drain film. A portion 218b intersecting with the lead wiring 221b is formed simultaneously with the gate 231 and the gate line 203 by patterning the gate film. A portion 218 a that intersects the routing wiring 221 a and a portion 218 b that intersects the routing wiring 221 b are connected via a contact hole 249 formed in the gate insulating film 232.

  In the first embodiment, the first protection element 9 is connected between the lateral band portion 16 of the short-circuit wiring 14 and the routing wiring 21, but in the third embodiment, the first protection element 209a. Are connected between the short-circuit wiring 218 and the lead-out wiring 221a, and the first protection element 209b is connected between the short-circuit wiring 218 and the lead-out wiring 221b. Both electrodes 291 a and 292 a of the protective element 209 a are formed from the drain film, one electrode 291 a is connected to the lead wiring 221 a through the contact hole 246, and the other electrode 292 a is the short-circuit wiring 218. It is integrally formed with a portion 218a that intersects with the lead wiring 221a. A resistor 293a formed at the same time as the semiconductor film 233 is connected between the electrode 291a and the electrode 292a by patterning the semiconductor film on the entire surface of the semiconductor film 233 of the thin film transistor 205. Both the electrodes 291b and 292b of the protective element 209b are formed from a drain film. One electrode 291b of the protective element 209b is integrally formed with the lead wiring 221b, and the other electrode 292b of the protective element 209b is a contact hole 249. Is connected to a portion 218b of the short-circuit wiring 218 that intersects the routing wiring 221b. A resistor 293b formed at the same time as the semiconductor film 233 is connected between the electrode 291b and the electrode 292b by patterning the semiconductor film on the entire surface of the semiconductor film 233 of the thin film transistor 205. These protection elements 209a and 209b are arranged along the short-circuit wiring 218 below the display area.

  Except for the above, portions corresponding to each other are similarly provided between the transistor array panel 201 of the third embodiment and the transistor array panel 1 of the first embodiment.

  Also in this embodiment, since the plurality of protection elements 209 are arranged along the short-circuit wiring 218 in the non-display region on the lower end side of the data line 204, the protection elements 209 are provided at the left and right ends of the gate line 203. Space to provide is not necessary. Therefore, the non-display area on the left and right end sides of the gate line 203 can be narrowed.

[Fourth Embodiment]
A transistor array panel 301 according to the fourth embodiment will be described with reference to FIGS. FIG. 11 is an equivalent circuit diagram of the transistor array panel 301, and FIG. 12 is a plan view showing the lower side of the right edge of the transistor array panel 301. In the following description, for the transistor array panel 301, a lower two-digit common number is assigned to a portion corresponding to any portion of the transistor array panel 201 in the third embodiment.

  In the third embodiment, the short-circuit wiring 217 is formed from the gate film and extends in the row direction so as to intersect the data line 204 in plan view. However, in the fourth embodiment, the short-circuit wiring 217 is formed from the drain film. The formed short-circuit wiring 318 does not intersect the data line 304 in plan view, and is parallel to the gate line 303 below the data terminal 308. The short-circuit wiring 318 extends in the row direction below the address terminals 322a and 322b, and does not intersect the routing wirings 321a and 321b in plan view. Further, the short-circuit wiring 318 is connected to the short-circuit wiring 310 through a contact hole 351 formed in the gate insulating film 332.

  The first protection element 309a is connected between the short-circuit wiring 318 and the routing wiring 321a, and the first protection element 309b is connected between the short-circuiting wiring 318 and the routing wiring 321b. Both electrodes 391a and 392a of the protective element 309a are formed of a drain film, one electrode 391a is connected to the lead wiring 321a through the contact hole 346, and the other electrode 392a is integrated with the short-circuit wiring 318. Is formed. A resistor 393a formed at the same time as the semiconductor film 333 is connected between the electrode 391a and the electrode 392a by patterning the semiconductor film on the whole surface of the semiconductor film 333 of the thin film transistor 305. Both electrodes 391b and 392b of the protective element 309b are formed from a drain film, one electrode 391b of the protective element 309b is integrally formed with the lead wiring 321b, and the other electrode 392b of the protective element 309b is a short-circuit wiring. 318 is integrally formed. A resistor 393b formed at the same time as the semiconductor film 333 is connected between the electrode 391b and the electrode 392b by patterning the semiconductor film on the entire surface of the semiconductor film 333 of the thin film transistor 305. These protection elements 309a and 309b are arranged along the short-circuit wiring 318 below the display area.

  Except for the above, portions corresponding to each other are similarly provided between the transistor array panel 301 of the fourth embodiment and the transistor array panel 201 of the third embodiment.

  Also in this embodiment, since the plurality of protection elements 309 are arranged along the short-circuit wiring 318 in the non-display region on the lower end side of the data line 304, the protection elements 309 are provided at the left and right ends of the gate line 303. Space to provide is not necessary. Therefore, the non-display area on the left and right end sides of the gate line 303 can be narrowed.

1 is an equivalent circuit diagram of a transistor array panel 1 in a first embodiment. 2 is a plan view showing a right edge portion of a transistor array panel 1. FIG. It is arrow sectional drawing of the surface along the cutting line III-III of FIG. 2 is a plan view showing a lower edge portion of a transistor array panel 1. FIG. It is an equivalent circuit diagram of the transistor array panel 101 in the second embodiment. 3 is a plan view showing a lower edge portion of a transistor array panel 101. FIG. FIG. 10 is an equivalent circuit diagram of a transistor array panel 201 in the third embodiment. 3 is a plan view showing a right edge portion of a transistor array panel 201. FIG. It is arrow sectional drawing of the surface along the cutting line IX-IX of FIG. 4 is a plan view showing a lower edge portion of a transistor array panel 201. FIG. It is an equivalent circuit diagram of the transistor array panel 301 in the fourth embodiment. 3 is a plan view showing a lower edge portion of a transistor array panel 301. FIG. FIG. 10 is an equivalent circuit diagram of a conventional transistor array panel 401.

Explanation of symbols

1, 101, 201, 301 Transistor array panel 2, 102, 202, 302 Insulating transparent substrate (substrate)
3, 103, 203, 303 Gate line 4, 104, 204, 304 Data line 5, 105, 205, 305 Thin film transistor 6, 106, 206, 306 Pixel electrode 7, 107, 207, 307 Second protection element 9, 109 , 209, 309 First protection element 10, 210, 310 Short-circuit wiring (another short-circuit wiring)
12, 212, 312 Lower side portion 14 Short-circuit wiring 16 Horizontal belt portion 117 Short-circuit wiring (another short-circuit wiring)
118, 218, 318 Short-circuit wiring 21, 121, 221a, 221b, 321a, 321b

Claims (2)

A plurality of gate lines and a plurality of data lines are formed orthogonally to each other through an insulating film on the substrate, and a thin film transistor is disposed at each intersection of the plurality of gate lines and the plurality of data lines. In a transistor array panel in which a gate is connected to the gate line and one of a source and a drain of the thin film transistor is connected to the data line,
A plurality of routing lines provided in parallel to the plurality of data lines are arranged on the end side of the plurality of gate lines, and one end of the plurality of routing lines is connected to the plurality of gate lines, respectively. And a short-circuit wiring provided in parallel to the plurality of gate lines is disposed on the other end side of the plurality of routing wirings, and is connected between the short-circuit wiring and the plurality of routing wirings, respectively. A plurality of first protection elements arranged along the short-circuit wiring ,
Another short-circuit wiring provided in parallel to the plurality of gate lines is disposed on the end side of the plurality of data lines, and is connected between the another short-circuit wiring and the plurality of data lines, respectively. A transistor array panel, wherein the plurality of second protective elements arranged along the another short-circuit wiring . 2. The transistor array panel according to claim 1 , wherein the short-circuit wiring and the other short-circuit wiring are connected.

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