JP4726425B2 - Information processing device - Google Patents

Description

  The present invention relates to an information processing apparatus such as a personal computer or PDA (Personal Digital Assistants) having an internal device such as a hard disk.

  As personal computers (hereinafter referred to as PCs), there are a desktop type and a notebook type. In general, desktop PCs are low-cost and high-performance, but not portable, and notebook PCs are portable because they are powered by batteries, but they are desktop-like in terms of performance. Is not enough.

  This is because a notebook PC uses a battery as a power source and adopts low-power consumption components that are disadvantageous in terms of performance, and it can be said that it pursues portability in exchange for performance. In particular, in pursuit of portability, and designed with “always carry” in mind, the small size, light weight and long life of the battery are extremely important, and the main body itself has been made lighter, thinner and shorter, and its performance I could not hope for improvement.

  For this reason, if the user wants both performance and portability for the PC, the user uses a desktop PC at the office or home and uses a notebook PC when going out. . There are other situations where multiple PCs are used properly. For example, there are situations where each user shares one PC and each user owns each PC, and there are situations where each PC is used properly according to each work content.

  By the way, when a plurality of PCs are used properly, data migration between the PCs is frequently performed. For example, data created on a notebook PC when going out may be migrated to a desktop PC, or data created on a desktop PC may be migrated to a notebook PC.

Conventionally, in order to transfer data between PCs, removable disk media (floppy (registered trademark) disk, MO disk, etc.) and memory cards (compact flash (registered trademark) , smart media (registered trademark), etc.) A recording medium was used. The method of using this recording medium is to record data on the recording medium on the data transfer source PC side, carry the recording medium from the data transfer source PC to the data transfer destination PC, and then on the data transfer destination PC side. Data is read from the recording medium.

There is also a method in which two PCs are connected through a serial cable, a USB (registered trademark) cable, or a LAN, and data is directly transferred from the transfer source PC to the transfer destination PC (see Patent Document 1). ).

  However, in the method of linking the two PCs, it is necessary to perform exclusive control in order to prohibit simultaneous access to the storage device of the transfer source PC by a plurality of PCs. For example, when a transfer source PC is connected to a data transfer destination PC via a bus, the storage device is disconnected from the CPU by the bus coupling unit and the arbitration unit, and access to the storage device by the CPU is prohibited. Then, this storage device is connected to the CPU of the transfer destination PC via the bus, so that the CPU of the transfer destination PC can directly access the storage device (see Patent Document 2).

4 (a) and 4 (b) schematically show two PCs connected to each other. When the transfer source PC 101 and the transfer destination PC 111 are not linked as shown in FIG. 4A, the CPU 102 is connected to the storage device 104 via the bus 103 in the transfer source PC 101, and the CPU 102 moves to the storage device 104. In addition, the bus 106 between the storage device 104 and the interface 105 is disconnected to prohibit access to the storage device 104 from the outside. Further, when the transfer source PC 101 and the transfer destination PC 111 are connected as shown in FIG. 4B, the bus 103 is disconnected in the transfer source PC 101 to prohibit the CPU 102 from accessing the storage device 104. In addition, the bus 106 between the storage device 104 and the interface 105 is connected to allow the transfer destination PC 111 to access the storage device 104. Thereby, access to the storage device 104 is performed exclusively.
JP 2000-21504 A Japanese Patent Laid-Open No. 10-105504

  However, in order to transfer data by connecting two PCs as described above, there are other points to consider in addition to exclusive control that prohibits simultaneous access to a storage device.

  In information processing apparatuses such as PCs and PDAs, in general, a standby state is set by using a power saving function, a standby function (screen saver function), etc., and if two PCs are connected, this standby state is considered. Should.

  This standby state is set when, for example, the information device has not been operated by the user for a certain period of time. Prior to setting the standby state, the CPU state (values of various CPU registers, etc.) and the state of some or all devices controlled by the CPU are saved in a storage device, and the PC OS (Operating System) must be in hibernation mode. The storage device is a volatile RAM (generally, a main storage device mapped to the CPU address space), a nonvolatile hard disk, or the like.

  The return from the standby state to the operating state (referred to as resume) is performed, for example, when the information device is operated by the user. With this restoration, the CPU state, device state, and the like are reset, and the OS of the PC enters the operating state.

  Here, in order to transfer data from one PC in the standby state to the other PC when one of the two PCs is in the standby state, it is necessary to set at least the storage device to the operating state in the PC in the standby state. There is.

  However, when the storage device of the PC in the standby state is accessed from the other PC, for example, when the data in the storage device is updated or deleted, the state of the CPU or device saved in the storage device And so on, and the OS of the PC is not completely restored. For this reason, an operation for correcting the OS of the PC that has not been completely restored becomes necessary, the load on the user increases, and a long time is spent for restoring the OS.

  Such a problem relating to data transfer from the PC in the standby state to the other PC occurs not only in the hard disk but also in the volatile RAM. For example, in cache processing in an OS or application software, the contents of a part of the hard disk are transferred to a buffer in the RAM, and read / write to the buffer makes apparent access to the hard disk faster. If a specific factor such as file closing occurs, the buffer contents are returned to the hard disk. If this cache processing is taken into consideration, it is clear that there arises a problem that the OS of the PC is not completely restored even if the save destination of the CPU state and the device state is a volatile RAM.

  This problem occurs not only in the standby state by the power saving function but also in the standby state by the standby function. That is, it is clear that there is a problem that the OS of the PC in the standby state does not completely recover in consideration of the fact that the data (file) on the standby screen can be deleted even in the standby state by the standby function.

  However, the data on the standby screen is generally stored in a storage area that cannot be accessed from the external device, or even if it is deleted by access from the external device, it does not cause a fatal injury to the OS.

  Accordingly, the present invention has been made in view of the above-described conventional problems, and provides an information processing apparatus that enables both external access to a storage device in a standby state and normal return from the standby state. The purpose is to do.

In order to solve the above problems, an information processing apparatus of the present invention includes a computing means for processing data, a plurality of storage devices that are controlled by said calculation means, either the state of the arithmetic means of each storage device is retracted, the off the standby state setting means for setting a standby state, and interface means for connecting each of said storage device and an external device, said interface means when said operation means is operated state of the operation means, Power control means for turning on the interface means when a standby state of the computing means is set, and the interface means is turned on by the power control means, and the external device turns the interface means on. When connected to each storage device, the access method from the external device is restricted for each storage device.

According to the information processing apparatus of the present invention, when access from an external device to the storage peripherals, the standby state of the operation means in accordance with whether it is set, it has given restrictions on the access. For example, when the standby state of the operation means has been set to disallow write access from the external device to the storage peripherals, to prevent access to a particular file. Thereby, it is possible to prevent the state of the calculation means from changing in the standby state, and for example, it is possible to ensure complete recovery of the OS of the PC in the standby state. Accordingly, an operation for correcting an OS that has not been completely restored as in the prior art is not required, the load on the user is not increased, and a long time is not spent for restoring the OS.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing Embodiment 1 of the information processing apparatus of the present invention. The information processing apparatus according to the present embodiment is a personal computer (hereinafter referred to as a PC) 10 and includes a CPU 11. The CPU 11 executes various programs and controls the system memory 12, the display control unit 13, the I / O control unit 14, and the like via the core logic 15. The CPU 11, the system memory 12, the display control unit 13, the I / O control unit 14, the core logic 15 and the like are connected through a bus.

  Here, a bus related to the CPU 11 is referred to as a processor bus 16a, a bus related to the system memory 12 is referred to as a memory bus 16b, and a bus related to the display control unit 13, the I / O control unit 14 and the like is referred to as a system bus 16c. In addition, there are a disk bus 16d, an I / O bus 16e, and the like.

  The system bus 16c is also connected to other devices such as a LAN (not shown) via the I / O control unit 14.

  The system memory 12 stores the OS (Operating System) and BIOS (Basic Input / Output System) program codes that are the core of the PC system, as well as application software program codes, work areas, and the like. Each program code is executed or work area is used.

  The display control unit 13 writes display data by the CPU 11, and controls the display device 20 through the display interface in response to this, and displays an image indicated by the display data on the screen of the display device 20. The display device 20 is a CRT, LCD, or the like.

  The I / O control unit 14 accesses the hard disk device 21 and the optical disk device 22 via the disk bus 16d in accordance with a data read request or write request from the CPU 11, and instructs the hard disk device 21 to read or write data. Or reading or writing data to or from the optical disk of the optical disk device 22.

    The I / O control unit 14 is connected to the keyboard / mouse control unit 23 and the power supply control unit 24 via the I / O bus 16e.

   The keyboard / mouse control unit 23 is connected to a keyboard 26 and a mouse (pointing device) 27, and outputs input data from the keyboard 26 and the mouse 27 to the CPU 11 via the I / O control unit 14.

   In the power saving control, the keyboard / mouse control unit 23 has a role of instructing the power control unit 24 to shift to the power saving state (corresponding to the standby state) in response to the operation state of the keyboard 26 and the mouse 27. Take on.

   This power saving control is performed by activating a specific program code (hereinafter, this program code is referred to as an idle detection unit) stored in the system memory 12 and used in the OS or BIOS. The idle detection unit monitors the operation state based on the input data of the keyboard 26 and the mouse 27 output from the keyboard / mouse control unit 23. If the idle state continues for a preset time, the idle detection unit The power supply control unit 24 is instructed to shift to the power saving state through the I / O control unit 14. In response to this, the power control unit 24 executes power saving control. Of course, the idle detection unit is realized by executing a specific program code by the CPU 11 and performing control from the CPU 11 via the core logic 15 and the I / O control unit 14.

  In addition, not only when the power saving state is determined when it is determined that the idle state is entered, but also when a special button (generally referred to as a suspend button) for instructing the power saving state is pressed, The power saving state may be set when the lid switch for detecting opening and closing of the display unit (lid) of the notebook PC is switched. Furthermore, the power saving state may be set when the voltage of the battery 30 becomes equal to or lower than a preset voltage.

  The power control unit 24 is connected to the I / O bus 16e, the power button 28, and the power control unit 29, and responds to an operation of the power button 28 or an instruction from the CPU 11 to shift to a power saving state. 29 is controlled to turn on / off the power of the PC 10. The power supply control unit 24 controls the power control unit 29 to shift the PC 10 from the operating state to the power saving state, return from the power saving state to the operating state, and charge / discharge the battery 30. to manage.

    In addition, the power control unit 24 outputs the operating state, non-operating state, power saving state, transition information of each state, and the like of the PC 10 to the interface bridge control unit 42.

   The power control unit 29 is connected to the battery 30 and the power connector 31, and distributes and supplies the power from the battery 30 or the external power received through the power connector 31 to the entire PC 10 or a part of the blocks.

   Here, the operating state of the PC 10 is set when a system-on signal is output from the power supply control unit 24 to the power control unit 29, and almost all blocks except the interface bridge control unit 42 and the interface bus connector 43 are set. It operates in response to power supply from the power control unit 29. Further, the non-operating state and the power saving state are set when a system off signal is output from the power supply control unit 24 to the power control unit 29, and the power supply control unit 24 and the bus selection unit shown by shading in FIG. 41, only the blocks such as the interface bridge control unit 42, the interface bus connector 43, the hard disk device 21, and the optical disc device 22 operate with power supplied from the power control unit 29.

   In the PC 10 of this embodiment, the state of the CPU 11 is saved in a non-volatile memory such as the hard disk device 21, and the power saving state in which the power supply to each block such as the system memory 12, the CPU 11, and the display control unit 13 is cut off. However, instead of this, the state of the CPU is saved in the system memory 12 and the CPU 11, the core logic 15, etc., except for the system memory 12, are illustrated. Transition to a power saving state in which power supply to the block is interrupted and return control from the power saving state may be performed.

   The bus selection unit 41 is controlled by the power supply control unit 24 to connect and disconnect the disk bus 16d of the hard disk device 21 and the optical disk device 22. When the system selection signal is input from the power supply control unit 24, the bus selection unit 41 connects the disk bus 16d of the hard disk device 21 and the optical disk device 22 to the I / O control unit 14, and the disk buses of the devices 21 and 22 are connected. 16d is disconnected from the interface bridge controller 42. In addition, when the system selection signal is input from the power control unit 24, the bus selection unit 41 disconnects the disk bus 16d of the hard disk device 21 and the optical disk device 22 from the I / O control unit 14, and the disk of each of the devices 21 and 22 is disconnected. The bus 16d is connected to the interface bridge controller 42.

   The interface bridge control unit 42 is connected to the bus selection unit 41, the interface bus connector 43, and the power supply control unit 24.

When the interface bridge control unit 42 is connected to the disk bus 16d via the bus selection unit 41, the interface bridge control unit 42 absorbs the difference in specifications between the external bus and the disk bus 16d interconnected via the interface bus connector 43. . For example, if the external bus is a USB (Universal Serial Bus) and the disk bus 16d is an ATAPI bus, the interface bridge control unit 42 converts the ATAPI bus specification into a USB (registered trademark) specification. Accordingly, the hard disk device 21 and the optical disk device 22 are recognized as USB (registered trademark) devices from the outside via the interface bus connector 43.

Note that a USB 2.0, IEEE 1394 bus, or the like may be used instead of USB (registered trademark) . Further, the interface bus connector is externally connected in accordance with the operating state, non-operating state, power saving state of the PC 10 which is set by the system on signal and the system off signal from the power supply control unit 24, and the transition information of each state. The access to the hard disk device 21 and the optical disk device 22 is controlled via 43, which will be described later.

   Next, the control content of the power control unit 24 in the PC 10 of this embodiment will be described in detail with reference to the flowchart shown in FIG.

   First, the power supply control unit 24 operates by receiving power supply from the power control unit 29 regardless of the operating state, non-operating state, and power saving state of the PC 10. Therefore, for example, when the user attaches the battery 30 to the PC 10, the power supply control unit 24 starts up and the control program of the power supply control unit 24 is entered. When the power supply control unit 24 starts up, the system on instruction (step S100) by the operation of the power button 28 (step S100), the instruction to shift to the power saving state by the CPU 11 (step S110), and the system off instruction by the operation of the power button 28 ( It is determined whether or not there has been step S120), and it waits until any instruction is given, and this determination is repeated.

   If there is an instruction to turn on the system by operating the power button 28 during each step S100, S110, S120 ("YES" in step S100), the power supply control unit 24 sends a system-on signal to the power control unit 29. Is output (step S101). As a result, most of the blocks except for the interface bridge control unit 42 and the interface bus connector 43 operate by receiving power supply from the power control unit 29, and the PC 10 starts up.

   When the PC 10 is started up, the power supply control unit 24 determines whether or not the previous state of the operating state is a power saving state (step S102). If the previous state is not the power saving state (“NO” in step S102), each step S103, S104 is skipped, and the process returns to the standby of each step S100, S110, S120.

   If the previous state is a power saving state (“YES” in step S102), the power supply control unit 24 sends a signal indicating return from the power saving state to the CPU 11, the I / O control unit 14, The data is output to the core logic 15 (S103).

   When the CPU 11, the I / O control unit 14, and the core logic 15 input a signal indicating a return from the power saving state, the state of the CPU 11 (the registers of various registers of the CPU 11) when entering the power saving state as described later. And the state of some or all of the devices that are I / O controlled by the CPU 11 are saved in the nonvolatile memory of the hard disk device 21, so that the state of the CPU 11 and the device state are read from the hard disk device 21. And execute the sequence for resetting.

   In a general PC architecture, the main part of the return control from the power saving state is processed by a specific program code (OS) stored in the system memory 12. However, a part of the return control, for example, the return control of the storage state of the system memory 12 is processed by the program code stored in the power supply control unit 24 or the nonvolatile part of the system memory 12.

   When the PC 10 is thus started up and in an operating state, the power supply control unit 24 outputs a system-on signal to the bus selection unit 41. When the system selection signal is input, the bus selection unit 41 connects the disk bus 16d of the hard disk device 21 and the optical disk device 22 to the I / O control unit 14, and controls the disk bus 16d of each of the devices 21 and 22 by interface bridge control. Disconnect from the unit 42 (S104). Thereafter, the process returns to standby in steps S100, S110, and S120.

   In addition, when there is an instruction to shift to the power saving state by the CPU 11 during each step S100, S110, and S120 ("YES" in S110), the power supply control unit 24 indicates the transition to the power saving state. A signal is output to CPU11, I / O control part 14, and core logic 15 (S111). In response to this, the state of the CPU 11 (values of various registers of the CPU 11) and the state of some or all of the devices controlled by the CPU 11 are saved in the nonvolatile memory of the hard disk device 21.

   In a general PC architecture, the main part of the transition control to the power saving state is also executed in a specific program code (OS) stored in the system memory 12 in the same manner as the return control from the power saving state. It is processed.

   Subsequently, the power supply control unit 24 outputs a system off signal to the power control unit 29 (step S112). When the system control signal is input, the power control unit 29 receives the power supply control unit 24, the bus selection unit 41, the interface bridge control unit 42, the interface bus connector 43, the hard disk device 21, the optical disk device 22, and the like shown by hatching in FIG. Power is supplied to only these blocks to operate these blocks.

   The power supply control unit 24 also outputs a system off signal to the bus selection unit 41. When the system selection signal is input from the power supply control unit 24, the bus selection unit 41 disconnects the disk bus 16d of the hard disk device 21 and the optical disk device 22 from the I / O control unit 14, and the disk bus of each of the devices 21, 22 16d is connected to the interface bridge controller 42 (step S113).

   Furthermore, the power supply control unit 24 outputs a power save signal indicating the transition to the power saving state to the interface bridge control unit 42 (step S114). Thereafter, the process returns to standby in steps S100, S110, and S120.

   In addition, when there is a system off instruction by operating the power button 28 during each step S100, S110, and S120 (“YES” in S120), the power control unit 24 sends a system off signal to the power control unit 29. (Step S121). As a result, as in the power saving state, only blocks such as the power supply control unit 24, the bus selection unit 41, the interface bridge control unit 42, the interface bus connector 43, the hard disk device 21, and the optical disk device 22 shown by shading in FIG. Operates with power supply.

   The power supply control unit 24 also outputs a system off signal to the bus selection unit 41. As a result, similarly to the power saving state, the disk bus 16d of the hard disk device 21 and the optical disk device 22 is disconnected from the I / O control unit 14, and the disk bus 16d of each of the devices 21 and 22 is connected to the interface bridge control unit 42. (Step S122).

   Furthermore, the power supply control unit 24 outputs a power-off signal indicating that it has shifted to the non-operating state to the interface bridge control unit 42 (step S123). Thereafter, the process returns to standby in steps S100, S110, and S120.

   As described above, in the operating state of the PC 10, most of the blocks except the interface bridge control unit 42 and the interface bus connector 43 operate with power supplied from the power control unit 29, and the disks of the hard disk device 21 and the optical disk device 22 are operated. The bus 16d is connected to the I / O control unit 14, and the disk bus 16d of each of the devices 21 and 22 is disconnected from the interface bridge control unit 42.

   Further, in the power saving state of the PC 10, only the blocks such as the power supply control unit 24, the bus selection unit 41, the interface bridge control unit 42, the interface bus connector 43, the hard disk device 21, and the optical disk device 22 shown by hatching in FIG. The disk bus 16d of the hard disk device 21 and the optical disk device 22 is disconnected from the I / O control unit 14, and the disk bus 16d of each of the devices 21 and 22 is connected to the interface bridge control unit 42. . Then, a power save signal is output to the interface bridge controller 42.

   Further, in the non-operating state of the PC 10, similarly to the power saving state, the power supply control unit 24, the bus selection unit 41, the interface bridge control unit 42, the interface bus connector 43, the hard disk device 21, and the optical disk, which are indicated by hatching in FIG. Only the block such as the device 22 operates by receiving power supply, the hard disk device 21 and the disk bus 16d of the optical disk device 22 are disconnected from the I / O control unit 14, and the disk bus 16d of each of the devices 21 and 22 is an interface bridge. Connected to the control unit 42. However, it differs from the power saving state in that a power-off signal is output to the interface bridge controller 42.

   By the way, the PC 10 and the external PC 61 are connected to each other, and data transfer may be performed between the PCs 10 and 61 by accessing the PC 10 from the external PC 61. Specifically, the interface bus connector 43 of the PC 10 is connected to the connector of the external PC 61 via the external bus 51, and data is transferred between the PCs 10 and 61 via the external bus 51.

   In the operating state of the PC 10, the interface bridge control unit 42 and the interface bus connector 43 are stopped, the hard disk device 21 and the disk bus 16 d of the optical disk device 22 are connected to the I / O control unit 14, and each of the devices 21, 22 disk bus 16d is disconnected from interface bridge control unit 42, first, interface bridge control unit 42 and interface bus connector 43 are set in an operating state by operating keyboard 26 and mouse 27, and hard disk device 21 and optical disk The disk bus 16 d of the device 22 is disconnected from the I / O control unit 14 and the disk bus 16 d of each of the devices 21 and 22 is connected to the interface bridge control unit 42. As a result, it is possible to transfer data between the PCs 10 and 61 by accessing the hard disk device 21 and the optical disk device 22 of the PC 10 from the external PC 61.

   On the other hand, since the keyboard 26 and the mouse 27 cannot be operated in the power saving state and the non-operating state of the PC 10, the access from the external PC 61 to the hard disk device 21 and the optical disk device 22 of the PC 10 is controlled by the interface bridge control unit 42. Enable.

   Next, details of the control of the interface bridge control unit 42 in the power saving state and the non-operating state will be described in detail with reference to the flowchart shown in FIG.

   As described above, the interface bridge control unit 42 operates by receiving power supply from the power control unit 29 that responds to the control of the power supply control unit 24 when the PC 10 shifts to a non-operating state or a power saving state. .

   When the interface bridge control unit 42 starts operation, the interface bridge control unit 42 first determines whether the power-off signal or the power save signal is output from the power supply control unit 24. (Each step S200, S201).

  For example, when a power-off signal is output and the device is in a non-operating state (“YES” in step S200), the interface bridge control unit 42 inputs / outputs signals from the external PC 61 to the hard disk device 21 or the optical disk device 22, and the hard disk device. 21 or the input / output signal from the optical disk device 22 to the external PC 61, when a signal is input / output to / from the external PC 61 (“YES” in step S210), the specification between the external bus 51 and the disk bus 16d is satisfied. While converting the difference, the input / output signal between the external PC 61 and the hard disk device 21 or the optical disk device 22 is relayed (step S211).

  Therefore, when the PC 10 is not in operation, the external PC 61 can read and write to the hard disk device 21 or the optical disk device 22. This is because in the non-operating state of the PC 10, the CPU 11 state, device state, etc. are not saved, and it is not necessary to protect the CPU 11 state, device state, etc.

  When the power save signal is output and the power saving state is set (“YES” in step S201), the interface bridge control unit 42 generates an input / output of a signal with the external PC 61 (“ YES ”), whether or not the input / output signal is from the external PC 61 to the hard disk device 21 (step S221), and whether or not the input / output signal is a write request (step S222). If it is not an input / output signal from the external PC 61 to the hard disk device 21 (“NO” in step S221) or not an input / output signal for a write request (“NO” in step S222), that is, an optical disc by the external PC 61. In the case of writing and reading of the device 22 and reading of the hard disk device 21 by the external PC 61, the interface bridge control unit 42 converts the difference in specifications between the external bus 51 and the disk bus 16d, and converts the external PC 61 and the hard disk device 21 or The input / output signal between the optical disk devices 22 is relayed (step S223).

   If the input / output signal is an input / output signal from the external PC 61 to the hard disk device 21 (“YES” in step S221) and an input / output signal for a write request (“YES” in step S222), that is, the hard disk device 21 by the external PC 61. Is written, the interface bridge control unit 42 outputs (replies) an error signal to the external PC 61 to prohibit access by the external PC 61 (step S224).

   However, in this case, since it is assumed that the optical disk device 22 is not writable, write request prohibition control is not performed. Therefore, in the power saving state, only reading of the hard disk device 21 or the optical disk device 22 by the external PC 61 is possible.

  If the hard disk device 21 is written by the external PC 61, an error signal is returned, and since it is assumed that the optical disk device 22 cannot be written, only read access from an external device is permitted. However, instead of this, for example, only a write request to a file or a storage area (such as a file in which the state of the CPU 11 or the device is saved) involved in the return control from the power saving state may be prohibited. (Condition suppression of write request).

In particular, when applying the present invention to DVD (registered trademark) player, resume function of DVD (registered trademark) player that resume playback after interrupt the playback of the content, Ya content changes when the playback interrupt Since the system operates normally unless deletion occurs, it is easy to design a condition for restricting the write request, and a system (apparatus) with less restrictions for the user can be realized by restricting the condition for the write request.

  As described above, in this embodiment, in the power saving state, only reading of the hard disk device 21 or the optical disk device 22 by the external PC 61 is permitted, or writing to a file or a storage area involved in return control from the power saving state is performed. Since only the request is prohibited, when returning from the power saving state to the operating state, it is possible to completely reproduce the state of the CPU 11 and the device state in the operating state immediately before this power saving state. The complete recovery of the OS of the PC 10 can be ensured. Accordingly, an operation for correcting an OS that has not been completely restored as in the prior art is not required, the load on the user is not increased, and a long time is not spent for restoring the OS.

  In addition, this invention is not limited to the said Example, It can deform | transform variously. For example, other types of buses may be applied as the bus in the PC 10. Further, an integrated CPU 11 and core logic 15, an integrated core logic 15 and I / O control unit 14, an integrated core logic 15 and display control unit 13, or the like may be applied.

  Further, the power saving state is illustrated as the standby state. However, when the standby screen data (file) is deleted in the standby state, the OS of the PC is not completely restored. Can be applied.

It is a block diagram which shows one Example of the information processing apparatus of this invention. It is a flowchart which shows the control content of the power supply control part in PC of a present Example. It is a flowchart which shows the control content of the interface bridge control part in PC of a present Example. (A) And (b) is a figure which shows the state by which two PC were cut | disconnected and the state connected, respectively.

Explanation of symbols

10 Personal computer (PC)
11 CPU
12 System Memory 13 Display Control Unit 14 I / O Control Unit 15 Core Logic 16a to 16e Bus 20 Display Device 21 Hard Disk Device 22 Optical Disk Device 23 Keyboard Mouse Control Unit 24 Power Control Unit 26 Keyboard 27 Mouse 28 Power Button 29 Power Control Unit 30 Battery 31 Power connector 41 Bus selection unit 42 Interface bridge control unit 43 Interface bus connector 51 External bus 61 Personal computer (external PC)

Claims (1)

Computing means for processing the data;
A plurality of storage devices that will be controlled by the computing means,
A standby state setting unit that saves the state of the arithmetic unit in any of the storage devices and sets the standby state of the arithmetic unit ;
Interface means for connecting each storage device and an external device;
Power supply control means for turning off the interface means when the computing means is in operation, and turning on the interface means when a standby state of the computing means is set,
When the interface unit is turned on by the power source control unit and the external device is connected to each storage device via the interface unit, the access method from the external device is restricted for each storage device. An information processing apparatus characterized by:

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