JP4724400B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus, and more particularly to an imaging apparatus including an image sensor that divides an imaging plane into blocks and reads out pixel values for each block.

  In recent years, CCD image sensors and CMOS image sensors are mainstream image sensors. Compared to a CCD image sensor, a CMOS image sensor can be manufactured at a low cost, and has any advantage that enables low power consumption operation.

  As one direction of such a CMOS image sensor, it is possible to operate with low power consumption as compared with a CCD image sensor. Therefore, the chip area (= light receiving area) of the CMOS image sensor is increased to further increase the number of pixels. There is a movement to measure. The CMOS image sensor consumes less power than the CCD image sensor, so the CMOS image sensor has more chip area when the general power consumption limit allowed by the system is given. Can be made larger (= more pixels).

  Since the time for reading out pixel data for one screen becomes longer due to the increase in the number of pixels, a technique for shortening the time for reading out pixel data for one screen has been developed. For example, there is a technique for shortening the time for reading pixel data for one screen by dividing the imaging surface of one CMOS image sensor into a plurality of blocks and reading the pixel data independently for each divided block. It has been developed (for example, see Patent Documents 1 and 2). For example, in Patent Document 1, two signal lines are placed per pixel row as shown in FIG. 8 and each pixel is connected to a different signal line, or one screen is divided into two as shown in FIG. A technique is disclosed in which the time required for reading one screen is reduced without reducing the scanning time per row by the configuration in which each is connected to a different signal line. Further, Patent Document 2 discloses a technique in which four large image sensors are configured by connecting four image sensor blocks as shown in FIG.

JP-A-8-111182 JP 2002-369078 A

  However, with the area per unit pixel gradually moving toward the reduction direction, it is practically not preferable to take the configuration shown in FIG. 8, and the configurations shown in FIGS. 9 and 10 are the usual solutions. Here, in the CMOS image sensor having a block-divided configuration as shown in FIG. 9 or FIG. 10, there is a problem in that mismatching between blocks occurs because the start and end of the accumulation time are different every other line. FIG. 11 is a timing diagram showing the accumulation and readout operations (scanning) of each row in the circuit configuration of FIG. FIG. 12 is a diagram showing a timing diagram showing the accumulation and reading operations of each row in the circuit configuration of FIG. As shown in FIGS. 11 and 12, in the CMOS image sensor, scanning with different accumulation timings in the pixels in each row is performed independently for each block.

  FIG. 13 is a diagram showing an output image image for a moving subject in the CMOS image sensor having the block-divided configuration shown in FIGS. 9 and 10. First, FIG. 13A shows an image of a moving subject. As shown in FIG. 13A, it is assumed that a quadrangular subject moves to the right and a triangular subject moves downward. When such a moving subject is photographed, the CMOS image sensor of FIG. 9 produces an output image image as shown in FIG. Further, in the CMOS image sensor of FIG. 10, an output image image as shown in FIG. As described above, in the conventional CMOS image sensor having a block-divided configuration, each block is scanned independently, so that only an image having a discontinuity at the boundary between the blocks can be obtained. Due to the nature of human vision, this discontinuity may be particularly noticeable, and there is a problem that it leads to a reduction in objective image quality.

  The present invention has been made in consideration of the above-described circumstances, and has a block configuration divided into at least two in the vertical direction, and when capturing an image with an image sensor that scans each block independently, An object of the present invention is to provide an imaging apparatus capable of eliminating the discontinuity that appears.

The present invention has been made to solve the above-described problems. In the imaging apparatus according to the present invention, a pixel group arranged in a matrix is composed of a plurality of blocks divided at least in the column direction, and each block A vertical signal output line commonly connected to pixels in each column direction, an image sensor that scans the pixels in the row direction and outputs pixel data in units of frames, and is divided into two in the column direction of the image sensor The frame delay means for giving a frame unit delay to the pixel data output from one block, the image data based on the pixel data delayed by the frame delay means and the pixel data output by the other block generated and a image data generating means for said imaging device, and the accumulation start and end time of the last row of the N frames of the one block, the other block (N + 1) -th frame of the first time relation between the accumulation start and end time of the line, said to be equal to the delay times in the respective rows of the one block, and wherein the scanning the pixels of the first row of .

As a result, the accumulation start and end times are aligned in one block and the other block, and image data is generated based on the pixel data output by one block given delay and the pixel data output by the other block. Therefore, the discontinuity that appears in a part of the moving subject can be eliminated.

In one embodiment of the imaging apparatus according to the present invention, the pixel group of the imaging element is also divided in the horizontal direction.
Thereby, even when the number of pixels in the row direction of the image sensor increases, it is possible to prevent the frame rate from decreasing.

Further, an aspect of the imaging apparatus according to the present invention is characterized by further comprising analog / digital conversion means connected to each of the vertical signal output lines.
As a result, even when the number of pixels in the row direction of the image sensor increases, a vertical signal can be output at high speed, so that a decrease in frame rate can be prevented.

In one aspect of the imaging apparatus according to the present invention, the analog / digital conversion means performs analog / digital conversion by a dual slope integration method or a multi-slope integration method.
As a result, the area of the peripheral circuit is reduced with the miniaturization of each pixel by using a dual slope integration method or multi-slope integration method analog / digital conversion circuit that can realize high-speed and high-precision AD conversion in a small area. It is possible to cope with cases that must be done.

According to the present invention, when a moving subject is imaged, discontinuities appearing in a part of the subject image can be eliminated.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a functional configuration that is a feature of the imaging apparatus according to the first embodiment of the present invention will be described. Note that the imaging apparatus in the present embodiment is an imaging apparatus that captures moving images.

  FIG. 1 is a diagram illustrating a functional configuration that is a feature of the imaging apparatus according to the first embodiment of the present invention. In FIG. 1, reference numeral 100 denotes an area image sensor (CMOS image sensor), which is composed of two blocks of an image sensor block 108 having the same configuration as the image sensor block 107. Reference numeral 101 denotes a pixel that accumulates charges by photoelectric conversion and outputs an electrical signal corresponding to the accumulated charges. In the image sensor blocks 107 and 108, pixels having the same configuration as the pixel 101 are arranged in a matrix. They are connected to a common column signal output line 102 in each column, and are connected to a horizontal output line 104 via a column signal processing circuit 103. The horizontal output line 104 is connected to an output terminal that outputs a signal to the outside of the area image sensor 100 through the signal processing circuit 105 again. Each pixel of the image sensor blocks 107 and 108 is scanned in the direction of the arrow shown in FIG.

  The 1-frame delay circuit 109 outputs pixel data delayed by 1 frame by storing the pixel data output from the image sensor block 107 for one frame. The image processing block 110 generates and outputs reproduced image data based on the pixel data output from the 1-frame delay circuit 109 and the pixel data output from the image sensor block 108.

  FIG. 2 is a diagram illustrating an example of a timing diagram for reading pixel data from the area image sensor 100 in the imaging apparatus illustrated in FIG. In FIG. 2, the upper block shows the image sensor block 107 and the lower block shows the image sensor block 108. In FIG. 2, the upper and lower blocks have pixels arranged in 5 rows and 5 columns, but this is for simplification of the description and drawings. In practice, an area image sensor having several million pixels may be used. For example, thousands of rows and thousands of columns.

  In addition, in order to capture a moving image, the imaging apparatus according to the present embodiment reads the first row in the next frame again after the last row of each area sensor block is read. Conventionally, since the final image is constructed using an image of the same Nth frame (N is an integer) in both the upper and lower blocks, when a moving subject as shown in FIG. 3A is imaged, as shown in FIG. It became a discontinuous figure.

  However, in the imaging apparatus according to the present embodiment, the output of the upper block (image sensor block 107) is delayed by one frame by the one-frame delay circuit 109, so that the image processing block 110 includes the Nth frame of the upper block and the lower frame. The final image is reproduced by adding the (N + 1) th frame of the block. As a result, as shown in FIG. 2, the pixel data started to be accumulated at the timing t1 in the upper block and the pixel data started to be accumulated at the timing t2 in the lower block are added together. These accumulation timings are accumulation timings having continuity between the upper block and the lower block, as indicated by underlining “accumulation” in FIG. That is, the time relationship between the accumulation start / end time of the last row of the Nth frame of the upper block and the accumulation start / end time of the first row of the (N + 1) th frame of the lower block is equal to the shift time between the rows. Thereby, it is possible to obtain a reproduced image having continuity (no discontinuity) as shown in FIG.

  As described above, the imaging device according to the present embodiment is an imaging device in which the start time and end timing of the accumulation time of each row do not match, and has a block configuration divided into two in the column direction. Is provided with an image sensor that outputs pixel data by scanning, and pixel data from one block divided in two in the column direction (the one from which pixels are read first) is delayed by one frame, so that each row The start and end timings of the accumulation time can be continuously changed to be constant. As a result, discontinuities appearing in a part of a moving subject that could not be resolved in the past when imaging with the area image sensor 100 having a block configuration divided at least in the vertical direction and independently scanning each block. Can be resolved.

  Although FIG. 1 shows a configuration including the one-frame delay circuit 109, the configuration is not limited to this configuration. For example, an extra frame buffer for delaying one frame may be provided with a function of a memory that is a part of a large frame buffer. The block configuration diagram shown in FIG. 1 is only for explaining functions, and does not limit the circuit configuration.

  In the above-described embodiment, the CMOS image sensor is used. However, the present invention is not limited to this, and the pixel configuration of the image sensor is not limited to any one. For example, the pixel may be CMD, BASIS, or the like. Various configurations of the function of scanning each pixel and reading out pixel data are also conceivable. For example, the column signal processing circuit 103 may include a gain amplifier, an AD converter, a reset noise removal circuit, and the like, and the signal processing circuit 105 may have functions such as a buffer, reset noise removal, CDS, and AD conversion. .

  In particular, by mounting an AD converter for each column of the pixel array of the area image sensor 100, the time for outputting pixel data to the outside can be shortened. That is, the column signal processing circuit 103 preferably includes an AD converter. In the future, when the absolute number of pixels is large, it is assumed that the technique of block division will mainly be used to increase the frame rate. In such a case, the frame rate is “the pixel data for one row is the column signal processing circuit. 103 ”or“ time for outputting pixel data processed by the column signal processing circuit 103 to the outside ”, whichever is later. Considering the actual application, it is a necessary condition to reduce the latter “time for outputting the pixel data processed by the column signal processing circuit 103 to the outside”, and in this case, the column signal processing circuit 103 includes an AD converter. Mounting is particularly effective.

  Also, various types of AD converters mounted on the column signal processing circuit 103 can be considered. However, “Dual-Slope Integrating AD Converter” (dual slope integration method) as shown in FIG. A / D converter circuit) or “Multi-Slope Integrating AD Converter” (multi-slope integration type A / D converter circuit) is preferably used. As a result, it is possible to increase the speed while keeping the circuit area small. The pixels of the image sensor are regularly arranged at intervals of several microns, and it is necessary to arrange the column signal processing circuit 103 including the AD converter according to the intervals, and the circuit of the AD converter is configured as shown in FIG. Keeping the area small can accommodate a finer pixel size.

[Second Embodiment]
Next, an imaging apparatus according to a second embodiment, which is different from the area image sensor 100 included in the imaging apparatus according to the first embodiment, in the block division configuration, will be described. Specifically, in the first embodiment, since the columns are not divided in the parallel direction, in the case of a sensor with a large number of columns, the time for outputting one column of data to the outside becomes long, and as a result, the frame rate is increased. It may happen that the desired rate cannot be achieved. Therefore, as the imaging apparatus in the second embodiment, the time required to output one column of data to the outside is shortened by dividing the column in the column direction and effectively reducing the number of columns, thereby achieving a desired frame rate. An imaging device including an image sensor that can be made to operate will be described.

  FIG. 4 is a diagram illustrating a functional configuration block of the imaging apparatus according to the second embodiment. As shown in FIG. 4, the imaging apparatus according to the present embodiment is an imaging apparatus that includes an area image sensor 200 and can capture a moving image. The area image sensor 200 is composed of four divided image sensor blocks 201-204. Outputs of the image sensor blocks 202 and 204 are input to the image processing block 207 via 1-frame delay circuits 205 and 206, respectively. The internal configuration of each of the image sensor blocks 201 to 204 is the same as that of the image sensor block 107 shown in FIG. The image processing block 207 outputs a reproduced image based on the image data output from the image sensor blocks 201 and 203 and the one-frame delay circuits 205 and 206.

  FIG. 5 is a diagram showing an example of a timing diagram for reading pixel data from the area image sensor 200 in the imaging apparatus shown in FIG. In FIG. 5, the upper right block indicates the image sensor block 202, the upper left block indicates the image sensor block 204, the lower right block indicates the image sensor block 201, and the lower left block indicates the image sensor block 203. In FIG. 4, the pixels in all four blocks are arranged in 5 rows and 5 columns, but this is for simplifying the explanation and the drawing. In practice, an area image sensor having several million pixels may be used. For example, thousands of rows and thousands of columns.

  As shown in FIG. 5, the image sensor blocks 201 to 204 start and end accumulation at the same timing. Although the circuit is divided in the scanning direction (right and left), the division in the scanning direction produces no by-products other than improved reading speed (it does not cause discontinuous images), so the right and left blocks There is no need to consider shifting the accumulation time between. Based on the same principle as in the first embodiment, it is only necessary to delay the output of one block in the upper and lower block divisions so that the output of the other block is a series of outputs.

  In the above-described embodiment, the block configuration example divided into two in the row direction and the block configuration example divided into two in the row direction and the column direction are shown. However, the present invention is not limited to this. The number of divisions in the direction is not limited to two.

[Third Embodiment]
Next, as a more specific embodiment of the imaging apparatus shown in FIG. 1 or FIG. 4, an embodiment of a video camera will be described as a third embodiment.
FIG. 7 is a diagram showing a schematic configuration of a video camera (imaging device) according to the third embodiment of the present invention. In FIG. 7, reference numeral 1 denotes a photographing lens, which includes a focus lens 1A for performing focus adjustment, a zoom lens 1B for performing a zoom operation, and an imaging lens 1C.

  2 is a stop, and 3 is a solid-state image sensor that photoelectrically converts an object image formed on the imaging surface into an electrical imaging signal. Here, the solid-state imaging device 3 has the same configuration as the area image sensors 100 and 200 described in the first and second embodiments. Reference numeral 4 denotes a sample hold circuit (S / H circuit) that samples and holds an image pickup signal output from the solid-state image pickup device 3 and further amplifies the level. This sample hold circuit outputs a video signal.

  A process circuit 5 performs predetermined processing such as gamma correction, color separation, and blanking processing on the video signal output from the sample hold circuit 4 and outputs a luminance signal Y and a chroma signal C. The chroma signal C output from the process circuit 5 is subjected to white balance and color balance correction by the color signal correction circuit 21 and output as color difference signals RY and BY. Also, the luminance signal Y output from the process circuit 5 and the color difference signals RY and BY output from the color signal correction circuit 21 are modulated by an encoder circuit (ENC circuit) 24 to generate a standard television signal ( For example, it is output as an NTSC signal). Then, it is supplied to a monitor EVF such as a video recorder (not shown) or an electronic viewfinder.

  Next, reference numeral 6 denotes an iris control circuit, which controls the iris driving circuit 7 based on the video signal supplied from the sample and hold circuit 4 and opens the aperture 2 so that the level of the video signal becomes a predetermined value. The ig meter 8 is automatically controlled to control the amount. Reference numerals 13 and 14 denote different band-limited bandpass filters (BPFs) for extracting high-frequency components necessary for performing focus detection from the video signal output from the sample and hold circuit 4. The signals output from the first band pass filter 13 (BPF 1) and the second band pass filter 14 (BPF 2) are gated by the gate circuit 15 and the focus gate frame signal, respectively, and the peak value is detected by the peak detection circuit 16. Is detected and held, and input to the logic control circuit 17. This signal is called a focus voltage, and the focus lens 1A is controlled by this focus voltage to adjust the focus.

  Reference numeral 18 denotes a focus encoder that detects the moving position of the focus lens 1A, 19 denotes a zoom encoder that detects the focal length of the zoom lens 1B, and 20 denotes an iris encoder that detects the opening amount of the diaphragm 2. The detection values of these encoders are supplied to a logic control circuit 17 that performs system control. The logic control circuit 17 performs focus detection by performing focus detection on the subject based on a video signal corresponding to the set focus detection area. That is, the peak value information of the high frequency components supplied from the respective band pass filters 13 and 14 is taken in, and the focus motor 10 is supplied to the focus drive circuit 9 to drive the focus lens 1A to the position where the peak value of the high frequency components is maximized. Control signals such as a rotation direction, a rotation speed, and rotation / stop are supplied and controlled.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

It is a figure which shows the function structure used as the characteristic of the imaging device in the 1st Embodiment of this invention. FIG. 2 is a diagram illustrating an example of a timing diagram for reading pixel data from an area image sensor 100 in the imaging apparatus illustrated in FIG. 1. It is a figure which shows the output image image with respect to the to-be-moved subject in the area image sensor of the structure divided into blocks shown in FIG. It is a figure which shows the functional structure block of the imaging device in 2nd Embodiment. FIG. 5 is a diagram illustrating an example of a timing diagram for reading pixel data from an area image sensor 200 in the imaging apparatus illustrated in FIG. 4. It is a figure which shows the circuit example of the A / D conversion circuit of a dual slope integration system. It is the figure which showed schematic structure of the video camera (imaging device) in the 3rd Embodiment of this invention. It is a figure which shows the circuit structural example of the conventional CMOS image sensor. It is a figure which shows the circuit structural example of the conventional CMOS image sensor. It is a figure which shows the circuit structural example of the conventional CMOS image sensor. FIG. 10 is a diagram illustrating a timing diagram showing accumulation and readout operations (scanning) of each row in the circuit configuration of FIG. 9. FIG. 11 is a timing diagram showing storage and read operations for each row in the circuit configuration of FIG. 10. It is a figure which shows the output image image with respect to the to-be-moved subject in the CMOS image sensor of the block-divided structure shown in FIG.9 and FIG.10.

Explanation of symbols

1 imaging lens 5 process circuit 17 logic control circuit 24 ENC circuit 100, 200 area image sensor 101 pixel 102 column signal output line 103 column signal processing circuit 104 horizontal output line 105 signal processing circuit 106 vertical shift registers 107, 108, 201, 202, 203, 204 Image sensor block 109, 205, 206 1 frame delay circuit 110, 207 Image processing block

Claims (5)

A group of pixels arranged in a matrix is composed of a plurality of blocks divided into at least two in the column direction, and includes a vertical signal output line commonly connected to pixels in each column direction in each block, and the row direction An image sensor that scans pixels and outputs pixel data in frame units;
Frame delay means for giving a delay in frame units to pixel data output from one block divided into two in the column direction of the image sensor;
Image data generating means for generating image data based on the pixel data delayed by the frame delay means and the pixel data output by the other block , and
The image sensor has a time relationship between the accumulation start / end time of the last row of the Nth frame of the one block and the accumulation start / end time of the first row of the (N + 1) th frame of the other block. An image pickup apparatus that scans the pixels in the first row so as to be equal to a shift time between each row of the block .   The image pickup apparatus according to claim 1, wherein the pixel group of the image pickup element is also divided in a horizontal direction.   3. The imaging apparatus according to claim 1, further comprising analog / digital conversion means connected to each of the vertical signal output lines.   4. The imaging apparatus according to claim 3, wherein the analog / digital conversion means performs analog / digital conversion by a dual slope integration method or a multi slope integration method. An optical system for forming a subject image on the light receiving surface of the image sensor;
The imaging apparatus according to claim 1, further comprising: a conversion unit that converts the image data generated by the image data generation unit into a standard television signal.

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