JP4703378B2 - Electronic camera - Google Patents

Description

  The present invention relates to an electronic camera, and more particularly to an electronic camera that reproduces a moving image based on a plurality of object scene images obtained by repeating an exposure operation, for example.

An example of a conventional camera of this type is disclosed in Patent Document 1. According to this prior art, when a real-time moving image of the scene is displayed on the LCD monitor, image data representing the scene is created every 1/15 seconds by the imaging device. The created image data is once written in the SDRAM and then read out every 1/30 seconds. That is, the image data of each frame is read twice from the SDRAM. On the LCD monitor, a real-time moving image based on the image data read out in this way is displayed.
JP 2000-125168 A [H04N 5/225, 5/907, 7/24]

  However, in the prior art, since the frame rate of the image data output from the imaging device is lower than the frame rate of the image data read from the SDRAM, there is a problem that the motion of the moving image reproduced on the LCD monitor becomes unnatural. is there.

  Here, if the frame rate of the image data output from the imaging device is doubled, a moving image that moves smoothly can be reproduced. However, there is a problem that power consumption increases due to an increase in the frame rate.

  Therefore, a main object of the present invention is to provide an electronic camera that can reduce power consumption and improve the quality of a reproduced image.

  An electronic camera (10) according to the invention of claim 1 includes an imaging means (14) having an imaging surface for capturing an object scene, an exposure means (18) for exposing the imaging surface at a rate of once per first period, and an exposure means. Reading means (S35) for reading out the object scene image generated on the imaging surface by the exposure process from the imaging means at a rate of one screen in the second period which is N times the first period (N: an integer of 2 or more); Extraction means (20, 24, 26, 28) for extracting a partial object scene image belonging to the extraction area from the object scene image read by the reading means, and a moving image based on the partial object scene image extracted by the extraction means Reproduction means (30) for reproducing the image, position setting means (S83) for setting the extraction area as a reference position every time the reading means executes the reading process, and imaging the extraction area every time the extracting means executes the extraction process A moving means (S89) for moving in the direction opposite to the movement direction of the surface is provided.

  The imaging means has an imaging surface that captures the object scene. The imaging surface is exposed by the exposure means at a rate of once in the first period. The readout means outputs the object scene image generated on the imaging surface by the exposure processing of the exposure means from the imaging means at a rate of one screen in the second period which is N times the first period (N: an integer equal to or greater than 2). read out.

  The extraction means extracts a partial object scene image belonging to the extraction area from the object scene image based on the electric charge read by the reading means. A moving image based on the partial scene image extracted by the extracting unit is reproduced by the reproducing unit.

  Here, the extraction area is set to the reference position by the position setting unit every time the reading unit executes the reading process. The extraction area is also moved in the direction opposite to the moving direction of the imaging surface by the moving means each time the extracting means executes the extraction process.

  By setting the readout cycle of the object scene image generated on the imaging surface to N times the exposure cycle, power consumption can be reduced. In addition, each time the readout process is executed, the extraction area is set as a reference position, and each time the extraction process is executed, the extracted area is moved in the direction opposite to the movement direction of the imaging surface to be reproduced. Has a smooth motion regardless of the lengthening of the readout cycle.

  The electronic camera according to the invention of claim 2 is dependent on claim 1, and the first information setting means (S17) for setting the state information to a specific value every time the reading means executes the reading process, and the state information is a specific value. Further includes determination means (S79) for determining whether or not the extraction means performs the extraction process, and the position setting means executes the setting process when the determination result of the determination means is affirmative.

  The electronic camera according to the invention of claim 3 is dependent on claim 2 and further comprises setting means (S85) for setting the state information to a numerical value different from the specific value every time the position setting means executes the setting process, and the moving means When the discrimination result of the discrimination means is negative, the movement process is executed.

  Thereby, the quality of the moving image can be improved regardless of the execution timing of each of the reading process and the extracting process.

  An electronic camera according to a fourth aspect of the invention is dependent on any one of the first to third aspects, and the extracting means executes an extraction process every third period shorter than the second period. In such a case, it is necessary to extract a partial object scene image twice or more from the same object scene image. The extraction area is set to a reference position in relation to the first extraction process, and is set to a position different from the reference position in relation to the second extraction process.

  The electronic camera according to the invention of claim 5 is dependent on claim 4, and the third period is different from the first period.

  An electronic camera according to a sixth aspect of the present invention is dependent on any one of the first to fifth aspects, wherein the extracting means includes a memory writing means (20, 24) for writing the object scene image into the memory (26), and a partial image. It includes memory reading means (24, 28) for reading the field image from the memory, the position setting means sets the extraction area to the reference position on the memory, and the moving means moves the extraction area on the memory. By providing the memory, it is possible to avoid the failure of the processing due to the difference between the execution cycle of the reading process and the execution cycle of the extraction process.

  According to the present invention, the power consumption can be reduced by setting the readout cycle of the object scene image generated on the imaging surface to N times the exposure cycle. In addition, each time the readout process is executed, the extraction area is set as a reference position, and each time the extraction process is executed, the extracted area is moved in the direction opposite to the movement direction of the imaging surface to be reproduced. Has a smooth motion regardless of the lengthening of the readout cycle.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

  Referring to FIG. 1, a digital camera 10 of this embodiment includes an optical lens 12. The optical image of the object scene is irradiated on the imaging surface of the image sensor 14 through the optical lens 12. The image sensor 14 is an interline transfer type CCD imager, and is formed by a plurality of light receiving elements 14p, 14p,..., A plurality of vertical transfer registers 14v, 14v,. Is done. The imaging surface is covered with a primary color filter 14f, and the charge generated by each light receiving element 14p has color information of any one of R (Red), G (Green), and B (Blue).

  When the camera mode is selected by operating the key input device 40, through image processing, that is, processing for displaying a real-time moving image of the object scene on the LCD monitor 30 is executed. First, a TG / SG 18 (Timing Generator / Signal Generator) generates a vertical synchronization signal Vsync1 and a horizontal synchronization signal Hsync1 with a period in consideration of the NTSC system. As shown in FIG. 7A, the vertical synchronization signal Vsync1 is generated at a rate of once every 1 / 59.94 seconds (= 1 field period). The TG / SG 18 also performs pre-exposure on the imaging surface every time the vertical synchronization signal Vsync1 is generated. As a result, a charge representing the object scene, that is, a raw image signal is generated on the imaging surface.

  The CPU 32 repeatedly changes the setting of the TG / SG 18 so that the charge generated by the pre-exposure is read out at a rate of once every two fields. The TG / SG 18 executes the charge thinning-out reading in response to the vertical synchronization signal Vsync1 generated at a certain timing, and interrupts the thinning-out reading in response to the next generated vertical synchronization signal Vsync1. Pre-exposure and thinning-out reading are executed as shown in FIG. Thus, the low-resolution raw image signal output from the image sensor 14 over two field periods corresponds to one frame image, thereby ensuring a frame rate of 29.97 fps.

  The raw image signal of each frame output from the image sensor 14 is subjected to a series of processes of noise removal, level adjustment and A / D conversion by the CDS / AGC / AD circuit 16, and thereby raw image data which is a digital signal. Is obtained. The CDS / AGC / AD circuit 16 executes these processes in response to the timing signal from the TG / SG 18.

  The signal processing circuit 20 performs processing such as white balance adjustment, color separation, and YUV conversion on the raw image data of each frame output from the CDS / AGC / AD circuit 16 to generate image data in YUV format. The generated image data is written into the SDRAM 26 by the memory control circuit 24.

  The CPU 32 supplies the memory control circuit 24 with a gate pulse (see FIG. 7B) that becomes H level in a field where thinning-out reading is executed and becomes L level in a field where thinning-out reading is interrupted. The memory control circuit 24 performs data writing when the gate pulse indicates the H level, and interrupts the data writing when the gate pulse indicates the L level. As a result, image data representing the object scene is taken into the SDRAM 26.

  As shown in FIG. 5, the SDRAM 26 includes a bank 26a (bank A), a bank 26b (bank B), and a work area 26c. The CPU 32 changes the write bank between the banks A and B in response to the rising edge of the gate pulse. The write bank is designated as shown in FIG. The image data of each frame output from the signal processing circuit 20 is written into the write bank thus designated.

  The motion detection circuit 22 detects a motion vector indicating the motion of the imaging surface due to pan / tilt or camera shake based on the image data representing the object scene output from the signal processing circuit 20. The CPU 32 fetches a motion vector from the motion detection circuit 22 in response to the rising edge of the gate pulse, and based on the motion vector fetched a correction vector (movement vector) to be referred to when an extraction area SP (see FIG. 6) described later is moved. To calculate.

  The direction of the correction vector is opposite to the direction of the detected motion vector, and the length of the correction vector is 3/5 of the length of the detected motion vector. The calculated correction vector is set in the register 32r.

  SG34 generates the vertical synchronization signal Vsync2 at a rate of once every 1/50 seconds in order to correspond to the PAL system. The vertical synchronization signal Vsync2 is periodically generated in the manner shown in FIG. The CPU 32 changes the read bank between the banks A and B in response to the first vertical synchronization signal Vsync2 after the gate pulse rises. The read bank is changed as shown in FIG. 7E to follow the write bank.

  The CPU 32 also assigns the extraction area SP to each reference position (center) of the banks A and B in response to the first vertical synchronization signal Vsync2 after the gate pulse rises. The CPU 32 further moves the extraction area SP according to the correction vector set in the register 32r in response to the second and subsequent vertical synchronization signals Vsync2 after the gate pulse rises. Therefore, the position of the extraction area SP changes as shown in FIG.

  The video encoder 28 accesses the SDRAM 26 through the memory control circuit 24 every time the vertical synchronization signal Vsync2 is generated, and reads out the partial image data belonging to the extraction area SP on the reading bank in an interlaced scanning manner. The field identification information of the read partial image data changes as shown in FIG.

  The video encoder 28 performs an enlargement zoom process on the read partial image data, and converts the enlarged partial image data into a composite video signal according to the PAL system. The converted composite video signal is given to the LCD monitor 30. As a result, a through image of the partial scene belonging to the extraction area SUB is displayed on the monitor screen.

  The numerical value “3/5” that defines the length of the correction vector is the ratio between the imaging cycle of the object scene (= 1 / 29.97 seconds) and the display image update cycle (= 1/50 seconds). Indicates.

  The access operation to the bank A is executed as shown in FIG. 7 (H), and the access operation to the bank B is executed as shown in FIG. 7 (I). Since the imaging cycle of the object scene is different from an integral multiple of the display image update cycle, frame dropping occurs at a rate of one field per several fields. However, since the read operation is performed in units of fields, not in units of frames, the motion of the reproduced moving image does not become unnatural due to dropped frames.

  When the imaging surface of the image sensor 14 that captures the stationary object X moves in the lower left direction, the image data of two consecutive frames written in the banks A and B change as shown in FIG. At this time, the extraction area SP allocated to each of the banks A and B is displaced as shown in FIG. That is, the extraction area SP moves in a direction that cancels out the movement of the imaging surface 14f in response to reading of the second field from the same frame. As a result, the stationary object X displayed on the LCD monitor 30 moves smoothly in the upper right direction as shown in FIG.

  When a recording operation is performed by the key input device 40, the CPU 32 interrupts the charge reading operation in response to the vertical synchronization signal Vsync1 that is generated first, and in response to the vertical synchronization signal Vsync1 that is generated the second time. The setting of TG / SG 18 is changed so that all pixel readout is executed. The TG / SG 18 performs main exposure on the imaging surface in response to the first vertical synchronization signal Vsync1, and reads out all the charges generated thereby in response to the next generated vertical synchronization signal Vsync1.

  A high-resolution raw image signal is read from the image sensor 14. The read raw image signal is converted to raw image data by the CDS / AGC / AD circuit 16 and converted to YUV format image data by the signal processing circuit 20.

  When a recording operation is performed, the CPU 32 designates the work area 26c (see FIG. 5) of the SDRAM 26 as a writing destination of image data and issues a compression command to the JPEG encoder 42 in order to execute a recording process.

  The high-resolution image data output from the signal processing circuit 20 is written into the work area 26 c of the SDRAM 26 by the memory control circuit 24. The JPEG codec 42 reads image data from the work area 26c through the memory control circuit 24, and compresses the read image data by the JPEG method. The JPEG data obtained in this way is written into the work area 26c through the memory control circuit 24.

  The JPEG data stored in the work area 26c is then recorded on the recording medium 38 through the I / F 36. The recording medium 38 is a detachable medium, and can be accessed through the I / F circuit 36 when it is loaded in a slot (not shown).

  The TG / SG 18 is configured as shown in FIG. 3 in connection with driving of the image sensor 14. The H counter 18a is incremented in response to a pixel clock from an oscillator (not shown). The count value of the H counter 18a is given to the comparator 18b and compared with a reference value corresponding to the number of horizontal pixels. The comparator 18b sets the output level to “L” when the given count value is different from the reference value, and sets the output level to “H” when the given count value matches the reference value. The H counter 18a is reset in response to the rise of the output of the comparator 18b.

  Therefore, the count value of the H counter 18b indicates the horizontal address of the pixel of interest at the present time. The pulse output from the comparator 18b corresponds to the horizontal synchronization signal Hsync1.

  The V counter 18c is incremented in response to the rise of the output of the comparator 18b. The count value of the V counter 18c is given to the comparator 18d and compared with a reference value corresponding to the number of vertical pixels. The comparator 18d sets the output level to “L” when the given count value is different from the reference value, and sets the output level to “H” when the given count value matches the reference value. The V counter 18c is reset in response to the rise of the output of the comparator 18d.

  Therefore, the count value of the V counter 18c indicates the vertical address of the pixel of interest at the present time. The pulse output from the comparator 18d corresponds to the vertical synchronization signal Vsync1.

  The decoder 18e repeatedly outputs a charge sweep pulse based on the count values of the H counter 18a and the V counter 18c, and interrupts the output of the charge sweep pulse for a specified period in each field. The charges generated by the light receiving element 14p are swept away by the drain when a charge sweeping pulse is output. When the output of the charge sweeping pulse is interrupted, the charge is accumulated in the light receiving element 14p.

  The decoder 18f repeatedly outputs vertical transfer pulses based on the count values of the H counter 18a and the V counter 18c. The vertical transfer pulse intermittently includes a read pulse component. The charge is read from the light receiving element 14p to the vertical transfer register 14v when a read pulse component appears. The read charge is transferred in the vertical direction by a transfer pulse component forming a vertical transfer pulse.

  The decoder 18g repeatedly outputs horizontal transfer pulses based on the count values of the H counter 18a and the V counter 18c. The charges that have reached the horizontal transfer register 14h by the vertical transfer are transferred in the horizontal direction by the horizontal transfer pulse.

  When the through image processing is executed, “decimation readout” is set in the decoder 18f. The decoder 18h applies the read pulse component only to some of the light receiving elements 14p, 14p,. Each of decoders 18f and 18g is switched between an on state and an off state for each field. The output operations of the vertical transfer pulse and the horizontal transfer pulse are executed in the on state, and are interrupted in the off state. As a result, thinning-out reading is realized once every two fields, and power saving is achieved.

  When the recording operation is performed, “read all pixels” is set in the decoder 18f. The decoder 18f applies the read pulse component to all the light receiving elements 14p, 14p,. Each of the decoders 18f and 18g is turned off in the field where the main exposure is performed, and is turned on in the field next to the field where the main exposure is performed. As a result, accurate all-pixel readout is realized while suppressing wasteful power consumption caused by unnecessary output of the transfer pulse.

  In connection with the through image display, the CPU 32 performs the main task shown in FIG. 9, the sensor read control task shown in FIG. 10, the memory write control task shown in FIG. 11, the motion detection task shown in FIG. The memory read control task is executed in parallel. Note that control programs corresponding to these tasks are stored in the flash memory 44.

  Referring to FIG. 9, in step S1, a sensor read control task, a memory write control task, a motion detection task, and a memory read control task are activated. As a result, through image processing is executed, and a through image is output from the LCD monitor 30. When the recording operation is performed, YES is determined in step S3, and the sensor read control task, the memory write control task, the motion detection task, and the memory read control task are stopped in step S5. As a result, the output of the through image is interrupted.

  In step S7, it is determined whether or not the vertical synchronization signal Vsync1 has been generated. If YES, the decoders 18f and 18g are turned off in step S9. By the processing in step S9, the output of the vertical transfer pulse and the horizontal transfer pulse is interrupted. In step S11, it is determined whether or not the vertical synchronization signal Vsync1 has been generated again.

  If YES here, "read all pixels" is set in the decoder 18f in step S13, and the decoders 18f and 18g are turned on in step S15. As a result, a high-resolution raw image signal formed by all the charges generated by the main exposure is output from the image sensor 14. In step S17, the raw image signal output in this way is subjected to recording processing, and then the process returns to step S1.

  Referring to FIG. 10, in step S21, flag Fch is set to “0”, and in step S23, “decimation readout” is set to decoder 18f. When the vertical synchronization signal Vsync1 is generated, YES is determined in step S25, and the state of the flag Fch is determined in step S27.

  If the flag Fch is “0”, “YES” is determined in the step S27, and each of the decoders 18f and 18g is turned off in a step S29. In step S31, the gate pulse is set to L level, and in step S33, the flag Fch is set to "1". When the process of step S33 is completed, the process returns to step S25.

  If the flag Fch is “1”, NO is determined in step S27, and each of the decoders 18f and 18g is turned on in step S35. In step S37, the gate pulse is set to H level, and in step S39, the flag Fch is set to "0". When the process of step S33 is completed, the process returns to step S25.

  As a result, the thinning-out reading process is performed once every two fields, and the gate pulse applied to the memory control circuit 24 is switched between the H level and the L level for each field. The field where the gate pulse indicates the H level matches the field where the thinning readout process is executed.

  Referring to FIG. 11, in step S41, flag Frd is set to “0”, and in step S43, it is determined whether or not the gate pulse has risen. If “YES” here, the bank A is designated as a writing bank of the current frame in a step S45. In step S47, it is determined again whether or not the gate pulse has risen. If YES, bank B is designated as the write bank of the current frame in step S49.

  Image data representing the object scene is output from the signal processing circuit 20 when the gate pulse indicates the H level. Therefore, the image data of the first frame representing the scene is written to the bank A by the process of step S45, and the image data of the second frame representing the scene is written to the bank B by the process of step S49.

  When the process of step S49 is completed, the flag Frd is set to “1” and the flag Fmv is set to “0” in step S51. The flag Frd is a flag for permitting / prohibiting the reading of image data from the bank A or B. “0” means “prohibited”, while “1” means “permitted”. The flag Fmv is a flag for permitting / prohibiting the movement of the extraction area SP assigned to each of the banks A and B. “0” means “prohibited”, while “1” means “permitted”. To do.

  When YES is determined in the step S47, the writing of the image data of the first frame to the bank A is completed. In step S51, a flag Frd is set to “1” to permit reading of the image data of the first frame. In step S51, the flag Fmv is set to “0” to prohibit the movement of the extraction area SP, that is, to set the extraction area SP to the reference position.

  In step S53, it is determined whether or not the gate pulse has risen. If YES, the write bank is changed in step S55. If bank A is a previous bank write bank, bank B is designated as the current frame write bank. If bank B is the write bank of the previous frame, bank A is designated as the write bank of the current frame. When the process of step S55 is completed, the flag Fmv is set to “0” in step S57 to set the extraction area SP to the reference position, and then the process returns to step S53. The image data of the third and subsequent frames representing the object scene are alternately written into the bank A or B by the process of step S55.

  Referring to FIG. 12, in step S61, register 32r is cleared, and in step S63, it is determined whether or not a gate pulse has risen. If YES is determined in the step S63, a motion vector is fetched from the motion detection circuit 22 in a step S65. In step S67, the correction vector of the extraction area SP is calculated based on the captured motion vector, and in step S69, the calculated correction vector is set in the register 32r. When the process of step S69 is completed, the process returns to step S63. The correction vector calculated in step S67 has a direction opposite to the direction of the motion vector captured in step S65, and the length of “3/5” of the length of the motion vector captured in step S65. Have.

  Referring to FIG. 13, in step S71, bank B is designated as a read bank, and in step S73, it is determined whether or not flag Frd indicates “1”. When the flag Frd is changed to “1” by the process of step S51 shown in FIG. 11, it is considered that reading of the image data is permitted, and the video encoder 28 is activated in step S75. In step S77, it is determined whether or not the vertical synchronization signal Vsync2 has been generated. If YES, the state of the flag Fmv is determined in step S79.

  If the flag Fmv indicates “0”, the read bank is changed in step S81. If bank A is a read bank for the previous frame, bank B is designated as the read bank for the current frame. If bank B is a read bank for the previous frame, bank A is designated as the read bank for the current frame. Since bank B is designated as a read bank in step S71, bank A is designated as the read bank for the current frame in the first processing of step S81.

  In step S83, the extraction area SP is set as a reference position. The video encoder 28 reads partial image data corresponding to one field belonging to the extraction area SP on the reading bank in an interlaced scanning manner. As a result, a corresponding partial scene image is output from the LCD monitor 30.

  When the process of step S83 is completed, the flag Fmv is set to “1” in step S85, and then the process returns to step S77. By setting the flag Fmv to “1”, the movement of the extraction area SP after the next field is permitted.

  If NO is determined in step S79, the process proceeds to step S87, and the correction vector set in the register 32r is read. In step S89, the extraction area SP assigned to each of the banks A and B is moved according to the read correction vector. The extraction area SP moves in the direction opposite to the movement direction of the imaging surface. As a result, the moving image output from the LCD monitor 30 moves smoothly. When the process of step S89 is completed, the process returns to step S77.

  As can be seen from the above description, the object scene image is repeatedly output from the image sensor 14 by thinning-out reading processing once every two fields, and is alternately written in the banks A and B formed in the SDRAM 26. The video encoder 28 extracts a partial scene image of one field belonging to the extraction area SP from the bank A or B, and the LCD monitor 30 reproduces a moving image based on the extracted partial scene image. The flag Fmv is set to a specific value, that is, “0” by the CPU 32 every time the thinning readout process is executed (S57). Whether or not the flag Fmv indicates “0” is determined by the CPU 32 every time the video encoder 28 executes extraction processing corresponding to one field (S79).

  If the determination result is affirmative, the extraction area SP is set to the reference position by the CPU 32 (S83). The CPU 32 also sets the flag Fmv to “1” every time the extraction area SP is set to the reference position (S85). If the determination result is negative, the extraction area SP is moved in the direction opposite to the movement direction of the imaging surface by the CPU 32 (S89).

  As described above, the thinning-out reading process is executed once every two fields, so that power consumption can be reduced.

  The extraction area SP is set as a reference position when the first extraction process is executed after the focused thinning readout process, and the movement of the imaging surface when the second and subsequent extraction processes are executed after the focused thinning readout process. It is set at the position moved in the opposite direction. That is, the extraction area SP moves in the direction opposite to the movement direction of the imaging surface with the reference position as a starting point when paying attention to the same object scene image. Thereby, it is possible to suppress deterioration in the quality of the reproduced moving image due to the movement of the imaging surface.

  Further, the flag Fmv is set to “0” every time the thinning readout process is executed, and is set to “1” every time the extraction area SP is set to the reference position. The value indicated by the flag Fmv is determined every time the extraction process is executed. As a result, the above-described quality deterioration can be suppressed regardless of the execution timing of the thinning-out reading process and the extraction process.

  In this embodiment, a single horizontal transfer register provided at one end in the vertical direction of the imaging surface is used to output charges from one path. However, a plurality of horizontal transfer registers are provided and a plurality of horizontal transfer registers are provided. Charges may be output from the path. In this embodiment, a video encoder that conforms to the PAL system is used, but a video encoder that conforms to the NTSC system may be used instead.

  Further, in this embodiment, the thinning-out reading process is executed once every two fields, but the thinning-out reading process may be executed once every three or more fields. .

It is a block diagram which shows the structure of one Example of this invention. It is an illustration figure which shows an example of a structure of the image sensor applied to FIG. 1 Example. It is a block diagram which shows an example of a structure of TG / SG for NTSC applied to the FIG. 1 Example. It is an illustration figure which shows an example of operation | movement of the image sensor shown in FIG. It is an illustration figure which shows an example of the mapping state of SDRAM applied to FIG. 1 Example. FIG. 5 is an illustrative view showing one example of an extraction area allocation state in each of banks A and B forming the embodiment in FIG. 2; (A) is an illustrative view showing an example of an output timing of a vertical synchronization signal Vsync1 used in the imaging system, (B) is an illustrative view showing an example of a change in a gate pulse for controlling data writing, and (C). FIG. 7 is an illustrative view showing an example of an output timing of a vertical synchronization signal Vsync2 used in the display system, (D) is an illustrative view showing an example of a change in a write bank, and (E) is an example of a change in a read bank. (F) is an illustrative view showing an example of a change in the position of an extraction area, (G) is an illustrative view showing an example of a change in a reproduction field, and (H) is an access to bank A. It is an illustrative view showing an example of the operation, and (I) is an illustrative view showing an example of an access operation to the bank B. (A) is an illustrative view showing a part of an operation for writing image data to SDRAM, (B) is an illustrative view showing a part of an operation for reading image data stored in SDRAM, and (C). FIG. 9 is an illustrative view showing one portion of a display operation of image data read from the SDRAM; It is a flowchart which shows a part of operation | movement of CPU applied to the FIG. 1 Example. It is a flowchart which shows a part of other operation | movement of CPU applied to the FIG. 1 Example. It is a flowchart which shows a part of other operation | movement of CPU applied to the FIG. 1 Example. FIG. 12 is a flowchart showing yet another portion of behavior of the CPU applied to the embodiment in FIG. 1. It is a flowchart which shows a part of other operation | movement of CPU applied to the FIG. 1 Example.

Explanation of symbols

10 ... Digital video camera
DESCRIPTION OF SYMBOLS 14 ... Image sensor 20 ... Signal processing circuit 22 ... Motion detection circuit 26 ... SDRAM
28 ... Video encoder 42 ... JPEG encoder 44 ... Flash memory

Claims (6)

An imaging means having an imaging surface for capturing an object scene;
Exposure means for exposing the imaging surface at a rate of once in a first period;
The object scene image generated on the imaging surface by the exposure process of the exposure unit is read out from the imaging unit at a rate of one screen in a second period that is N times the first period (N: an integer of 2 or more). Reading means,
Extraction means for extracting a partial object scene image belonging to the extraction area from the object scene image read by the reading means;
Reproduction means for reproducing a moving image based on the partial scene image extracted by the extraction means;
A position setting unit that sets the extraction area to a reference position that is a predetermined position on a memory in which the object scene image is stored each time the reading unit executes a reading process; and An electronic camera comprising a moving means for moving the extraction area in a direction that cancels out the movement of the imaging surface each time. A first information setting unit that sets state information to a specific value each time the reading unit executes a reading process; and each time the extracting unit executes an extraction process whether or not the state information indicates the specific value And further comprising a discriminating means for discriminating,
The electronic camera according to claim 1, wherein the position setting unit executes a setting process when a determination result of the determination unit is affirmative. A setting means for setting the state information to a numerical value different from the specific value every time the position setting means executes a setting process;
The electronic camera according to claim 2, wherein the moving unit executes a moving process when a determination result of the determining unit is negative.   The electronic camera according to any one of claims 1 to 3, wherein the extraction unit executes an extraction process every third period shorter than the second period.   The electronic camera according to claim 4, wherein the third period is different from the first period. The extraction means includes memory reading means for reading the memory writing means writes the object scene image in the memory, and the partial object scene image from said memory,
The position setting means sets the extraction area to a reference position on the memory,
The electronic camera according to claim 1, wherein the moving unit moves the extraction area on the memory.

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