JP4679814B2 - PLL circuit - Google Patents

Description

  The present invention relates to a PLL circuit in which a plurality of multiplication settings are possible, and a built-in VCO configuration can be switched according to the number of multiplications or required output characteristics.

The PLL circuit is now widely used not only in the communication field but also in all technical fields. Corresponding to the recent increase in speed of various systems, it can be said that the required specifications for the PLL circuit are also increasing in speed and bandwidth.
In general, the PLL circuit in this frequency domain is integrated, but it is technically difficult to obtain optimized characteristics in all frequency bands.

  FIG. 7 is a block diagram showing a configuration of a conventional PLL circuit. In FIG. 7, the PLL circuit 1 is compared with a frequency dividing circuit 2 that performs PLL multiplication setting, and a phase comparator 3 that compares the phases of the reference input signal and the feedback signal divided by the frequency dividing circuit 2. A charge pump 4 that outputs a pulse signal corresponding to the phase difference, a low-pass filter 5 that outputs a voltage Vcnt after removing ripples from the pulse signal, and a voltage control that outputs an output signal having a frequency corresponding to the input voltage Vcnt It comprises an oscillator (hereinafter referred to as VCO) 6.

  In the conventional circuit configuration as shown in FIG. 7, if the power supply voltage of the PLL is lowered in order to reduce the current consumption, it is easily affected by external noise. In a PLL that requires multiple multiplication settings with a single PLL, increasing the multiplication setting increases the output phase correction interval, which increases jitter, especially long-term jitter. However, lowering the power supply voltage affects noise. Long term jitter increases.

  In order to reduce jitter, it is conceivable to increase the external power noise by increasing the power supply voltage of the PLL. In this case, in the conventional configuration, even when the frequency is low, the jitter does not deteriorate as much as the high frequency. Current consumption increases.

  In the technology of Patent Document 1, the upper and lower limit voltages set by the window comparator are compared with the charge pump output voltage, and when the output voltage is outside the comparator setting range, the bias current supplied to the ring oscillator is switched and operates within the setting range. Thus, since the VCO frequency is forcibly controlled and changed, it is not necessary to increase the VCO gain more than necessary, and the operation of the PLL circuit can be further stabilized.

However, when the power supply voltage decreases, the VCO control voltage range also decreases, and the VCO gain increases. Further, when the power supply voltage is lowered, the ring oscillator in the VCO is easily affected by external noise, and the long term jitter at high multiplication increases.
JP 2000-004156 A

  The present invention has been made in consideration of the above-described circumstances, and includes a VCO configured with different power supply voltages in a PLL circuit, and switching for selectively automatically switching the VCO according to the multiplication number. It is an object of the present invention to provide a PLL circuit which can be provided with a circuit and can have a circuit configuration suitable for required specifications of current consumption and jitter of the PLL.

In order to solve the above problems, the invention of claim 1 compares the phase of an input signal and an output signal and outputs a voltage corresponding to the phase difference, and the voltage output from the phase comparator. a voltage controlled oscillator for generating and outputting a signal having a frequency corresponding to (hereinafter, VCO) in the PLL circuit having a power consumption two different VCO and the desired one of the two VCO according to the multiplication factor A switching circuit for switching to a VCO, wherein the output signal is a frequency-divided signal output from the VCO, and the switching circuit sets the multiplication number in a register for setting the multiplication number of the programmable counter. the bit data is controlled in accordance with the data in the same number of upper bits of the two VCO at other bit data, the two other V other than the selected VCO that of VCO O to and controlling the sleep mode.

According to a second aspect of the present invention, in the PLL circuit according to the first aspect, the switching circuit has a dynamic range of the VCO circuit that is one of the conditions under which the jitter of the PLL deteriorates. Switching to a VCO with high power consumption in order to increase it and make it more resistant to external noise, and switching to a VCO with low power consumption so as to reduce current consumption when the multiplication factor is set small .

According to a third aspect of the present invention, in the PLL circuit according to the first or second aspect, the switching circuit includes a signal for switching to a VCO that consumes a large amount of power when a highly accurate jitter characteristic is required for the PLL circuit, and a PLL circuit. When a very high jitter characteristic is not required, a signal for switching to a VCO with low power consumption is input from the outside, and a plurality of VCOs are switched by any one of these switching signals.

According to a fourth aspect of the present invention, in the PLL circuit according to any one of the first to third aspects, one switching is selected from among a switching signal output from the programmable counter and a switching signal input from the outside. Selection means for selecting a signal is provided, wherein the switching circuit switches a plurality of VCOs according to a switching signal selected by the selection means.

  According to the present invention, since the VCO configured with different power supply voltages can be selectively switched according to the multiplication number, the VCO is configured with the optimal power supply voltage according to the characteristics required of the PLL. be able to.

In addition, when the multiplication factor is large, switching to a VCO configured with a high power supply voltage is performed, and when the multiplication factor is small, switching to a VCO configured with a low power supply voltage is adopted. When a certain multiplication number is set large, the dynamic range of the VCO circuit can be expanded to increase resistance to external noise and reduce jitter.
Further, when the multiplication number is set small, the jitter is smaller than when the multiplication number is large, so that the current consumption can be reduced by lowering the power supply voltage of the VCO.

  In addition, the switching by the multiplication number is controlled by register data, so that the switching multiplication number can be optimally set according to the specification.

Further, when a switching signal for selecting a plurality of VCO circuits is given from the outside of the PLL circuit, and when the PLL circuit requires a highly accurate jitter characteristic, the VCO circuit is switched to a VCO configured with a high power supply voltage. By expanding the dynamic range, it is possible to withstand external noise and reduce jitter.
Further, when the jitter circuit is not required to have a very high jitter characteristic, the current consumption of the PLL circuit can be reduced by switching to a VCO configured with a low power supply voltage.

Hereinafter, preferred embodiments of the PLL circuit of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a PLL circuit of the present invention. In FIG. 1, a PLL circuit 11 performs PLL multiplication setting, and also outputs a switching control signal to the VCO 16, VCO 17, and selector 18 according to data for setting the multiplication number, and a reference input signal and the programmable counter 12. A phase comparator 13 that compares each phase with the feedback signal that has been rotated, a charge pump 14 that outputs a pulse signal corresponding to the phase difference compared by the phase comparator 13, a ripple after removing the ripple of this pulse signal, Low-pass filter 15 that outputs to VCO 16 and VCO 17 as Vcnt, VCO 16 and VCO 17 that outputs an output signal having a frequency corresponding to voltage Vcnt, and a VCO output that is in an operating state is selected by a switching control signal output from programmable counter 12; Programmable It receives an input to counter 12, a selector 18 for output as an output signal of the PLL circuit 11.
Here, the VCO 16 and the VCO 17 are configured with different power supply voltages (VCC), and both the VCOs have a sleep function, and one of the VCOs is operated by a switching control signal output from the programmable counter 12. When in the state, the other VCO is controlled to go to sleep.

Hereinafter, the VCO 16 will be described as a VCO configured with a high power supply voltage, and the VCO 17 will be described as a VCO configured with a low power supply voltage.
The charge pump 14 and the low-pass filter 15 are configured with high VCC, and a control voltage is input to the VCO 16 and VCO 17.

For example, if the programmable counter 12 can be set up to 16 times by a 4-bit register, the switching control signal is L (Low) until 4 times when the upper 2 bits are 0, and the switching control signal is H at times of 4 times or more. (High).
In response to the switching control signal from the programmable counter 12, the VCO 17 configured with low VCC operates at the time of low multiplication up to four times, and this output is selected by the selector 18 to become an output signal. During this time, the VCO 16 configured with high VCC is in the sleep state.
In response to the switching control signal from the programmable counter 12, when the frequency is multiplied by 4 or more, the VCO 16 configured with high VCC operates, and this output is selected by the selector 18 to become an output signal. During this time, the VCO 17 configured with low VCC is in the sleep state.

FIG. 2 is a circuit diagram showing the programmable counter 12.
The programmable counter 12 includes a register 22 that sets a PLL multiplication number, a counter 23 that compares the output of the counter 21 and the register 22, and a VCO output signal output from the selector 18 is divided by a register. The number is divided so as to be a number and output to the phase comparator 13, and a control signal is output to the VCO 16, VCO 17, and selector 18 in accordance with the upper 2 bits of data in the register 22.

FIG. 3 is a circuit diagram showing the VCO 16 configured with high VCC. In the figure, a VCO 16 includes a VI converter 34 that generates a current obtained by adding a constant current 32 and a current 33 corresponding to a control voltage Vcnt, and a current amplifier 35 that amplifies the generated current and supplies the amplified current to a ring oscillator 36. The ring oscillator 36 outputs a frequency corresponding to the supplied current, and the comparator 37 outputs the differential signal oscillated by the ring oscillator 36, converts the differential signal into a single signal, and outputs the signal.
Each part is composed of a high VCC transistor. When the control voltage increases, the current supplied to the ring oscillator 36 increases and the oscillation frequency increases. When the control voltage decreases, the oscillation frequency decreases.

Further, the switching control signal from the programmable counter 12 is input to the V-I converter 34 and the ring oscillator 36 as a sleep signal of the VCO 16, and during sleep, the current of the V-I converter 34 is cut and the ring oscillator 36 receives the current. Cut the supplied current.
Then, the output of the ring oscillator 36 (the output of the differential amplifier at the right end of the differential amplifiers arranged in three stages) is fixed at the low-phase output terminal O− to “Low”, and the in-phase output terminal O + is set to “High”. And the output of the comparator 37 is set to “Low”.
Alternatively, the output state of the differential amplifier and the comparator at the time of sleep may be set such that the negative phase output terminal O− is fixed to “High”, the common phase output terminal O + is fixed to “Low”, and the output of the comparator 37 is set to “High”. Good.

FIG. 4 is a circuit diagram showing the VCO 17 configured with low VCC. In the figure, a VCO 17 generates a current obtained by adding a constant current 42 and a current 43 corresponding to the control voltage Vcnt by a VI converter 44, amplifies the generated current by a current amplifying unit 45, and outputs this current to an NMOS 46. Wrap it around. The V-I converter 44, the current amplifying unit 45, and the NMOS 46 are composed of high VCC transistors.
Then, the current folded by the NMOS 46 is subjected to current amplification by a current amplifying unit 47 composed of a low VCC transistor, and the power supply voltage of the subsequent circuits is converted to low VCC. The current generated here is supplied to the ring oscillator 48 of low VCC. The differential signal oscillated by the ring oscillator 48 is input, and the differential signal is converted into a single by the comparator 49 and output.

Further, the switching control signal from the programmable counter 12 is input to the V-I converter 44 and the ring oscillator 48 as a sleep signal of the VCO 17, and during sleep, the current of the V-I converter 44 is cut and the ring oscillator 48 receives the current. Cut the supplied current.
Then, the output of the ring oscillator 48 (the output of the rightmost differential amplifier of the three stages of differential amplifiers) is fixed to the low-phase output terminal O− at “Low”, and the common-phase output terminal O + is set to “High”. And the output of the comparator 49 is set to “Low”.
Alternatively, the output state of the differential amplifier and the comparator at the time of sleep can be set such that the negative phase output terminal O− is fixed to “High”, the common phase output terminal O + is fixed to “Low”, and the output of the comparator 49 is set to “High”. Good.

FIG. 5A is a circuit diagram of a differential amplifier inverter, and FIG. 5B is a symbol diagram of the circuit of FIG.
The differential amplifier type inverter 51 is controlled by load PMOS transistors QP11 and QP12 controlled by a control signal Pcnt, a constant current source NMOS transistor QN11 controlled by a control signal Ncnt, and an input signal line pair I + and I−. The differential pair NMOS transistors QN21 and QN22 are output from the common-phase output terminal O + and the negative-phase output terminal O- of the differential amplifier.

  Generally, when the power supply voltage of the PLL is lowered in order to reduce current consumption, the VCO unit is particularly susceptible to external noise. In a PLL that requires multiple multiplication settings with a single PLL, increasing the multiplication setting increases the output phase correction interval, which increases jitter, especially long-term jitter. However, lowering the power supply voltage affects noise. Long term jitter increases. In order to reduce jitter, it is conceivable that the power supply voltage of the PLL is increased to make it more resistant to external noise. However, in the conventional configuration, the current consumption increases even at low multiplications where jitter does not deteriorate as high multiplications occur. .

  In order to solve this problem, the PLL circuit is configured as shown in FIG. 1, so that at the time of low multiplication, switching to a VCO configured with low VCC so as to reduce current consumption, By switching to a VCC configured with VCC and expanding the dynamic range of the VCO circuit, it is possible to increase resistance to external noise and reduce jitter.

  Further, by adopting a configuration in which the power supply voltage of the circuit is converted after the VI conversion as shown in FIG. 4, it is not necessary to provide charge pump circuits having different power supply voltages for the VCO 16 and VCO 17 configured with different power supply voltages. The circuit scale can be reduced.

  If the charge pump and the VCO are all configured with a low VCC, the range of the control voltage Vcnt output from the charge pump is reduced. However, in this configuration, the charge pump is configured with a high VCC, so the control voltage Vcnt In this configuration, the VCO gain can be reduced with respect to a VCO that outputs the same oscillation frequency range, so that it is more resistant to noise and jitter can be reduced.

  Further, as shown in FIG. 6, a VCO selection signal for selecting a plurality of VCOs is given from outside the PLL circuit, and the control circuit 19 starts from the programmable counter 12 when the VCO selection signal from the outside is not used. Data to be input is output. When an external VCO selection signal is used, VCO selection data input from the outside is output.

By configuring the PLL circuit of the present invention in such a configuration, when a highly accurate jitter characteristic is required for the PLL circuit, the PLL circuit is switched to a VCO configured with a high VCC to be resistant to external noise and reduce jitter. Can do. However, when the jitter circuit is not required to have such a high jitter characteristic, the current consumption of the PLL circuit can be reduced by switching to a VCO configured with a low VCC.
In this way, a circuit configuration suitable for the required current consumption and jitter specifications of the PLL can be obtained.

It is a block diagram which shows the structure of the PLL circuit of this invention. It is a circuit diagram which shows a programmable counter. It is a circuit diagram which shows VCO comprised by high VCC. It is a circuit diagram which shows VCO comprised by low VCC. It is a circuit diagram of a differential amplifier type inverter. It is a block diagram which shows the other structure of the PLL circuit of this invention. It is a block diagram which shows the structure of the conventional PLL circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Conventional PLL circuit, 2 ... Frequency divider, 3, 13 ... Phase comparator, 4, 14 ... Charge pump, 5, 15 ... Low-pass filter, 6, 16, 17 ... Voltage controlled oscillator, 11 ... PLL circuit, 12 ... programmable counter, 18 ... selector, 21 ... counter, 22 ... register, 23 ... comparator, 32, 42 ... constant current source, 34, 44 ... V-I converter, 35, 45, 47 ... current Symbols of amplifying unit, 36, 48 ... ring oscillator, 37 ... comparator, 46 ... NMOS transistor, 51 ... differential amplifier inverter, 52 ... differential amplifier inverter.

Claims (4)

A phase comparator that compares phases of an input signal and an output signal and outputs a voltage corresponding to the phase difference, and a voltage controlled oscillator that generates and outputs a signal having a frequency corresponding to the voltage output from the phase comparator (Hereinafter referred to as VCO)
Two VCOs with different power consumption,
A switching circuit for switching to a desired VCO among the two VCOs according to the multiplication number;
The output signal is a signal output from the VCO and divided.
In the register for setting the multiplication number of the programmable counter, the switching circuit is bit data different from the bit data for setting the multiplication number, and is in accordance with data in the same number of upper bits as the number of the two VCOs. Controlled,
A PLL circuit that controls a VCO other than the selected VCO in the two VCOs to a sleep mode. The PLL circuit according to claim 1,
The switching circuit is one of the conditions under which the jitter of the PLL deteriorates. When the multiplication number is set large, the switching circuit increases the dynamic range of the VCO circuit to make it more resistant to external noise. A PLL circuit characterized by switching to a VCO with low power consumption so as to reduce current consumption when switching is set to a small number. The PLL circuit according to claim 1 or 2,
The switching circuit includes a signal for switching to a VCO with high power consumption when high precision jitter characteristics are required for the PLL circuit, and a signal for switching to a VCO with low power consumption when high jitter characteristics are not required for the PLL circuit. Is input from the outside, and a plurality of VCOs are switched by any one of these switching signals. The PLL circuit according to any one of claims 1 to 3,
A selection means for selecting one switching signal from among the switching signal output from the programmable counter and the switching signal input from the outside;
The switching circuit switches a plurality of VCOs according to a switching signal selected by the selection means.

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