JP4679428B2 - Test apparatus and test method - Google Patents

Description

  The present invention relates to a test apparatus and a test method. In particular, the present invention relates to a test apparatus and a test method for testing a plurality of devices under test in parallel.

Patent Document 1 describes a test apparatus that tests a plurality of devices under test in parallel and includes a universal buffer memory that stores individual patterns corresponding to each of the plurality of devices under test. ing. The test equipment basically supplies a common pattern to a plurality of devices under test, and supplies individual patterns stored in the universal buffer memory to each device under test instead of the common pattern at a specified timing. To do. Thus, according to the test apparatus, a plurality of devices under test to be supplied with different patterns can be tested in parallel, so that the test throughput can be improved.
JP 2005-276317 A

  Incidentally, the test apparatus described in Patent Document 1 includes a universal buffer memory for each device under test to be tested in parallel or for each of a plurality of terminals of each device under test. Since these universal buffer memories are operated with the reference clock of the test apparatus, the total power consumption of all the universal buffer memories has been increased.

  Accordingly, an object of the present invention is to provide a test apparatus and a test method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  In order to solve the above-described problems, in the first embodiment of the present invention, a test apparatus for testing a plurality of devices under test in parallel and generating a common pattern to be commonly supplied to the plurality of devices under test Common pattern generators, a plurality of individual pattern generators that are provided corresponding to each of the plurality of devices under test and generate individual patterns that are individually supplied to the corresponding devices under test, and a plurality of devices under test A plurality of pattern selectors, each of which is provided correspondingly, and selects which of the common pattern generated by the common pattern generator and the individual pattern generated by the corresponding individual pattern generator is supplied to the corresponding device under test; Each individual pattern generator has a different cycle for supplying a plurality of individual patterns to be supplied individually to the corresponding device under test. A universal buffer memory for storing two or more supplied individual patterns so as to correspond to different bit fields in data of the same address, and performing a write operation and a read operation in synchronization with a reference clock of the test apparatus; An address pointer section that holds the address where the next individual pattern in the universal buffer memory is stored, and a reference clock that is input to the universal buffer memory during a period when the address held in the address pointer section is not changed. When the mask and the address held in the address pointer part are changed and the individual pattern included in the data stored in the changed address is supplied to the corresponding device under test, the reference clock is supplied to the universal buffer memory. Enter and change the address When the mask part for reading the stored data and two or more individual patterns stored at the address specified by the address pointer part are sequentially supplied to the device under test, they are read from the universal buffer memory. There is provided a test apparatus including a data selection unit that sequentially selects individual patterns to be supplied to each cycle from data and supplies them to a corresponding pattern selection unit.

  Each universal buffer memory may have a clock input terminal for inputting a reference clock and at least one command input terminal for instructing a write operation or a read operation.

  When each individual pattern generator receives an instruction to sequentially write a plurality of individual patterns to be supplied individually to the corresponding device under test to the universal buffer memory, each individual pattern generator generates all the bit fields included in the data at the same address. It further has a write buffer unit that sequentially buffers received individual patterns until a plurality of individual patterns to be written are prepared, and the mask unit should write to all bit fields included in the data of the same address in the write buffer unit When the reference clock input to the universal buffer memory is masked until multiple individual patterns are collected, and data including two or more individual patterns buffered in the write buffer is written to the universal buffer memory Reference clock to universal buffer memory It may be input to Li.

  The mask unit is buffered in the write buffer unit by inputting a reference clock to the universal buffer memory in response to the tail individual pattern to be written in the universal buffer memory being buffered in the write buffer unit. Data may be written to the universal buffer memory. When the write buffer unit receives an instruction to sequentially write a plurality of individual patterns supplied individually to the corresponding device under test to the universal buffer memory, the data of the address to which the individual pattern is to be written is already another individual pattern. May be buffered sequentially after the other individual patterns are read out and buffered.

  In order to solve the above-described problem, in the second embodiment of the present invention, a test method for testing a plurality of devices under test in parallel, and generating a common pattern to be commonly supplied to the plurality of devices under test A common pattern generation stage, a plurality of individual pattern generation stages that are provided corresponding to each of the plurality of devices under test, and that generate individual patterns that are individually supplied to the corresponding devices under test, and a plurality of devices under test A plurality of pattern selection stages, each of which is provided correspondingly, and selects which of the common pattern generated in the common pattern generation stage and the individual pattern generated in the corresponding individual pattern generation stage is supplied to the corresponding device under test; Each of the individual pattern generation stages includes a write operation and a synchronization with a reference clock of the test apparatus. A plurality of individual patterns that are individually supplied to a corresponding device under test in a universal buffer memory that performs an output operation, and two or more individual patterns that are supplied in different cycles correspond to different bit fields in data of the same address During the storage phase, the address pointer phase holding the address where the next individual pattern in the universal buffer memory is stored, and the universal buffer buffer during the period when the address held by the address pointer phase is not changed. When the reference clock input to the memory is masked, the address held by the address pointer stage is changed, and the individual pattern included in the data stored in the changed address is supplied to the corresponding device under test. Clock universe The mask stage for reading data stored in the changed address input to the buffer memory and the two or more individual patterns stored in the address held in the address pointer stage are sequentially supplied to the device under test. In this case, there is provided a test method including a data selection step of sequentially selecting individual patterns to be supplied to each cycle from data read from the universal buffer memory and supplying them to the corresponding pattern selection step.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  According to the present invention, power consumption can be reduced.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  FIG. 1 shows a configuration of a test apparatus 10 according to this embodiment together with a device under test 100. The test apparatus 10 tests a plurality of devices under test 100 in parallel. The test apparatus 10 includes a common pattern generator 12. The test apparatus 10 includes a plurality of individual pattern generation units 14, a plurality of pattern selection units 16, a plurality of waveform shaping units 18, and a plurality of determination units provided corresponding to the plurality of devices under test 100. 20 is further provided.

  The common pattern generator 12 generates a common pattern that is supplied to a plurality of devices under test 100 in common. In addition to this, the common pattern generator 12 may generate a common pattern for pass / fail judgment common to the plurality of devices under test 100. Each of the individual pattern generators 14 generates an individual pattern to be individually supplied to the corresponding device under test 100. In addition, each of the individual pattern generation units 14 may generate an individual pattern for determining whether the corresponding device under test 100 is good or bad.

  Each of the pattern selection units 16 selects which of the common pattern generated by the common pattern generation unit 12 and the individual pattern generated by the corresponding individual pattern generation unit 14 is supplied to the corresponding device under test 100. In addition, each of the pattern selection units 16 selects which of the common pattern generated by the common pattern generation unit 12 and the individual pattern generated by the corresponding individual pattern generation unit 14 is supplied to the corresponding determination unit 20. May be.

  Each waveform shaping section 18 generates a test signal based on the pattern selected by the corresponding pattern selection section 16 and supplies it to the corresponding device under test 100. Each of the determination units 20 inputs an output signal output according to the test signal from the corresponding device under test 100. Each of the determination units 20 compares the pattern selected by the corresponding pattern selection unit 16 with the input output signal, and determines whether the corresponding device under test 100 is good or bad.

  According to such a test apparatus 10, the individual pattern generated by the individual pattern generation unit 14 is selected and tested at a designated timing, and the common pattern generation unit 12 performs a test at a timing other than the designated timing. The generated common pattern is selected and tested. As a result, according to the test apparatus 10, a plurality of devices under test 100 that must generate and test individually corresponding patterns can be tested in parallel.

  The common pattern generation unit 12 may generate a common pattern common to a plurality of terminals of the device under test 100. In this case, the plurality of individual pattern generation units 14, the plurality of pattern selection units 16, the plurality of waveform shaping units 18, and the plurality of determination units 20 may be provided corresponding to the plurality of terminals of the device under test 100, respectively. Good.

  FIG. 2 shows the configuration of the individual pattern generation unit 14 according to this embodiment together with the pattern selection unit 16. Each of the individual pattern generation units 14 includes a universal buffer memory (hereinafter referred to as UBM) 30, an address pointer unit 32, a data selection unit 34, a write buffer unit 36, a mask unit 38, and a control. Part 40.

The UBM 30 stores a plurality of individual patterns individually supplied to the corresponding device under test 100 so that two or more individual patterns supplied in different cycles correspond to different bit fields in the data of the same address. In this embodiment, the UBM 30 includes 2 ^N bit fields (N is a positive integer), and each bit field includes data including an individual pattern to be generated in one cycle. Remember. In the present embodiment, the UBM 30 may sequentially include 2 ^N individual patterns (hereinafter referred to as individual pattern groups) that should be generated sequentially in a continuous bit field of data at one address. Thereby, according to the UBM 30, it is possible to output 2 ^N continuous individual patterns by reading one data. Further, the UBM 30 may sequentially store individual pattern groups to be generated successively as data of continuous addresses. Thereby, according to UBM30, the continuous individual pattern group can be read by sequentially increasing the address.

  The UBM 30 further includes a data input terminal 42 for inputting data to be written, a data output terminal 44 for outputting stored data, an address terminal 46 for inputting an address, and a clock input terminal 48 for inputting a reference clock. And at least one command input terminal 50 for instructing a write operation or a read operation. When an instruction for a write operation is input via the command input terminal 50, the UBM 30 writes the data input via the data input terminal 42 into an area corresponding to the address input via the address terminal 46. . When an instruction for a read operation is input via the command input terminal 50, the UBM 30 reads data stored in an area corresponding to the address input via the address terminal 46, and sets the data output terminal 44 to Output via. The UBM 30 performs a writing operation and a reading operation in synchronization with the reference clock of the test apparatus 10 input via the clock input terminal 48.

  The address pointer unit 32 holds an address where the next individual pattern in the UBM 30 is stored. Then, the address pointer unit 32 supplies the held address to the UBM 30 via the address terminal 46. In the present embodiment, the address pointer unit 32 holds an address pointer. The address pointer designates an address where the next individual pattern in the UBM 30 is stored, and a bit field including the next individual pattern in the data of the address. As an example, the address pointer may be represented by a binary number of N + M bits (M is a positive integer). The upper M bits of the address pointer in this example designate an address in the UBM 30 in which an individual pattern to be generated next is stored. The lower N bits of the address pointer in this example designate the position of the bit field including the individual pattern to be generated next in the data.

  Further, as an example, the address pointer unit 32 may receive an address pointer load signal that specifies the initial value of the address pointer and a control signal that indicates the timing at which the individual pattern should be generated. When the address pointer load signal is input, the address pointer unit 32 holds the address pointer specified by the address pointer load signal. When receiving a control signal, the address pointer unit 32 increments the held address pointer by one.

Such an address pointer unit 32 increments the address pointer by 1 in accordance with the control signal, so that 2 ^N bit fields included in the data of an arbitrary address are sequentially generated using the lower N bits of the address pointer. Can be specified. Furthermore, the address pointer unit 32 increments the upper M bits of the address pointer by 1 in accordance with the carry of the lower N bits, and therefore, using the upper M bits of the address pointer, After specifying the bit field, the next address can be specified.

When the data selection unit 34 sequentially supplies two or more individual patterns stored at the address designated by the address pointer unit 32 to the device under test 100, the data selection unit 34 supplies each cycle from the data read from the UBM 30. Patterns are sequentially selected and supplied to the corresponding pattern selection unit 16. In the present embodiment, the data selection unit 34 inputs data (2 ^N individual patterns) stored in the address specified by the upper M bits of the address pointer output from the UBM 30. Then, the data selection unit 34 selects the individual pattern of the bit field specified by the lower N bits of the address pointer in the input data, and outputs the selected individual pattern to the corresponding pattern selection unit 16. As a result, the data selection unit 34 can sequentially output ^2N individual patterns included in the data of the address designated by the address pointer according to the order of the bit fields.

When receiving an instruction to sequentially write a plurality of individual patterns supplied individually to the corresponding device under test 100 to the UBM 30, the write buffer unit 36 writes a plurality of bits to be written in all the bit fields included in the data of the same address. The received individual patterns are sequentially buffered until the individual patterns are prepared. In the present embodiment, the write buffer unit 36 inputs a capture target signal that sequentially includes individual patterns to be written to the UBM 30. When the device under test 100 is a flash memory or the like, the write buffer unit 36 may input fail information indicating a defective position of the corresponding device under test 100 as a capture target signal. In this embodiment, the write buffer unit 36 has 2 ^N individual patterns to be included in the data of the same address, and further, until these 2 ^N individual patterns are written to the corresponding addresses of the UBM 30, Buffer received individual patterns.

  Further, when the write buffer unit 36 receives an instruction to sequentially write a plurality of individual patterns to be individually supplied to the corresponding device under test 100 to the UBM 30, the data of the address where the individual pattern is to be written is already another individual pattern. May be buffered sequentially after the other individual patterns are read out and buffered. Thus, when rewriting an individual pattern of a part of the bit field in the data at an arbitrary address, the write buffer unit 36 is included in advance in the bit field that does not rewrite the data stored at the arbitrary address. A new individual pattern can be included in the data without erasing the individual pattern.

  The mask unit 38 masks the reference clock input to the UBM 30 during a period when the address held in the address pointer unit 32 is not changed during data reading. In the present embodiment, the mask unit 38 masks the reference clock input to the UBM 30 during a period in which the upper M bits of the address pointer are not changed. The mask unit 38 changes the address held in the address pointer unit 32, and supplies the reference clock to the corresponding device under test 100 when the individual pattern included in the data stored in the changed address is supplied. The data input to the UBM 30 and read at the changed address is read.

  The mask unit 38 masks the reference clock input to the UBM 30 until a plurality of individual patterns to be written in all the bit fields included in the data of the same address are prepared in the write buffer unit 36 at the time of data writing. . The mask unit 38 inputs a reference clock to the UBM 30 when writing data including two or more individual patterns buffered in the write buffer unit 36 to the UBM 30.

  Further, in response to the tail individual pattern to be written to the UBM 30 being buffered in the write buffer unit 36, the mask unit 38 inputs the reference clock to the UBM 30 and transfers the data buffered in the write buffer unit 36 to the UBM 30. May be written. In the present embodiment, the mask unit 38 inputs the reference clock to the UBM 30 and receives the data buffered in the write buffer unit 36 in response to the input of the pattern end signal indicating the read end or write end timing. Write to UBM 30. Thereby, according to the mask part 38, an individual pattern can be reliably memorize | stored in UBM30 to the end.

  The control unit 40 causes the UBM 30 to perform a read operation or a write operation by supplying a write instruction command or a read instruction command to the UBM 30. In the present embodiment, the control unit 40 may issue a write instruction command or a read instruction command to the UBM 30 when there is a change in the upper M bits of the address pointer. Further, the control unit 40 issues a write instruction command or a read instruction command in response to a pattern start signal indicating the read start or write start timing to start the read operation or the write operation for the UBM 30, and thereafter The writing instruction or reading instruction command may continue to be issued until the pattern end signal is input.

  The pattern selection unit 16 inputs the common pattern output by the common pattern generation unit 12 and the individual pattern output by the corresponding individual pattern generation unit 14, and selects and outputs one of them. In the present embodiment, the pattern selection unit 16 selects and outputs either a common pattern or an individual pattern according to a control signal.

  According to such an individual pattern generation unit 14, a plurality of individual patterns included in the data of one address can be read from the UBM 30 at a time, so that the number of times of data reading with respect to the UBM 30 can be reduced. Furthermore, the individual pattern generator 14 masks the reference clock input to the UBM 30 at a timing other than the time of reading. Thus, according to the individual pattern generation unit 14, the number of reference clocks input to the UBM 30 at the time of reading can be reduced, and as a result, the power consumed by the UBM 30 can be reduced.

  Further, according to such an individual pattern generation unit 14, when writing an individual pattern, after all the individual patterns to be included in the data of the same address are prepared, the data is collectively written into the UBM 30, so that the UBM 30 It is possible to reduce the number of times data is written to. Furthermore, the individual pattern generation unit 14 masks the reference clock input to the UBM 30 at a timing other than at the time of writing. Thus, according to the individual pattern generation unit 14, the number of reference clocks input to the UBM 30 at the time of writing can be reduced, and as a result, the power consumed by the UBM 30 can be reduced.

  Note that each of the individual pattern generation unit 14 and the pattern selection unit 16 may receive a control signal from the common pattern generation unit 12. Further, the individual pattern generation unit 14 may input an address pointer load signal, a pattern start signal, and a pattern end signal from the common pattern generation unit 12. The individual pattern generation unit 14 may input a reference clock from a reference clock generation unit provided in the test apparatus 10. Further, each of the individual pattern generation unit 14 and the pattern selection unit 16 individually supplies an individual pattern supplied to the corresponding determination unit 20 for pass / fail determination in addition to the individual pattern supplied individually to the corresponding device under test 100. A similar process may be performed.

  FIG. 3 shows an example of the configuration of the UBM 30 according to the present embodiment, together with the address pointer unit 32, the data selection unit 34, and the write buffer unit 36. For example, the UBM 30 may include a memory cell 52, an address control unit 54, an input control unit 56, and an output control unit 58.

The memory cell 52 is assigned an address in units of words that can store at least data including ^2N (for example, 4) bit fields. The address control unit 54 designates a corresponding word on the memory cell 52 according to the upper M bits of the address pointer. When an instruction for a write operation is input via the command input terminal 50, the input control unit 56 inputs data from the write buffer unit 36, and a word designated by the address control unit 54 in synchronization with the reference clock. Write to.

  When a read operation instruction is input via the command input terminal 50, the output control unit 58 reads data stored in the word designated by the address control unit 54 in synchronization with the reference clock. The data selection unit 34 outputs the value of the bit field specified by the lower N bits of the address pointer in the data read by the output control unit 58 to the pattern selection unit 16 as an individual pattern. The data selection unit 34 can output the data read by the output control unit 58 to the pattern selection unit 16 without synchronizing with the reference clock. According to the UBM 30 as described above, two or more individual patterns can be stored corresponding to different bit fields in the data of the same address.

  FIG. 4 shows an example of the configuration of the write buffer unit 36 according to the present embodiment, together with the UBM 30, the address pointer unit 32, the mask unit 38, and the control unit 40. As an example, the write buffer unit 36 may include an input selection unit 62, a plurality of registers 64, and an address decoding unit 66.

  The input selection unit 62 inputs either the capture target signal or the signal read from the address where the capture target signal is to be written. When the input selection unit 62 receives an instruction to sequentially write the capture target signal to the UBM 30, the input selection unit 62 stores another individual pattern in the bit field in which the capture target signal is not written in the data of the UBM 30 address to which the capture target signal is to be written. When the signal to be captured is input, the data stored in the address is input from the UBM 30 before the capture target signal is input.

  In addition, the input selection unit 62 receives an instruction to sequentially write the capture target signal to the UBM 30, and the data at the address of the UBM 30 to which the capture target signal is to be written other than the individual pattern included in the capture target signal. When the individual pattern is not included, or when reading of the data of the address to which the capture target signal is to be written is completed, the capture target signal is input.

  Each of the registers 64 is provided corresponding to each bit field in the data of the address of the UBM 30, and buffers a signal input via the input selection unit 62. As an example, the register 64 may include first to fourth registers 64-1 to 64-4 when the data includes four bit fields. The address decoding unit 66 selects the register 64 corresponding to the bit field specified by the lower N bits of the address pointer among the plurality of registers 64 as a register to hold data.

  Such a write buffer unit 36 sequentially stores the individual patterns included in the capture target signal in the register 64 of the corresponding bit field. When all the individual patterns to be included in one address are prepared, the UBM 30 inputs all the individual patterns stored in the plurality of registers 64 and stores them in the corresponding addresses. Thereby, according to the write buffer unit 36, the individual patterns can be sequentially buffered until a plurality of individual patterns to be written in all the bit fields included in the data of the same address are prepared.

  Furthermore, when the data at the address of the UBM 30 to be written includes another individual pattern, the write buffer unit 36 once reads the other individual pattern from the UBM 30 and buffers it in the register 64 of the corresponding bit field. To do. Thereafter, the write buffer unit 36 sequentially buffers the individual patterns included in the capture target signal in the register 64 of the corresponding bit field. Thus, the write buffer unit 36 can sequentially buffer the received individual patterns after reading and buffering the other individual patterns.

  FIG. 5 shows an example of the timing of each signal of the test apparatus 10 at the time of reading. In FIG. 5, (A) shows a reference clock. (B) shows a test period (cycle). (C) shows a common pattern. (D) shows a pattern start signal. (E) shows a control signal. (F) shows an address pointer load signal. (G) indicates the upper M bits of the address pointer. (H) indicates the lower N bits of the address pointer. (I) indicates a reference clock input to the UBM 30. (J) shows the D [3] bit field of the output data of the UBM 30. (K) indicates the D [2] bit field of the output data of the UBM 30. (L) indicates the D [1] bit field of the output data of the UBM 30. (M) indicates a D [0] bit field of the output data of the UBM 30. (N) indicates an individual pattern. (O) shows an application pattern applied to the device under test 100. (P) shows the time of the timing chart. The test apparatus 10 performs the test when the test cycle (cycle) shown in (B) is H logic.

  First, at time t1, the individual pattern generator 14 inputs a pattern start signal (D) and an address pointer load signal (F). Next, at time t2, the address pointer unit 32 holds the address pointer (G, H) designated by the address pointer load signal. Further, at time t2, the mask unit 38 inputs the reference clock to the UBM 30 in response to the input of the pattern start signal (I). In response to the input of the reference clock, the UBM 30 outputs the data stored at the address specified by the upper M bits of the address pointer (J, K, L, M). Then, the data selection unit 34 selects the bit field (H) designated by the lower N bits of the address pointer in the data output from the UBM 30, and outputs it as an individual pattern (N).

  Next, at each timing of times t3, t4, and t5, the individual pattern generator 14 inputs a control signal (E). The address pointer unit 32 increments the address pointer by 1 (G, H) according to the control signal. Then, the data selection unit 34 selects the bit field (H) designated by the lower N bits of the address pointer and sequentially outputs it as an individual pattern (N). The mask unit 38 masks the reference clock input to the UBM 30 because the upper M bits of the address pointer do not change at times t3, t4, and t5 (I).

  Next, at time t6, the individual pattern generation unit 14 inputs a control signal (E). The address pointer unit 32 increments the address pointer according to the control signal (G, H). Here, at time t6, the lower N bits of the address pointer carry, so the upper M bits of the address pointer increase by 1 (G). The mask unit 38 supplies the reference clock to the UBM 30 according to the change of the upper M bits of the address pointer (I). Then, the UBM 30 outputs data at the address specified by the upper M bits of the address pointer in response to the supply of the reference clock.

  As described above, according to the individual pattern generation unit 14, the reference clock is supplied to the UBM 30 at the timing of reading data from the UBM 30, and the reference clock input to the UBM 30 is masked at a timing other than the timing of reading data from the UBM 30. Thereby, according to the individual pattern generation unit 14, the power consumed by the UBM 30 can be reduced.

  FIG. 6 shows an example of the timing of each signal of the test apparatus 10 at the time of writing. In FIG. 6, (A) shows a reference clock. (B) shows a test period (cycle). (C) shows a pattern start signal. (D) shows a control signal. (E) shows a capture target signal. (F) indicates the upper M bits of the address pointer. (G) indicates the lower N bits of the address pointer. (H) shows an enable signal for operating the first register 64-1 storing the D [3] bit field. (I) indicates a value held by the first register 64-1 that stores the D [3] bit field. (J) shows an enable signal for operating the second register 64-2 storing the D [2] bit field. (K) indicates a value held by the second register 64-2 that stores the D [2] bit field. (L) indicates an enable signal for operating the third register 64-3 storing the D [1] bit field. (M) indicates a value held by the third register 64-3 that stores the D [1] bit field. (N) indicates an enable signal for operating the fourth register 64-4 storing the D [0] bit field. (O) indicates a value held by the fourth register 64-4 storing the D [0] bit field. (P) indicates a reference clock input to the UBM 30. (Q) indicates the time of the timing chart. The test apparatus 10 performs the test when the test cycle (cycle) shown in (B) is H logic.

  First, at time t11, the individual pattern generation unit 14 inputs a pattern start signal (C). Next, at time t12, the individual pattern generator 14 inputs a control signal and a capture target signal. Furthermore, at time t12, the first register 64-1 corresponding to the bit field (D [3]) designated by the lower N bits of the address pointer buffers the capture target signal according to the input of the control signal ( H, I).

  Next, at each timing of times t13, t14, and t15, the individual pattern generator 14 inputs a control signal (D). The address pointer unit 32 increments the address pointer by 1 in accordance with the control signal (F, G). At time t13, the second register 64-2 corresponding to the bit field (D [2]) designated by the lower N bits of the address pointer buffers the capture target signal according to the input of the control signal (J, K ). At time t14, the third register 64-3 corresponding to the bit field (D [1]) designated by the lower N bits of the address pointer buffers the capture target signal according to the input of the control signal (L, M ). At time t14, the fourth register 64-4 corresponding to the bit field (D [0]) designated by the lower N bits of the address pointer buffers the capture target signal according to the input of the control signal (N, O ). Note that the mask unit 38 masks the reference clock input to the UBM 30 because the upper M bits of the address pointer do not change at times t13, t14, and t15 (I).

  Next, at time t16, the individual pattern generator 14 inputs a control signal (D). The address pointer unit 32 increments the address pointer according to the control signal (F, G). Here, at time t16, the lower N bits of the address pointer carry, so the upper M bits of the address pointer increase by 1 (F). The mask unit 38 supplies the reference clock to the UBM 30 according to the change of the upper M bits of the address pointer (P). Then, the UBM 30 writes the values buffered in the first to fourth registers 64-1 to 64-4 to the address specified by the upper M bits of the address pointer in response to the supply of the reference clock.

  As described above, according to the individual pattern generation unit 14, the reference clock is supplied to the UBM 30 at the timing of writing data from the UBM 30, and the reference clock input to the UBM 30 is masked at a timing other than the timing of writing data from the UBM 30. Thereby, according to the individual pattern generation unit 14, the power consumed by the UBM 30 can be reduced.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention, together with a device under test 100. The structure of the separate pattern generation part 14 which concerns on embodiment of this invention is shown with the pattern selection part 16. FIG. An example of the configuration of the UBM 30 according to the embodiment of the present invention is shown together with an address pointer unit 32, a data selection unit 34, and a write buffer unit 36. An example of the configuration of the write buffer unit 36 according to the embodiment of the present invention is shown together with the UBM 30, the address pointer unit 32, and the mask unit 38. An example of the timing of each signal of the test apparatus 10 at the time of reading is shown. An example of the timing of each signal of the test apparatus 10 at the time of writing is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Test apparatus 12 Common pattern generation part 14 Individual pattern generation part 16 Pattern selection part 18 Waveform shaping part 20 Determination part 30 UBM
32 Address pointer section 34 Data selection section 36 Write buffer section 38 Mask section 40 Control section 42 Data input terminal 44 Data output terminal 46 Address terminal 48 Clock input terminal 50 Command input terminal 52 Memory cell 54 Address control section 56 Input control section 58 Output control unit 62 Input selection unit 64 Register 66 Address decoding unit 100 Device under test

Claims (6)

A test apparatus for testing a plurality of devices under test in parallel,
A common pattern generator for generating a common pattern to be supplied in common to the plurality of devices under test;
A plurality of individual pattern generation units that are provided corresponding to each of the plurality of devices under test and generate individual patterns that are individually supplied to the corresponding devices under test;
Each of the plurality of devices under test is provided corresponding to each of the plurality of devices under test, and the common pattern generated by the common pattern generator and the individual patterns generated by the corresponding individual pattern generator are supplied to the corresponding devices under test. And a plurality of pattern selection sections for selecting
Each of the individual pattern generators is
A plurality of individual patterns individually supplied to the corresponding device under test are stored so that two or more individual patterns supplied in different cycles correspond to different bit fields in the data of the same address, and the reference of the test apparatus A universal buffer memory that performs a write operation and a read operation in synchronization with a clock; and
An address pointer section for holding an address at which the next individual pattern in the universal buffer memory is stored;
The reference clock input to the universal buffer memory during a period in which two or more individual patterns having the same address are sequentially supplied to the device under test without changing the address held in the address pointer section. , The address held in the address pointer section is changed, and the individual pattern included in the data stored in the changed address is supplied to the corresponding device under test. A mask part that inputs to the buffer memory and reads the data stored at the changed address;
In the case where two or more individual patterns stored at the address specified by the address pointer unit are sequentially supplied to the device under test, the individual patterns supplied to each cycle from the data read from the universal buffer memory A data selection unit that sequentially selects and supplies the corresponding pattern selection unit;
Test equipment with   2. The test apparatus according to claim 1, wherein each of the universal buffer memories has a clock input terminal for inputting the reference clock and at least one command input terminal for instructing a write operation or a read operation. Each of the individual pattern generators is
A plurality of individual patterns to be written in all the bit fields included in the data of the same address when receiving an instruction to sequentially write a plurality of individual patterns supplied individually to the corresponding device under test to the universal buffer memory Until it is complete, further has a write buffer unit for sequentially buffering the received individual patterns,
The mask unit masks the reference clock input to the universal buffer memory until a plurality of individual patterns to be written in all the bit fields included in the data of the same address are prepared in the write buffer unit. The test according to claim 1, wherein the reference clock is input to the universal buffer memory when data including two or more individual patterns buffered in the write buffer unit is written into the universal buffer memory. apparatus.   The mask unit inputs the reference clock to the universal buffer memory in response to the tail individual pattern to be written to the universal buffer memory being buffered in the write buffer unit. The test apparatus according to claim 3, wherein data buffered in a buffer unit is written to the universal buffer memory.   When the write buffer unit receives an instruction to sequentially write a plurality of individual patterns supplied individually to the corresponding device under test to the universal buffer memory, the data of the address to which the individual pattern is to be written is already another The test apparatus according to claim 3, wherein the received individual patterns are sequentially buffered after the other individual patterns are read out and buffered in response to storing the individual patterns. A test method for testing a plurality of devices under test in parallel,
A common pattern generation stage for generating a common pattern to be supplied in common to the plurality of devices under test;
A plurality of individual pattern generation stages that are provided corresponding to each of the plurality of devices under test and generate individual patterns that are individually supplied to the corresponding devices under test;
Each of the plurality of devices under test is provided corresponding to each of the plurality of devices under test, and the common pattern generated at the common pattern generation stage and the corresponding individual pattern generated at the individual pattern generation stage are supplied to the corresponding device under test. A plurality of pattern selection stages for selecting
Each of the individual pattern generation steps includes:
A plurality of individual patterns supplied individually to the corresponding devices under test are supplied to different universal cycles in a universal buffer memory that performs a write operation and a read operation in synchronization with a reference clock of the test apparatus. Storing the individual patterns corresponding to different bit fields in the data of the same address;
An address pointer stage holding an address at which the next individual pattern in the universal buffer memory is stored;
The reference clock input to the universal buffer memory during a period in which two or more individual patterns of the same address are sequentially supplied to the device under test without changing the address held by the address pointer stage. And the address held by the address pointer stage is changed, and when the individual pattern included in the data stored in the changed address is supplied to the corresponding device under test, the reference clock is A mask stage for inputting data to the buffer memory and reading the data stored at the changed address;
In the case where two or more individual patterns stored in the address held in the address pointer stage are sequentially supplied to the device under test, the individual patterns supplied to each cycle from the data read from the universal buffer memory A data selection step of sequentially selecting and supplying the corresponding pattern selection step;
A test method having:

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