JP4674293B2 - Manufacturing method of MOS transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor, and more particularly to a method for manufacturing a MOS transistor suitable for a driver of a liquid crystal display device in which a high voltage MOS transistor and a low voltage MOS transistor are mixed, or for a flash memory.
[0002]
[Prior art]
A driver of a liquid crystal display device and a flash memory MOS transistor are formed by mixing a high voltage MOS transistor and a low voltage MOS transistor.
Conventionally, in the manufacture of this type of MOS transistor, the formation of impurity regions by ion implantation is performed by applying a resist to a semiconductor substrate, removing the resist only in the regions where ions are to be implanted, and forming openings in the other regions. Ion implantation is performed.
[0003]
FIG. 37 is a process chart for explaining an example of a conventional impurity region forming process. First, (a) an oxide film INS is formed on a semiconductor substrate SUB, (b) a photoresist REG is applied thereon, a photomask PMSK is applied, and a resist in a region where ions are to be implanted by exposure / development processing. Remove. (C) Ion ION is implanted through the oxide film INS through the opening from which the resist has been removed to form an ion implanted layer having a low impurity concentration or an ion implanted layer IONL / R having a high impurity concentration. Finally, (d) the remaining resist is removed.
[0004]
Thus, conventionally, one photomask is required for each impurity region, and two photomasks are required to form two regions having different impurity regions.
[0005]
FIG. 38 is a process chart for explaining another example of the conventional impurity region forming process. In this process, first, (a) an oxide film INS is formed on the semiconductor substrate SUB, ions are implanted into the entire surface thereof, (b) an ion implantation layer IONL having a low impurity concentration is formed, and (c) an oxide film is formed. A resist REG is applied thereon, and the resist in a region where ions are to be implanted is removed by exposure / development processing through a photomask PMSK having an opening in a region having a high impurity concentration. (D) An ion ION is implanted through the oxide film INS through the opening from which the resist is removed, and (e) a region IONR having a high impurity concentration is formed.
[0006]
In this process, two types of impurity regions having different ion concentrations can be formed with one photomask. However, two ion implantation steps are required, and in the first ion implantation, ions are formed on the entire surface of the semiconductor substrate SUB. Will be driven in.
[0007]
FIG. 34 and FIG. 35 are schematic process diagrams for explaining a manufacturing process of an active matrix liquid crystal panel driver having a high breakdown voltage MOS transistor. SUB is a semiconductor substrate, HNW is a well of a high breakdown voltage PMOS transistor, and HPW is high. The well of the breakdown voltage NMOS transistor, NW is the well of the low breakdown voltage PMOS transistor, PW is the well of the low breakdown voltage NMOS transistor, PF is the well HNW of the high breakdown voltage PMOS transistor and the well NW of the low breakdown voltage PMOS transistor. A channel stopper, NP is a channel stopper in the field region of the well HPW of the high breakdown voltage NMOS transistor and a well PW of the low breakdown voltage NMOS transistor, FR is a field region covered with a thick oxide film, and HPM is a high breakdown voltage PMOS transistor. The field relaxation layer of the drain / source part of the transistor, HNM is the field relaxation layer of the drain / source part of the high breakdown voltage NMOS transistor, PPG and PNG are the gate electrodes of the high breakdown voltage MOS transistor, and LPG and LNG are the low breakdown voltage MOS transistor. The gate electrode is shown.
[0008]
This process will be described with reference to FIGS. 39 and 40 in order. First, (a) the wells HNW and HPW of the high breakdown voltage MOS transistor are formed on the semiconductor substrate SUB with one photomask. Thereafter, (b) wells NW and PW of the low breakdown voltage MOS transistor are formed using respective photomasks. In this step, two photomasks are used.
[0009]
Next, (c) field regions and channel stoppers NF and PF are formed. In this step, three photomasks are used.
[0010]
Then, (d) after forming the electric field relaxation layers HNM and HPM of the high voltage MOS transistor using the respective photomasks, (e) forming the gate electrodes PPG, PNG, LPG and LNG to form the high voltage PMOS transistor A high breakdown voltage NMOS transistor, a low breakdown voltage PMOS transistor, and a low breakdown voltage NMOS transistor are obtained.
[0011]
The photomasks used in all the processes described above are required only for well formation, three for mask formation, two for channel stopper formation, and two for formation of the electric field relaxation layer in the drain / source portion of the high voltage MOS transistor. Including the formation, 8 photomasks are required in total.
[0012]
Further, the conventional process described with reference to FIG. 38 requires ion implantation for each different impurity concentration.
[0013]
[Problems to be solved by the invention]
As described above, when impurity regions having different ion concentrations are formed, the conventional impurity region forming process requires a photomask for each, and ion implantation is also performed a number of times corresponding to the number of impurity regions having different concentrations. I was trying.
[0014]
That is, when a high breakdown voltage MOS transistor and a low breakdown voltage MOS transistor are mixed, due to the short channel effect between the drain and source of the high breakdown voltage MOS transistor, the well of the high breakdown voltage MOS transistor has a low impurity concentration and a low impurity concentration. It is necessary to increase the impurity concentration of the well of the breakdown voltage MOS transistor. For this reason, in the conventional manufacturing process described above, ion implantation is performed a plurality of times using a large number of expensive photomasks.
[0015]
The object of the present invention is to eliminate the above-mentioned problems of the prior art, reduce the number of photomasks required for the manufacture of MOS transistors, reduce the number of ion implantations, reduce the number of manufacturing steps, and reduce the cost. It is to provide a method for manufacturing a transistor.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is characterized in that the ion implantation depth is controlled using the difference in thickness of the oxide film to form a plurality of types of ion implantation layers having different concentrations.
[0017]
FIG. 1 is a schematic diagram for explaining the principle of ion implantation in the method of manufacturing a MOS transistor of the present invention. In the present invention, oxide films having different thicknesses are formed on the surface of the semiconductor substrate SUB. The oxide film INS is formed thick in the field region and thin in the active region.
[0018]
When ion implantation is performed so as to pass through the oxide film INS, a high concentration ion implantation layer is formed on the surface of the semiconductor substrate SUB in the field region where the oxide film is thick, and in the active region where the oxide film INS is thin, the semiconductor substrate SUB. An ion implantation layer is formed in a deep portion.
[0019]
As a result, the surface impurity concentration is lower than that of the field region, and two types of ion implantation layers having different concentrations can be formed.
[0020]
Examples of typical configurations of the present invention are as described in the following (1) and (2).
[0021]
(1) In a manufacturing method of a MOS transistor including a step of forming well regions having different impurity concentrations by ion implantation in a semiconductor substrate,
An oxide film having a different thickness is coated on the upper layer of the semiconductor substrate, and regions having different impurity concentrations are formed by a difference in thickness of the oxide film by one ion implantation.
[0022]
(2) A high breakdown voltage MOS transistor used at a high voltage and a low breakdown voltage MOS transistor used at a low voltage are mixed on the same semiconductor substrate due to a difference in use voltage, and a well region having a different impurity concentration is formed due to a difference in use voltage. In a method for manufacturing a MOS transistor,
First, a well of a high breakdown voltage MOS transistor having a low impurity concentration is formed, then a field oxide film for electrically isolating the MOS transistors is formed, and then a well of a low breakdown voltage MOS transistor having a high impurity concentration is formed. In the well ion implantation process of the low breakdown voltage MOS transistor, the electric field relaxation layer of the drain / source portion of the high breakdown voltage MOS transistor and the channel stopper for the parasitic MOS transistor are formed at the same time.
[0023]
The present invention is not limited to the above configuration, and various modifications can be made without departing from the technical idea of the present invention and without sticking to the following embodiments.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the illustrated examples.
[0025]
2 and 3 are process charts schematically showing one embodiment of a method of manufacturing a MOS transistor according to the present invention. In FIG. 2, the same reference numerals as in FIGS. 34 and 35 correspond to the same parts.
[0026]
First, (a) the wells HNW and HPW of the high voltage MOS transistor are formed on the semiconductor substrate SUB with a single photomask. (B) A field region FR is formed of a thick oxide film on the boundary between the wells HNW and HPW of the high voltage MOS transistor.
A single photomask is used to form this field region.
[0027]
Next, (c) the well NW of the low breakdown voltage MOS transistor (channel stopper and electric field relaxation layer) is formed with two photomasks ((c-1), (c-2)).
The following goes to the gate electrode formation process.
[0028]
As described above, in the present invention, the field region is formed after the well of the high voltage MOS transistor is formed by changing the order of the conventional manufacturing process, and then the low voltage well is formed. In this ion implantation for forming wells, ions are implanted by utilizing the difference in thickness between the oxide film in the field region and the active region. Therefore, a low-voltage well photomask is used as a substitute for the photomask for the channel stopper and the electric field relaxation layer. Therefore, it is possible to form the same structure as the conventional one with four photomasks, and it is possible to delete the four photomasks (the channel stopper and the electric field relaxation layer in each of the N region and the P region).
[0029]
4, 5, 6 and 7 are process diagrams for explaining an embodiment in which the present invention is applied to a liquid crystal panel driver manufacturing process. This step includes a well formation process (a) for a high breakdown voltage MOS transistor, a field region formation process (b), a well formation process (c) for a low breakdown voltage MOS transistor, and a gate electrode formation process (d). .
[0030]
First, (a) in a well formation process of a high voltage MOS transistor, (a-1) a through oxide film INS and a nitride film SIN for ion implantation are formed on the surface of the semiconductor substrate SUB. By applying and patterning the resist film REG, the SIN in the region that becomes the well HNW of the PMOS transistor is removed to form an opening, and ions are implanted into the region through the opening. Then, (a-2) after ion implantation, the resist film REG is removed and thermal oxidation is performed. Since the region where the nitride film SIN exists during this thermal oxidation is not oxidized, if the nitride film SIN is removed after the thermal oxidation, the oxide film in the region where the nitride film SIN existed remains a thin film, so that the well of the PMOS transistor A thick oxide film INS (TINS) is obtained in the HNW region, and a thin oxide film INS (SINS) is obtained in the well HPW region of the NMOS transistor. Using this thick oxide film INS (thermal oxide film TINS) as a resist film, ions are implanted into the well HPW region of the NMOS transistor.
[0031]
Next, in (b) the formation process of the field region, (b-1) the well region is stretched by long-time thermal diffusion, and the thermal oxide film TINS and the nitride film SIN are again formed on the surface of the semiconductor substrate SUB. After forming a film and forming a resist film (not shown), the nitride film is etched using a photomask for field region formation. (B-2) When thermal oxidation is performed after the nitride film is etched, a thick field oxide film FINS is formed in a region where the nitride film SIN does not exist.
[0032]
(C) In the well formation of the low breakdown voltage MOS transistor, (c-1) In the formation of the well NW of the low breakdown voltage PMOS transistor, a resist film is applied and patterned using a photomask to form a well region of the low breakdown voltage PMOS transistor. An opening is formed in By performing ion implantation through the opening of the resist film, the channel stopper NW (CS) in the well HNW region of the high breakdown voltage PMOS transistor as well as the well region NW of the low breakdown voltage PMOS transistor and the electric field relaxation of the high breakdown voltage NMOS transistor The region NW (FD) is formed.
[0033]
Since this ion implantation utilizes the difference in thickness of the oxide film, ions are implanted with a high concentration in the channel stopper NW (CS) and a low concentration in the well region NW and the electric field relaxation region FD.
[0034]
Similarly, in (c-2) forming the well PW of the low breakdown voltage NMOS transistor, ion implantation is performed after forming an opening in the well PW region of the low breakdown voltage NMOS transistor by patterning the resist film in the same manner as described above. The channel stopper PW (FD) of the well region HPW of the high breakdown voltage NMOS transistor is formed together with the well PW of the low breakdown voltage NMOS transistor. Thereafter, (c-3) the well of the low breakdown voltage MOS transistor and the electric field relaxation layer of the high breakdown voltage MOS transistor are extended by thermal diffusion.
[0035]
Thereafter, (d) go to the gate electrode formation process, and form the gate electrodes PPG and PNG of the high voltage MOS transistor and the gate electrodes LPG and LNG of the low voltage MOS transistor to provide a driver (IC) suitable for the liquid crystal panel. obtain.
[0036]
In the application of the present invention, in the above process flow, the well of the high voltage MOS transistor is formed first, and then the field oxide film for electrically separating the MOS transistors is formed. As shown in FIG. 1, a field oxide film is first formed by using a single mask, and then a high-voltage well ion implantation is performed with a high energy that passes through a thick oxide film. The present invention can also be applied to a process flow in which an electric field relaxation layer and a channel stopper of a high voltage MOS transistor are simultaneously formed by ion implantation for forming a low voltage well after forming a well.
[0037]
Further, the present invention can be applied not only to the planar type MOS transistor shown in FIG. 10 but also to the production of the LOCOS offset type MOS transistor shown in FIG. As shown in FIG.
[0038]
As described in the above embodiment, according to the manufacturing method employing the process according to the present invention, four photomasks can be reduced and the number of ion implantations can be reduced as compared with the conventional process.
[0039]
Next, an active matrix type color liquid crystal display device to which a driver employing a MOS transistor manufactured according to the present invention is applied will be described.
[0040]
13 is a plan view for explaining the configuration of one pixel of an active matrix liquid crystal display device to which the present invention is applied and its periphery, FIG. 14 is a cross-sectional view taken along line 3-3 in FIG. 13, and FIG. FIG. 16 is a cross-sectional view taken along line 4-4 of FIG. 13, and FIG. 16 is a plan view showing a state where a plurality of pixels shown in FIG. 13 are arranged.
[0041]
As shown in FIG. 13, each pixel includes two adjacent scanning signal lines (gate signal line or horizontal signal line) GL and two adjacent video signal lines (drain signal line or vertical signal line) DL. In the intersection region (in the region surrounded by four signal lines).
[0042]
Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1, and a storage capacitor element Cadd. The scanning signal lines GL extend in the column direction, and a plurality of scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are formed in the column direction.
[0043]
As shown in FIG. 14, a thin film transistor TFT and a transparent pixel electrode ITO1 are formed on the side of the lower transparent glass substrate SUB1 with reference to the liquid crystal LC, and a color filter FIL and a light-shielding black matrix pattern are formed on the upper transparent glass substrate SUB2 side. A BM is formed. The upper and lower transparent glass substrates SUB2,1 have a thickness of about 1.1 mm, for example, and a silicon oxide film SIO is formed on each of both surfaces by dipping or the like. For this reason, even if there are fine scratches on the surfaces of the transparent glass substrates SUB1 and SUB2, the scanning signal lines GL, the light shielding film (black matrix) BM, etc., which are flattened by the coating of the silicon oxide film SIO and formed thereon, etc. The film quality can be kept uniform.
[0044]
A light shielding film BM, a color filter FIL, and an upper alignment film ORI2 are sequentially stacked on the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2.
[0045]
<Outline of the matrix area>
FIG. 17 is a plan view of the main part around the matrix AR of the liquid crystal panel PNL including the upper and lower transparent glass substrates SUB2 and SUB1, and FIG. 18 is a plan view showing the peripheral part of the matrix AR shown in FIG. 19 is an enlarged plan view of the vicinity of the seal portion SL corresponding to the upper left corner of the liquid crystal panel of FIGS. 20 is a cross-sectional view taken along line 19a-19a in FIG. 19 on the left side with the cross section in FIG. 14 being the center, and a cross-sectional view in the vicinity of the external connection terminal DTM to which the video signal line drive circuit is to be connected FIG. 21 is a cross-sectional view of the vicinity of the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross-sectional view of the vicinity of the seal portion where there is no external connection terminal on the right side.
[0046]
In the manufacture of this liquid crystal panel, if it is a small size, a plurality of glass substrates are processed at the same time and separated to improve the throughput. The glass substrate having a size as described above is processed to be reduced to a size suitable for each type, and in each case, the glass substrate is cut after going through one process.
[0047]
FIGS. 17 to 19 show the latter example. In both FIGS. 17 and 18, the upper and lower glass substrates SUB2 and SUB1 are cut, FIG. 19 shows the state before cutting, and LN is the glass substrate. Numerals CT1 and CT2 indicate positions at which the glass substrates SUB1 and SUB2 should be cut, respectively.
[0048]
In either case, the size of the upper glass substrate SUB2 is lower glass so that the portions (upper and lower sides and left side in the figure) where the external connection terminal groups Tg and Td (subscript omitted) exist in the completed state are exposed. It is limited to the inner side than the substrate SUB1.
[0049]
The external connection terminal groups Tg and Td are respectively a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, which will be described later, and a tape carrier package TCP (FIGS. 22 and 23) on which an integrated circuit chip CHI is mounted. (Refer to the unit). The lead-out wiring from the matrix portion of each group to the external connection terminal portion is inclined as it approaches both ends. This is because the terminals DTM and GTM of the liquid crystal panel PNL are matched with the arrangement pitch of the tape carrier package TCP and the connection terminal pitch of each tape carrier package TCP.
[0050]
A seal pattern SL (hereinafter also referred to as a sealing material) is formed between the transparent glass substrates SUB1 and SUB2 so as to seal the liquid crystal LC except for the liquid crystal sealing inlet INJ along the edge. The material of the seal pattern is made of, for example, an epoxy resin. The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to the lead-out wiring INT formed on the lower transparent glass substrate SUB1 side by silver paste material AGP at least at four points here in the liquid crystal panel. The lead-out wiring INT is formed in the same manufacturing process as a gate terminal GTM and a drain terminal DTM described later.
[0051]
The alignment films ORI1 and ORI2, the transparent pixel electrode ITO1, and the common transparent pixel electrode ITO2 are formed on the inner side of the seal pattern SL. The polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.
[0052]
The liquid crystal LC is sealed in a region partitioned by a seal pattern SL between the lower alignment film ORI1 and the upper alignment film ORI2 that set the direction of liquid crystal molecules. The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.
[0053]
In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the upper transparent glass substrate SUB2 side. The glass substrate SUB2 is overlaid, liquid crystal is injected from the opening INJ (injection port) of the sealing material SL, the injection port INJ is sealed with an epoxy resin or the like, and the upper and lower transparent glass substrates are cut.
[0054]
<< Thin Film Transistor TFT >>
The thin film transistor TFT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is set to zero, the channel resistance increases.
[0055]
The thin film transistor TFT of each pixel is divided into two (plural) in the pixel, and is composed of thin film transistors (divided thin film transistors) TFT1 and TFT2. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (the channel length and the channel width are the same). Each of the divided thin film transistors TFT1 and TFT2 includes a gate electrode GT, a gate insulating film GI, an i-type semiconductor made of i-type (intrinsic, intrinsic, conductivity type-determining impurity is not doped) amorphous silicon (Si). It has a layer AS, a pair of source electrodes SD1, and a drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and in this circuit of the liquid crystal display device, the polarity is inverted during operation, so that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.
[0056]
<< Gate electrode GT >>
The gate electrode GT is perpendicular to the scanning signal line GL (upward in FIGS. 13 and 24) as shown in FIG. 25 is a plan view illustrating only the second conductive film g2 and the i-type semiconductor layer AS in FIG. It is comprised by the shape which protrudes in (it is branched by the T-shape).
[0057]
The gate electrode GT protrudes beyond the active regions of the thin film transistors TFT1 and TFT2. The gate electrodes GT of the thin film transistors TFT1 and TFT2 are continuously formed. Here, the gate electrode GT is formed of a single-layer second conductive film g2. The second conductive film g2 is formed with a film thickness of about 1000 to 5500 mm using, for example, an aluminum (Al) film formed by sputtering. An aluminum anodic oxide film AOF is provided on the gate electrode GT.
[0058]
As shown in FIGS. 13, 14 and 26, the gate electrode GT is formed larger than the i-type semiconductor layer AS (as viewed from below). Therefore, when a backlight BL such as a fluorescent tube is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of this opaque aluminum film is shaded and light from the backlight is applied to the i-type semiconductor layer AS. Therefore, the conductive phenomenon due to light irradiation, that is, the deterioration of the OFF characteristics of the thin film transistor TFT hardly occurs. Note that the original size of the gate electrode GT is the minimum necessary for straddling between the source electrode SD1 and the drain electrode SD2 (the alignment margin between the gate electrode GT, the source electrode SD1, and the drain electrode SD2). And the depth length that determines the channel width W is the ratio of the distance (channel length) L between the source electrode SD1 and the drain electrode SD2, that is, the factor W / L that determines the mutual conductance gm. It is decided by how many. Of course, the size of the gate electrode GT in this liquid crystal display device is larger than the original size described above.
[0059]
<< Scanning signal line GL >>
The scanning signal line GL is composed of the second conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT and is integrally formed. Also, an aluminum anodic oxide film AOF is provided on the scanning signal line GL.
[0060]
<Insulating film GI>
The insulating film GI is used as the gate insulating film of each of the thin film transistors TFT1 and TFT2. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. The insulating film GI is formed using, for example, a silicon nitride film formed by plasma CVD, and has a thickness of 1200 to 2700 mm (in this liquid crystal display device, a thickness of about 2000 mm). As shown in FIG. 19, the gate insulating film GI is formed so as to surround the entire matrix part AR, and the peripheral part is removed so as to expose the external connection terminals DTM and GTM.
[0061]
<< i-type semiconductor layer AS >>
As shown in FIG. 24, the i-type semiconductor layer AS is used as a channel formation region of each of the thin film transistors TFT1 and TFT2 divided into a plurality of parts. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film, and has a thickness of 200 to 220 mm (in this liquid crystal display device, a thickness of about 200 mm).
[0062]
This i-type semiconductor layer AS is made of Si by changing the components of the supply gas.₂N_FourIn succession to the formation of the insulating film GI used as the gate insulating film, it is formed by the same plasma CVD apparatus and without being exposed to the outside from the plasma CVD apparatus.
[0063]
Similarly, the N (+) type semiconductor layer d0 (FIG. 14) doped with 2.5% of phosphorus (P) for ohmic contact is continuously 200 to 500 mm thick (about 300 mm in this liquid crystal display device). Film thickness). Thereafter, the lower transparent glass substrate SUB1 is taken out from the CVD apparatus, and the N (+) type semiconductor layer d0 and the i type semiconductor layer AS are independent as shown in FIG. 13, FIG. 14 and FIG. It is patterned into an island shape.
[0064]
As shown in FIGS. 13 and 24, the i-type semiconductor layer AS is also provided between both of the intersections (crossover portions) between the scanning signal lines GL and the video signal lines DL. This crossing portion i-type semiconductor layer AS reduces a short circuit between the scanning signal line GL and the video signal line DL at the crossing portion.
[0065]
<< Transparent pixel electrode ITO1 >>
The transparent pixel electrode ITO1 constitutes one of the pixel electrodes of the liquid crystal panel. The transparent pixel electrode ITO1 is connected to both the source electrode SD1 of the thin film transistor TFT2 and the source electrode SD1 of the thin film transistor TFT2. For this reason, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut by a laser beam or the like. Otherwise, the other thin film transistor operates normally. You can just leave it. It is rare that two thin film transistors TFT1 and TFT2 have defects at the same time, and the occurrence probability of point defects and line defects can be extremely reduced by such a redundancy method.
[0066]
The transparent pixel electrode ITO1 is composed of a first conductive film d1. The first conductive film d1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering and has a thickness of 1000 to 2000 mm (in this liquid crystal display device, a thickness of about 1400 mm). Is done.
[0067]
<< Source electrode SD1, drain electrode SD2 >>
The source electrode SD1 and the drain electrode SD2 of each of the thin film transistors TFT1 and TFT2 divided into a plurality are shown in FIGS. 13, 14 and 25 (a plan view illustrating only the first to third conductive films d1 to d3 in FIG. As shown in FIG. 3, the i-type semiconductor layer AS is provided separately from each other.
[0068]
Each of the source electrode SD1 and the drain electrode SD2 is configured by sequentially superposing a second conductive film d2 and a third conductive film d3 from the lower layer side in contact with the N (+) type semiconductor layer d0. The second conductive film d2 and the third conductive film d3 of the source electrode SD1 are formed in the same manufacturing process as the second conductive film d2 and the third conductive film d3 of the drain electrode SD2.
[0069]
The second conductive film d2 uses a chromium (Cr) film formed by sputtering and is formed with a thickness of 500 to 1000 mm (in this liquid crystal display device, a thickness of about 600 mm). The Cr film constitutes a so-called barrier layer that prevents aluminum Al of a third conductive film d3 described later from diffusing into the N (+) type semiconductor layer d0. As the second conductive film d2, in addition to the Cr film, a film of a refractory metal (Mo, Ti, Ta, W, etc.), a refractory metal silicide (MoSi)₂TiSi₂, TaSi₂, WSi₂Etc.) can also be used.
[0070]
The third conductive film d3 is formed to a thickness of 3000 to 5000 mm (in this liquid crystal display device, a thickness of about 4000 mm) by sputtering of aluminum Al. The aluminum Al film is less stressed than the chromium Cr film, can be formed thick, and is configured to reduce the resistance values of the source electrode SD1, the drain electrode SD2, and the video signal line DL. In addition to forward aluminum, an aluminum film containing silicon or copper (Cu) as an additive can also be used as the third conductive film d3.
[0071]
After the second conductive film d2 and the third conductive film d3 are patterned with the same mask pattern, the N (+) type semiconductor layer d0 is used by using the same mask or by using the second conductive film d2 and the third conductive film d3 as a mask. Is removed. That is, the N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS is removed by self-alignment except for the second conductive film d2 and the third conductive film d3. At this time, since the N (+) type semiconductor layer d0 is etched so that the entire thickness thereof is removed, the surface portion of the i type semiconductor layer AS is also slightly etched. What is necessary is just to control by processing time.
[0072]
The source electrode SD1 is connected to the transparent pixel electrode ITO1. The source electrode SD1 is a step of the i-type semiconductor layer AS (the thickness of the second conductive film d2, the thickness of the anodic oxide film AOF, the thickness of the i-type semiconductor layer AS, and the thickness of the N (+)-type semiconductor layer d0). (Step corresponding to the film thickness obtained by adding). Specifically, the source electrode SD1 includes a second conductive film d2 formed along the step of the i-type semiconductor layer AS and a third conductive film d3 formed on the second conductive film d2. Yes. The third conductive film d3 of the source electrode SD1 cannot be thickened due to the increase in stress of the Cr film of the second conductive film d2 and cannot overcome the step of the i-type semiconductor layer AS. It is configured. That is, step coverage is improved by increasing the thickness of the third conductive film d3. Since the third conductive film d3 can be formed thick, it greatly contributes to the reduction of the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).
[0073]
<< Protective film PSV1 >>
A protective film PSV1 is provided on the thin film transistor TFT and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly to protect the thin film transistor TFT from moisture, and a film having high transparency and good moisture resistance is used. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of about 1 μm.
[0074]
As shown in FIG. 19, the protective film PSV1 is formed so as to surround the entire matrix part AR, the peripheral part is removed so as to expose the external connection terminals DTM and GTM, and the upper transparent glass substrate SUB2 is shared. A portion where the electrode COM is connected to the external connection terminal connection lead line INT of the lower transparent glass substrate SUB1 by the silver paste AGP is also removed. Regarding the thickness relationship between the protective film PSV1 and the gate insulating film GI, the former is thickened in consideration of the protective effect, and the latter is thinned in consideration of the mutual conductance gm of the transistor. Therefore, as shown in FIG. 14, the protective film PSV1 having a high protective effect is formed larger than the gate insulating film GI so as to protect the peripheral portion over as wide a range as possible.
[0075]
<< Light shielding film BM >>
On the upper transparent glass substrate SUB2 side, a light shielding film BM is provided so that external light (light from above in FIG. 14) does not enter the i-type semiconductor layer AS used as a channel formation region. The light shielding film BM has a pattern as shown by hatching in FIG. FIG. 26 is a plan view illustrating only the first conductive film d1, the color filter FIL, and the light shielding film BM made of the ITO film in FIG.
[0076]
The light shielding film BM is formed of a film having a high light shielding property, for example, an aluminum film or a chromium film. In this liquid crystal display device, the chromium film is formed to a thickness of about 1300 mm by sputtering.
[0077]
Therefore, the i-type semiconductor layer AS of the thin film transistors TFT1 and TFT2 is sandwiched between the upper and lower light shielding films BM and the large gate electrode GT, and the portion is not exposed to external natural light or backlight light. As shown by hatching in FIG. 21, the light shielding film BM is formed around the pixels, that is, the light shielding film BM is formed in a lattice shape (so-called black matrix), and the effective display area of one pixel is partitioned by this lattice. ing. By this light shielding film BM, the outline of each pixel is clear and the contrast is improved. That is, the light shielding film BM has two functions of light shielding for the i-type semiconductor layer AS and a black matrix.
[0078]
Further, since the portion (the lower right portion in FIG. 13) facing the edge portion on the base side in the rubbing direction of the transparent pixel electrode ITO1 is shielded by the light shielding film BM, even if the domain is generated in the above portion, the domain is not Since it cannot be seen, display characteristics are not deteriorated.
[0079]
In addition, a backlight can be attached to the upper transparent glass substrate SUB2 side, and the lower transparent glass substrate SUB1 can be used as an observation side (external exposure side).
[0080]
As shown in FIG. 19, the light shielding film BM is also formed in a frame-like pattern as shown in FIG. 19, and the pattern is formed continuously with the pattern of the matrix portion shown in FIG. 26 provided with a plurality of dots. ing. As shown in FIGS. 18 to 21, the light shielding film BM in the peripheral portion is extended to the outside of the seal portion SL to prevent leakage light such as reflected light caused by mounting equipment such as a personal computer from entering the matrix portion. Yes. On the other hand, the light-shielding film BM is held about 0.3 to 1.0 mm inside from the edge of the upper transparent glass substrate SUB2, and is formed so as to avoid the cutting region of the upper transparent glass substrate SUB2.
[0081]
<Color filter FIL>
The color filter FIL is configured by coloring a dye on a dyeing substrate formed of a resin material such as an acrylic resin. The color filters FIL are formed in stripes at positions facing the pixels (FIG. 27) and dyed separately (FIG. 27 shows only the first conductive film d1, the light shielding film BM, and the color filter FIL in FIG. The color filters FIL of R, G, B are hatched at 45 ° and 135 °, respectively, so that the color filter FIL covers all of the transparent pixel electrode ITO1 as shown in FIGS. The light shielding film BM is formed inside the periphery of the transparent pixel electrode ITO1 so as to overlap the edge portions of the color filter FIL and the transparent pixel electrode ITO1.
[0082]
The color filter FIL can also be formed as follows. First, a dyeing base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. Thereafter, the dyeing substrate is dyed with a red dye, and a fixing process is performed to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing the same process.
[0083]
<< Protective film PSV2 >>
The protective film PSV2 is provided to prevent the dyes obtained by dyeing the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is formed of a transparent resin material such as an acrylic resin or an epoxy resin.
[0084]
<< Common transparent pixel electrode ITO2 >>
The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is between each pixel electrode ITO1 and the common transparent pixel electrode ITO2. Changes in response to potential difference (electric field). A common voltage Vcom is applied to the common transparent pixel electrode ITO2. In this case, the common voltage Vcom is set to an intermediate potential between the low-level drive voltage Vdmin and the high-level drive voltage Vdmax applied to the video signal line DL, but the power supply of the integrated circuit used in the video signal drive circuit. When it is desired to reduce the voltage to about half, an AC voltage may be applied. For the planar shape of the common transparent pixel electrode ITO2, see FIGS.
[0085]
<Gate terminal section>
28A and 28B are explanatory diagrams of a connection structure from the scanning signal line GL to the external connection terminal GTM in the display matrix portion of the liquid crystal pattern, in which FIG. 28A is a plan view and FIG. FIG. This figure corresponds to the vicinity of the lower part of FIG. 19, and the diagonal wiring portion is shown in a straight line for convenience.
[0086]
AO is a mask pattern for photographic processing, in other words, a selective anodic oxidation photoresist pattern. Accordingly, the photoresist is removed after the anodic oxidation, and the pattern AO shown in the drawing does not remain as a finished product, but the oxide film AOF is selectively formed on the gate wiring GL as shown in the sectional view of FIG. The trajectory remains. In the plan view of (A), the left side is a region where the resist is covered with resist and not anodized with reference to the photoresist boundary line AO, and the right side is a region exposed from the resist and anodized. The anodized aluminum Al layer g2 has an oxide AAl on its surface.₂O_ThreeThe film AOF is formed, and the volume of the lower conductive portion is reduced. Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains. The mask pattern AO does not intersect with the scanning signal line GL on a single straight line, but bends and intersects with a crank shape.
[0087]
In the drawing, the aluminum Al layer g2 is hatched for easy understanding, but the region not anodized is patterned in a comb shape. This is because whisker is generated on the surface when the aluminum Al layer is wide, so that the width of each one is narrowed and a plurality of them are bundled in parallel to prevent whisker generation. The aim is to minimize the probability of disconnection and the sacrifice of conductivity. Accordingly, here, the portion corresponding to the root of the comb is also shifted along the mask AO.
[0088]
The gate terminal GTM has a good adhesion to the silicon oxide SIO layer, and has a higher resistance to corrosion than aluminum Al. Further, the gate terminal GTM protects the surface and is transparent at the same level (same layer and simultaneous formation) as the pixel electrode ITO1. It is comprised with the conductive layer d1. Note that the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof are so formed that the conductive layers g2 and g1 are not etched together due to pinholes or the like when the conductive layers d2 and d3 are etched. It remains as a result of covering the area with photoresist. Further, the ITO layer d1 extending over the gate insulating film GI and extending in the right direction is one in which the same measures are further taken.
[0089]
In the plan view of FIG. 28A, the gate insulating film GI is formed on the right side of the boundary line, the protective film PSV1 is formed on the right side of the boundary line, and the terminal portion GTM located on the left side is formed from them. It is exposed and can be in electrical contact with external circuits. In the figure, only one pair of the gate line GL and the gate terminal is shown, but actually, a plurality of such pairs are arranged vertically as shown in FIG. 12, and a terminal group Tg (FIG. 13, FIG. 14), and the left side of the gate terminal is extended beyond the cutting region CT1 of the substrate in the manufacturing process and short-circuited by the wiring SHg. Such a short-circuit line SHg in the manufacturing process has an effect of preventing electrostatic breakdown that occurs during power feeding during anodization (during anodization) and rubbing of the alignment film ORI1.
[0090]
<< Drain terminal DTM >>
FIG. 29 is an explanatory diagram of the connection from the video signal line DL to the external connection terminal DTM. FIG. 29A is a plan view, and FIG. 29B is a cross-sectional view taken along line BB in FIG. Note that FIG. 29 corresponds to the vicinity of the upper right in FIG. 19, and the orientation of the drawing is changed for convenience, but the right end direction corresponds to the upper end (or lower end) of the lower transparent glass substrate SUB1.
[0091]
TSTd is an inspection terminal, to which no external circuit is connected, but is wider than the wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal DTM is also wider than the wiring portion so that it can be connected to an external circuit. A plurality of inspection terminals TSTd and external connection terminals DTM are alternately arranged in a staggered manner in the vertical direction, and the inspection terminals TSTd terminate without reaching the end of the lower transparent glass substrate SUB1, as shown in the figure. As shown in FIG. 14, the drain terminal DTM constitutes a terminal group Td (subscript omitted), is further extended beyond the cutting line CT1 of the lower transparent glass substrate SUB1, and all of them are used for preventing electrostatic breakdown during the manufacturing process. Are short-circuited to each other by the wiring SHd. A drain connection terminal is connected to the opposite side across the matrix of video signal lines DL where the inspection terminals TSTd exist, and conversely, an inspection terminal is connected to the opposite side across the matrix of video signal lines DL where the drain terminals DTM exist. Is done.
[0092]
The drain terminal DTM is formed of two layers of the chromium Cr layer g1 and the ITO layer d1 for the same reason as the gate terminal GTM described above, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed. The semiconductor layer AS formed on the end portion of the gate insulating film GI is used for etching the video signal in a tapered shape at the edge of the gate insulating film GI. Of course, the protective film PSV1 is removed on the drain terminal DTM in order to connect to an external circuit. AO is the anodic oxidation mask described above, and the left side of the boundary line is covered with the mask. However, since the layer g2 does not exist in the portion not covered in this figure, this pattern is not directly related.
[0093]
As shown in FIG. 20C, the lead-out wiring from the matrix portion to the drain terminal DTM portion has the same level as that of the video signal line DL immediately above the layers d1 and g1 at the same level as the drain terminal DTM portion. The layers d2 and d3 are laminated to the middle of the seal pattern SL, but this can minimize the probability of disconnection, and the aluminum Al layer d3 that is susceptible to electrolytic corrosion can be formed with the protective film PSV1 or the seal pattern SL. It is only an aim to protect.
[0094]
<< Structure of Retention Capacitance Element Cadd >>
The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. As is apparent from FIGS. 13 and 17, this superposition is performed by a storage capacitor element (capacitance element) in which the transparent pixel electrode ITO1 is one electrode PL2 and the adjacent scanning signal line GL is the other electrode PL1. Configure Cadd. The dielectric film of the storage capacitor element Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.
[0095]
As is apparent from FIG. 24, the storage capacitor element Cadd is formed in a portion where the width of the second conductive film g2 of the scanning signal line GL is increased. Note that the portion of the second conductive film g2 that intersects the video signal line DL is thinned in order to reduce the probability of the video signal line DL and its short circuit.
[0096]
In the step portion of the electrode PL1 of the storage capacitor element Cadd, even if the transparent pixel electrode ITO1 is disconnected, the island region configured by the second conductive film d2 and the third conductive film d3 formed so as to straddle the step. The failure is compensated by.
[0097]
<< Equivalent circuit for the entire display device >>
FIG. 30 is a connection diagram of an equivalent circuit of the display matrix section and its peripheral circuits. Although this figure is a circuit diagram, it is drawn corresponding to the actual geometric arrangement. AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.
[0098]
In the figure, X means a video signal line DL, and subscripts G, B, and R are added corresponding to green, blue, and red pixels, respectively. Y means the scanning signal line GL, and subscripts 1, 2, 3,..., End are added according to the order of scanning timing.
[0099]
The video signal line X (subscript omitted) is connected to the upper video signal drive circuit He. That is, as with the scanning signal line Y, the video signal line X has a terminal drawn only on one side of the video signal panel PNL. The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.
[0100]
SUP is a power supply circuit for dividing a single voltage source into a plurality of voltage sources and a CRT (cathode ray tube) information from a host (high-order processing unit) to obtain information for a TFT liquid crystal display device. This is a circuit including a circuit to be replaced.
[0101]
<< Equivalent Circuit and Operation of Retention Capacitance Element Cadd >>
FIG. 31 is an equivalent circuit diagram of the pixel shown in FIG. In FIG. 31, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The dielectric films of the parasitic capacitance element Cgs are the insulating film GI and the anodic oxide film AOF. Cpix is a liquid crystal capacitance formed between the transparent pixel electrode ITO1 (PIX) and the common transparent pixel electrode ITO2 (COM). The dielectric films of the liquid crystal capacitor Cpix are the liquid crystal LC, the protective film PSV1, and the alignment films ORI1 and ORI2. V1c is a midpoint potential.
[0102]
The capacitance of the storage capacitor element Cadd (retention capacitor Cadd) serves to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) V1c when the thin film transistor TFT is switched. This situation is expressed by the following equation.
[0103]
ΔV1c = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg
Here, ΔV1c represents a change in the midpoint potential due to ΔVg. The change ΔV1c causes a direct current component applied to the liquid crystal LC, but the value can be reduced as the storage capacitor Cadd is increased. In addition, the storage capacitor element Cadd also has an action of extending the discharge time, and accumulates video information after the thin film transistor TFT is turned off. Reduction of the direct current component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce the so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.
[0104]
As described above, since the gate electrode GT is enlarged so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, so that the parasitic capacitance Cgs is increased. The potential V1c has the adverse effect of being easily affected by the gate (scanning) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor element Cadd.
[0105]
The storage capacitor Cadd of the storage capacitor element Cadd is 4 to 8 times the liquid crystal capacitor Cpix (4 · Cpix <Cadd <8 · Cpix) and 8 to 32 times (8 · 32 times) the parasitic capacitance Cgs from the pixel writing characteristics. A value of about Cgs <Cadd <32 · Cgs) is set.
[0106]
<< Connection Method of Retention Capacitance Element Cadd Electrode Line >>
First-stage scanning signal line GL (Y used only as a storage capacitor electrode line₀) Is set to the same potential as the common transparent pixel electrode ITO2 (Vcom), as shown in FIG. In the example shown in FIG. 19, the first-stage scanning signal line is short-circuited to the common electrode COM through the terminal GTO, the lead-out line INT, the terminal DT0, and the external wiring. Alternatively, the first stage storage capacitor electrode line Y₀Is connected to the scanning signal line Yend at the final stage, connected to a DC potential point (AC grounding point) other than Vcom, or one extra scanning pulse Y from the vertical scanning circuit V₀You may connect to receive.
[0107]
<Connection structure with external circuit>
As shown in FIG. 22, the tape carrier package TCP is a flexible wiring board (commonly referred to as TAB; Tape, Automated Bonding) in which an integrated circuit chip CHI constituting the scanning signal driving circuit V and the video signal driving circuits He, Ho is formed. FIG. 20 shows a state in which this is connected to the video signal circuit terminal DTM of the video signal panel PNL. The liquid crystal panel driving integrated circuit (liquid crystal driver) constituting the video signal driving circuit He and the vertical scanning circuit V uses the MOS transistor manufactured by the manufacturing method of the present invention described above.
[0108]
TB is an input terminal / wiring portion of the integrated circuit CHI, TM is an output terminal / wiring portion of the integrated circuit CHI, and a bonding pad PAD of the integrated circuit CHI is a so-called face at each inner tip (commonly referred to as inner lead). Connected by down bonding method. The outer tips (commonly referred to as outer leads) of the terminals TB and TM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively, and are soldered to the CRT / TFT conversion circuit / power supply circuit SUP by an anisotropic conductive film ACF. The connection terminal DTM on the liquid crystal panel PNL side is connected to the liquid crystal panel so as to cover the protective film PSV1 exposed. Accordingly, since the external connection terminal DTM (GTM) is covered with at least one of the protective film PSV1 and the tape carrier package TCP, it is strong against electric corrosion.
[0109]
BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking the solder so that it does not stick to an extra portion during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is protected by an epoxy resin EPX or the like after cleaning, and a silicone resin SIL is further filled between the tape carrier package TCP and the upper transparent glass substrate SUB2 to multiplex the protection. Yes.
[0110]
"Production method"
Next, a manufacturing method on the lower transparent glass substrate SUB1 side of the liquid crystal display device described above will be described with reference to FIGS. In each figure, the central letter is an abbreviation of the process name, the left side shows the pixel portion shown in FIG. 14, and the right side shows the processing flow as seen in the cross-sectional shape near the gate terminal shown in FIG. In addition, except for the step D, the steps A to I are divided according to each photographic processing, and any cross-sectional view of each step shows a stage where the processing after the photographic processing is finished and the photoresist is removed. Yes. Note that the photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask and development thereof, and repeated description is avoided. Hereinafter, it demonstrates according to the divided process.
[0111]
Process A (FIG. 32)
After the silicon oxide film SIO is provided on both surfaces of the lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dipping, baking is performed at 500 ° C. for 60 minutes. A first conductive film g1 made of chromium Cr having a thickness of 1100 mm is provided on the lower transparent glass substrate SUB1 by sputtering, and after the photographic processing, the first conductive film g1 is selectively used with a second cerium ammonium nitrate solution as an etching solution. The gate terminal GTM, the drain terminal DTM, the anodized bus line SHg connecting the gate terminal GTM, the bus line SHd short-circuiting the drain terminal DTM, and the anodized pad connected to the anodized bus line SHg (not shown) ).
Process B (FIG. 32)
A second conductive film g2 made of Al—Pd, Al—Si, Al—Si—Ta, Al—Si—Cu, or the like having a thickness of 2800 mm is provided by sputtering. After the photographic processing, the second conductive film g2 is etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.
[0112]
Process C (FIG. 32)
After photographic processing (after the formation of the anodic oxidation mask AO described above), a solution in which 3% tartaric acid was adjusted to pH 6.25 ± 0.05 with ammonia was diluted 1: 9 with an ethylene glycol liquid into an anodic oxidation liquid. The lower transparent glass substrate SUB1 is immersed, and the formation current density is 0.5 mA / cm.²Adjust (constant current formation). Next, predetermined Al₂O_ThreeAnodization is performed until the formation voltage of 125 V necessary to obtain the film thickness is reached. Then, it is desirable to hold for several tens of minutes in this state (constant voltage formation). This is a uniform Al₂O_ThreeIt is important for obtaining a film. Thereby, the conductive film g2 is anodized, and an anodic oxide film AOF having a thickness of 1800 mm is formed on the scanning signal line GL, the gate electrode GT, and the electrode PL1.
[0113]
Process D (FIG. 33)
Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a silicon nitride film having a thickness of 2000 mm, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to form an i-type amorphous film having a thickness of 2000 mm. After providing the Si film, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form an N (+) type amorphous Si film having a thickness of 300 mm.
[0114]
Process E (FIG. 33)
After photo processing, SF as dry etching gas₆, CCl_FourIs used to selectively etch the N (+) type amorphous Si film and the i type amorphous Si film, thereby forming an island of the i type semiconductor layer AS.
[0115]
Process F (FIG. 33)
After photo processing, SF as dry etching gas₆Is used to selectively etch the Si nitride film.
[0116]
Process G (FIG. 34)
A first conductive film d1 made of an ITO film having a thickness of 1400 mm is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, thereby forming the gate terminal GTM, the uppermost layer of the drain terminal DTM, and the transparent pixel electrode ITO1.
[0117]
Process H (FIG. 34)
A second conductive film d2 made of chromium Cr with a thickness of 600 mm is provided by sputtering, and a third conductive film made of Al-Pd, Al-Si, Al-Si-Ti, Al-Si-Cu, etc. with a thickness of 4000 mm. The film d3 is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as in the process B, and the second conductive film d2 is etched with the same liquid as in the process A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. To do. Next, in the dry etching apparatus, CCl_Four, SF₆Then, the N (+) type amorphous Si film is etched to selectively remove the N (+) type semiconductor layer d0 between the source and drain.
[0118]
Step I (FIG. 34)
Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a 1 μm-thick Si nitride film. After photo processing, SF as dry etching gas₆The protective film PSV1 is formed by selectively etching the Si nitride film by a photo-etching technique (photolithographic technique) using the above.
[0119]
An alignment film is formed on the innermost surface of the lower transparent glass substrate SUB1 manufactured in this way, and the upper transparent glass substrate SUB2 produced in a separate manufacturing process is bonded, and the liquid crystal LC is sandwiched between the bonding gaps. A liquid crystal panel PNL is obtained by sealing with a sealing material and attaching polarizing plates (POL1, 2) on both sides.
[0120]
This liquid crystal panel PNL is laminated together with a backlight, other optical films, etc., and various drive circuit boards are incorporated to be integrated into a liquid crystal display device (liquid crystal display module).
[0121]
FIG. 35 is a plan view showing a state in which the liquid crystal panel and the drive circuit board are connected. CHI is an integrated circuit (IC) chip for driving the liquid crystal panel PNL (the lower five are ICs on the vertical scanning circuit side, and the ten on the left are ICs on the video signal drive circuit side. The number depends on the resolution of the liquid crystal panel, and the higher the resolution, the greater the number required.
[0122]
As shown in FIGS. 22 and 23, TCP is a tape carrier package (TCP) in which an IC chip CHI of a drive circuit is mounted by a tape automated bonding (TAB) method, and PCB 1 is mounted with the above TCP, a capacitor, and the like. The driving circuit board is divided into two for the video signal driving circuit and for the scanning signal driving circuit.
[0123]
FGP is a frame ground pad, and a spring-shaped piece cut into the shield case SHD is soldered. FC is a flat cable that electrically connects the lower drive circuit board PCB1 and the left drive circuit board PCB1.
[0124]
As shown in the figure, the flat cable FC uses a plurality of lead wires (phosphor bronze material plated with Sn plating) sandwiched between a striped polyethylene layer and a polyvinyl alcohol layer. To do.
[0125]
<< TCP connection structure >>
FIG. 22 is a cross-sectional view of a tape carrier package in which an integrated circuit chip CHI constituting the scanning signal driving circuit V and the video signal driving circuit H is mounted on a flexible wiring board, and FIG. It is principal part sectional drawing which shows the state connected to the terminal GTM for scanning signal circuits.
[0126]
TTB is an input terminal / wiring part of the integrated circuit chip CHI, and TTM is an output terminal / wiring part of the integrated circuit chip CHI, which is made of, for example, Cu, and an integrated circuit is provided at each inner tip (inner lead). As described above, the bonding pads PAD of the chip CHI are connected by the so-called face-down bonding method.
[0127]
Further, the outer end portions (outer leads) of the terminals TTB and TTM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively, and an anisotropic conductive film is connected to the CRT / TFT conversion circuit / power supply circuit SUP by soldering or the like. As described above, the ACF is connected to the liquid crystal panel PNL.
[0128]
The package TCP is connected to the liquid crystal panel PNL so that the tip thereof covers the protective film PSV1 exposing the connection terminal GTM on the liquid crystal panel PNL side. Accordingly, the outer connection terminal GTM (DTM) is strong against electric corrosion because the protective film PSV1 is covered with at least one of the packages TCP.
[0129]
As described above, BF1 is a base film made of a resin such as polyimide, and SRS is a solder resist film for masking the solder so that it does not adhere to extra portions during soldering. The gap between the upper and lower transparent glass substrates outside the seal pattern SL is protected with an epoxy resin EPX after cleaning, and the protection between the package TCP and the upper transparent glass substrate SUB2 is further filled with a silicon resin SIL to multiplex the protection. ing.
[0130]
<< Drive circuit board PCB2 >>
Electronic components such as an IC, a capacitor, and a resistor are mounted on the drive circuit board PCB2. As described above, the drive circuit board PCB2 includes a power supply circuit for obtaining a plurality of voltage sources stabilized by dividing from one voltage source, and information for a CRT from a host as information for a liquid crystal display device. A circuit SUP including a circuit to be converted is mounted. CJ is a connector connection portion for a connector (not shown) connected to the outside.
[0131]
The drive circuit board PCB1 and the drive circuit board PCB2 are electrically connected by a joiner JN such as a flat cable FC.
[0132]
FIG. 36 is an external view of a notebook personal computer which is an example of an electronic apparatus in which the liquid crystal display device according to the present invention is mounted.
[0133]
This notebook personal computer has a keyboard part and a display part connected by a hinge, a host computer comprising a CPU or the like is mounted on the keyboard part, and the liquid crystal display device according to the present invention is a liquid crystal display module on the display part. (MDL).
[0134]
Around the liquid crystal panel PNL constituting the liquid crystal display module, drive circuit boards PCB1, PCB2, and PCB3, an inverter power supply IV for backlight, and the like are mounted. CT is a connector connected to the host side, and TCON is a control circuit that generates signal processing, timing signals, and the like for displaying an image on the liquid crystal panel PNL based on a display signal input from the host side.
[0135]
It goes without saying that the liquid crystal display device according to the present invention can be used not only for portable computers such as notebook computers as shown in FIG. 36, but also for stationary personal computers such as desktop monitors and other display devices.
[0136]
Note that the present invention is not limited to the above-described type in which a driver is mounted on the TCP, but can be similarly applied to a method in which a transistor is directly formed around an insulating substrate (glass substrate) constituting a liquid crystal panel. Further, the present invention is not limited to a vertical electric field type active matrix liquid crystal display device, and similarly applied to a horizontal electric field type active matrix liquid crystal display device or a simple matrix type liquid crystal display device. it can.
[0137]
【The invention's effect】
As described above, according to the present invention, a conventional photomask for each ion implantation layer has been facilitated. On the other hand, the difference in the thickness of the through oxide film for ion implantation and the manufacturing process of the MOS transistor By changing the order, the impurity regions having different concentrations can be formed by one ion implantation, the number of photomasks can be reduced, and the number of processes can be greatly reduced.
[Brief description of the drawings]
FIG. 1 is a schematic diagram for explaining the principle of ion implantation in a method for producing a MOS transistor of the present invention.
FIG. 2 is a process diagram schematically showing one embodiment of a method of manufacturing a MOS transistor according to the present invention.
FIG. 3 is a process diagram subsequent to FIG. 2, schematically showing one embodiment of a method of manufacturing a MOS transistor according to the present invention.
FIG. 4 is a process diagram illustrating an embodiment in which the present invention is applied to a manufacturing process of a driver of a liquid crystal panel.
FIG. 5 is a process drawing subsequent to FIG. 4 for explaining an embodiment in which the present invention is applied to a manufacturing process of a driver of a liquid crystal panel.
6 is a process drawing subsequent to FIG. 5 for explaining an embodiment in which the present invention is applied to a manufacturing process of a driver of a liquid crystal panel. FIG.
FIG. 7 is a process drawing subsequent to FIG. 6 for explaining an embodiment in which the present invention is applied to a manufacturing process of a driver of a liquid crystal panel.
FIG. 8 is a process chart schematically showing another embodiment of the MOS transistor manufacturing method according to the present invention.
FIG. 9 is a process diagram following FIG. 8 schematically showing another embodiment of the method for manufacturing a MOS transistor according to the present invention.
FIG. 10 is a schematic structural diagram of a planar type MOS transistor to which the present invention can be applied.
FIG. 11 is a schematic structural diagram of a LOCOS offset MOS transistor to which the present invention can be applied.
FIG. 12 is a schematic structural diagram of a LOCOS offset MOS transistor to which the present invention is applied.
FIG. 13 is a plan view showing a light shielding region of a pixel and a black matrix BM and a periphery thereof constituting a vertical electric field type active matrix color liquid crystal display device according to the present invention.
14 is a cross-sectional view showing one pixel and its periphery along a section line 3-3 in FIG.
15 is a cross-sectional view of the additional capacitance element Cadd taken along the line 4-4 in FIG.
16 is a plan view of a main part of a liquid crystal display unit in which a plurality of the pixels of FIG. 8 are arranged.
FIG. 17 is a plan view for explaining the configuration of the periphery of the matrix of the display panel.
FIG. 18 is a plan view illustrating the peripheral portion of FIG. 12 slightly exaggerated and more specifically.
FIG. 19 is an enlarged plan view of a corner portion of a liquid crystal panel including electrical connection portions of upper and lower transparent glass substrates.
FIG. 20 is a cross-sectional view showing the vicinity of a corner of a liquid crystal panel and the vicinity of a video signal terminal on both sides with the pixel portion of the matrix at the center.
FIG. 21 is a cross-sectional view showing an edge portion of a liquid crystal panel without a scanning signal terminal on the left side and an external connection terminal on the right side.
FIG. 22 is a cross-sectional view showing a structure of a tape carrier package in which an integrated circuit chip constituting a drive circuit is mounted on a flexible wiring board.
FIG. 23 is a cross-sectional view of the principal part showing a state in which the tape carrier package is connected to the video signal circuit terminals of the liquid crystal panel.
24 is a plan view illustrating only a conductive layer g2 and an i-type semiconductor layer AS of the pixel illustrated in FIG. 8;
25 is a plan view illustrating only conductive layers d1, d2, and d3 of the pixel shown in FIG.
26 is a plan view illustrating only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel illustrated in FIG. 8;
27 is a plan view of relevant parts depicting only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel array shown in FIG. 11. FIG.
FIG. 28 is an explanatory diagram in the vicinity of a connection portion between a gate terminal and a gate wiring;
FIG. 29 is an explanatory diagram in the vicinity of a connection portion between a drain terminal and a video signal line.
FIG. 30 is an equivalent circuit diagram showing a liquid crystal display section of an active matrix type color liquid crystal display device.
31 is an equivalent circuit diagram of the pixel shown in FIG.
FIG. 32 is an explanatory diagram of a manufacturing process on the lower transparent glass substrate side.
FIG. 33 is an explanatory diagram following FIG. 32 of the manufacturing process on the lower transparent glass substrate side.
34 is an explanatory diagram of the manufacturing process on the lower transparent glass substrate side, following FIG. 33. FIG.
FIG. 35 is a plan view showing a state in which the liquid crystal panel and the drive circuit board are connected to each other.
FIG. 36 is an external view of a notebook computer for explaining an example of an electronic device on which the liquid crystal display device of the present invention is mounted.
FIG. 37 is a process diagram illustrating an example of a conventional impurity region formation process.
FIG. 38 is a process diagram illustrating another example of a conventional impurity region formation process.
FIG. 39 is a schematic process diagram illustrating the manufacturing process of the driver of the active matrix type liquid crystal panel having the high breakdown voltage MOS transistor.
FIG. 40 is a schematic process diagram following FIG. 39 for explaining the manufacturing process of the driver of the active matrix liquid crystal panel having the high voltage MOS transistor.
[Explanation of symbols]
HNW High-voltage PMOS transistor well
HPW High voltage NMOS transistor well
NW Well of low voltage PMOS transistor
PW Low breakdown voltage NMOS transistor well
HNM High-voltage NMOS transistor drain / source field relaxation layer
HPM High-voltage PMOS transistor drain / source field relaxation layer
NF Channel stopper for field region of well of high breakdown voltage NMOS transistor and well of low breakdown voltage NMOS transistor
PF A channel stopper for the field region of the well of the high breakdown voltage PMOS transistor and the well of the low breakdown voltage PMOS transistor.

Claims (2)

In a method of manufacturing a MOS transistor in which a high voltage MOS transistor used at a high voltage and a low voltage MOS transistor used at a low voltage are mixed on the same semiconductor substrate,
First, the well of a high voltage MOS transistor with a low impurity concentration is formed,
Next, a thick field oxide film that electrically isolates the MOS transistors is formed,
In a single ion implantation process for a well of a low breakdown voltage MOS transistor, a channel stopper for a parasitic MOS transistor is simultaneously formed under the electric field relaxation layer of the drain / source portion of the high breakdown voltage MOS transistor and the thick field oxide film,
A method of manufacturing a MOS transistor, wherein the electric field relaxation layer has a low impurity concentration, and the channel stopper has a high impurity concentration. In a method of manufacturing a MOS transistor in which a high voltage MOS transistor used at a high voltage and a low voltage MOS transistor used at a low voltage are mixed on the same semiconductor substrate,
First, the well of a high voltage MOS transistor with a low impurity concentration is formed,
Next, a thick field oxide film that electrically isolates the MOS transistors is formed,
In the step of ion implantation for the well of the low breakdown voltage PMOS transistor, a channel stopper for the parasitic MOS transistor of the high breakdown voltage PMOS transistor is simultaneously formed under the electric field relaxation layer of the drain / source portion of the high breakdown voltage NMOS transistor and the thick field oxide film. And
In the well ion implantation step of the low voltage NMOS transistor, the high耐庄P MOS field relaxation layer of the drain-source section of the transistors and the channel stopper for the parasitic MOS transistor of the high voltage N MOS transistors under the thick field oxide film Forming at the same time,
A method of manufacturing a MOS transistor, wherein the electric field relaxation layer has a low impurity concentration, and the channel stopper has a high impurity concentration.

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