JP4671715B2 - Display device and driving method thereof - Google Patents

Description

  The present invention relates to a voltage control type active matrix display device such as a liquid crystal display device using a switching element such as a thin film transistor, and a driving method thereof.

In an impulse-type display device such as a CRT (Cathode Ray Tube), focusing on individual pixels, a lighting period in which an image is displayed and a light-off period in which no image is displayed are alternately repeated. For example, even when a moving image is displayed, since an extinguishing period is inserted when an image for one screen is rewritten, an afterimage of an object moving in human vision does not occur. For this reason, the background and the object are clearly distinguished, and the moving image is visually recognized without a sense of incongruity. On the other hand, in an active matrix type display device of a voltage control system such as a liquid crystal display device using a thin film transistor (TFT), the luminance of each pixel is determined by the voltage held in each pixel capacitor. The holding voltage in the capacitor is maintained for one frame period when it is rewritten once. As a result, when a moving image is displayed on a voltage-controlled active matrix display device, an afterimage of a moving object is generated in human vision. Specifically, the outline of the moving object is visually recognized in a blurred state. Such a phenomenon is called “motion blur” or the like, and is considered to be caused by the followability of human eyes. In the active matrix type display device of the voltage control type, such a motion blur occurs when displaying a moving image. Therefore, an impulse type display device is conventionally used for a display such as a television mainly displaying a moving image. It is common. However, in recent years, there has been a strong demand for weight reduction and thinning of displays such as televisions, and voltage controlled active matrix display devices such as liquid crystal display devices that can be easily reduced in weight and thickness for such displays. Adoption is progressing rapidly.
JP 2003-22061 A JP 2002-23707 A JP 2001-290122 A Japanese Patent Laid-Open No. 5-203994

  As a method of improving blur due to line-of-sight tracking in an active matrix type display device of voltage control type, a method of (quasi) impulse-displaying a display in a liquid crystal display device by performing black display in one frame or the like, A method is known in which a period is divided into a plurality of subframe periods, and the display luminance is made different between the subframe periods so as to approach an impulse-type display (for example, Patent Document 1).

  As shown in FIG. 2, the display unit of the active matrix liquid crystal display device includes a plurality (N) of scanning signal lines GL (1) to GL (N) and a plurality ( A plurality of (N × M) video signal lines SL (1) to SL (M) and a plurality (N × M) arranged in a matrix corresponding to the intersections of the plurality of scanning signal lines and the plurality of video signal lines. Pixel forming portions P (1,1) to P (N, M), and each pixel forming portion has a liquid crystal capacitance (“pixel capacitance” formed by a pixel electrode Epix and an electrode facing the pixel electrode Epix. It is also called Ccl). As shown in FIGS. 2 and 3, each pixel electrode Epix is provided with two video signal lines SL (m) and SL (m + 1) so as to sandwich them, and these two video signals are arranged. Parasitic capacitance exists between each of the lines and the pixel electrode Epix. One of these two video signal lines SL (m) is connected to the pixel electrode Epix via the TFT 10. Hereinafter, a parasitic capacitance formed between the video signal line (hereinafter referred to as “own source line”) SL (m) and the pixel electrode Epix is indicated by a reference symbol “Csda”, and these two video signals are displayed. A parasitic capacitance formed between the other video signal line (hereinafter referred to as “other source line”) SL (m + 1) of the lines and the pixel electrode Epix is denoted by a reference sign “Csdb”. In this liquid crystal display device, the auxiliary capacitance line CsL is formed in parallel with each scanning signal line GL (n). In each pixel formation portion P (n, m), the pixel electrode Epix and the auxiliary capacitance line CsL A storage capacitor Ccs is formed in between.

  In the active matrix type liquid crystal display device as described above, when the TFT 10 connected to the pixel electrode Epix is in an on state (conductive state) in each pixel formation portion P (n, m), the self source line SL (m) When a voltage is applied from the TFT 10 through the TFT 10 and the TFT 10 is turned off (cut off), the applied voltage is held in the pixel capacitor Ccl (and the auxiliary capacitor Ccs) until the TFT 10 is turned on next time. Pixels are displayed according to the voltage (n = 1, 2,..., N; m = 1, 2,..., M). However, the pixel electrode Epix that forms the pixel capacitor Ccl is connected to the source line SL (m) through the parasitic capacitor Csda and to the other source line SL (m + 1) through the parasitic capacitor Csdb. Yes. Therefore, while the TFT 10 connected to the pixel electrode Epix is in the cut-off state, the potential of the pixel electrode Epix (the retention voltage of the pixel capacitor) changes in the potential of the self source line SL (m) via the parasitic capacitance Csda. As well as the potential change of the other source line SL (m + 1) via the parasitic capacitance Csdb. In this manner, the potential of the pixel electrode Epix and the holding voltage in the pixel capacitor Ccl are affected by the potential of the video signal lines SL (m) and SL (m + 1), so that the amount of transmitted light of the liquid crystal varies and a desired gradation is obtained. A phenomenon (called “crosstalk”) occurs that cannot be obtained. In a liquid crystal display device that displays a color image, three pixel forming units for forming R (red), G (green), and B (blue) pixels as display units of the color image are adjacent to each other. A phenomenon in which a desired color cannot be displayed when the influence (degree or direction) of the potential of the pixel electrode due to crosstalk differs among the three pixel formation portions corresponding to each display unit. (Referred to as “color crosstalk”).

  On the other hand, as described in Patent Document 4, even if the parasitic capacitance is reduced at the design stage, the amount of crosstalk can only be reduced, and color crosstalk cannot be completely eliminated. In addition, it is conceivable to compensate for crosstalk by newly providing a shield electrode or wiring. However, when such a means is used, a new component is added to the display device. This increases the manufacturing cost of the device. Further, as described in Patent Document 3, the voltage applied to each pixel is a column to which the active element of the pixel is connected during the period from the selection of the active element of the pixel to the next selection. In the case of adopting a liquid crystal display element driving method characterized in that correction is performed based on the voltage to be applied to the electrodes, in order to perform such correction, the circuit configuration becomes complicated and the cost increases accordingly. . In this driving method, the influence on the pixel electrode potential due to the potential change of the other source line is not taken into consideration.

  Therefore, the present invention is a voltage control capable of preventing image quality degradation due to crosstalk caused by parasitic capacitance between a pixel electrode and a video signal line with a simple configuration while suppressing motion blur when displaying a moving image. An object of the present invention is to provide an active matrix display device of the type.

According to a first aspect of the present invention, a plurality of video signal lines for transmitting a plurality of video signals based on an image to be displayed, a plurality of scanning signal lines intersecting the plurality of video signal lines, and the plurality of video signal lines And a plurality of pixel forming portions arranged in a matrix corresponding to intersections of the plurality of scanning signal lines and a drive control circuit for driving the plurality of video signal lines and the plurality of scanning signal lines A subframe in which a frame period that is a period during which an image for one screen is displayed is a subframe period in which a relatively low brightness is displayed and a dark display period in which a relatively low brightness is displayed. A display device that divides into a plurality of subframe periods including a bright display period, which is a period, and displays luminance determined based on the gradation of the image for one screen in each of the plurality of subframe periods There,
Each pixel forming part
A switching element that is turned on or off according to a signal applied to a scanning signal line passing through a corresponding intersection;
A pixel electrode connected via the switching element to a video signal line passing through a corresponding intersection;
A common electrode provided in common to the plurality of pixel formation portions;
A pixel capacitance formed by the pixel electrode and the common electrode;
An electro-optic element that displays a pixel according to a voltage held in the pixel capacitor,
The drive control circuit causes a parasitic capacitance to be formed between the pixel signal and a video signal to be applied to a first video signal line connected to the pixel electrode of each pixel formation portion via a switching element. A signal that is corrected based on information indicating the potential of the second video signal line so that the variation in the holding voltage in the pixel capacitance of the pixel formation portion due to the potential change of the second video signal line arranged in the pixel is compensated Including correction means,
The signal correction means includes
A correction table that stores a correction amount of a video signal to be applied to the first video signal line in association with information indicating a potential of the second video signal line when the switching element is in the conductive state; Table storage means for holding each of the plurality of subframes and voltage polarity combinations;
From a correction table held in the table storage means, a subframe period including a time point when the video signal is applied to the first video signal line and a voltage polarity of the video signal with reference to the potential of the common electrode. By selecting a correction table for the combination and referring to the selected correction table, it corresponds to information indicating the potential of the second video signal line when the switching element changes from the conductive state to the cut-off state. Correction amount determining means for determining the correction amount to be performed.

According to a second invention, in the first invention,
The drive control circuit generates the plurality of video signals so that the voltages of the plurality of video signals are substantially alternating within each subframe period with reference to the potential of the common electrode. Applied to
The signal correction unit is configured to output a video signal to be applied to the first video signal line when the switching element is in a conductive state, at the time when the switching element changes from the conductive state to the cutoff state. The correction is based on information indicating the potential of the video signal line.

According to a third invention, in the second invention,
The signal correction means is configured to output a video signal to be applied to the first video signal line when the switching element is in a conductive state, at the time when the switching element changes from the conductive state to the cutoff state. The correction is based on information indicating the potential of the second video signal line.

According to a fourth invention, in the first invention,
Each correction table held in the table storage unit associates the correction amount with a combination of information indicating the potential of the first video signal line and information indicating the potential of the second video signal line. It is characterized by being stored.

According to a fifth invention, in the first invention,
The drive control circuit generates the plurality of video signals so that a voltage polarity based on the potential of the common electrode is different between adjacent video signal lines, and applies the generated video signals to the plurality of video signal lines,
Each correction table stored in the table storage means stores the correction amount in association with information indicating a potential difference between the potential of the first video signal line and the potential of the second video signal line. It is characterized by.

A sixth invention is the second invention, wherein:
The signal correction means corrects the voltage of the video signal to be applied to the first video signal line when the switching element is in the conductive state based on a correction amount ΔV1b defined by the following equation. To:
ΔV1b = (V2−Vcom) ・ Csdb / Cpix
Here, V2 represents the potential of the second video signal line when the switching element changes from the conduction state to the cutoff state, Vcom represents the potential of the common electrode, and Csdb represents the pixel electrode and the pixel electrode. The value of the parasitic capacitance formed between the second video signal line and Cpix represents the value of the total capacitance formed between the pixel electrode and another electrode.

A seventh invention is the sixth invention, wherein
The signal correction means corrects the voltage of the video signal to be applied to the first video signal line when the switching element is in the conductive state based on a correction amount ΔV1 defined by the following equation. To:
ΔV1 = (V1−Vcom) · Csda / Cpix + (V2−Vcom) · Csdb / Cpix
Here, V1 and V2 represent the potentials of the first and second video signal lines when the switching element changes from the conductive state to the cut-off state, respectively, Vcom represents the potential of the common electrode, and Csda Represents the value of the parasitic capacitance formed between the pixel electrode and the first video signal line, and Csdb represents the value of the parasitic capacitance formed between the pixel electrode and the second video signal line. Cpix represents the value of the total capacitance formed between the pixel electrode and the other electrode.

According to an eighth aspect of the present invention, a plurality of video signal lines for transmitting a plurality of video signals based on an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signal lines And a plurality of pixel forming portions arranged in a matrix corresponding to intersections of the plurality of scanning signal lines and a drive control circuit for driving the plurality of video signal lines and the plurality of scanning signal lines A subframe in which a frame period that is a period during which an image for one screen is displayed is a subframe period in which a relatively low brightness is displayed and a dark display period in which a relatively low brightness is displayed. A display device that divides into a plurality of subframe periods including a bright display period, which is a period, and displays luminance determined based on the gradation of the image for one screen in each of the plurality of subframe periods There,
Each pixel forming part
A switching element that is turned on or off according to a signal applied to a scanning signal line passing through a corresponding intersection;
A pixel electrode connected via the switching element to a video signal line passing through a corresponding intersection;
A common electrode provided in common to the plurality of pixel formation portions;
A pixel capacitance formed by the pixel electrode and the common electrode;
An electro-optic element that displays a pixel according to a voltage held in the pixel capacitor,
The drive control circuit causes a parasitic capacitance to be formed between the pixel signal and a video signal to be applied to a first video signal line connected to the pixel electrode of each pixel formation portion via a switching element. A signal that is corrected based on information indicating the potential of the second video signal line so that the variation in the holding voltage in the pixel capacitance of the pixel formation portion due to the potential change of the second video signal line arranged in the pixel is compensated Including correction means,
The signal correcting unit corrects a video signal to be applied to the first video signal line only in the bright display period when the switching element is in the conductive state.

According to a ninth aspect of the invention, a plurality of video signal lines for transmitting a plurality of video signals based on an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signal lines And a plurality of pixel forming portions arranged in a matrix corresponding to intersections of the plurality of scanning signal lines and a drive control circuit for driving the plurality of video signal lines and the plurality of scanning signal lines A subframe in which a frame period that is a period during which an image for one screen is displayed is a subframe period in which a relatively low brightness is displayed and a dark display period in which a relatively low brightness is displayed. A display device that divides into a plurality of subframe periods including a bright display period, which is a period, and displays luminance determined based on the gradation of the image for one screen in each of the plurality of subframe periods There,
Each pixel forming part
A switching element that is turned on or off according to a signal applied to a scanning signal line passing through a corresponding intersection;
A pixel electrode connected via the switching element to a video signal line passing through a corresponding intersection;
A common electrode provided in common to the plurality of pixel formation portions;
A pixel capacitance formed by the pixel electrode and the common electrode;
An electro-optic element that displays a pixel according to a voltage held in the pixel capacitor,
The drive control circuit causes a parasitic capacitance to be formed between the pixel signal and a video signal to be applied to a first video signal line connected to the pixel electrode of each pixel formation portion via a switching element. A signal that is corrected based on information indicating the potential of the second video signal line so that the variation in the holding voltage in the pixel capacitance of the pixel formation portion due to the potential change of the second video signal line arranged in the pixel is compensated Including correction means,
The signal correction means is configured to apply a gradation value corresponding to a potential of a video signal to be applied to the first video signal line to the second video signal line when the switching element is in the conductive state. When the gradation value is smaller than the gradation value corresponding to the signal potential, correction of the video signal to be applied to the first video signal line is suppressed when the switching element is in the conductive state.
In a tenth aspect based on the eighth or ninth aspect ,
The drive control circuit generates the plurality of video signals so that the voltages of the plurality of video signals are substantially alternating within each subframe period with reference to the potential of the common electrode. Applied to
The signal correction unit is configured to output a video signal to be applied to the first video signal line when the switching element is in a conductive state, at the time when the switching element changes from the conductive state to the cutoff state. The correction is based on information indicating the potential of the video signal line.
In an eleventh aspect based on the tenth aspect ,
The signal correction means is configured to output a video signal to be applied to the first video signal line when the switching element is in a conductive state, at the time when the switching element changes from the conductive state to the cutoff state. The correction is based on information indicating the potential of the second video signal line.

In a twelfth aspect of the invention, any one of the first to seventh aspects of the invention,
The drive control circuit includes:
A scanning signal line driving circuit for driving the plurality of scanning signal lines;
A video signal line driving circuit for driving the plurality of video signal lines;
A control signal to be supplied to the scanning signal line drive circuit and the video signal line, and a display control circuit for generating an image signal to be supplied to the video signal line drive circuit,
The video signal line driving circuit generates the plurality of video signals based on the image signal supplied from the display control circuit and applies the generated video signals to the plurality of video signal lines,
The signal correction unit is configured to supply the video signal line driving circuit with the image so that the video signal to be applied to the first video signal line is corrected to compensate for the variation in the holding voltage. The signal is corrected.

According to the first aspect of the invention, one frame period is divided into a plurality of subframe periods including a dark display period and a bright display period, and in each of the plurality of subframe periods, the gradation of an image for one screen is obtained. In the display device that displays the luminance determined based on the second video signal line, the video signal to be applied to the first video signal line connected to the pixel electrode of each pixel formation portion via the switching element is Is corrected based on the information indicating the potential of the second video signal line so that the variation in the holding voltage in the pixel capacitance of the pixel formation portion due to the potential change is compensated. As a result, in a voltage-controlled active matrix display device that incorporates an impulse effect for improving moving images, image quality degradation due to crosstalk caused by parasitic capacitance between the pixel electrode and the video signal line can be prevented with a simple configuration. can do.
According to the first aspect of the invention, one frame period is divided into a plurality of subframe periods including a dark display period and a bright display period, and an image floor for one screen in each of the plurality of subframe periods. In the display device that displays the luminance determined based on the key, the correction amount of the video signal to be applied to the first video signal line is the plurality of times when the video signal is applied to the first video signal line. The subframe period is changed depending on which period is within. Thus, in the active matrix display device of the voltage control system incorporating the impulse effect for improving the moving image, when the liquid crystal is used as an electro-optical element for displaying the pixel according to the holding voltage in the pixel capacitor, the pixel capacitor Since the video signal can be corrected in consideration of the voltage dependency of the pixel voltage, the fluctuation of the holding voltage in the pixel capacitance can be more reliably compensated.
According to the first aspect, the correction table for the combination of the subframe period including the application time point of the video signal to the first video signal line and the voltage polarity of the video signal is selected, and the selected correction is performed. By referring to the table, the correction amount of the video signal to be applied to the first video signal line is determined. As a result, in addition to the above effects, the luminance is distributed to the subframe periods TD and TB for each polarity from the viewpoint of DC correction or the like as in the active matrix liquid crystal display device incorporating the impulse effect for improving the moving image. Even if it is changed, the variation of the holding voltage in the pixel capacitance can be compensated more reliably. Since the correction amount is determined based on the reference to the correction table, the processing for obtaining the correction amount is speeded up, and high-definition display can be supported.

  According to the second aspect of the invention, since the voltage of each video signal is substantially alternating within each subframe period with reference to the potential of the common electrode, the potential of each video signal is equal to the potential of the common electrode on average. Can be considered. Therefore, the influence of the potential change of the second video signal line on the holding voltage in the pixel capacitor (the change in the holding voltage due to crosstalk) occurs when the switching element connected to the pixel capacitor changes from the conductive state to the cut-off state. It is determined by the potential of the second video signal line. Therefore, the fluctuation of the holding voltage is compensated by correcting the video signal to be applied to the first video signal line based on the information indicating the potential of the second video signal line at the time. Thereby, it is possible to prevent image quality degradation due to crosstalk caused by parasitic capacitance between the pixel electrode and the video signal line with a simple configuration.

  According to the third aspect, the video signal to be applied to the first video signal line when the switching element of each pixel forming portion is in the conductive state changes from the conductive state to the cutoff state. The correction is based not only on the information indicating the potential of the second video signal line at the time but also on the information indicating the potential of the first video signal line. As a result, the influence of the potential change of the first video signal line on the holding voltage in the pixel capacitance of the pixel formation portion when the switching element is in the cut-off state also affects the video signal to be applied to the first video signal line. It can be suppressed by correction. In addition, since the potential of the first video signal line when the switching element is in a conductive state corresponds to the voltage applied to the pixel capacitor, even if the pixel capacitor depends on the applied voltage, the dependency is reduced. In consideration of this, by correcting the video signal to be applied to the first video signal line, it is possible to more reliably compensate for the variation in the holding voltage.

According to the fourth invention, the correction table stores the correction amount in association with the combination of the information indicating the potential of the first video signal line and the information indicating the potential of the second video signal line. As a result, in the active matrix display device of the voltage control system incorporating the impulse effect for improving the moving image, even when the pixel capacitance has voltage dependency, the video signal can be corrected in consideration of the dependency. Therefore, it is possible to more reliably compensate for the variation in the holding voltage in the pixel capacitance.

According to the fifth aspect , each correction table stores a correction amount in association with information indicating a potential difference between the potential of the first video signal line and the potential of the second video signal line. As a result, the configuration of the correction table is simplified, and the processing for determining the correction amount with reference to the correction table is simplified.

According to the sixth aspect , the potential V2 of the second video signal line, the common electrode potential Vcom, the pixel at the time when the switching element connected to the pixel capacitance of each pixel formation portion changes from the conductive state to the cutoff state. The video to be applied to the first video signal line based on the correction amount defined by the expression expressed by the parasitic capacitance Csdb between the electrode and the second video signal line and the total capacitance Cpix connected to the pixel electrode A correction amount of the signal is determined. Thereby, it is possible to prevent image quality degradation due to crosstalk caused by parasitic capacitance between the pixel electrode and the second video signal line with a simple configuration.

According to the seventh aspect , the potential V1 of the first video signal line and the potential of the second video signal line at the time when the switching element connected to the pixel capacitance of each pixel forming portion changes from the conductive state to the cutoff state. V2, the common electrode potential Vcom, the parasitic capacitance Csda between the pixel electrode and the first video signal line, the parasitic capacitance Csdb between the pixel electrode and the second video signal line, and the total connected to the pixel electrode The correction amount of the video signal to be applied to the first video signal line is determined based on the correction amount defined by the expression expressed by the capacitance Cpix. Accordingly, it is possible to prevent image quality deterioration due to crosstalk caused by parasitic capacitance between the pixel electrode and the first and second video signal lines with a simple configuration.

According to the eighth aspect of the invention, the video signal to be applied to the first video signal line is corrected only during the bright display period in which the influence of the crosstalk on the luminance of the display image is relatively large. As a result, in the active matrix type display device of the voltage control system incorporating the impulse effect for improving the moving image, the image quality is deteriorated due to the crosstalk caused by the parasitic capacitance between the pixel electrode and the video signal line with a simpler configuration. Can be prevented.

According to the ninth aspect , the gradation value corresponding to the potential of the video signal to be applied to the first video signal line when the switching element of each pixel forming portion is in the conductive state is applied to the second video signal line. When the gradation value is smaller than the gradation value corresponding to the potential of the video signal to be applied, the correction of the video signal to be applied to the first video signal line is suppressed, so that the process for determining the correction amount is simple. It becomes. Accordingly, it is possible to prevent image quality deterioration due to crosstalk caused by parasitic capacitance between the pixel electrode and the video signal line with a simpler configuration.

According to the twelfth aspect of the present invention, the first video signal is corrected so that the variation in the holding voltage in the pixel capacitance of each pixel forming unit is compensated by correcting the image signal to be supplied to the video signal line driving circuit. The video signal to be applied to the line is corrected. Thereby, it is possible to prevent image quality degradation due to crosstalk caused by parasitic capacitance between the pixel electrode and the video signal line with a simple configuration.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the display unit is of a vertical alignment method and is configured to be normally black. As a driving method, the applied voltage to the liquid crystal is inverted every frame period and every scanning signal line. In addition, it is assumed that a dot inversion driving method that inverts every video signal line is employed, but the present invention is not limited to this.

<1. Overall Configuration and Operation of Liquid Crystal Display Device>
FIG. 1 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to an embodiment of the present invention. The liquid crystal display device includes a display control circuit 200, a drive control unit including a source driver (video signal line drive circuit) 300, and a gate driver (scanning signal line drive circuit) 400, and a display unit 500. The display unit 500 includes a plurality (M) of video signal lines SL (1) to SL (M), a plurality (N) of scanning signal lines GL (1) to GL (N), and a plurality of these. A plurality of (M × N) pixels provided corresponding to the intersections of the video signal lines SL (1) to SL (M) and the plurality of scanning signal lines GL (1) to GL (N), respectively. The pixel forming portion corresponding to the intersection of the scanning signal line GL (n) and the video signal line SL (m) is indicated by the reference symbol “P (n, m)”. ), As shown in FIG. 2 and FIG. Here, FIG. 2 schematically shows a configuration of the display unit 500 in the present embodiment, and FIG. 3 shows an equivalent circuit of the pixel formation unit P (n, m) in the display unit 500.

  As shown in FIGS. 2 and 3, each pixel forming portion P (n, m) is connected to the scanning signal line SL (n) passing through the corresponding intersection and the video signal passing through the intersection. The TFT 10 which is a switching element having a source terminal connected to the line SL (m), the pixel electrode Epix connected to the drain terminal of the TFT 10, and the plurality of pixel formation portions P (i, j) (i = 1) ˜N, j = 1 to M) and the common electrode Ecom, and the plurality of pixel formation portions P (i, j) (i = 1 to N, j = 1 to M). And a liquid crystal layer as an electro-optic element sandwiched between the pixel electrode Epix and the common electrode Ecom.

  In each pixel formation portion P (n, m), a liquid crystal capacitor (also referred to as “pixel capacitor”) Ccl is formed by the pixel electrode Epix and the common electrode Ecom that faces the pixel electrode Epix across the liquid crystal layer. Each pixel electrode Epix is provided with two video signal lines SL (m) and SL (m + 1) so as to sandwich the pixel electrode Epix, and one of the two video signal lines SL ( The self source line m) is connected to the pixel electrode Epix via the TFT 10. There is a parasitic capacitance Csda between the source line and the pixel electrode Epix, and the other video signal line SL (m + 1) of the two video signal lines is between the other source line and the pixel electrode Epix. A parasitic capacitance Csdb exists. Further, an auxiliary capacitance line CsL is formed in parallel with each scanning signal line GL (n), and in each pixel formation portion P (n, m), an auxiliary capacitance Ccs is provided between the pixel electrode Epix and the auxiliary capacitance line CsL. Is formed. Note that the total capacitance formed between the pixel electrode Epix and the other electrodes in one pixel formation portion P (n, m) (that is, the total capacitance connected to the pixel electrode Epix) is referred to as “pixel total capacitance”. The symbol “Cpix” is used. The capacitance values of these capacitors Ccl, Csda, Csdb, Ccs, and Cpix are also indicated by the same symbols “Ccl”, “Csda”, “Csdb”, “Ccs”, and “Cpix”, respectively.

  The display control circuit 200 receives a data signal DAT and a timing control signal TS sent from the outside, and receives a digital image signal DV, a source start pulse signal SSP for controlling the timing of displaying an image on the display unit 500, and a source clock. A signal SCK, a latch strobe signal LS, a gate start pulse signal GSP, and a gate clock signal GCK are output.

  The source driver 300 receives the digital image signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and each pixel forming unit P (n, In order to charge the pixel capacitor Ccl (and auxiliary capacitor Ccs) of m), a driving video signal is applied to the video signal lines SL (1) to SL (M). At this time, the source driver 300 sequentially holds the digital image signal DV indicating the voltage to be applied to each of the video signal lines SL (1) to SL (M) at the timing when the pulse of the source clock signal SCK is generated. . At the timing when the pulse of the latch strobe signal LS is generated, the held digital image signal DV is converted into an analog voltage, and all the video signal lines SL (1) to SL (M) are simultaneously transmitted as drive video signals. To be applied. That is, in the present embodiment, the line sequential driving method is adopted as the driving method of the video signal lines SL (1) to SL (M). For the source start pulse signal SSP and the source clock signal SCK, all the video signal lines SL within a period corresponding to one half of the conventional one horizontal scanning period in each of the first half and the second half of each frame period. Pulses are generated so that the voltages to be applied to (1) to SL (M) are respectively applied.

  The gate driver 400 applies an active scanning signal to the scanning signal lines GL (1) to GL (N) based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200. In the present embodiment, a gate start pulse signal GSP pulse is generated at the start of each frame period, and the gate start pulse signal is again output when a period corresponding to one half of one frame period has elapsed after the generation. A GSP pulse is generated. As for the gate clock signal GCK, pulses are generated at intervals of a period corresponding to one half of the conventional one horizontal scanning period in both the first half and the second half of each frame period. The scanning signal is supplied to the scanning signal lines GL (1) to GL (N) based on the gate start pulse signal GSP and the gate clock signal GCK as described above, so that one frame period has two subframe periods. It is divided into

  Conventionally, when one frame period is divided into two subframe periods as in the above-described pseudo impulse drive, one of them is not displayed (a black image is inserted) and a non-display period The other is a display period during which image display is performed. On the other hand, in the present embodiment, one frame period is a period during which a relatively dark image is displayed (hereinafter referred to as “dark display period”) and a period during which a relatively bright image is displayed (hereinafter referred to as “bright display”). It is divided into “period”. That is, the first half of each frame period is a dark display period, and the second half is a bright display period.

  As described above, the driving video signal is applied to the video signal lines SL (1) to SL (M) and the scanning signal is applied to the scanning signal lines GL (1) to GL (N). The image is displayed on the display unit 500. The common electrode Ecom and the auxiliary capacitance line CsL are supplied with a predetermined voltage by a power supply circuit (not shown) and are held at the common electrode potential Vcom.

  Here, the difference between the image display state during one frame period in the present embodiment and the image display state during one frame period in the conventional display device will be described with reference to FIG. FIG. 4 is a diagram for explaining a display state of an image in one frame period (1f). FIG. 4A shows a display state of a display device that does not have a conventional non-display period (a display device that does not divide one frame period into subframe periods). In this display device, an image is always displayed during one frame period. FIG. 4B shows a display state of a display device in which conventional pseudo impulse driving is employed. In this display device, image display is performed in the first half of one frame period, and image display is not performed in the second half of one frame period. FIG. 4C shows a display state in the present embodiment. In the present embodiment, a relatively dark image is displayed in the first half of one frame period, and a relatively bright image is displayed in the second half of one frame period.

<2. Configuration and operation of display control circuit>
FIG. 5 is a configuration diagram of the display control circuit 200 in the present embodiment. The display control circuit 200 includes a timing control unit 21, a frame frequency conversion unit 22, a gradation generation unit 23, a dark display LUT 25, a bright display LUT 26, and a gradation correction unit 30. The LUT is a look-up table (Look Up Table) that is referred to when data conversion processing is performed and in which data before conversion is associated with data after conversion.

  The timing control unit 21 receives a timing control signal TS sent from the outside, and receives a first control signal CTL1 for controlling the operation of the frame frequency conversion unit 22 and a first control signal for controlling the operation of the gradation generation unit 23. 2, the third control signal CLT 3 for controlling the operation of the gradation correction unit 30, the polarity signal Ip, the subframe period identification signal Isf, and the timing for displaying the image on the display unit 500. A source start pulse signal SSP, a source clock signal SCK, a latch strobe signal LS, a gate start pulse signal GSP, and a gate clock signal GCK are output. Here, the polarity signal Ip is a voltage to be applied to any of the video signal lines SL (1) to SL (M) based on the digital image signal DV to be supplied to the source driver 300 (based on the common electrode potential). ) A signal indicating whether the polarity is positive or negative, and the subframe period identification signal Isf indicates in which subframe period in each frame period the video signal for driving corresponding to the digital image signal DV is output. This is a signal for identifying whether a dark display period corresponding to the first half of each frame period or a bright display period corresponding to the second half. Note that in this specification, the voltage polarity of the video signal is defined by the magnitude relationship with respect to the common electrode potential of the source voltage generated corresponding to the signal.

  The frame frequency conversion unit 22 outputs a display data signal DAT2 obtained by doubling the frequency of the data signal DAT based on the data signal DAT sent from the outside and the first control signal CTL1 output from the timing control unit 21. To do. That is, the frame frequency conversion unit 22 outputs a signal indicating an image for one screen as the display data signal DAT2 twice in one frame period.

  The gradation generation unit 23 receives the display data signal DAT2 output from the frame frequency conversion unit 22 and the second control signal CTL2 output from the timing control unit 21, and outputs a gradation signal Lsig. More specifically, the gradation generation unit 23 displays the gradation and dark display period of an image based on the display data signal DAT2 (the same image as the image based on the data signal DAT in one frame period) during the dark display period. The display data signal DAT2 is converted into the gradation signal Lsig while referring to the dark display LUT 25 associated with the gradation of the power image. On the other hand, in the bright display period, the image level based on the display data signal DAT2 is converted. The display data signal DAT2 is converted into the gradation signal Lsig while referring to the bright display LUT 26 in which the tone and the gradation of the image to be displayed in the bright display period are associated with each other. These conversions are performed based on the second control signal CTL2 output from the timing control unit 21. The gradation signal Lsig obtained in this way shows an image based on the data signal DAT as a relatively dark image during the dark display period, and relatively displays an image based on the data signal DAT during the bright display period. Is a signal shown as a bright image.

  The above-described dark display LUT 25 and bright display LUT 26 display an image for one screen of luminance based on the data signal DAT (display data signal DAT2) in one frame period consisting of one dark display period and one bright display period. Has been created to be. This will be described with reference to FIG. FIG. 7 shows the brightness of an image to be displayed during the dark display period (hereinafter referred to as “dark display brightness”) and the brightness of the image to be displayed during the bright display period (hereinafter referred to as “dark display brightness”). FIG. 4 is a diagram for explaining conversion to “bright display luminance”). In FIG. 7, the left column shows the luminance of the image based on the data signal DAT, and the right column shows the dark display luminance and the bright display luminance. 7 (a), (b), (c), (d), and (e), the luminance of the image based on the data signal DAT is 0%, 25%, 50%, 75%, and 100%, respectively. Shows the case. Note that the minimum luminance of the image displayed on the display unit 500 is 0%, and the maximum luminance is 100%.

First, calculation of bright display luminance will be described. When the luminance Bdat of the image based on the data signal DAT is 50% or less, the bright display luminance Bb is calculated by the following equation (1).
Bb = Bdat × 2 (1)
As a result, as shown in FIGS. 7A, 7B, and 7C, the luminance of the image based on the data signal DAT is converted to the bright display luminance.

  On the other hand, when the luminance Bdat of the image based on the data signal DAT is larger than 50%, the bright display luminance Bb is set to 100 (%). As a result, as shown in FIGS. 7D and 7E, the luminance of the image based on the data signal DAT is converted to the bright display luminance.

  Next, calculation of dark display luminance will be described. When the image brightness Bdat based on the data signal DAT is 50% or less, the dark display brightness Bd is set to 0 (%). Thereby, as shown in FIGS. 7A, 7B, and 7C, the luminance of the image based on the data signal DAT is converted into the dark display luminance.

On the other hand, when the luminance Bdat of the image based on the data signal DAT is larger than 50%, the dark display luminance Bd is calculated by the following equation (2).
Bd = Bdat × 2-100 (2)
As a result, as shown in FIGS. 7D and 7E, the luminance of the image based on the data signal DAT is converted into the dark display luminance. Note that FIG. 7 and numerical examples are typical and symbolic examples for explaining the display principle, and are not limited to 0% and 100%, depending on actual demands such as smoothing gradation display. It is acceptable that dark luminance and sufficiently bright luminance are expressed, and even if so, the effect of the present invention is not impaired. For example, when displaying a luminance of 50%, the bright display luminance is 90% and the dark display luminance is 10%, and it may be considered that each luminance sequentially changes in the vicinity thereof.

  As described above, the dark display LUT 25 and the bright display LUT 26 are created so that the luminance based on the data signal DAT (display data signal DAT2) is converted into the bright display luminance and the dark display luminance. Then, a signal indicating the gradation of the image is converted based on the dark display LUT 25 and the bright display LUT 26, so that the bright display luminance is obtained during the bright display period and the dark display luminance is obtained during the dark display period. Each appears.

  As described above, the gradation signal Lsig is generated by converting the signal indicating the gradation of the image based on the dark display LUT 25 and the bright display LUT 26 by the gradation generation unit 23, and the gradation correction unit 30. Is input. The gradation correction unit 30 is a signal correction means for correcting each driving video signal S (m) by correcting the gradation signal Lsig to compensate for a variation in the holding voltage in the pixel capacitance due to crosstalk. . That is, the gradation correction unit 30 compensates for the influence (crosstalk) caused by the potential change of the adjacent video signal lines SL (m) and SL (m + 1) on the holding voltage of the pixel capacitor Ccl in each pixel formation unit P (n, m). Therefore, the gradation signal Lsig is corrected, and the corrected signal is output as the digital image signal DV.

  This digital image signal DV is supplied to the source driver 300. In the source driver 300, the digital image signal DV is converted into an analog voltage and applied to the video signal lines SL (1) to SL (M) as driving video signals. The voltages applied as video signals for driving to the video signal lines SL (1) to SL (M) in this way are the TFTs 10 that are turned on by sequential application of active scanning signals by the gate driver 400, respectively. Is applied to the pixel electrode Epix of each pixel formation portion P (n, m) and is held in the pixel capacitance Ccl (and total pixel capacitance Cpix) of the pixel formation portion P (n, m). An image is displayed by applying a holding voltage in the pixel capacitor Ccl to the liquid crystal and controlling the light transmittance of the display unit 500. As described above, each frame period is composed of two subframe periods, a dark display period and a bright display period, and the display luminance in these subframe periods is temporally averaged, whereby an image of each frame is obtained. The gradation display for is realized.

<3. Details of Tone Correction Unit>
<3.1 Configuration of Tone Correction Unit>
FIG. 6 is a block diagram illustrating a configuration of the gradation correction unit 30 in the present embodiment. The gradation correction unit 30 includes a 1-dot delay unit 32, a correction amount determination unit 34, and a table storage unit that stores four correction tables including first to fourth correction tables Pd, Pb, Nd, and Nb. 36 and an adder 38, and the gradation signal Lsig is input to the 1 dot delay unit 32 and the correction amount determination unit 34. The correction amount determination unit 34 also receives the polarity signal Ip and the subframe period identification signal Isf from the timing control unit 21. The operation of each unit in the gradation correction unit 30 is controlled by a third control signal CLT3 from the timing control unit 21.

  The 1 dot delay unit 32 delays the input gradation signal Lsig by one dot (one pixel), that is, one pulse repetition period in the source clock signal SCK. Here, in order to identify the gradation signal Lsig before and after the delay by the 1 dot delay unit 32, the gradation signal Lsig after the delay is indicated by a symbol “Lsig (A)”, and the gradation signal Lsig before the delay is represented by The symbol “Lsig (B)” is used. In this case, the gradation signals Lsig (A) and Lsig (B) correspond to the voltage to be held in the pixel capacitor Ccl in the two pixel formation portions adjacent to each other in the horizontal direction, that is, the voltage applied to the liquid crystal. Now, focusing on the pixel formation portion P (n, m) including the pixel capacitance Ccl that should hold the voltage corresponding to the gradation signal Lsig (A), the pixel electrode Epix in the pixel formation portion P (n, m) is applied. The video signal line connected via the TFT 10 corresponds to the own source line SL (m) to which the voltage corresponding to the gradation signal Lsig (A) is applied from the source driver 300. The video signal line connected via the TFT 10 to the pixel electrode Epix in the adjacent pixel formation portion P (n, m + 1) including the pixel capacitor Ccl that should hold the voltage corresponding to the gradation signal Lsig (B) is A voltage corresponding to the gradation signal Lsig (B) is a video signal line applied from the source driver 300 and corresponds to the other source line SL (m + 1) when viewed from the target pixel formation portion P (n, m). (See FIGS. 2 and 3). Therefore, the gradation signals Lsig (A) and Lsig (B) corresponding to the voltages to be applied to the own source line SL (m) and the other source line SL (m + 1) for each pixel formation portion P (n, m), respectively. It is sequentially obtained as gradation signals before and after the delay by the 1 dot delay unit 32.

  The correction amount determination unit 34 obtains the gradation signal (hereinafter referred to as “own source gradation signal”) Lsig (A) corresponding to the voltage to be applied to the own source line SL (m) obtained in this way, and the like. Based on a gradation signal (hereinafter referred to as “other source gradation signal”) Lsig (B) corresponding to a voltage to be applied to the source line SL (m + 1), a correction amount ΔL for the self source gradation signal Lsig (A) is obtained. decide. At this time, the correction amount determination unit 34 selects one of the first to fourth correction tables Pd, Pb, Nd, and Nb based on the polarity signal Ip and the subframe period identification signal Isf, and the selected correction The correction amount ΔL is determined with reference to the table.

  The adder 38 corrects the self-source gradation signal Lsig (A) by adding the correction amount ΔL determined as described above to the self-source gradation signal Lsig (A), and the corrected self-source. The gradation signal Lsig (A) + ΔL is output as the digital image signal DV.

<3.2 Principle of gradation correction>
FIG. 8 is a signal waveform diagram for explaining the operation of the active matrix liquid crystal display device according to the present embodiment. As described above, in this embodiment, each frame period includes two sub-displays including a dark display period TD in which a relatively low luminance display is performed and a bright display period TB in which a relatively high luminance display is performed. It is divided into frame periods (FIG. 4 (c)). Along with this, the pixel electrode potential Vpix in one pixel formation portion changes as shown in FIG. That is, the pixel electrode potential Vpix based on the common electrode potential Vcom, that is, the applied voltage (absolute value) to the pixel liquid crystal is in the dark display period TD that is the first half period of each frame period Tfi (i = 1, 2,...). The pixel electrode potential Vpix and the voltage applied to the video signal line (drive video signal) are the common electrode potential unless otherwise specified. The voltage polarity is considered with reference to Vcom). Further, since the liquid crystal display device generally requires AC driving, the polarity of the pixel electrode potential Vpix is inverted every frame period. Further, in this embodiment, since the dot inversion driving method is employed, the polarity of the voltage applied to the video signal lines SL (1) to SL (M) differs depending on the video signal lines SL (1) to SL (M) even in the same frame period. The polarity of the voltage applied to the video signal line also changes every horizontal period. Therefore, whether the voltage applied to the video signal lines SL (1) to SL (M) is applied to the dark display period that is the first half period of each frame period or the bright display period that is the second half period, and It can be classified into four types depending on whether it is positive or negative. Therefore, as shown in FIG. 8E, the positive voltage applied to the video signal line during the dark display period is referred to as “positive voltage for dark display”, which is indicated by the reference sign “S0 +”, and is displayed during the bright display period. The positive voltage applied to the signal line is referred to as “bright display positive voltage” and is indicated by the reference sign “S1 +”, and the negative voltage applied to the video signal line during the dark display period is referred to as “dark display negative voltage”. The negative voltage applied to the video signal line during the bright display period is referred to as “bright negative voltage for display” and is indicated by the reference sign “S1-”.

  Hereinafter, paying attention to the pixel formation portion P (1, 1) corresponding to the intersection of the first scanning signal line GL (1) and the first video signal line SL (1) in the display portion 500, see FIG. However, the change in the pixel electrode potential Vpix will be described in detail. Note that the method of changing the pixel electrode potential in the other pixel formation portions is substantially the same as the timing is shifted by a predetermined time compared to the case of the pixel formation portion P (1, 1) of interest.

  When the scanning signal G (1) shown in FIG. 8A becomes active (high level) in the dark display period TD that is the first half of the frame period Tf1, the TFT 10 of the pixel formation portion P (1,1) becomes conductive. The voltage (positive polarity) S0 + of the video signal line SL (1) is applied to the pixel electrode Epix as the driving video signal S (1) (see FIG. 2). As a result, in the pixel total capacitance Cpix including the pixel capacitance Ccl and the auxiliary capacitance Ccs of the pixel formation portion P (1,1), the pixel electrode potential Vpix becomes equal to the potential (positive polarity) S0 + of the video signal line SL (1). Until the voltage corresponding to the positive potential S0 + is maintained. After that, when the scanning signal G (1) becomes inactive (low level), the TFT 10 of the pixel forming portion P (1,1) is cut off, and next, the dark display is performed until the scanning signal G (1) becomes active. During the period TD, the potential S0 + of the pixel electrode potential Vpix is maintained as it is. When the dark display period TD ends and the bright display period TB starts, the scanning signal G (1) becomes active again. In this active period, the TFT 10 becomes conductive again, and a positive voltage S1 + larger than that in the dark display period TD is applied to the pixel electrode Epix as the driving video signal S (1) as the voltage of the video signal line SL (1). The As a result, the total pixel capacitance Cpix including the pixel capacitance Ccl and the auxiliary capacitance Ccs is charged until the pixel electrode potential Vpix becomes equal to the potential (positive polarity) S1 + of the video signal line SL (1). The corresponding voltage is held. After that, when the scanning signal G (1) becomes inactive, the TFT 10 is cut off, and the pixel electrode potential Vpix is maintained as it is until the scanning signal G (1) becomes active next time, that is, during the bright display period TB. .

  When the next frame period Tf2 (the dark display period TD) starts, the scanning signal G (1) becomes active again, and the TFT 10 becomes conductive again. At this time, since the negative voltage S0− is applied to the video signal line SL (1) as the driving video signal S (1) for the AC driving of the liquid crystal, the negative voltage S0− is also applied to the pixel electrode Epix. Applied. Thereby, the total pixel capacity Cpix including the pixel capacity Ccl and the auxiliary capacity Ccs is charged until the pixel electrode potential Vpix becomes equal to the potential (negative polarity) S0− of the video signal line SL (1), and the negative potential S0 thereof. The voltage corresponding to − is held. Thereafter, when the scanning signal G (1) becomes inactive, the TFT 10 is cut off, and the pixel electrode potential Vpix is maintained as it is until the scanning signal G (1) becomes active next, that is, during the dark display period TD. . When the dark display period TD ends and the bright display period TB starts, the scanning signal G (1) becomes active again, and the TFT 10 becomes conductive again. As a result, the negative voltage S1- having a larger absolute value than that in the dark display period TD is applied as the voltage of the video signal line SL (1) to the pixel electrode Epix as the driving video signal S (1). As a result, the total pixel capacitance Cpix including the pixel capacitance Ccl and the auxiliary capacitance Ccs is charged until the pixel electrode potential Vpix becomes equal to the potential (negative positive polarity) S1- of the video signal line SL (1). The voltage corresponding to S1- is held. After that, when the scanning signal G (1) becomes inactive, the TFT 10 is cut off, and the pixel electrode potential Vpix is maintained as it is until the scanning signal G (1) becomes active next time, that is, during the bright display period TB. .

  When the next frame period Tf3 (the dark display period TD) starts and the scanning signal G (1) becomes active again, the TFT 10 becomes conductive again, and the positive voltage S0 + is applied to the video signal line SL (1). Similar to the change in the frame period Tf1, the pixel electrode potential Vpix changes (the specific value of the pixel electrode potential Vpix differs for each frame period depending on the display image). Thereafter, potential changes similar to those in the frame periods Tf1 to Tf2 are repeated.

  Corresponding to the driving video signal S (j) to be applied to each video signal line SL (j) (j = 1, 2,..., M) in order to change the pixel electrode potential in each pixel forming portion as described above. As described above, the gradation signal Lsig to be generated is generated by the gradation generation unit 23 based on the display data signal DAT2 (data signal DAT) (see FIG. 5). At this time, the voltage to be applied as the driving video signal to any of the video signal lines SL (1) to SL (M) based on the gradation signal Lsig to be generated is the dark display positive voltage S0 + and the bright display positive voltage. Depending on which of the voltage S1 +, the dark display negative voltage S0 +, and the bright display negative voltage S1-, the gradation value indicated by the display data signal DAT2 is converted as shown in FIG. A gradation signal Lsig is generated. As can be seen from FIG. 9, the gradation signal Lsig is based on the voltage polarity of the driving video signal S (j) to be applied to the video signal line SL (j) (j = 1, 2,..., M). Regardless, the dark display period TD, which is the first half of each frame period, is generated with reference to the dark display LUT 25, and the bright display period TB, which is the second half of each frame period, is generated with reference to the bright display LUT 26. Is done.

  As described above, in the present embodiment, in each pixel formation portion P (n, m), when the TFT 10 is in a conductive state, the voltage of its own source line that is the corresponding video signal line SL (m) is applied to the pixel electrode Epix. When applied, the pixel electrode potential Vpix is charged until the self source line SL (m) becomes equal to the potential, and thereafter, when the TFT 10 enters the cutoff state, the charge potential is maintained during the cutoff state (FIG. 8). reference). However, in reality, while the TFT 10 is in the cut-off state, the potential Vpix of the pixel electrode Epix (and the holding voltage in the pixel capacitor Ccl) is two video signal lines arranged so as to sandwich the pixel electrode Epix, that is, the self-source. It is affected by potential changes of the line SL (m) and the other source line SL (m + 1). That is, as shown in FIGS. 2 and 3, each pixel electrode Epix has a parasitic capacitance Csda between itself and the source line SL (m), and a parasitic capacitance Csdb between the other source line SL (m + 1). Each exists. Thereby, the potential Vpix of the pixel electrode Epix is passed through the parasitic capacitance Csda while the TFT 10 connected to the pixel electrode Epix is cut off (that is, while the scanning signal G (n) applied to the gate terminal of the TFT 10 is inactive). In addition to being affected by the potential change of the self source line SL (m), it is also affected by the potential change of the other source line SL (m + 1) via the parasitic capacitance Csdb. In the present embodiment, in order to compensate for variations in the pixel electrode potential Vpix (holding voltage at the pixel capacitance Ccl) caused by such parasitic capacitances Csda and Csdb, that is, to compensate for crosstalk, The gradation signal Lsig is corrected with reference to the correction table Pd, Pb, Nd, Nb of No. 4 (FIGS. 5 and 6). Hereinafter, the principle of this correction will be described.

The magnitude and direction of the influence of the potential change of the own source line SL (m) on the pixel electrode potential Vpix of each pixel formation portion P (n, m) is the own source line at the time when the TFT 10 changes from the conductive state to the cut-off state. This is determined by how the potential of the source line SL (m) changes in the cutoff state with respect to the potential of SL (m) (hereinafter referred to as “V1”). Here, the potential V1 can be regarded as the potential of the driving video signal S (m) for holding the applied voltage to the liquid crystal in the pixel capacitor Ccl, that is, the writing potential to the pixel formation portion P (n, m). . By the way, in this embodiment, each video signal line SL (j) (j = 1 to M) is driven so that the voltage applied to the liquid crystal is inverted for each video signal line, that is, each subframe period (dark) In each of the display period TD and the bright display period TB), the voltage of the drive video signal S (j) is substantially AC with reference to the common electrode potential Vcom (FIGS. 8C and 8D). The time average of the video signal lines SL (j) (j = 1 to M) can also be regarded as being equal to the common electrode potential Vcom. Therefore, the change ΔV1a of the pixel electrode potential Vpix due to the potential change of the self source line SL (m) is expressed by the following equation, considering the capacitance ratio.
ΔV1a = (Vcom−V1) · Csda / Cpix (1)
Here, Cpix is the total capacitance connected to the pixel electrode Epix (Cpix≈Ccl + Ccs), and the pixel electrode potential Vpix is affected so as to increase when ΔV1a> 0 and decrease when ΔV1a <0.

Similarly, the magnitude and direction of the influence of the potential change of the other source line SL (m + 1) is also the potential of the other source line SL (m + 1) (hereinafter referred to as “V2”) when the TFT 10 changes from the conductive state to the cutoff state. It is determined by how the potential of the other source line SL (m + 1) changes in the cutoff state. Here, the potential V2 can be regarded as the potential of the driving video signal S (m + 1) for holding the applied voltage to the liquid crystal in the pixel capacitor Ccl, that is, the writing potential to the pixel formation portion P (n, m + 1). Further, as described above, the time average of any source line potential can be regarded as being equal to Vcom. Therefore, the change ΔV1b of the pixel electrode potential due to the potential change of the other source line SL (m + 1) is expressed by the following equation, considering the capacitance ratio.
ΔV1b = (Vcom−V2) · Csdb / Cpix (2)
Here, the pixel electrode potential is affected so as to increase when ΔV1b> 0 and decrease when ΔV1b <0.

Therefore, in consideration of both the influence due to the potential change of the self source line SL (m) and the influence due to the potential change of the other source line SL (m + 1), the pixel electrode potential Vpix (the holding voltage of the pixel capacitance) in the cutoff state of the TFT 10. The fluctuation ΔV (s) of ΔV (s) = ΔV1a + ΔV1b (3)
Therefore, the actual potential RV (V1, V2) of the pixel electrode Epix is
RV (V1, V2) = V1 + (Vcom-V1) .Csda / Cpix
+ (Vcom−V2) ・ Csdb / Cpix (4)
It becomes. Here, for RV (Va, Vb), the potential of the source line SL (m) at the time when the TFT 10 changes from the conductive state to the cutoff state is Va, and the potential of the other source line SL (m + 1) is Vb. The actual potential at the pixel electrode Epix (temporal average value in one subframe period) is shown.

  As can be seen from the above equation (4), in order to bring the actual potential RV (V1, V2) of the pixel electrode Epix closer to the original potential V1, the driving image is set so that the variation ΔV (s) is offset. The voltage to be applied to the source line SL (m) as the signal S (m) may be corrected (the correction amount ΔVm of the voltage applied to the source line is (V1−Vcom) · Csda / Cpix + (V2−Vcom) -Csdb / Cpix may be used). That is, based on the information indicating the potential V1 of the source line SL (m) and the potential V2 of the other source line SL (m + 1) at the time when the TFT 10 changes from the conductive state to the cut-off state, What is necessary is just to correct | amend the voltage which should be applied to self-source line SL (m) so that fluctuation | variation (DELTA) V (s) may be canceled. For this purpose, for example, as in this embodiment, the value of the self-source gradation signal Lsig (A) corresponding to the voltage to be applied to the self-source line SL (m) is changed to the self-source gradation signal Lsig (A) and The digital image signal DV to be supplied to the source driver 300 may be generated by correcting based on the other source gradation signal Lsig (B) (FIG. 5).

<3.3 First Configuration Example of Correction Table>
The total pixel capacity Cpix included in the equation (4) includes a liquid crystal capacity (pixel capacity) Ccl. Since the liquid crystal capacitance Ccl changes depending on the state of the liquid crystal molecules, it depends on the applied voltage, that is, the potential difference between the pixel electrode potential Vpix and the common electrode potential Vcom. However, even if the voltage applied to the liquid crystal (the pixel electrode potential Vpix based on the common electrode potential Vcom) reaches the target value within one active period of the scanning signal, that is, within one horizontal period, the liquid crystal is used as an electro-optical element. The response time is much longer than one horizontal period. On the other hand, as in the present embodiment, in the case of driving by dividing each frame period into a dark display period TD as the first half period and a bright display period TB as the second half period, the second half of each frame period is used. Since a new voltage is immediately applied to the liquid crystal, there is almost no time margin for the liquid crystal to respond as an electro-optical element to the fluctuation of the pixel electrode potential caused by the parasitic capacitances Csda and Csdb. It can also be said that the torque applied to the liquid crystal molecules in the early stage of the response dominates the subsequent response. Therefore, based on the value of the liquid crystal capacitance Ccl immediately before the voltage application to the pixel electrode Epix at the time of updating the voltage held in the liquid crystal capacitance Ccl, the variation in the holding voltage of the pixel capacitance Ccl due to the subsequent source line potential variation ( It is necessary to consider (variation in pixel electrode potential Vpix) ΔV (s). Therefore, this variation ΔV (s) is applied to the dark display period or the bright display period even if the voltage to be applied to the source line SL (m) corresponds to the same gradation value. Varies depending on the voltage to be used. Further, in the present embodiment, the distribution of luminance (FIG. 7) to the subframe periods TD and TB is changed for each polarity from the viewpoint of DC correction or the like. Therefore, the compensation amount for the variation of the pixel electrode potential Vpix due to the parasitic capacitances Csda and Csdb, that is, the correction amount for crosstalk compensation is changed according to the polarity information and the subframe period information (first half or second half of the frame period). Is preferred.

  Therefore, in a conventional liquid crystal display device that does not employ a driving method in which one frame period is divided into a plurality of subframe periods including a dark display period TD and a bright display period TB, the correction amount ΔL of the gradation signal Lsig (FIG. 5). For example, a single correction table as shown in FIG. 10 is used as a correction table for determining the source gray level signal Lsig (A) and the other source grayscale signal Lsig (B). In the present embodiment, as the first to fourth correction tables Pd, Pb, Nd, and Nb, for example, the correction tables shown in FIGS. 11A to 11D are used. As described above, in the correction amount determination unit 34 (FIG. 6) in the gradation correction unit 30, any one of the first to fourth correction tables Pd, Pb, Nd, and Nb is the polarity signal Ip. The correction amount ΔL is determined by referring to the selected correction table, which is selected based on the subframe period identification signal Isf. The correction table selected here is the first correction table Pd when the voltage to be applied to the source line SL (m) is the dark display positive voltage S0 +, and when the voltage to be applied is the bright display positive voltage S1 +. Is the second correction table Pb, the third correction table Nd in the case of the dark display negative voltage S0-, and the fourth correction table Nb in the case of the bright display negative voltage S1-.

  Note that the correction tables shown in FIGS. 10 and 11 (a) to 11 (d) are a combination of the value of the own source tone signal Lsig (A) and the value of the other source tone signal Lsig (B) and the own source tone. This is a look-up table (LUT) for associating the correction amount ΔL with the signal Lsig (A), and it is assumed that the liquid crystal display device is of a vertical alignment type and configured to be normally black. Further, although the “NC” (no care) portion in these correction tables may be corrected, it is not necessary to correct because it is an area where the effect of the correction is small, that is, an area where the error is originally hardly visible. This is due to the following reason. That is, in the portion “NC” (no care), the gradation value corresponding to the voltage applied to the source line SL (m) is smaller than the gradation value corresponding to the voltage applied to the other source line SL (m + 1). It is an area. That is, it is a region where Lsig (A) <Lsig (B) when expressed by the gradation signal shown in FIG. In this case, even if crosstalk occurs between the pixel electrode Epix and the own source line SL (m), the gradation level of the pixel formation portion P (n, m) including the pixel electrode Epix is low. The influence of crosstalk on the display level of the pixel formation portion P (n, m) is reduced.

<3.4 Second Configuration Example of Correction Table>
Emphasizing the simplification of the configuration for correction rather than the correction accuracy for canceling the variation ΔV (s) (compensation for crosstalk), the correction amount using only the correction table of FIG. ΔL may be determined. In this case, there is only one correction table, and a configuration for selecting a correction table based on the polarity signal Ip and the subframe period identification signal Isf is also unnecessary.

<3.5 Third Configuration Example of Correction Table>
The change ΔV1a (the above formula (1)) of the pixel electrode potential Vpix due to the potential change of the self source line SL (m) is compensated in the gradation setting (operation for associating desired luminance with the voltage to be applied to the source line). Is possible. When such compensation is performed in the gradation setting, the change ΔV1b in the pixel electrode potential Vpix due to the potential change in the other source line SL (m + 1) (the above formula (2)), that is, ΔV1b = (Vcom−V2)・ Csdb / Cpix
Paying attention to only this, the correction amount ΔL of the gradation signal Lsig may be determined so that the change ΔV1b is canceled out. Therefore, based on the information indicating the potential V2 of the other source line SL (m + 1) at the time when the TFT 10 changes from the conductive state to the cut-off state, the driving video is canceled so as to cancel out the change ΔV1b expressed by the above equation (2). The voltage to be applied to the source line SL (m) as the signal S (m) may be corrected (the correction amount ΔVm of the voltage applied to the source line may be (V2−Vcom) · Csdb / Cpix). . In this case, as the first to fourth correction tables Pd, Pb, Nd, and Nb shown in FIG. 6, four correction tables that provide the correction amount ΔL to the value of the other source gradation signal Lsig (B) are prepared. (These correction tables are correction tables that use other source gradation signal values as indexes, and can be regarded as correction tables that use information indicating potentials to be applied to other source lines as indexes.) However, the total pixel capacitance Cpix including the liquid crystal capacitance Ccl depends on the voltage applied to the liquid crystal capacitance Ccl and is a function of the voltage V1 of the self source line SL (m). Therefore, in order to correct more accurately, the values of the self source gradation signal Lsig (A) and the other source gradation signal are used as the first to fourth correction tables Pd, Pb, Nd, and Nb shown in FIG. It is preferable to prepare four correction tables that give the correction amount ΔL for the combination with the value of Lsig (B).

<3.6 Fourth Configuration Example of Correction Table>
In general, in a display device, since gamma (γ) in white display is important, gradation setting is usually performed in white display. In white display, since the gradation of each color is equal, that is, the value of the self source gradation signal Lsig (A) is equal to the value of the other source gradation signal Lsig (B).
ABS (V1-Vcom) = ABS (V2-Vcom) (5)
(Where “ABS (X)” represents the absolute value of the value X). In this embodiment, since the dot inversion driving method is adopted, if the absolute value symbol “ABS” in the above equation (5) is removed,
V1-Vcom =-(V2-Vcom) (6)
It becomes. Substituting Equation (6) into Equation (4) yields the following equation that gives the actual potential RV (V1, V1) of the pixel electrode Epix in white display.
RV (V1, V1) = V1 + (Vcom−V1) · Csda / Cpix
+ (V1-Vcom) ・ Csdb / Cpix (7)
Usually, the voltage V1 to be applied to the self source line SL (m) is set after receiving the influence on the pixel electrode potential Vpix due to the potential change of the self source line SL (m) and the other source line SL (m + 1). The That is, the gradation is set so as to cancel out the variation (Vcom−V1) · Csda / Cpix + (V1−Vcom) · Csdb / Cpix in the equation (7). If such gradation setting is assumed, correction is not necessary in the white display state, and a desired voltage can be obtained on the source line SL (m).

In this case, when the voltage V1 to be applied to the own source line SL (m) and the voltage V2 to be applied to the other source line SL (m + 1) are different (the value of the own source gradation signal Lsig (A) and the other source level). When the value of the adjustment signal Lsig (B) is different), the voltage V1 to be applied to the source line SL (m) may be corrected by ΔVm = RV (V1, V1) −RV (V1, V2). From the above formulas (4) and (7), ΔVm = RV (V1, V1) −RV (V1, V2)
= {(V1-Vcom)-(Vcom-V2)}. Csdb / Cpix (8)
It becomes. Considering that the dot inversion driving method is adopted in this embodiment, (V1−Vcom) in the above equation (8) corresponds to the value of the self source gradation signal Lsig (A), and (Vcom−V2). Can be regarded as corresponding to the value of the other source gradation signal Lsig (B). Accordingly, as the first to fourth correction tables Pd, Pb, Nd, and Nb shown in FIG. 6, the difference between the value of the own source gradation signal Lsig (A) and the value of the other source gradation signal Lsig (B). It is sufficient to prepare four correction tables (correction tables using the difference as an index) for giving a correction amount ΔL to the image. In this way, although the correction accuracy is reduced as compared with the first configuration example, the configuration of the correction table can be simplified. Note that such a correction table can be regarded as a table using information indicating the potential difference between the potential of the source line and the potential of the other source line as an index.

<4. Effect>
As described above, according to the present embodiment, during one frame period, which is a period during which an image for one screen is displayed, an image relatively brighter than a dark display period during which a relatively dark image is displayed is displayed. It is composed of a bright display period, and the dark display period and the bright display period are alternately repeated. For this reason, a dark image is inserted when the image for one screen is rewritten. Thereby, an afterimage of an object moving in human vision is not generated, and motion blur is suppressed.

  In the present embodiment, not only the variation of the pixel electrode potential (the holding voltage in the pixel capacitor) due to the potential change of the source line but also the variation of the pixel electrode potential due to the potential change of the other source line is compensated, that is, In order to compensate for the crosstalk, the voltage to be applied to the source line as the driving video signal is corrected by correcting the gradation signal. In this way, the crosstalk is suppressed by correcting the gradation signal to be supplied to the source driver 300 without suppressing the complication of the circuit configuration and without adding new components in the display unit. The Thereby, in the liquid crystal display device for color display, color crosstalk is suppressed, and color reproducibility in image display is improved. Therefore, according to the present embodiment, it is possible to prevent image quality deterioration due to crosstalk caused by parasitic capacitance between the pixel electrode and the video signal line with a simple configuration while suppressing motion blur when displaying a moving image. it can.

<5. Modification>
In the above embodiment, the gradation signal Lsig is corrected in both the dark display period TD and the bright display period TB in order to compensate for the variation (crosstalk) in the pixel electrode potential Vpix caused by the parasitic capacitances Csda and / or Csdb. However, the influence on the luminance of the display image due to the crosstalk in the dark display period TD corresponding to the first half of each frame period is small. Therefore, when the correction table according to the first, third, or fourth configuration example is used, only the bright display period (the second half of each frame period) in which the influence of the crosstalk on the luminance of the display image is relatively large. The adjustment signal Lsig may be corrected. In this way, the correction table when the voltage to be applied to the source line as the drive video signal is the bright display positive voltage S1 + and the correction when the voltage to be applied is the bright display negative voltage S1−. Only two correction tables, ie, a table, need be prepared, and the configuration for correcting the gradation signal Lsig can be simplified.

  In the above embodiment, the voltage to be applied to the video signal line as the drive video signal is corrected by correcting the gradation signal Lsig in the display control circuit 200 in order to compensate for crosstalk. The source driver 300 may be configured to correct a signal for correcting a voltage to be applied to the signal line.

  In the above embodiment, the number of divisions of one frame period into sub-frame periods is 2, but the number of divisions may be 3 or more as long as it is divided so that the dark display period and the bright display period are included. . In the above embodiment, the dark display period precedes the bright display period in each frame period, but the order of the dark display period and the bright display period in each frame period is not limited to this. However, considering the responsiveness of the liquid crystal as an electro-optical element, it is preferable to precede the dark display period in time within each frame period.

  In the above description, the active matrix type liquid crystal display device has been described as an example. However, the display device is an active matrix type voltage control display device in which parasitic capacitance exists between the pixel electrode and the video signal line. If it is a device, the present invention can be applied to devices other than liquid crystal display devices.

1 is a block diagram illustrating an overall configuration of an active matrix liquid crystal display device according to an embodiment of the present invention. It is a figure which shows typically the structure of the display part of an active matrix liquid crystal display device. It is a circuit diagram showing an equivalent circuit of a pixel formation portion in an active matrix liquid crystal display device. It is a figure for demonstrating the display state of the image in 1 frame period. It is a block diagram which shows the structure of the display control circuit in the said embodiment. It is a block diagram which shows the structure of the gradation correction | amendment part in the said embodiment. The figure for demonstrating conversion into the brightness | luminance of the image which should be displayed in the dark display period about the brightness | luminance of the image based on the data signal input from the outside in the said embodiment, and the brightness | luminance of the image which should be displayed in a bright display period. It is. It is a signal waveform diagram for demonstrating operation | movement of the active matrix type liquid crystal display device which concerns on the said embodiment. It is a figure for demonstrating the LUT for bright display and the LUT for dark display in the said embodiment. It is a figure which shows the correction table at the time of employ | adopting the conventional drive system which does not convert 1 frame period into several sub-frame periods. It is a figure which shows the correction table in the said embodiment.

Explanation of symbols

10 ... TFT (switching element)
22 ... frame frequency conversion unit 23 ... gradation generation unit 25 ... dark display LUT
26 ... Bright display LUT
DESCRIPTION OF SYMBOLS 30 ... Gradation correction | amendment part 32 ... 1 dot delay part 34 ... Correction amount determination part 36 ... Table memory | storage part 38 ... Adder Pd, Pb, Nd, Nb ... Correction table 200 ... Display control circuit 300 ... Source driver 400 ... Gate driver 500 ... Display section Lsig ... Gradation signal Ccl ... Liquid crystal capacitance (pixel capacitance)
Ccs ... Auxiliary capacitance Csda, Csdb ... Parasitic capacitance Ecom ... Common electrode Epix ... Pixel electrode GL (n) ... Scanning signal line (n = 1 to N)
SL (m) Data line (m = 1 to M)
P (n, m): Pixel formation portion (n = 1 to N, m = 1 to M)

Claims (12)

A plurality of video signal lines for transmitting a plurality of video signals based on an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines, and the plurality of scanning signals A plurality of pixel formation portions arranged in a matrix corresponding to intersections with the lines, and a drive control circuit for driving the plurality of video signal lines and the plurality of scanning signal lines. A bright display period that is a sub-frame period in which a relatively high luminance display is performed, and a dark display period that is a sub-frame period in which a relatively low-intensity display is performed. Each of the plurality of subframe periods, and each of the plurality of subframe periods displays a luminance determined based on the gradation of the image for one screen,
Each pixel forming part
A switching element that is turned on or off according to a signal applied to a scanning signal line passing through a corresponding intersection;
A pixel electrode connected via the switching element to a video signal line passing through a corresponding intersection;
A common electrode provided in common to the plurality of pixel formation portions;
A pixel capacitance formed by the pixel electrode and the common electrode;
An electro-optic element that displays a pixel according to a voltage held in the pixel capacitor,
The drive control circuit causes a parasitic capacitance to be formed between the pixel signal and a video signal to be applied to a first video signal line connected to the pixel electrode of each pixel formation portion via a switching element. A signal that is corrected based on information indicating the potential of the second video signal line so that the variation in the holding voltage in the pixel capacitance of the pixel formation portion due to the potential change of the second video signal line arranged in the pixel is compensated Including correction means,
The signal correction means includes
A correction table that stores a correction amount of a video signal to be applied to the first video signal line in association with information indicating a potential of the second video signal line when the switching element is in the conductive state; Table storage means for holding each of the plurality of subframes and voltage polarity combinations;
From a correction table held in the table storage means, a subframe period including a time point when the video signal is applied to the first video signal line and a voltage polarity of the video signal with reference to the potential of the common electrode. By selecting a correction table for the combination and referring to the selected correction table, it corresponds to information indicating the potential of the second video signal line when the switching element changes from the conductive state to the cut-off state. Correction amount determining means for determining the correction amount to be
A display device comprising: The drive control circuit generates the plurality of video signals so that the voltages of the plurality of video signals are substantially alternating within each subframe period with reference to the potential of the common electrode. Applied to
The signal correction unit is configured to output a video signal to be applied to the first video signal line when the switching element is in a conductive state, at the time when the switching element changes from the conductive state to the cutoff state. The display device according to claim 1, wherein correction is performed based on information indicating a potential of the video signal line.   The signal correction means is configured to output a video signal to be applied to the first video signal line when the switching element is in a conductive state, at the time when the switching element changes from the conductive state to the cutoff state. The display device according to claim 2, wherein correction is performed based on information indicating a potential of the second video signal line. Each correction table held in the table storage unit associates the correction amount with a combination of information indicating the potential of the first video signal line and information indicating the potential of the second video signal line. The display device according to claim 1 , wherein the display device is stored. The drive control circuit generates the plurality of video signals so that a voltage polarity based on the potential of the common electrode is different between adjacent video signal lines, and applies the generated video signals to the plurality of video signal lines,
Each correction table stored in the table storage means stores the correction amount in association with information indicating a potential difference between the potential of the first video signal line and the potential of the second video signal line. The display device according to claim 1 , wherein the display device is provided. The signal correction means corrects the voltage of the video signal to be applied to the first video signal line when the switching element is in the conductive state based on a correction amount ΔV1b defined by the following equation. The display device according to claim 2, wherein:
ΔV1b = (V2−Vcom) ・ Csdb / Cpix
Here, V2 represents the potential of the second video signal line when the switching element changes from the conduction state to the cutoff state, Vcom represents the potential of the common electrode, and Csdb represents the pixel electrode and the pixel electrode. The value of the parasitic capacitance formed between the second video signal line and Cpix represents the value of the total capacitance formed between the pixel electrode and another electrode. The signal correction means corrects the voltage of the video signal to be applied to the first video signal line when the switching element is in the conductive state based on a correction amount ΔV1 defined by the following equation. The display device according to claim 6 , wherein:
ΔV1 = (V1−Vcom) · Csda / Cpix + (V2−Vcom) · Csdb / Cpix
Here, V1 and V2 represent the potentials of the first and second video signal lines when the switching element changes from the conductive state to the cut-off state, respectively, Vcom represents the potential of the common electrode, and Csda Represents the value of the parasitic capacitance formed between the pixel electrode and the first video signal line, and Csdb represents the value of the parasitic capacitance formed between the pixel electrode and the second video signal line. Cpix represents the value of the total capacitance formed between the pixel electrode and the other electrode. A plurality of video signal lines for transmitting a plurality of video signals based on an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines, and the plurality of scanning signals A plurality of pixel formation portions arranged in a matrix corresponding to intersections with the lines, and a drive control circuit for driving the plurality of video signal lines and the plurality of scanning signal lines. A bright display period that is a sub-frame period in which a relatively high luminance display is performed, and a dark display period that is a sub-frame period in which a relatively low-intensity display is performed. Each of the plurality of subframe periods, and each of the plurality of subframe periods displays a luminance determined based on the gradation of the image for one screen,
Each pixel forming part
A switching element that is turned on or off according to a signal applied to a scanning signal line passing through a corresponding intersection;
A pixel electrode connected via the switching element to a video signal line passing through a corresponding intersection;
A common electrode provided in common to the plurality of pixel formation portions;
A pixel capacitance formed by the pixel electrode and the common electrode;
An electro-optic element that displays a pixel according to a voltage held in the pixel capacitor,
The drive control circuit causes a parasitic capacitance to be formed between the pixel signal and a video signal to be applied to a first video signal line connected to the pixel electrode of each pixel formation portion via a switching element. A signal that is corrected based on information indicating the potential of the second video signal line so that the variation in the holding voltage in the pixel capacitance of the pixel formation portion due to the potential change of the second video signal line arranged in the pixel is compensated Including correction means,
The display device according to claim 1, wherein the signal correction unit corrects a video signal to be applied to the first video signal line only in the bright display period when the switching element is in the conductive state. A plurality of video signal lines for transmitting a plurality of video signals based on an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines, and the plurality of scanning signals A plurality of pixel formation portions arranged in a matrix corresponding to intersections with the lines, and a drive control circuit for driving the plurality of video signal lines and the plurality of scanning signal lines. A bright display period that is a sub-frame period in which a relatively high luminance display is performed, and a dark display period that is a sub-frame period in which a relatively low-intensity display is performed. Each of the plurality of subframe periods, and each of the plurality of subframe periods displays a luminance determined based on the gradation of the image for one screen,
Each pixel forming part
A switching element that is turned on or off according to a signal applied to a scanning signal line passing through a corresponding intersection;
A pixel electrode connected via the switching element to a video signal line passing through a corresponding intersection;
A common electrode provided in common to the plurality of pixel formation portions;
A pixel capacitance formed by the pixel electrode and the common electrode;
An electro-optic element that displays a pixel according to a voltage held in the pixel capacitor,
The drive control circuit causes a parasitic capacitance to be formed between the pixel signal and a video signal to be applied to a first video signal line connected to the pixel electrode of each pixel formation portion via a switching element. A signal that is corrected based on information indicating the potential of the second video signal line so that the variation in the holding voltage in the pixel capacitance of the pixel formation portion due to the potential change of the second video signal line arranged in the pixel is compensated Including correction means,
The signal correction means is configured to apply a gradation value corresponding to a potential of a video signal to be applied to the first video signal line to the second video signal line when the switching element is in the conductive state. When the gradation value is smaller than the gradation value corresponding to the signal potential, correction of the video signal to be applied to the first video signal line when the switching element is in the conductive state is suppressed. Display device. The drive control circuit generates the plurality of video signals so that the voltages of the plurality of video signals are substantially alternating within each subframe period with reference to the potential of the common electrode. Applied to
The signal correction unit is configured to output a video signal to be applied to the first video signal line when the switching element is in a conductive state, at the time when the switching element changes from the conductive state to the cutoff state. The display device according to claim 8 , wherein correction is performed based on information indicating the potential of the video signal line. The signal correction means is configured to output a video signal to be applied to the first video signal line when the switching element is in a conductive state, at the time when the switching element changes from the conductive state to the cutoff state. The display device according to claim 10 , wherein correction is performed based on information indicating a potential of the second video signal line. The drive control circuit includes:
A scanning signal line driving circuit for driving the plurality of scanning signal lines;
A video signal line driving circuit for driving the plurality of video signal lines;
A control signal to be supplied to the scanning signal line drive circuit and the video signal line, and a display control circuit for generating an image signal to be supplied to the video signal line drive circuit,
The video signal line driving circuit generates the plurality of video signals based on the image signal supplied from the display control circuit and applies the generated video signals to the plurality of video signal lines,
The signal correction unit is configured to supply the video signal line driving circuit with the image so that the video signal to be applied to the first video signal line is corrected to compensate for the variation in the holding voltage. and correcting the signal, the display device according to any one of claims 1 to 7.

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