JP4661810B2 - Data transfer control device and electronic device - Google Patents

Description

  The present invention relates to a data transfer control device and an electronic device.

  In recent years, high-speed serial transfer interfaces such as LVDS (Low Voltage Differential Signaling) have attracted attention as interfaces for the purpose of reducing EMI noise. In this high-speed serial transfer, the transmitter circuit transmits serialized data using differential signals, and the receiver circuit differentially amplifies the differential signal to realize data transfer.

  A typical mobile phone includes a first device part provided with buttons for inputting a telephone number and characters, a second device part provided with a main LCD (Liquid Crystal Display), a sub LCD and a camera, and a second device part. 1. It is comprised by connection parts, such as a hinge which connects the 2nd apparatus part. Therefore, if the data transfer between the first board provided in the first device portion and the second board provided in the second device portion is performed by serial transfer using a differential signal, the connection portion It is possible to reduce the number of wires passing through the terminal.

  By the way, when data transfer at such a connection portion is performed by serial transfer, the transfer efficiency is preferably as high as possible. In particular, when displaying a moving image or the like on the LCD, it is desirable that packets from the host side (first device portion side) can be transferred to the target side (second device portion side) without interruption.

Some display drivers for driving a display panel such as an LCD output a vertical synchronizing signal (VCIN) for notifying a non-display period of the display panel. That is, for example, in a display driver with a built-in RAM, the display driver side controls switching between a non-display period and a display period of the display panel. Therefore, it is necessary for the display driver side to inform the host side of the non-display period of the display panel. For this purpose, the display driver outputs a vertical synchronization signal to the host side. Therefore, when the data transfer at the connection part of the first and second device parts described above is realized by serial transfer, how to efficiently transmit the vertical synchronization signal output from the display driver to the host side. Whether it can be done is an issue.
JP 2001-222249 A

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a data transfer control device capable of increasing the efficiency of serial transfer and an electronic apparatus including the same. is there.

  The present invention relates to a data transfer control device for controlling data transfer, a link controller that analyzes a packet received via a serial bus, and a packet reception end or reception start based on the received packet analysis result A packet detection circuit for detecting a packet, first and second packet buffers in which a packet received via the serial bus is written, and a switching circuit for performing switching control of a write destination of the received packet. When the Kth packet is written in one of the first and second packet buffers and the reception end of the Kth packet or the start of reception of the next K + 1 packet is detected. , Data for switching the write destination of the (K + 1) th packet to the other packet buffer different from the one. Relating to transfer control device.

  According to the present invention, when the Kth packet is written into, for example, the first packet buffer and reception of the Kth packet is completed or reception of the next K + 1th packet is detected, the next K + 1th packet is received. Is switched from the first packet buffer to the second packet buffer. Therefore, the partner device (host side) does not have to wait for the packet buffer to become empty, and can continuously transmit packets. Therefore, continuous packet transfer such as stream transfer can be realized, and the efficiency of serial transfer can be improved.

  According to the present invention, when the packet received via the serial bus is a read request packet, the link controller sets the first packet buffer as a reception packet buffer, and the second packet buffer. Is set in the transmission packet buffer, and when the packet received via the serial bus is a write request packet, the first and second packet buffers are received by the switching circuit. It may be set in the packet buffer for use.

  In this way, the first and second packet buffers are set to a single buffer configuration or a double buffer configuration depending on the type of request packet. Therefore, the efficiency of data transfer can be improved without enlarging the circuit scale so much.

  In the present invention, the write request packet has a response request field for notifying whether to perform handshake transfer using an acknowledge packet, and the link controller receives the write request packet via the serial bus as a write request packet. When the response request field is a packet and no response request is set in the response request field, the first and second packet buffers are changed to reception packet buffers whose write destinations are switched by the switching circuit. You may make it set.

  In this way, since a response request by an acknowledge packet is not required and packet transfer by a double buffer configuration can be realized, data transfer can be further improved in efficiency.

  In the present invention, when an interface circuit that performs interface processing with a display driver connected via an interface bus and a vertical synchronization signal for notifying a non-display period of the display panel are input from the display driver And a signal detection circuit for detecting the vertical synchronization signal and outputting a detection signal. When the link controller receives a read request packet for requesting reading of the status of the vertical synchronization signal, And the second packet buffer is set as a transmission packet buffer, and the signal detection circuit waits for the detection signal to be output from the signal detection circuit. The read request packet is provided on condition that the detection signal is output. For the response packet or the acknowledge packet is read from the second packet buffer as a transmission packet buffer may be performed a process of transmitting through the serial bus.

In this way, the vertical synchronization signal output from the display driver can be efficiently transmitted to the counterpart device (host side). The partner device does not need to monitor the detection of the vertical synchronization signal in the period from when the read request packet is transmitted until the response packet or the acknowledge packet is returned. Therefore, the partner device can perform other processing during the period, and the performance of the entire system can be improved. In the present invention, when the link controller receives the read request packet, The response packet or the acknowledge packet for the read request packet is generated, written to the second packet buffer that is a transmission packet buffer, and the detection signal is output from the signal detection circuit. The response packet or the acknowledge packet written in the second packet buffer may be read from the second packet buffer and transmitted via the serial bus.

  In this way, it is possible to shorten the time lag from when the vertical synchronization signal is detected until the response packet or acknowledge packet is returned, and the display device is in the non-display period in a short time. Can be communicated to.

  In the present invention, when the link controller receives a write request packet for requesting writing of a command or data after the response packet or the acknowledge packet is transmitted via the serial bus, The second packet buffer is set as a reception packet buffer whose write destination is switched by the switching circuit, and the command or the data requested to be written is sent to either the first packet buffer or the second packet buffer. The interface circuit may output the command or the data output from the link controller to the display driver via the interface bus.

  This makes it possible to transfer commands and data from the counterpart device to the display driver during the non-display period of the display panel. As a result, it is possible to prevent a situation in which writing of commands and data adversely affects display operation of the display panel.

  In the present invention, the write request packet has a response request field for notifying whether or not to perform handshake transfer by an acknowledge packet, and a response request value without a response request is set in the response request field. When the link controller receives the write request packet in which a response request value with no response request is set, the command requested to be written without instructing transmission of an acknowledge packet for the write request packet. Alternatively, the data may be output to the interface circuit.

  In this way, even when the non-display period of the display panel is short, commands and data can be transferred to the display driver within this short period.

  The present invention further includes an edge setting register for setting whether to detect a rising edge or a falling edge of the vertical synchronization signal, and the signal detection circuit detects a rising edge in the edge setting register. Is set, the detection signal is output on the condition that the rising edge of the vertical synchronization signal is detected, and the detection of the falling edge is set in the edge setting register. The detection signal may be output on condition that a falling edge of the vertical synchronization signal is detected.

  In this way, it becomes possible to deal with various types of display drivers with different signal forms of the vertical synchronization signal.

  In the present invention, the read request packet that includes a read register for reading the status of the vertical synchronization signal, and that requests reading of the status of the vertical synchronization signal is a packet that requests reading of the read register. Also good.

  This makes it possible to implement a process of waiting for detection of a vertical synchronization signal and returning a response packet or an acknowledge packet without providing a special register or the like.

  In the present invention, the interface circuit may be an MPU interface circuit that generates an interface signal for an MPU interface.

  In the present invention, the packet detection circuit may detect the end of packet reception based on a data length set in the header of the packet.

  Further, the present invention may include a transceiver that transmits and receives packets to and from the host-side data transfer control device using the differential signal line of the serial bus.

  The present invention also relates to an electronic apparatus including any one of the data transfer control devices described above and the display driver connected to the data transfer control device via the interface bus.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. System Configuration FIG. 1 shows a data transfer control device (data transfer control circuit) of this embodiment and a system configuration example thereof. In the present embodiment, a so-called bridge function between a system bus and an interface bus is realized by using the host-side and target-side data transfer control devices 10 and 30 in FIG.

  The data transfer control devices 10 and 30 are not limited to the configuration shown in FIG. 1, and some of the circuit blocks shown in FIG. 1 may be omitted, the connection form between the circuit blocks may be changed, or circuit blocks different from those shown in FIG. May be added. For example, the configuration of the transceiver 20 in the host-side data transfer control device 10 may be omitted, or the configuration of the transceiver 40 in the target-side data transfer control device 30 may be omitted. The data transfer control device 30 and the display driver 6 may be configured with two chips (semiconductor chips), but may be configured with one chip. For example, when the data transfer control device 30 is used as an IP (Intellectual Property) core, the data transfer control device 30 can be built in the semiconductor chip of the display driver 6. Similarly, the host device 5 (system device) and the data transfer control device 10 can be configured by one chip.

  The host (TX) side data transfer control device 10 and the target (RX) side data transfer control device 30 perform packet transfer via a serial bus of differential signals. More specifically, packets are transmitted / received by current driving or voltage driving differential signal lines of the serial bus.

  The host-side data transfer control device 10 includes an interface circuit 92 that performs interface processing with the host device 5 (CPU, baseband engine, display controller, etc.). The interface circuit 92 is connected to the host device 5 via a system bus (host bus). The system bus can be used as an RGB interface bus or an MPU (Micro Processor Unit) interface bus. When used as an RGB interface bus, the system bus can include signal lines such as a horizontal synchronization signal, a vertical synchronization signal, a clock signal, and a data signal. When used as an MPU interface bus, the system bus can include signal lines such as a data signal, a read signal, a write signal, an address 0 signal (command / parameter identification signal), and a chip select signal.

  The host-side data transfer control device 10 includes a link controller 90 (link layer circuit) that performs link layer processing. The link controller 90 generates a packet (request packet, stream packet, etc.) that is transferred to the target-side data transfer control device 30 via the serial bus (LVDS), and performs processing for transmitting the generated packet. Specifically, a transmission transaction is activated to instruct the transceiver 20 to transmit the generated packet.

  The host-side data transfer control device 10 includes a transceiver 20 (PHY) that performs physical layer processing and the like. The transceiver 20 transmits the packet instructed by the link controller 90 to the target-side data transfer control device 30 via the serial bus. The transceiver 20 also receives a packet from the target-side data transfer control device 30. In this case, the link controller 90 analyzes the received packet and performs a link layer (transaction layer) process.

  The target-side data transfer control device 30 includes a transceiver 40 (PHY) that performs physical layer processing and the like. The transceiver 40 receives a packet from the host-side data transfer control device 10 via the serial bus. The transceiver 40 also transmits a packet to the host-side data transfer control device 10. In this case, the link controller 100 generates a packet to be transmitted and instructs transmission of the generated packet.

  The target-side data transfer control device 30 includes a link controller 100 (link layer circuit). The link controller 100 receives a packet from the host-side data transfer control device 10 and performs a link layer (transaction layer) process for analyzing the received packet.

  The target-side data transfer control device 30 includes an interface circuit 110 that performs interface processing with the display driver 6 (display driver circuit) that drives the display panel 7 (LCD or the like). The interface circuit 110 generates various interface signals and outputs them to the interface bus. The interface circuit 110 can include an RGB interface circuit, an MPU interface circuit, or a serial interface circuit (first to Nth interface circuits in a broad sense). Note that the interface circuit 110 may perform an interface process with the camera device or the sub LCD.

  When the system bus on the host side (host device 5) is used as the RGB interface bus, the interface bus on the target side (display driver 6) is also used as the RGB interface bus. The interface circuit 110 (RGB interface circuit) generates RGB interface signals and outputs them to the display driver 6 (device in a broad sense). When the host-side system bus is used as the MPU interface bus, the target-side interface bus is also used as the MPU interface bus. The interface circuit 110 (MPU interface circuit) generates an MPU interface signal and outputs it to the display driver 6. Note that the interface formats of the host side and target side interface buses may be different. For example, the host system bus is set to the RGB interface bus, the target interface bus is set to the MPU interface bus, the host system bus is set to the MPU interface bus, and the target interface bus is set to the RGB interface bus. May be set.

  By providing the interface circuits 92 and 110 as described above, in this embodiment, a bus bridge function between the system bus on the host side and the interface bus on the target side is realized. That is, when the system bus is used as an RGB interface bus, the RGB interface signal output from the host device 5 is transmitted to the target side by packet transfer via the differential signal serial bus. Then, the target-side interface circuit 110 outputs an RGB interface signal corresponding to the RGB interface signal from the host side to the display driver 6. When the system bus is used as an MPU interface bus, the MPU interface signal output from the host device 5 is transmitted to the target side by packet transfer via the differential signal serial bus. Then, the target-side interface circuit 110 outputs an MPU interface signal corresponding to the MPU interface signal from the host side to the display driver 6.

  Specifically, the internal register 350 of the target-side data transfer control device 30 stores interface information for defining the signal format (output format) of the interface signal output from the interface circuit 110. That is, the internal register 350 stores timing information for specifying the timing at which the signal level of the interface signal changes. In this case, of the information stored in the internal register 250 of the data transfer control device 10 on the host side, the information necessary for the target side is transferred to the target side via the serial bus and written to the internal register 350 on the target side. It is. That is, the target-side internal register 350 is a subset (shadow register) of the host-side internal register 250. Based on the timing information set in the target-side internal register 350, the interface circuit 110 generates and outputs an interface signal (interface control signal, data signal) whose signal level changes at a timing according to the timing information. To do.

  More specifically, the host device 5 sets interface signal timing information in the internal register 250 on the host side as an initial setting prior to data transfer. The host device 5 instructs the start of register transfer using the register transfer start register included in the internal register 250 on the host side. Then, the interface signal timing information written in the host-side internal register 250 is packet-transferred from the host-side data transfer control device 10 to the target-side data transfer control device 30 via the serial bus. The transferred timing information is written in the internal register 350 on the target side.

  After such initial setting, the host device 5 writes data (command, parameter) to the port write register of the internal register 250 on the host side. Then, a packet in which data is set in the data field is transmitted from the host-side data transfer control device 10 to the target-side data transfer control device 30 via the serial bus. Then, the interface circuit 110 outputs an interface signal including a data signal set in the packet to the interface bus at a timing according to the timing information set in the internal register 350 on the target side.

  In the following, for simplification of description, the configuration and operation of the present embodiment when the host-side data transfer control device 10 transmits a request packet to the target-side data transfer control device 30 will be described. The same configuration and operation are performed when the data transfer control device 30 transmits a request packet to the data transfer control device 10 on the host side.

2. Packet Format FIGS. 2A to 3B show a format example of a packet transferred by the data transfer control device of this embodiment. The field configuration and arrangement of each packet are not limited to the examples shown in FIGS. 2A to 3B, and various modifications can be made. That is, some of these fields may be omitted, or other types of fields may be provided.

  The write request packet in FIG. 2A is a packet for requesting data (command) write. This write request packet has fields of response request, packet type, label, retry, address size, standard number, data length, and address / command. It also has fields of CP, A +, A + size, port number, data / parameter, CRC (Cyclic Redundancy Check).

  The read request packet in FIG. 2B is a packet for requesting data read. This read request packet has a read data request size field instead of the data / parameter field of the write request packet in FIG. 2A, and is otherwise the same as the write request packet.

  The response packet in FIG. 3A is a packet for returning the response to the read request packet in FIG. In this response packet, the data / parameter returned as a response is set (inserted) in the data / parameter field.

  The acknowledgment packet (handshake packet) in FIG. 3B is a packet for transmitting an acknowledgment (ACK) or a negative acknowledgment (NACK). This acknowledge packet is not provided with a data / parameter field.

  The response request field included in the request packet (write request packet, read request packet) is a field for notifying whether or not to perform handshake transfer using an acknowledge packet (ACK, NACK). For example, when the response request value (response request flag) in the response request field is “0”, it indicates that an acknowledge packet is not required, and when it is “1”, it indicates that an acknowledge packet is required.

  The packet type field is a field for notifying the packet type. In this embodiment, a write request packet, a read request packet, a response packet, an acknowledge packet, and the like are prepared as packet types. The label field is a field for setting a label for distinguishing the current transaction from other transactions. The retry field is a field for indicating whether or not the current transaction is retrying. The address size field is a field for notifying the size of the address (command) set in the address / command field.

The data length field is a field for notifying the data length. This data length indicates the number of bytes from CP to CRC1, for example (data length = subheader + transfer data + CRC). The address / command field is a field for notifying an address (command). The CP field is a field for instructing data packet division. The A + field is a field for setting the address automatic update mode, and the A + size field is a field for setting the address automatic update size (automatic update count). The port number field is a field for designating a port number (transaction execution destination) that is a packet destination. The data / parameter field is a field for setting (inserting) write data (parameter). The read data request size field is a field for designating the data length of data returned by the response packet. The CRC field is a field for checking a packet header and data error. For example, a standard expression (algorithm) such as G (X) = X ¹⁶ + X ¹² + X ⁵ +1 can be used as a CRC generator polynomial.

  The data / parameter field of the response packet is a field for setting (inserting) the read data requested by the read request packet. For example, when a read request packet is transmitted to the counterpart device, the counterpart device sets the read data corresponding to the read request packet in the data / parameter field of the response packet and transmits it.

  The response code field of the acknowledge packet is a field for notifying the reception status of the received packet. For example, when the response code value is “F”, it indicates that the reception has been successful, and when the response code value is “0”, it indicates that the reception has failed.

  In the present embodiment, as shown in FIGS. 2A and 2B, the request packet has a response request field. Then, when the host side (or the target side) transmits a request packet in which the response request field is set in the response request field to the target side (or the host side), the target side sends an acknowledge packet (ACK, NACK) is transmitted to the host side. On the other hand, when the host transmits a request packet in which no response request is set in the response request field to the target, the target does not transmit an acknowledge packet to the host. Thereby, efficient data transfer such as stream transfer can be realized.

  4A and 4B show an example of a transaction when a response request is set, and FIG. 4C shows an example of a transaction when a response request is not set.

  As described above, in this embodiment, the request packet has a response request field. This allows one type of request packet to be handshake transferred to reliably transfer data to the partner device, and data transfer that maintains isochronism at the expense of reliability, such as stream data. It is possible to use them separately for different types of packets. That is, a request packet having the same field configuration can be used as an asynchronous transfer packet or an isochronous transfer packet by rewriting the response request field. Thereby, it becomes possible to cope with various situations while reducing the types of packets, and it is possible to realize efficient data transfer with a small number of types of packets.

  Further, according to the present embodiment, when a request packet in which no response request is set in the response request field is transmitted, there is no need to wait for a response from the other side, and at what timing the transmission side requests the request packet. Can be sent. As a result, the transmission side can generate and transmit stream data request packets at arbitrary timing, and can realize efficient data transfer with a small number of types of packets.

3. Configuration Example of Data Transfer Control Device The target-side data transfer control device 30 (link controller 100) in FIG. 1 is provided with a reception packet buffer for writing a packet transmitted from the host side. However, it has been found that there are the following problems when the packet buffer for reception has a so-called single buffer configuration.

  That is, if the packet buffer for reception has a single buffer configuration, all packets received from the host side are written into the packet buffer, and after all packet analysis such as CRC check is completed, the received packet is moved to the subsequent stage (application layer etc.) Will be sent out. Then, after all of the packets (data) are sent to the subsequent stage, it is necessary to start receiving the next packet and write it to the packet buffer for reception.

  Therefore, the host side (transmission side) has to wait until the reception packet buffer on the target side (reception side) becomes empty after the transmission of a packet until the start of transmission of the next packet. For this reason, the host side cannot continuously transmit packets to the target side. In particular, when displaying a moving image on the display panel 7, the host side needs to transmit packets to the target side without interruption so that the moving image is not interrupted. However, if the receiving packet on the target side has a single buffer configuration, it is difficult to realize such a packet transfer (stream transfer) without interruption.

  FIG. 5 shows a configuration example of the data transfer control device of this embodiment that solves the above-described problems. Note that some of the circuit blocks in FIG. 5 may be omitted, the connection form between the circuit blocks may be changed, or other circuit blocks different from those in FIG. 5 may be added. Further, the packet buffers 301 and 302, the switching circuit 303, the packet detection circuit 312 and the like may be provided inside the link controller 100 or outside.

  In FIG. 5, a transceiver 40 including a physical layer analog circuit receives a packet (data) transmitted from the host-side data transfer control device 10 via a differential signal line of a serial bus. Further, the packet is transmitted to the data transfer control device 10 on the host side via the differential signal line of the serial bus.

  The packet buffers 301 and 302 (first and second packet buffers) are buffers (receiving packet buffers) to which packets received via the serial bus are written. That is, a packet received via the serial bus is input from the transceiver 40 via the switching circuit 303 and written into the packet buffer 301 or 302. These packet buffers 301 and 302 can be configured by, for example, FIFO (First In First Out). The packet buffers 301 and 302 can also have a ring buffer structure.

  The switching circuit 303 performs switching control of the write destination of the received packet. That is, it is switched between which of the packet buffers 301 and 302 the received packet is written.

  The multiplexer 306 selects one of the outputs of the packet buffers 301 and 302. For example, when the information written in the packet buffer 301 is output, the output of the packet buffer 301 is selected, and when the information written in the packet buffer 302 is output, the output of the packet buffer 302 is selected.

  The packet analysis circuit 310 analyzes a packet received via the serial bus. Specifically, the header and data of the received packet are separated and the header is extracted. Then, the response request field is analyzed to determine whether a response request is necessary, or the packet type field is analyzed to determine the type of received packet (write request packet, read request packet, etc.). The address size field is analyzed to determine the size of the address set in the address / command field.

  The packet detection circuit 312 receives the analysis result of the received packet from the packet analysis circuit 310. Based on the analysis result, the reception end (end position) of the packet is detected. Specifically, as shown in FIG. 6A, the end of reception of the packet (Kth packet) is detected based on the data length set in the header of the packet. That is, the end of CRC1 in FIGS. 2A and 2B is detected. The packet detection circuit 312 can be realized by a byte counter that performs a count process based on the data length. As shown in FIG. 6B, the packet detection circuit 312 may detect the reception start (start position) of the packet (K + 1th packet). That is, the beginning of the response request field in FIGS. 2A and 2B may be detected.

  The transaction controller 330 performs processing related to the transaction layer of data transfer. Specifically, packet transfer control such as a request packet, a response packet, and an acknowledge packet is performed to control a transaction composed of a plurality of packets. The transaction controller 330 performs overall control of each circuit block in the link controller 100.

  The signal generator 112 included in the interface circuit 110 generates an interface signal (for example, an MPU interface signal) based on data from the link controller 100, interface information (timing information), and the like. The generated interface signal is output to the display driver 6 via the interface bus.

  In the present embodiment, the packet buffers 301 and 302 have a so-called double buffer configuration. Specifically, as shown in FIG. 6A, the switching circuit 303 writes the Kth (K is an integer) packet in one of the packet buffers 301 and 302, and the reception of the Kth packet is terminated by the packet detection circuit. When detected by 312, the writing destination of the (K + 1) th packet is switched to the other packet buffer. For example, when the first packet is written in the packet buffer 301 and the end of reception of the first packet is detected, the writing destination of the next received second packet is switched to the packet buffer 302. When the second packet is written to the packet buffer 302 and the end of reception of the second packet is detected, the write destination of the next received third packet is switched to the packet buffer 301.

  As shown in FIG. 6B, when the Kth packet is written in one of the packet buffers 301 and 302 and the reception start of the next K + 1th packet is detected, the K + 1th packet write destination May be switched to the other packet buffer. For example, when the first packet is written in the packet buffer 301 and the start of reception of the next second packet is detected, the write destination of the second packet is switched to the packet buffer 302. When the second packet is written in the packet buffer 302 and the reception start of the next third packet is detected, the third packet write destination is switched to the packet buffer 301.

  If the packet buffers 301 and 302 are configured as a double buffer as described above, data transfer can be made efficient. In other words, when the reception packet buffer has a single buffer configuration, the host side has to wait for the reception packet buffer to become empty, and packets could not be continuously transmitted to the target side. . On the other hand, according to the present embodiment, since the packet buffers 301 and 302 have a double buffer configuration, the host side does not need to wait for the packet buffer to become empty, and continuously sends packets to the target side. Can be sent to. In particular, when a moving image such as a television image is displayed on the display panel 7, the host side needs to transmit packets to the target side without interruption so that the moving image is not interrupted. In this regard, according to the present embodiment, since the packet buffers 301 and 302 have a double buffer configuration, packet transfer (stream transfer) without interruption can be realized, and moving image display on the display panel 7 can be facilitated.

4). First Modification FIG. 7 shows a first modification of this embodiment. In the first modification of FIG. 7, a packet generation circuit 320 is provided in addition to the configuration of FIG. The packet generation circuit 320 generates a packet (header) to be transmitted via the serial bus. Specifically, a header of a packet to be transmitted is generated, and the packet is assembled by combining the header and data. In this case, a header corresponding to the type of packet to be transmitted is generated. For example, when a response packet is transmitted, a header as shown in FIG. 3A is generated, and when an acknowledge packet is transmitted, a header as shown in FIG. 3B is generated.

  In the first modification of FIG. 7, the packet buffer 302 (second packet buffer) is a packet buffer for both transmission and reception.

  That is, when the packet received via the serial bus is a read request packet, the link controller 100 sets the packet buffer 301 as a reception packet buffer and sets the packet buffer 302 as a transmission packet as shown in FIG. Set to buffer. The received read request packet is written in the reception packet buffer 301, while the response packet and acknowledge packet to be transmitted are written in the transmission packet buffer 302. For example, data (parameter) requested by the read request packet written in the reception packet buffer 301 is set (inserted) in the data / parameter field of the response packet. The response packet is written into the transmission packet buffer 302 and output to the transceiver 40 via the multiplexer 304. Then, the transceiver transmits the input response packet to the host side via the serial bus.

  On the other hand, as shown in FIG. 9, when the received packet is a write request packet, the link controller 100 uses both of the packet buffers 301 and 302 to receive packets whose switching destinations are switched by the switching circuit 303. Set to buffer. That is, the packet buffers 301 and 302 have a so-called double buffer configuration. Specifically, the switching circuit 303 writes the Kth packet in one packet buffer of the packet buffers 301 and 302, and the packet detection circuit 312 indicates that the reception of the Kth packet has ended (or the reception of the K + 1th packet has started). Is detected, the write destination of the (K + 1) th packet is switched to the other packet buffer different from the one. Data and commands set in the write request packet written in the packet buffer 301 or 302 are output to the display driver 6 via the interface circuit 110.

  As described above, in the first modification, the packet buffers 301 and 302 are configured as a single buffer or a double buffer according to the type of request packet, so that the data transfer rate can be increased without increasing the circuit scale. Increase efficiency.

  That is, when the received packet is a read request packet, a response packet to the read request packet needs to be returned to the host side. In such a case, in the first modification, as shown in FIG. 8, the packet buffer 301 is set as a reception packet buffer, and the packet buffer 302 is set as a transmission packet buffer. Therefore, a response packet corresponding to the read request packet written in the reception packet buffer 301 can be written in the transmission packet buffer 302 and transmitted to the host side, and data transfer can be made efficient.

  Particularly in the second modification, the packet generation circuit 320 generates the response packet (header) based on the analysis result of the read request packet in the packet analysis circuit 310 and writes it in the transmission packet buffer 302 in advance. be able to. When it is determined that the response packet should be transmitted, the response packet written in the transmission packet buffer 302 can be immediately transmitted to the host side. Accordingly, it is possible to shorten the time lag from the reception of the read request packet to the transmission of the response packet, thereby further improving the efficiency of data transfer.

  On the other hand, if the received packet is a write request packet, there is no need to return a response packet to the write request packet to the host side. Therefore, in this case, as shown in FIG. 9, both the packet buffers 301 and 302 are set as reception packet buffers to form a double buffer configuration. In this way, the host side does not need to wait for the packet buffer to become empty, and can continuously transmit packets to the target side. Therefore, packet transfer without interruption (stream transfer) can be realized, and moving image display on the display panel 7 can be facilitated.

  As described with reference to FIG. 2A, the write request packet has a response request field for notifying whether or not to perform handshake transfer using an acknowledge packet. In FIG. 9, it is desirable that a response request value without a response request is set in the response request field of the write request packet transmitted from the host side. When the packet received via the serial bus is a write request packet and a response request value without a response request is set, the link controller 100 sets the packet buffers 301 and 302 to the write destination by the switching circuit 303. Is set in the reception packet buffer to be switched.

  In this way, when the link controller 100 receives a write request packet in which a response request value without a response request is set, the link controller 100 requests a write without instructing transmission of an acknowledge packet for the write request packet. Commands or data can be output to the interface circuit 110. That is, packet transfer such as stream transfer shown in FIG. 4C can be performed, and efficient data transfer can be realized.

  Note that the switching circuit 303 may cancel the switching of the write destination of the received packet when an error is detected in the received packet. In this way, useless switching control is not performed, and the processing can be made efficient.

5. Notification of Non-Display Period by Vertical Synchronization Signal As shown in FIG. 10A, some display drivers 6 that drive a display panel 7 such as an LCD output a vertical synchronization signal VCIN. By using this VCIN, the display driver 6 can inform the host side of the non-display period (vertical synchronization period) of the display panel 7.

  When such a vertical synchronization signal VCIN is output, in the first comparative example of FIG. 10A, the target-side data transfer control device 30 receives this VCIN and transfers the interrupt signal TGINT to the host-side data transfer. Output to the control device 10. When the host-side data transfer control device 10 receives TGINT, it outputs an interrupt signal INT to the host device 5. By doing so, the host device 5 can know that the display panel 7 is in the non-display period.

  However, in the first comparative example shown in FIG. 10A, a TGINT signal line is required separately from the serial bus even though a serial bus that can reduce the number of signal lines is used. End up. Accordingly, the purpose of reducing the number of signal lines in the connection portion between the first device portion provided with the telephone number button and the second device portion provided with the LCD and the camera becomes insufficient.

  In the second comparative example of FIG. 10B, a VCIN read register 352 for reading the status of the vertical synchronization signal VCIN is provided in the data transfer control device 30 on the target side. Then, as indicated by A1 in FIG. 11, the host side transmits a read request packet RREQ (FIG. 2B) for requesting the status reading of the VCIN read register 352. When VCIN is not input from the display driver 6, the target side sends a response packet RESP (FIG. 3 (A)) notifying that VCIN is not input to the host side, as indicated by A2 in FIG. return. On the other hand, when VCIN is input from the display driver 6, a response packet RESP notifying that the VCIN has been input is returned to the host as shown in A3. Then, as shown at A4, the host side transmits a write request packet WREQ set with a command and data to the target side.

  However, in the second comparative example of FIG. 10B, the host device 5 always polls the status of the VCIN read register 352 until the display driver 6 outputs VCIN as shown by A5 in FIG. Must be monitored. For this reason, during this period, the host device 5 cannot perform the processing that should be performed (the overall control of the electronic device and the processing as the baseband engine), and the processing of the host device 5 is hindered.

6). Second Modified Example FIG. 12 shows a method of a second modified example that can solve the above problems. That is, as shown at B1 in FIG. 12, when the host side transmits a read request packet RREQ requesting to read the status of VCIN, the target side (data transfer control device 30) does not immediately return a response packet RESP for RREQ. Then, the vertical synchronization signal VCIN input from the display driver 6 is detected. Then, as shown at B2 in FIG. 12, when VCIN from the display driver 6 is detected, the detection signal VDET becomes active. When VDET becomes active, the target side transmits a response packet RESP for the read request packet RREQ indicated by B1 to the host side as indicated by B3. Instead of transmitting the response packet RESP, an acknowledge packet may be transmitted.

  The host side that has received the response packet RESP indicated by B3 in FIG. 12 transmits a write request packet WREQ set with a command and data to the target side, as indicated by B4. Then, the target side outputs the command and data set in the write request packet WREQ to the display driver 6. By doing so, commands and data can be transferred to the display driver 6 during the non-display period of the display panel 7. Therefore, it is possible to prevent the transfer of commands and data from adversely affecting the display operation of the display panel 7.

  FIG. 13 shows a configuration of a second modification of the present embodiment that can realize the technique of FIG. In the second modification example of FIG. 13, a transfer circuit 340, an internal register 350, and a signal detection circuit 360 are provided in addition to the configuration of the first modification example of FIG. 7. These circuits may be provided inside the link controller 100 or outside.

  The transfer circuit 340 controls the transfer of information within the link controller 100. Specifically, the information written in the packet buffer 301 is transferred to the interface circuit 110 or transferred to the internal register 350. Information from the interface circuit 110 and information from the internal register 350 are transferred to the packet buffer 302.

  The internal register 350 includes various control registers and status registers. The internal register 350 stores interface information for defining the signal format (output format) of the interface signal output from the interface circuit 110.

  A VCIN read register 352 (dummy register) included in the internal register 350 is a register for reading the status of the vertical synchronization signal VCIN from the display driver 6. In the second modification, when a read request packet for requesting reading of the status of VCIN is received from the host side, a response packet (FIG. 3A) for the read request packet (FIG. 2B) is immediately received. Will not reply. Then, it waits for the detection signal VDET to be output from the signal detection circuit 360, and on the condition that VDET is output, a response packet (or an acknowledge packet) for the read request packet is transmitted to the host side via the serial bus. .

  The edge setting register 354 included in the internal register 350 is a register for setting which of the rising edge and falling edge of VCIN is detected.

  The signal detection circuit 360 is a circuit that detects VCIN and outputs a detection signal VDET when a vertical synchronization signal VCIN for notifying a non-display period of the display panel is input from the display driver 6. In this case, the signal detection circuit 360 detects VCIN according to the setting in the edge setting register 354 (setting of the edge polarity of VCIN). For example, when rising edge detection is set in the edge setting register 354, VDET is output on condition that the rising edge of VCIN is detected. On the other hand, if the falling edge detection is set in the edge setting register 354, VDET is output on condition that the falling edge of VCIN is detected. For example, in the case of B2 in FIG. 12, since the falling edge detection is set in the edge setting register 354, the detection signal VDET is active at the falling edge of VCIN. Some types of display drivers output a low active (negative logic) VCIN and others output a high active (positive logic) VCIN. If the edge setting register 354 is provided, it becomes possible to cope with such various display drivers.

  Next, the operation of the second modification will be described with reference to FIGS. As shown in FIG. 14, when a read request packet is received from the host side, the received read request packet is written into the packet buffer 301 for reception via the multiplexer 304 and the switching circuit 303. The packet analysis circuit 310 analyzes the received read request packet.

  When the received read request packet is a packet requesting to read the status of the vertical synchronization signal VCIN (a packet requesting reading of the VCIN read register 352), the read operation (dummy read) of the VCIN read register 352 is performed. Is called. In this case, in the second comparative example of FIG. 10B and FIG. 11, a response packet for returning the status of the VCIN read register 352 is immediately returned. On the other hand, in the second modification, a response packet is not sent back immediately, but a wait is made for the VCIN detection signal VDET to be output from the signal detection circuit 360.

  In this case, when the packet generation circuit 320 (header generation circuit) receives a read request packet requesting to read the VCIN status, it generates and prepares a header of a response packet (acknowledge packet) for the read request packet in advance. deep. Specifically, as shown in FIG. 15, a response packet (acknowledge packet) for the read request packet is generated in advance and written in the transmission packet buffer 302 in advance. If a response packet (acknowledge packet) is prepared in advance as described above, a response packet can be returned immediately upon detection of VCIN, and the efficiency of packet transfer can be improved. That is, since the time lag from when VCIN is detected to when a response packet is returned can be shortened, the display panel 7 can be notified to the host side in a short time that it is in the non-display period.

  As shown in FIG. 16, when the display panel 7 enters a non-display period and the display driver 6 outputs the vertical synchronization signal VCIN, the signal detection circuit 360 detects this VCIN and outputs the detection signal VDET (FIG. 16). 12 B2). Then, the link controller 100 (transaction controller 330) performs a process of transmitting a response packet (acknowledge packet) to the read request packet via the serial bus (see B3 in FIG. 12). That is, the response packet information is output to the transceiver 40 to instruct the transmission of the response packet.

  In addition, when the packet generation circuit 320 generates a response packet (acknowledge packet) in advance and writes it in the packet buffer 302 for transmission, the written response packet (acknowledge packet) is read from the packet buffer 302, Performs transmission processing via the serial bus. As a result, the time lag from when VCIN is detected until the response packet is returned can be shortened.

  The host side that has received the response packet recognizes that the display panel 7 is in the non-display period. In order to write the command or data (parameter) to the register or RAM of the display driver 6 during the non-display period, a write request packet for requesting writing of the command or data is transmitted via the serial bus as shown in FIG. . That is, a write request packet in which a command is set (inserted) in the address / command field and a write request packet in which data is set in the data / parameter field are transmitted (see B4 in FIG. 12).

  When the link controller 100 receives a write request packet for requesting writing of a command or data after the response packet (acknowledge packet) is transmitted via the serial bus in this way, the write is requested as shown in FIG. Output the command or data (parameter) to the interface circuit 110. That is, the command or data set in the write request packet is extracted from the write request packet written in the reception packet buffer 301 via the multiplexer 304 and output to the interface circuit 110.

  Then, the interface circuit 110 outputs the command or data output from the link controller 100 to the display driver 6 via the interface bus. FIG. 18 shows a signal waveform example of the interface bus in this case.

  In FIG. 18, when the CS signal is at a low level, the display driver 6 is chip-selected. When the A0 signal is at the low level, the display driver 6 recognizes that the DATA_O signal is a command, and when the A0 signal is at the high level, the DATA_O signal is recognized as data (command parameter). Is done. When the WR signal is at a low level, a DATA_O command or data is written into the display driver 6.

  In this way, commands and data from the host side can be written to the register and RAM of the display driver 6 during the non-display period of the display panel 7. As a result, it is possible to prevent a situation in which the command or data writing operation adversely affects the display operation of the display panel 7.

  In FIG. 17, it is desirable that a response request value without a response request is set in the response request field of the write request packet transmitted from the host side. In this way, the link controller 100 can output the command or data requested to be written to the interface circuit 110 without instructing transmission of an acknowledge packet for the write request packet, thereby realizing efficient data transfer. it can.

  In particular, when the non-display period of the display panel 7 is short, it is necessary to write commands and data to the display driver 6 within this short period. In this regard, in the second modification, a response request value without a response request is set in the write request packet, and the host does not need to wait for an acknowledge packet to be returned. Therefore, as shown at B4 in FIG. 12, the host side can transmit many write request packets in a short period. Therefore, even when the non-display period of the display panel 7 is short, commands and data can be properly written in the display driver 6 within this short period.

7). Data Transfer Method Using Differential Signal Next, the serial transfer method of this embodiment will be described with reference to FIG. In FIG. 19, DTO + and DTO- are data (OUT data) output from the host side (data transfer control device 10) to the target side (data transfer control device 30). CLK + and CLK− are clocks supplied from the host side to the target side. The host side outputs DTO +/− in synchronization with the CLK +/− edge (for example, a rising edge or a falling edge). Therefore, the target side can sample and capture DTO +/− using CLK +/−. Further, in FIG. 19, the target side operates based on the clock CLK +/− supplied from the host side. That is, CLK +/− becomes the system clock on the target side. Therefore, the PLL (Phase Locked Loop) circuit 12 (clock generation circuit in a broad sense) is provided on the host side, and is not provided on the target side.

  DTI + and DTI- are data (IN data) output from the target side to the host side. STB + and STB- are strobes (clocks in a broad sense) supplied from the target side to the host side. The target side generates and outputs STB +/− based on CLK +/− supplied from the host side. The target side outputs DTI +/− in synchronization with the STB +/− edge (for example, a rising edge or a falling edge). Therefore, the host side can sample and capture DTI +/− using STB +/−.

  In each of DTO +/−, CLK +/−, DTI +/−, and STB +/−, a transmitter circuit (driver circuit), for example, drives differential signal lines (Differential Signal Lines) corresponding to each of these, for example, current drive (or voltage drive) To be transmitted. In order to realize faster transfer, two or more pairs of DTO +/− and DTI +/− differential signal lines may be provided.

  The transceiver 20 on the host side includes transmitter circuits 22 and 24 for OUT transfer (data transfer in a broad sense) and clock transfer, IN transfer (data transfer in a broad sense), and strobe transfer (clock in a broad sense). (Receiver) receiver circuits 26 and 28 are included. The target-side transceiver 40 includes receiver circuits 42 and 44 for OUT transfer and clock transfer, and transmitter circuits 46 and 48 for IN transfer and strobe transfer. Note that a configuration in which some of these circuit blocks are not included may be employed.

  The transmitter circuits 22 and 24 for OUT transfer and clock transfer transmit DTO +/− and CLK +/− by driving the differential signal lines of DTO +/− and CLK +/−, respectively. The receiver circuits 42 and 44 for OUT transfer and clock transfer perform current / voltage conversion based on the current flowing through the differential signal lines of DTO +/− and CLK +/−, respectively, and are obtained by current / voltage conversion. By performing a comparison process (differential amplification process) of the differential voltage signals (first and second voltage signals), DTO +/− and CLK +/− are received.

  The IN transfer and clock transfer transmitter circuits 46 and 48 transmit DTI +/− and STB +/− by driving the differential signal lines of DTI +/− and STB +/−, respectively. The IN transfer and strobe transfer receiver circuits 26 and 28 perform current / voltage conversion based on the current flowing through the differential signal lines of DTI +/− and STB +/−, respectively, and are obtained by current / voltage conversion. By performing a comparison process (differential amplification process) of the differential voltage signals (first and second voltage signals), DTI +/− and STB +/− are received.

8). Electronic Device FIG. 20 shows a configuration example of the electronic device of this embodiment. This electronic device includes the data transfer control devices 502, 512, 514, 520, and 530 described in the present embodiment. Further, it includes a baseband engine 500 (a communication device in a broad sense), an application engine 510 (a processor in a broad sense), a camera 540 (an imaging device in a broad sense), or an LCD 550 (a display device in a broad sense). Note that some of these may be omitted. According to this configuration, a mobile phone having a camera function and an LCD (Liquid Crystal Display) display function can be realized. However, the electronic device of the present embodiment is not limited to a mobile phone, and can be applied to various electronic devices such as a digital camera, a PDA, an electronic notebook, an electronic dictionary, or a portable information terminal.

  As shown in FIG. 20, this embodiment is implemented between a host-side data transfer control device 502 provided in the baseband engine 500 and a target-side data transfer control device 512 provided in the application engine 510 (graphic engine). The serial transfer described in the embodiment is performed. The present embodiment also includes a host-side data transfer control device 514 provided in the application engine 510, a data transfer control device 520 including a camera interface circuit 522, and a data transfer control device 530 including an LCD interface circuit 532. The serial transfer described in (1) is performed. Note that the baseband engine 500 and the application engine 510 may be realized by the same hardware (CPU or the like).

  According to the configuration of FIG. 20, EMI noise can be reduced as compared with a conventional electronic device. Further, by realizing a reduction in the size and power consumption of the data transfer control device, it is possible to further reduce the power consumption of the electronic device. In the case where the electronic device is a mobile phone, the signal line passing through the connection portion (hinge portion) of the mobile phone can be a serial signal line, and the mounting can be facilitated.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term (display driver, host-side data transfer control device, etc.) described together with a different term (device, counterpart device, etc.) in a broader sense or the same meaning at least once in the specification or the drawing It can also be replaced with the different terminology.

  Further, the configuration and operation of the data transfer control device and the electronic device are not limited to the configuration and operation described in this embodiment, and various modifications can be made. Also, the format of each packet such as a write request packet is not limited to the one described with reference to FIGS. Signal waveforms such as a vertical synchronization signal, a detection signal, and an interface signal are not limited to those described in the present embodiment.

The data transfer control apparatus of this embodiment, and its system structural example. 2A and 2B show packet format examples. 3A and 3B show packet format examples. 4A to 4C show examples of transactions related to response requests. 1 is a configuration example of a data transfer control device according to the present embodiment. FIGS. 6A and 6B are explanatory diagrams of a detection method of the end of packet reception and the start of reception. The 1st modification of this embodiment. Operation | movement explanatory drawing of the 1st modification of this embodiment. Operation | movement explanatory drawing of the 1st modification of this embodiment. 10A and 10B are explanatory diagrams of a comparative example. Explanatory drawing of a comparative example. Explanatory drawing of the method of the 2nd modification of this embodiment. The 2nd modification of this embodiment. Operation | movement explanatory drawing of the 2nd modification of this embodiment. Operation | movement explanatory drawing of the 2nd modification of this embodiment. Operation | movement explanatory drawing of the 2nd modification of this embodiment. Operation | movement explanatory drawing of the 2nd modification of this embodiment. An example of a waveform of an MPU interface signal. Explanatory drawing of the serial transfer of this embodiment. Configuration example of an electronic device.

Explanation of symbols

5 Host device, 6 Display driver, 7 Display panel,
10 data transfer control device (host side), 20 transceiver,
30 data transfer control device (target side), 40 transceiver,
90, 100 link controller, 92, 110 interface circuit,
250 internal register, 301, 302 packet buffer, 303 switching circuit,
304, 306 multiplexer, 310 packet analysis circuit,
312 packet detection circuit, 320 packet generation circuit,
330 transaction controller, 340 transfer circuit, 350 internal register,
352 VCIN read register, 354 edge setting register,
360 Signal detection circuit

Claims (8)

A data transfer control device for controlling data transfer,
A link controller that analyzes packets received via the serial bus;
Based on the analysis result of the received packet, a packet detection circuit that detects the reception end or reception start of the packet;
First and second packet buffers in which packets received via the serial bus are written;
A switching circuit that performs switching control of the write destination of the received packet;
An interface circuit that performs interface processing with a display driver connected via an interface bus;
A signal detection circuit that detects the vertical synchronization signal and outputs a detection signal when a vertical synchronization signal for notifying a non-display period of the display panel is input from the display driver;
The switching circuit is
When the Kth packet is written into one of the first and second packet buffers and the reception end of the Kth packet or the reception start of the next K + 1th packet is detected, Switch the write destination of the (K + 1) th packet to the other packet buffer different from the one,
The link controller
When a read request packet for requesting reading of the status of the vertical synchronization signal is received, the first packet buffer is set as a reception packet buffer, and the second packet buffer is set as a transmission packet buffer. ,
It waits for the detection signal to be output from the signal detection circuit, and on the condition that the detection signal is output from the signal detection circuit, a response packet or an acknowledge packet for the read request packet is transmitted as a transmission packet buffer. A process of reading from the second packet buffer and transmitting via the serial bus,
When a write request packet for requesting a command or data write is received after the response packet or the acknowledge packet is transmitted via the serial bus, the first and second packet buffers are switched. The write destination is set in the reception packet buffer whose circuit is switched by the circuit, and the command or the data requested to be written is output to the interface circuit via either the first or second packet buffer. ,
The interface circuit is
The data transfer control device, wherein the command or the data output from the link controller is output to the display driver via the interface bus. In claim 1,
The write request packet has a response request field for notifying whether or not to perform handshake transfer by an acknowledge packet, and a response request value without a response request is set in the response request field,
The link controller
When the write request packet in which the response request value without response request is set is received, the interface circuit outputs the command or the data requested to be written without instructing transmission of an acknowledge packet with respect to the write request packet. A data transfer control device characterized by: In claim 1 or 2,
An edge setting register for setting whether to detect a rising edge or a falling edge of the vertical synchronization signal;
The signal detection circuit includes:
When the rising edge detection is set in the edge setting register, the detection signal is output on the condition that the rising edge of the vertical synchronization signal is detected, and the falling edge is detected in the edge setting register. When the detection is set, the data transfer control device outputs the detection signal on condition that a falling edge of the vertical synchronization signal is detected. In any one of Claims 1 thru | or 3,
A read register for reading the status of the vertical synchronization signal;
The data transfer control device according to claim 1, wherein the read request packet that requests reading of the status of the vertical synchronization signal is a packet that requests reading of the read register. In any one of Claims 1 thru | or 4,
The data transfer control device, wherein the interface circuit is an MPU interface circuit that generates an interface signal for an MPU interface. In any one of Claims 1 thru | or 5,
The packet detection circuit includes:
A data transfer control device that detects the end of reception of a packet based on a data length set in a header of the packet. In any one of Claims 1 thru | or 6.
A data transfer control device comprising: a transceiver for transmitting and receiving packets to and from a host-side data transfer control device using the differential signal line of the serial bus. A data transfer control device according to any one of claims 1 to 7,
An electronic device comprising: the display driver connected to the data transfer control device via the interface bus.

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