JP4647010B2 - Electronic control unit - Google Patents

Description

  The present invention includes a volatile RAM memory and a non-volatile data memory that cooperate with a microprocessor, and is configured to save a learning control constant stored in the RAM memory in the non-volatile data memory, for example. The present invention relates to an electronic control device such as a device or a transmission control device, and relates to an improvement for suppressing the number of batch erases of a flash memory used as a nonvolatile data memory.

  A microprocessor connected to the input signal circuit and the output signal circuit; a non-volatile program memory cooperating with the microprocessor; a volatile RAM memory; and a non-volatile data memory. An electronic control device for sending a control output signal to the output signal circuit in response to an output control program, a value of a control constant stored in the nonvolatile data memory, and a signal state of the input signal circuit, the nonvolatile memory As a data memory, it is known to use a flash memory having a plurality of divided blocks that can be individually erased in units of blocks.

  Conventionally, as an alternative to the flash memory, there is an EEPROM memory that can electrically read in units of 1 byte (8 bits). However, in the case of a flash memory, an inexpensive and large-capacity memory capacity is obtained. On the other hand, there is a problem that it is necessary to perform batch erase in units of blocks of many bytes before data writing / rewriting, and the number of batch erases is limited in terms of lifetime.

  For example, according to the following Patent Document 1 “In-vehicle electronic control device”, the first block of the non-volatile flash memory is used as a program memory, and the second and third blocks are used as a data memory. They are classified as follows. First, the control device specific information is calibration value information for correcting component variations such as the output voltage accuracy of the constant voltage power supply device built in the in-vehicle electronic control device and the conversion accuracy of the AD converter. Even if it is a different value, it is a semi-fixed control constant that does not change thereafter once stored as an initial measurement value.

  Next, the vehicle-specific information is environmental information such as vehicle type information for selecting and determining a control specification of a vehicle on which the vehicle-mounted electronic control device is mounted, or characteristic accuracy information of a vehicle-mounted sensor externally connected to the vehicle-mounted electronic control device. Even if it is a different value for each vehicle, once it is stored as an initial value or initial measured value, it is a control constant that does not change thereafter until the externally connected parts are replaced. Or they belong to either semi-fixed control constants.

  Further, the learning storage information is driving control information obtained as a result of actually measuring the driving characteristics of the vehicle, or fluctuation information such as on-vehicle sensor / electric load characteristic deterioration information, and is temporarily stored as an initial value at the start of driving. Thereafter, the variable control constant is assumed to fluctuate within a predetermined range. The abnormality occurrence history information is data on the number of occurrences of abnormality for each category obtained by aggregating various types of abnormality information generated during the operation of the vehicle based on the category of occurrence of abnormality, and is handled as a kind of variable control constant.

  The reference data is initial value data that is an allowable upper / lower limit value and an initial set value for the semi-fixed control variable or the variable control constant, and is treated as a fixed control constant. Further, the program specific information is a fixed control constant that is a constant design constant determined in association with the input / output control program.

  In the first block, fixed control constants are stored together with an input / output control program from an external tool, and semi-fixed control constants are additionally stored after the shipment adjustment operation of the in-vehicle electronic control device.

  Only the variable control constant is stored in one of the second and third blocks, and when the number of times the additional writing is sequentially performed in one of the second block or the third block reaches a predetermined value, After all data written in the block is erased, additional writing is sequentially performed on the other block. Therefore, by writing fixed control constants and semi-fixed control constants with low writing frequency to the first block, the amount of data written to the second and third blocks is reduced, and variable control constants are made as many times as possible. It is configured so that additional writing can be performed.

  In Patent Document 1, the fixed / semi-fixed control constant written in the first block corresponds to the first and second constants in the present invention to be described later, and one of the second and third blocks. The variable control constant to be alternately written corresponds to the third constant in the present application.

  Furthermore, in the following Patent Document 2 “Method for increasing the number of times of writing to the flash memory”, the data storage area is divided into sector units (minimum unit capable of batch erasure and corresponding to a block in the present invention). In a control device having a flash memory capable of erasing data in units of sectors and having an internal circuit controlled by an embedded microprocessor, a control program is written in sectors A to F of the flash memory, and 1 shows a control device in which process adjustment data set at the time of production with a low rewrite frequency is written, and user adjustment data with a high rewrite frequency is written in the sector H.

  Further, in Patent Document 2, the sector H is stored to store user adjustment data that is given whenever necessary for the purpose of instructing the optimum operation of the control device at the time of use, and the data size of the user adjustment data is further equal. A plurality of divided storage blocks (which are write / read units and correspond to sections in the present invention) are divided into a plurality of storage blocks, and unwritten areas are stored in units of the storage blocks every time the user adjustment data is updated. When the user adjustment data is sequentially written, and there is no unwritten area in the sector, the entire sector data storing the user adjustment data is collectively erased and the user adjustment data is stored again. A method of increasing the guaranteed number of write times of a flash memory that enables writing is disclosed.

  According to this method, a device control program and device adjustment data are stored in the same flash memory. For adjustment data having a high rewrite frequency, one sector, which is a division unit of the flash memory, is further divided into a plurality of storage blocks. Each time adjustment data is changed, the data is written to an unwritten storage block. When all of one sector is written, the latest adjustment data is saved in the RAM memory, and then the sector is erased once and a new storage block unit is written. By making it possible to write in, it becomes unnecessary to use the EEPROM used in the past, cost reduction, reduction of the number of parts, high-speed data reading is possible, and the number of write guarantees can be substantially increased substantially. It is said that a highly reliable control device can be provided.

  In Patent Document 2, the step adjustment data written in the sector G corresponds to the first constant in the present invention described later, and the user adjustment data sequentially written in the sector H is in this application. It corresponds to the second constant.

Japanese Patent Laid-Open No. 2006-072461 (FIG. 4, claim 2, claim 3) Japanese Patent Laid-Open No. 2002-007221 (FIG. 1, Abstract, Paragraph [0014])

(1) Description of problems in the prior art The “on-vehicle electronic control device” according to Patent Document 1 is configured to write a fixed control constant and a semi-fixed control constant in a first block in which an input / output control program is written. Therefore, it is possible to reduce the amount of data in the second and third blocks. For example, in a service store that performs maintenance and inspection, only the input / output control program is changed while leaving the semi-fixed control constant, There is a problem that it is difficult to collectively change only the semi-fixed control constant while leaving the input / output control program.

  Further, according to the “method for increasing the guaranteed number of writing of flash memory” according to Patent Document 2, the control program area, the stroke adjustment data area, and the user adjustment data area are written in different sectors in a batch erase unit. Although it becomes easy to individually rewrite and change the data, if there is no unwritten area in the sector and there is a power failure at the time of erasing the data of the entire sector, the past adjustment data is lost. In addition, it is necessary to allocate a dedicated sector G for the process adjustment data area with a small amount of data, and there is a problem in that the memory utilization efficiency is lowered.

(2) Description of the object of the invention The present invention eliminates the problems in the conventional apparatus, increases the use efficiency of the nonvolatile data memory, which is a flash memory, and suppresses the number of batch erases. The present invention has been made for the purpose of providing an electronic control device that can ensure a long service life.

An electronic control device according to the present invention includes:
A microprocessor to which an input signal circuit and an output signal circuit are connected, a nonvolatile program memory that cooperates with the microprocessor, a volatile RAM memory, and a nonvolatile data memory, and an input / output written in the nonvolatile program memory An electronic control device for sending a control output signal to the output signal circuit in response to a control program, a value of a control constant stored in the nonvolatile data memory, and a signal state of the input signal circuit,
The non-volatile data memory is constituted by a non-volatile memory having a plurality of divided blocks that can be collectively erased in units of blocks,
Each of the divided blocks is sorted into a plurality of data storage areas having different writing frequencies or writing times,
Each of the data storage areas is composed of a plurality of sections serving as read / write units. A plurality of individual data is written in a predetermined order in the section, and the data capacity of one section is individually written. It is composed of the number of bytes corresponding to the number of data,
In the plurality of sections, new data is sequentially stored in section units after batch erasure of the target divided blocks, and any data storage area in the target divided blocks becomes full. When there is no empty section to which no data has been written, new data is written to the top section of the corresponding data storage area of another divided block that has been erased in advance,
The latest data written in the other data storage area in the original divided block is transferred and stored in the first section of the corresponding data storage area in the new divided block.
The data in the original divided block is erased at least after the transfer writing of the latest data to the new divided block is completed, and
The number of sections in the data storage area is such that a larger number of sections are allocated as the frequency of writing increases.

  According to the electronic control unit of the present invention, as the nonvolatile data memory that cooperates with the microprocessor, a nonvolatile memory having a plurality of divided blocks that can be individually erased in units of blocks is used, and each divided block further includes a plurality of divided blocks. As the number of sections in each data storage area is allocated more frequently, the more sections are allocated, the data is written in the same block as the I / O program. Semi-fixed control constants can be stored in a single data storage area in a non-volatile data memory division block, and only the I / O program can be changed while the semi-fixed control constants are left. It is possible to change only the semi-fixed constants at once.

  Furthermore, by setting the number of sections in the data storage area for storing semi-fixed control constants with low writing frequency, when there is no empty section in a specific data storage area and a transition is made to a new divided block, The number of empty sections remaining in the data storage area is small, and the number of empty sections that are erased unnecessarily at one time is reduced. As a whole, the number of times flash memory is erased is reduced, extending its lifetime. There is an effect that can be done.

  In addition, since the original divided block is erased all at once after the latest data is transferred and stored between a plurality of divided blocks, there is an effect that data is not lost when a power failure occurs during the transfer process.

1 is a block diagram showing an overall configuration of an electronic control device according to Embodiment 1 of the present invention. FIG. It is a section block diagram of the non-volatile data memory in the electronic controller by Embodiment 1 of this invention. It is explanatory drawing of the erasing / writing process of the non-volatile data memory in the electronic control apparatus by Embodiment 1 of this invention. It is explanatory drawing of the search / read-out process of the non-volatile data memory in the electronic controller by Embodiment 1 of this invention. It is explanatory drawing of the abnormal process of the non-volatile data memory in the electronic controller by Embodiment 1 of this invention. It is a flowchart of the whole operation | movement in the electronic controller by Embodiment 1 of this invention.

It is a whole flowchart of the data write-in process in the electronic controller by Embodiment 1 of this invention. It is a flowchart of the initialization process of the non-volatile data memory in the electronic control apparatus by Embodiment 1 of this invention. It is a flowchart of the write-in process of the non-volatile data memory in the electronic controller by Embodiment 1 of this invention. It is a flowchart of the all block erase process in the electronic control apparatus by Embodiment 1 of this invention. It is a flowchart of the transfer process in the electronic control apparatus by Embodiment 1 of this invention. It is a whole flowchart of the data read-out process in the electronic controller by Embodiment 1 of this invention.

It is a flowchart of the newest data search process in the electronic control apparatus by Embodiment 1 of this invention. It is a flowchart of the newest block search process in the electronic control apparatus by Embodiment 1 of this invention. It is a flowchart of the newest section search process in the electronic control apparatus by Embodiment 1 of this invention. It is a block diagram which shows the whole structure of the electronic controller by Embodiment 2 of this invention. It is a section block diagram of the non-volatile data memory in the electronic controller by Embodiment 2 of this invention.

Embodiment 1 FIG.
(1) Detailed Description of Configuration Hereinafter, the configuration of the electronic control device according to Embodiment 1 of the present invention will be described with reference to FIG. 1 which is a block diagram showing the overall configuration and FIG. 2 which is a section configuration diagram of a nonvolatile data memory. This will be described in detail.

  First, in FIG. 1, an electronic control unit 100A is composed mainly of a microprocessor 110A, a nonvolatile program memory 111A, a volatile RAM memory 112A, and a nonvolatile data memory 113A that is a flash memory. An in-vehicle electronic control device such as an engine control device is configured, and power is supplied from an external power source 101A, which is an in-vehicle battery, via a power relay 102. The power relay 102 is configured to close immediately when a power switch (not shown) is turned on, and to open after a predetermined delay power feeding period when the power switch is turned off.

  The input signal circuit 103 is an open / close sensor or an analog sensor connected via a connector (not shown). The input signal circuit 103 is connected to the microprocessor 110A via an input interface circuit (not shown) and an input signal bus 130. Yes. The output signal circuit 104 is an electric load such as a driving device or a display connected via a connector (not shown). The output signal circuit 104 is connected to the microprocessor 110A via an output interface circuit and an output signal bus 140 (not shown). It is connected to the.

  The first tool 105A is connected to the microprocessor 110A via the serial signal bus 150 at the time of shipment adjustment / inspection or maintenance inspection of the electronic control unit 100A. The first tool 105A is a keyboard (not shown). And a portable device provided with a display. The second tool 106A is serially connected to the electronic control device 100A in place of the first tool 105A, and the second tool 106A is manufactured by a manufacturer of a combined product such as a vehicle in which the electronic control device 100A is assembled. It is prepared as a shipping adjustment facility at the time of shipping adjustment of the combined product, or used by the facility management department of the user who uses the electronic control unit 100A at the time of installation adjustment of the facility. Therefore, it is constituted by a portable device provided with a keyboard and a display (not shown). The equipment management department and the manufacturer of the combined product belong to the same category, and in the following description, these will be referred to as the manufacturer of the combined product.

  The second tool 106A has the same configuration as the first tool 105A. For example, the second tool 106A is provided by the manufacturer of the electronic control device 100A and is used by simply sharing functions. The first tool 105A stores an input / output control control program 107A used in the electronic control unit 100A. The microprocessor 110A uses the boot program stored in the mask ROM memory 111a to store the input / output control program 107A in a nonvolatile program. It is configured to transfer to the memory 111A.

  The input / output control control program 107A includes a communication processing program for the first tool 105A and the second tool 106A. Further, the input / output control control program 107A includes fixed constants that do not change with respect to the input / output control program 107A, and the first constant 108a, the second constant 108b, which will be described later, stored in the nonvolatile data memory 112A, And a reference constant 107a related to the third constant 108c.

  This reference constant 107a includes upper and lower limit value data that is an allowable fluctuation range relating to a part of fluctuation information in the first constant 108a, the second constant 108b, and the third constant 108c, or a part of learning information of driving characteristics. , Initial setting data applied to uncertain constants among the first constant 108a, the second constant 108b, and the third constant 108c. The initial value setting data is at least the first time of the electronic control unit 100A. Before the start of operation, a first constant area S10, a second constant area S20, and a third constant in one of a first divided block 113a, a second divided block 113b, a third divided block 113c, and a fourth divided block 113d described later. It is configured to be transferred and stored in the first section of the area S300.

  The first tool 105A further includes a first constant 108a transferred to the non-volatile data memory 113A. The first constant 108a is a control constant or input / output corresponding to the model classification of the electronic control unit 100A itself. This is control device specific information such as a part of the selection number information of the control program 107A, a calibration constant for correcting variation in variations in the component characteristics inside the electronic control device 100A, and the manufacturing number of the electronic control device. . The input / output control program 107A includes various partial programs and constant tables assuming various control specifications, and determines which partial program or constant table is selected and used in accordance with the actual control specifications. This is the meaning of the selection number information.

  The first constant 108a is transferred from the first tool 105A to the non-volatile data memory 113A at the time when a transfer operation key provided in the first tool 105A is pressed, or for transfer of the first tool 105A. When the operation key is pressed, the data is transferred to the RAM memory 112A, and the power switch for the electronic control device 100A is opened, and the data is transferred from the RAM memory 112A to the nonvolatile data memory 113A at the timing when the delay power is supplied by the power relay 102. The

  The second tool 106A includes a second constant 108b transferred to the non-volatile data memory 113A. The second constant 108b is a control constant corresponding to the model name / model of the combined product / equipment in which the electronic control unit 100A is incorporated. Or part of selection number information of the input / output control program 107A, or united product unique information such as a calibration constant for correcting variation in the component characteristics of the input / output components connected to the electronic control unit 100A.

  The transfer timing of the second constant 108b is the same as that of the first constant 108a, and is transferred from the second tool 106A to the non-volatile data memory 113A when a transfer operation key provided on the second tool 106A is pressed. Or, when the operation key for transfer of the second tool 106A is pressed, it is transferred to the RAM memory 112A, the power switch for the electronic control unit 100A is opened, and the power supply relay 102 performs delayed power feeding. The data is transferred from the RAM memory 112A to the nonvolatile data memory 113A at the timing.

  The microprocessor 110A that performs the driving operation by the input / output control program 107A stored in the nonvolatile program memory 111A learns to obtain the characteristic variation information of the built-in component or the external connection component of the electronic control unit 100A or the improved driving characteristic. The third constant 108c such as information or abnormality occurrence history information is generated and stored in the RAM memory 112A. The non-volatile data memory 113A is a flash memory that is collectively erased in units of blocks, and includes a first divided block 113a, a second divided block 113b, a third divided block 113c, and a fourth divided block 113d.

  In FIG. 2 showing the configuration in each of the divided blocks 113a to 113d, the first divided block 113a to the fourth divided block 113d have the same configuration, and are the check area S0 and the first fixed block that becomes the data storage area. A number region S10, a second constant region S20, and a third constant region S300 are provided. The check area S0 is composed of, for example, a section S1 having a data capacity C0 of 16 bytes and a spare section S2 that is used as a substitute when the section S1 becomes abnormal.

  The first constant area S10 is composed of, for example, two sections S11 and S12 having a data capacity C10 of 32 bytes. Accordingly, the number of sections N10 [= 2], and the overall data capacity is [ C10 × N10 = 32 × 2 = 64] bytes.

  The second constant area S20 is composed of, for example, four sections S21, S22, S23, and S24 having a data capacity C20 of 96 bytes. Accordingly, the number of sections is N20 [= 4], and the entire data capacity Is [C20 × N20 = 96 × 4 = 384] bytes.

  The third constant area S300 is composed of, for example, 20 sections S301, S302, S303,... S320 having a data capacity C300 of 384 bytes, and therefore the number of sections is N300 [= 20]. The data capacity is [C300 × N300 = 384 × 20 = 7680] bytes.

  Each section described above is a minimum unit of writing / reading, a plurality of individual data is written in a predetermined order in each section, and the values of the data capacities C10, C20, and C300 of one section are written. The number of bytes corresponds to the number of individual data to be processed. Each section is added with sum data for detecting a code error or error correcting code data in addition to a plurality of individual data.

  In the first embodiment, among the divided blocks 113a to 113d, the total data capacity of the main data storage area S300 having the largest product of the number of sections N10, N20, and N300 and the data capacity C10, C20, and C300. A [= N300 × C300 = 20 × 384 = 7680] and the total data capacity B [= N0 × C0 + N10 × C10 + N20, which is a product of the number of sections and the data capacity of the other subordinate data storage areas S0, S10, and S20. The ratio B / (A + B) [= 480 / (7680 + 480) = 0.06] with × C20 = 16 × 2 + 32 × 2 + 96 × 4 = 480] is smaller than the reciprocal of the number of divided blocks N = 4. ing.

  Returning to FIG. 1, the erase / write control circuit 114 receives various command signals COMn from the microprocessor 110A to control the nonvolatile data memory 113A, and sends the answer signal ANSn obtained from the nonvolatile data memory 113A to the microprocessor 110A. It is configured to reply. Of the command signals, the command signal COM1 is a batch erase command, and the block number to be batch erased is input to the erase / write control circuit 114 by the address signal ADR. The erase / write control circuit 114 is configured to store the designated block number, erase the designated block of the nonvolatile data memory 113A at once, and generate an erase completion reply signal ANS1 when the erase is completed.

  The command signal COM2 is an erase confirmation command (blank check), and the block number and section number to be confirmed for erase are input to the erase / write control circuit 114 by the address signal ADR. The erase / write control circuit 114 stores the designated block number and the designated section number, and checks whether or not the designated section in the designated block of the nonvolatile data memory 113A is erased. The response signal ANS2 is generated.

  The command signal COM3 is a write command, and the block number and section number to be written are input to the erase / write control circuit 114 by the address signal ADR. The erase / write control circuit 114 stores the designated block number and the designated section number, writes the write data WRD to the designated section of the designated block of the nonvolatile data memory 113A, and when the writing is completed, the write completion reply The signal ANS3 is generated.

  The command signal COM4 is a read command, and the block number and section number to be read are input to the erase / write control circuit 114 by the address signal ADR. The erase / write control circuit 114 stores the designated block number and the designated section number, reads the read data RDD stored in the designated section of the designated block of the nonvolatile data memory 113A, and when the reading is completed, the read completion reply signal It is configured to generate ANS4.

  The write data WRD and read data RDD are configured to be exchanged with the RAM memory 112A via a direct memory access controller (not shown).

  The RAM memory 112A includes an image memory area 108. The image memory 108 is used as a relay memory when transferring the first constant 108a from the first tool 105A to the nonvolatile data memory 113A, or from the second tool 106A. The third constant 108C is configured to be used as a relay memory when transferring the two constants 108b to the nonvolatile data memory 113A, or to store a third constant 108C generated during operation of the microprocessor 110A.

  The RAM memory 112A includes a status memory 112a in which data corresponding to the erase / write state of the non-volatile data memory 113A is written. The status memory 112a includes at least the latest data that is currently being written. The identification number information of the divided blocks 113a to 113d and the section number information in which the latest data is written in each of the data storage areas S10, S20, and S300 in the latest divided block are stored. .

  The image memory area 108 and the status memory 112a can use a buffer memory provided in the erase / write control circuit 114.

  The power supply circuit 109A is supplied with power via an output contact of the power supply relay 102 energized when the driving power supply switch is closed from an external power supply 101A, for example, an in-vehicle battery, and a drive power supply terminal 102a. Power is supplied from an external power source 101A serving as an external battery via an auxiliary power source terminal 101a without an output contact of the relay 102.

  The power supply circuit 109A generates a stabilized control voltage Vcc of, for example, DC5 [V] when the power supply relay 102 is energized, and the microprocessor 110A, the nonvolatile program memory 111A, the RAM memory 112A, and the nonvolatile data memory To 113A. Further, when the power supply relay 102 is not energized, the power supply circuit 109A generates a stabilized holding voltage Vup of, for example, DC3 [V] and supplies it as a backup power to the RAM memory 112A.

  When the voltage of the in-vehicle battery 101A serving as an auxiliary power supply is abnormally reduced during the period when the power supply relay 102 is turned off, or the auxiliary power supply circuit is shut off and the stored contents of the RAM memory 112A are lost, or the status At least the third data storage area in the non-volatile data memory 113A when the contents of the memory 112a are abnormal, when the power relay 102 is energized and the microprocessor 110A starts operation, or during the operation of the microprocessor 110A The contents of the latest section written in S300 are transferred to the image memory area 108 of the RAM memory 112A, and the microprocessor 110A controls input / output based on the third constant 108c written in the image memory area 108. .

  Actually, when the microprocessor 110A starts operation, not only the third constant 108c but also the first and second constants 108a and 108b are transferred and read from the nonvolatile data memory 113A to the RAM memory 112A, and the microprocessor 110A Control is performed while referring to the image memory area 108 of the RAM memory 112A.

  Further, as an abnormality of the status memory 112a, the identification number information of the latest divided block 113a to 113d that is currently being written is not stored, or each data storage area S10 in the latest divided block is stored. In S20 and S300, the section number information in which the latest data is written is not stored, and there are cases where bit information is mixed or missing due to a code error in the RAM memory 112A as a whole. included.

  Next, the concept of a processing method for erasing / writing processing of the nonvolatile data memory in the electronic control apparatus according to Embodiment 1 of the present invention will be described. FIG. 3 is an explanatory diagram of the erasing / writing process of the nonvolatile data memory in the electronic control device according to the first embodiment of the present invention, in the case where the third constant region S300 of the first block 113a is full. The concept of the writing process is shown in the order of (A), (B), and (C).

  (A) of FIG. 3 shows the contents of the first block 113a that has been actually written. The section S1 of the check area S0 includes a predetermined fixed constant indicating that it is not a blank block, Stored is check data C indicating the cumulative batch erase count. Further, in the section S11 of the first constant area S10, the first constant 108a transferred from the first tool 105A through the RAM memory 112A is stored as the initial data F1, and the section S12 is still written with data. It is an empty section (blank) that is not included.

  In the section S21 of the second constant area S20, the second constant 108b transferred from the second tool 106A through the RAM memory 112A is stored as the initial data Se1, and transferred to the section S22 for the second time. The second constant 108b is stored as the next data Se2, and the sections S23 and S24 are empty sections (blanks) in which data has not yet been written.

  Further, in the section S301 of the third constant area S300, the third constant 108c stored in the RAM memory 112A is stored as initial data T1 immediately after the electronic controller 100A is stopped, and in the section S302, the electronic control is performed. Immediately after the next operation stop of the apparatus 100A, it is stored as the next data T2, and in the same manner, the third constant 108c immediately after the 20th operation stop is stored as the 20th stored data T20, and the data is not yet written. No empty section is full.

  FIG. 3B shows the contents of the divided blocks 113c in order, and even if data has already been written in the divided blocks 113c, the divided blocks 113a are full and the next data is written. At the time when it is necessary to insert, the divided blocks 113c of the next order are erased all at once, and all sections in the check area S0, first constant area S10, second constant area S20, and third constant area S300 are empty sections. It has become.

  FIG. 3C shows the contents of the divided block 113b of the next order, and this divided block 113b has already been erased in batch, but the batch erase is performed again as a confirmation process, and then the current divided block 113b. The next third constant 108c that is full in the block 113a is written in the first section S301 of the third constant area S300. Next, the storage data Se2 which is the latest data (second constant 108b written last) in the second constant area S20 of the divided block 113a is the first section in the second constant area S20 of the divided block 113b. Transferred to S21.

  Next, the stored data F1, which is the latest data (first constant 108a written last) in the first constant area S10 of the divided block 113a, is stored in the first constant area S10 of the divided block 113b. To the first section S11. Finally, a predetermined definite constant indicating that the divided block 113b is not a blank block and a cumulative value of the batch erase count are stored in the check area S0 of the divided block 113b.

  In this way, the divided block 113a moves to the divided block 113b, and the divided block 113b becomes a new current block.

  In the first half area of one section S1 in the check area S0, the divided blocks 113a to 113d are collectively erased, and then the data is stored in at least one section in all the data storage areas of the data storage areas S10, S20, and S300. On the other hand, when a valid data is written, a predetermined fixed constant is written, and even if any one data storage area, valid data is written to any section in the data storage area. If not, a blank block state in which the fixed constant is not written is obtained.

  In the second half area of one section S1 in the check area S0, the batch erasure count data for the divided block is written when the definite constant is written, and when the divided block is transferred, the divided area after the transfer is transferred. The number of batch erases of a block is a value obtained by adding 1 to the number of batch erases written in the check area of the current divided block immediately before the transfer.

  One of each of the divided blocks 113a to 113d is erased at once in the transition process of the previous divided block and the transition process of the current divided block, but if all the sections are erased by the first batch erase, Even if the second batch erase is performed, the number of lifetimes is not affected, and the number of batch erases stored in the check area S0 is the number of batch erases for one by the second batch erase.

Next, the concept of the processing method for search / read processing in the electronic control apparatus according to Embodiment 1 of the present invention will be described. FIG. 4 is an explanatory diagram of the search / read processing of the nonvolatile data memory in the electronic control unit according to Embodiment 1 of the present invention. FIG. 4 (A) shows the latest block in which data is read. The search procedure is shown, and FIG. 4B shows the search procedure for the latest section from which data is read.

  In (1) of FIG. 4A showing the search procedure for the latest block from which data is read, the data is written to the first block 113a after all of the first to fourth blocks are erased at once. The latest block N is searched for a blank block whose check area S0 is blank, and a block that is not a blank block before the blank block is searched as the latest block.

  In (2) in FIG. 4A, one of the first, second, and third areas S10, S20, and S300 of the first block 113a is full and the latest data is transferred to the second block 113b. The latest block N is the second block 113b before the third block 113c, which is a blank block, and the first block 113a is the latest previous block N-1.

  (3) in FIG. 4A is a diagram in the case where any area of the second block 113b is full and the latest data is transferred to the third block 113c. The latest block N is a blank block. Is the third block 113c before the fourth block 113d, the first block 113a is the latest two previous blocks N-2, and the second block 113b is the latest previous block N-1. ing.

  (4) in FIG. 4A is a diagram in the case where any area of the third block 113c is full and the latest data is transferred to the fourth block 113d. The first block 113a, which is two blocks after the third block 113c, is collectively erased, and then the transition to the fourth block is performed. Therefore, the latest block N is the fourth block 113d before the first block 113a, which is a blank block, the second block 113b is the latest two previous block N-2, and the third block 113c is the latest one. This is the previous block N-1.

  (5) in FIG. 4A is a diagram in the case where any area of the fourth block 113d is full and the latest data is transferred to the first block 113a. After the second block 113b, which is two blocks after the four blocks, is collectively erased, the transition to the first block 113a is performed. Therefore, the latest block N becomes the first block 113a before the second block 113b, which is a blank block, the third block 113c becomes the latest two previous block N-2, and the fourth block 113d becomes the latest one. This is the previous block N-1.

  In FIG. 4A, (6) is a diagram when one of the areas of the first block 113a is full and the latest data is transferred to the second block 113b. After the batch erasure of the third block 113c two blocks after the one block is performed, the transition to the second block 113b is performed. Therefore, the latest block N is the second block 113b before the third block 113c, which is a blank block, the fourth block 113d is the latest two previous block N-2, and the first block 113a is the latest one. This is the previous block N-1.

  In (6) of FIG. 4A, when any area of the second block 113b is full and the process proceeds to the third block 113c, first, the second block 113b two after the second block 113b. Since the transition to the third block 113c is performed after the batch erasure of the four blocks 113d, the transition to the state (3) in FIG.

Note that when the divided block is transferred, writing is started after performing batch erasure of the transferred divided block as a precaution.

  As described above, the non-volatile data memory 113A includes at least three or more divided blocks 113a to 113d, and in any of the data storage areas S10, S20, and S300 in the divided block 113a currently being written. When there is no empty section, first, the next-order divided block 113c is collectively erased, and then the next-order divided block 113b is collectively erased as a confirmation process. New data is written in the first section of the storage area, and the latest data written in the other data storage areas in the original divided block 113a is the corresponding data storage area of the next divided block 113b. In the transfer of the divided blocks 113a to 113d, the first section is transferred and stored. Is configured to shift to divide blocks of blank blocks in front of the blank block is already erased.

  In FIG. 4B showing the search procedure of the latest section from which data is read, a definite constant indicating that it is not a blank block and the number of batch erases are written as data C in the check area S0. Yes. In the first section S11 of the first constant area S10, the latest data F1 of the first constant 108a is written, and the subsequent section S12 is in an unwritten state.

  In the first section S21 of the second constant area S20, the previous data Se1 of the second constant 108b is written, the latest data Se2 of the second constant 108b is written in the subsequent section S22, and the subsequent sections S23 and S24 are not yet stored. Write status.

  The first section T301 of the third constant 108c is written in the first section S301 of the third constant area S300, the second data T2 of the third constant 108c is written in the succeeding section S302, and the second section T303 is followed by the second section T303. The third data T3 of the three constants 108c is written, but a power failure occurs during the writing, and a partial area of the section S303 is blank. Subsequent sections S304 to S320 are in an unwritten state.

  The microprocessor 110A generates a batch erase command signal and a blank check command signal (erase confirmation command signal) for the nonvolatile data memory 113A, and the nonvolatile data memory 113A that has received the blank check command has been erased at least for each section. The determination information of whether or not there is returned.

  The microprocessor 110A determines that the erased section is an empty section by performing batch erase, and there is a section that cannot be erased even after batch erase, or data for the nonvolatile data memory 113A. If it is detected that a data write part and a non-write part are mixed in one section due to a power failure during writing, the section is an invalid section. And a section that is not an invalid section because data exists in the section is determined to be a valid section.

  When reading data from the nonvolatile data memory 113A, the microprocessor 110A searches for a valid section from the last section to the top section of each data storage area, and reads data stored in the valid section detected for the first time.

  Next, the concept of the processing method for abnormality processing in the electronic control apparatus according to Embodiment 1 of the present invention will be described. FIG. 5 is an explanatory diagram of the abnormal processing of the nonvolatile data memory in the electronic control unit according to Embodiment 1 of the present invention, and FIG. 5A shows a processing method when a writing abnormality occurs. FIG. 5B shows a processing method in the case where an abnormal erasure occurs in the batch erase of the divided blocks.

  In FIG. 5A showing a processing method when a writing abnormality occurs, here, a case where there is a cell abnormality in the section S302 or data has been written and an invalid section is shown. ing. When writing to the nonvolatile data memory 113A, the microprocessor 110A searches for a valid section from the last section to the top section of each data storage area, and searches for a valid section that was detected for the first time in the reverse direction. When data is written to the section and data cannot be correctly written to the empty section, the search is further performed in the reverse direction and the data is written to the newly detected empty section.

  When an error occurs in the block erase shown in FIG. 5B, a retry is performed only once. However, if the block erase is abnormal even after retrying, a blank check is performed on the check area. The erasure is considered normal. This is because even if there is an unerased portion in a section, the next section is written and there is no actual harm.

(2) Detailed Description of Action / Operation Next, the operation / action of the electronic control apparatus according to Embodiment 1 of the present invention will be described. FIG. 6 is a flowchart of the overall operation in the electronic control apparatus according to Embodiment 1 of the present invention. In FIG. 6, first, when a power switch (not shown) is turned on in step 600a, the power relay 102 is energized and the electronic control unit 100A is driven to supply power. In step 601, the microprocessor 110A starts its operation. To do.

  In the subsequent step 602a, it is artificially determined whether or not the input / output program 107A is to be transferred to the non-volatile program memory 111A. If transfer is desired, the first tool 105A is connected and then the transfer operation key is pressed. Yes, and the process proceeds to step block 602b. If the transfer operation key has not been pressed or if the input / output program 107A has already been written to the nonvolatile program memory 111A, the determination of No is made. This is a determination step to go to step 603a.

  Step block 602b is a step in which the input / output program 107A stored in the first tool 105A is transferred and stored in the nonvolatile program memory 111A by the boot program stored in the mask ROM memory 111a, and the process proceeds to step 603a. The output control program 107A includes fixed constants that are specific to the program and reference constants 107a.

  In step 603a, whether the divided block is initialized by determining whether any of the divided blocks of the first to fourth blocks has a set fixed value written in the check area S0. In this determination step, if the initialization is performed, the determination of Yes is performed and the process proceeds to step 604a. If the initialization is not performed, the determination of No is performed and the process proceeds to step 603b.

  In step 603b, first, initial setting values of the first constant 108a, the second constant 108b, and the third constant 108c are written into the image memory area 108 of the RAM memory 112A. The initial setting values are written in the nonvolatile program memory 111A. The stored reference constant 107a is applied, and for the individual data to which no reference constant is given, for example, an arbitrary constant such as a numerical value 0 is written as an assumed number.

  Step 604a artificially determines whether or not to transfer the first constant 108a to the RAM memory 112A, and if so, connects the first tool 105A and then presses the transfer operation key. If the determination of Yes is made and the process proceeds to step 605a and the transfer operation key is not pressed or the first tool 105A is not connected, the determination of No is performed and the process proceeds to step 604b.

  Step 605a is a step in which the first constant 108a obtained from the first tool 105A is transferred to the image memory area 108 of the RAM memory 112A, and then the process proceeds to step 606.

  Step 604b artificially determines whether or not to transfer the first constant 108b to the RAM memory 112A, and if so, connects the second tool 106A and then presses the transfer operation key. If the determination of Yes is made and the process proceeds to step 605b and the transfer operation key is not pressed or the second tool 106A is not connected, the determination of No is performed and the process proceeds to step 604c.

  In step 605b, the second constant 108b obtained from the second tool 106A is transferred to the image memory area 108 of the RAM memory 112A, and then the process proceeds to step 606. In step 604c, when the learning memory information to be written to the RAM memory 112A is generated during the practical operation of the electronic control unit 100A, the determination of Yes is made and the process proceeds to step 605c, and the learning memory information is generated. If not, it is a determination step of determining No and proceeding to Step 606.

  Step 605c is a step in which the learning information obtained during the practical operation of the electronic control unit 100A is written with the third constant 108c in the image memory area 108 of the RAM memory 112A, and then the process proceeds to step 606. Step 606 is a step for determining whether the power switch is turned on or off. If the power switch is turned on, the determination is No and the operation shifts to step 609, and within a predetermined time when the power switch is turned off. A determination of Yes is made and the process proceeds to step block 700.

  The step block 700 is a data memory write processing step which will be described later with reference to FIG. 7. In this step block, the first constant written in the image memory area 108 of the RAM memory 112A in steps 605a, 605b and 605c. 108a or the second constant 108b or the third constant 108c is transferred and written to the first constant area S10, the second constant area S20 or the third constant area S300 of the non-volatile data memory 113A, and then the process proceeds to step 600c. It is configured.

The initial setting value, which is a temporary value, is written in the step block 603b in the image memory area 108 of the RAM memory 112A, and then updated and rewritten sequentially in steps 605a, 605b, and 605c. In step block 700, the data transferred to the non-volatile data memory 113A is the updated data, and if any of the processes 605a, 605b, and 605c has not been executed yet, Any one of the first constant 108a, the second constant 108b, and the third constant 108c is the initial set value set in step 603b.

  In step 600c, the power supply relay 102 is de-energized and power supply to the electronic control unit 100A is stopped. In the operation end step 609, another control program is executed, and the operation is returned to the operation start step 601 again within a predetermined time. Thereafter, the same control is repeatedly executed.

  The flowchart of FIG. 6 is a general representation of a combination of various processes executed at different times. First, as a first process, step 600a to step block 602b, step 603b, step 605a, step block 700, and step 600c are executed to transfer the input / output control program 107A and the first constant for the nonvolatile data memory 113A. The transfer of 108a and the transfer process of the initial setting values for the second and third constants are performed.

  As the subsequent second processing, Step 600a, Step 605b, Step Block 700, and Step 600c are executed, and the second constant 108b for the nonvolatile data memory 113A is transferred. Similarly, as the third process, the process 600a, step 605c, step block 700, and step 600c are executed and the third constant 108c for the non-volatile data memory 113A is transferred, but for the third constant 108c, step 601 is performed. A large number of individual data are sequentially expanded and stored in the RAM memory 112A while circulating through step 605c, step 606, step 609, and step 601, and immediately after the power switch is turned off, the step block 700 collectively transfers to the nonvolatile data memory 113A. Will be transferred.

  FIG. 7 is an overall flowchart of data write processing in the electronic control apparatus according to Embodiment 1 of the present invention. In FIG. 7, step 700 is a step of starting data writing to the data memory. The subsequent step 701 is a step of determining whether or not to initialize the nonvolatile data memory 113A. In this step 701, data is written in all of the divided blocks, and the divided block to be written next cannot be specified. When it is in a state or when valid data is not written anywhere in all blocks, it is determined that the initialization is necessary and the process proceeds to step block 800, and the latest block search described later with reference to FIG. If it can be done, it is determined that initialization is not required and the process proceeds to step block 900.

  Step block 800 is a data memory initialization process step, which will be described later with reference to FIG. In the subsequent step 702, when the initialization process by the step block 800 is normally completed, a determination of Yes is made and the process proceeds to the step block 900. When the initialization process is not normal, a determination of No is performed and the process proceeds to step 707. It is a step.

  Step block 900 is a data write processing step of the data memory described later with reference to FIG. In the subsequent step 703, when the writing process by the step block 900 is normally completed, a determination of Yes is made and the process proceeds to step 704, and when it is abnormal (there is no empty section in the block), a determination of No is made. This is a determination step to go to step block 1100.

  In step 704, the read section number in the status memory 112a provided in the RAM memory 112A is updated, and the process proceeds to step 705. The step block 1100 is a divided block transition processing step which will be described later with reference to FIG. The subsequent step 706 is a determination step in which a Yes determination is made when the transfer process by the step block 1100 has been completed normally, and the process proceeds to step 705. is there. Step 705 is a writing normal end step, and step 707 is a writing abnormal end step.

  It is a flowchart of the initialization process of the non-volatile data memory in the electronic control apparatus by Embodiment 1 of this invention. In FIG. 8, step 801 is a start step of the initialization process. A subsequent step block 1000 is a batch erasure processing step for all blocks, which will be described later with reference to FIG. The subsequent step 802 is a determination step in which a Yes determination is made when the erasing process by the step block 1000 is normally completed, and the process proceeds to step 803, and a No determination is performed when the erase process is not normal, and the process proceeds to step 811. is there.

  In step 803, the writing section is determined to be the first block 113a which is the first block, and then the process proceeds to step block 900. Step block 900 is a writing process step which will be described later with reference to FIG. 9, and the first section S11 of the first constant area S10, the first section S21 of the second constant area S20, and the third constant area S300 of the first block 113a. The initial setting value is written into the first section S301 of the.

  In the subsequent step 804, when the writing process by the step block 900 is normally completed, a determination of Yes is made and the process proceeds to step 805. When the writing process is not normal, a determination of No is performed and the process proceeds to step 811. It is.

  In step 805, it is determined whether or not the writing of data to the first section of each data storage area is completed in step block 900. If it is not completed, the determination is No and the process returns to step 803, and if completed, This is a determination step in which the determination becomes Yes and the process proceeds to step 806. Step 806 is a step of writing a predetermined fixed numerical value and the number of batch erasures “1” into the section S1 provided in the check area S0 of the first block 113a.

  In the subsequent step 807, if the check area writing process in step 806 has been completed normally, a determination of Yes is made and the process proceeds to step 808. If it is not normal, a determination of no is performed and the process proceeds to step 811. This is a determination step. In step 808, the block number of the latest block in the status memory 112a provided in the RAM memory 112A is set as the head block number, and then the process proceeds to step 809.

  Step 809 is a step in which the read section number in the status memory 112a provided in the RAM memory 112A is set as the head start number, and then the process proceeds to step 810. Step 810 is an initialization normal end step, and step 811 is an initialization abnormal end step.

  FIG. 9 is a flowchart of the writing process of the nonvolatile data memory in the electronic control apparatus according to Embodiment 1 of the present invention. In FIG. 9, step 901 is the start step of the writing process. In the subsequent step 902, whether or not an empty section remains in the current write block is determined based on the contents of the status memory 112a in the RAM memory 112A. If there is an empty section, the determination is Yes and the process proceeds to step 903. If there is no empty section, No is determined and the process proceeds to step 911.

  Step 903 is a step of performing a blank check to confirm whether the section to be written is an empty section. In the subsequent step 904, if the section to be written as a result of the blank check in step 903 is an empty section, the determination of Yes is performed and the process proceeds to step 905. If not, the determination of No is performed and the process proceeds to step 907. This is a determination step.

  In step 905, data is written in the writing section, and then the process proceeds to step 906. Step 906 is a determination step in which a determination of Yes is made if the data writing in step 905 is normal and the process proceeds to step 910, and a determination of No is made if the data writing is not normal and the process proceeds to step 907.

  Step 907 is a step in which the write section number is advanced and then the process returns to step 902. If the write is abnormal, the write section is advanced, blank check and write are performed again, and an empty section is found in the block. If it disappears, the process ends abnormally in step 911, and if it is normally written, it ends normally in step 910.

  FIG. 10 is a flowchart of the all block erasing process in the electronic control apparatus according to Embodiment 1 of the present invention, and shows the erasing process of the designated divided block. In FIG. 10, step 1001 is a starting step of the erasing process. In the subsequent step 1002, the current value of the retry counter is set to “0”, and then the process proceeds to step 1003.

  Step 1003 is a step in which the process proceeds to Step 1004 after erasing the divided blocks. In step 1004, it is determined whether or not the designated divided block has been erased by performing a blank check. If erased, the determination is Yes and the process proceeds to step 1010. In this determination step, the determination is made and the process proceeds to step 1005.

  Step 1005 is a step in which “1” is added to the current value of the retry counter, and then the process proceeds to Step 1006. In Step 1006, if the current value of the retry counter is less than “2”, the determination of Yes to permit the retry is performed, and the process returns to Step 1003. If the current value is “2” or more, the retry is not permitted. This is a determination step in which the determination is made and the process proceeds to step 1007.

  Step 1007 is a step of performing a blank check of the check area S0. In the subsequent step 1008, if the check area S0 is blank as a result of the blank check in step 1007, the determination is Yes and the process proceeds to the normal end step 1010. If the check area S0 is not blank, the determination is No. This is a determination step for shifting to the abnormal end step 1011.

  If the check area is blank, the search for the latest block works normally, and if there is a process that writes to the next section if it is not an empty section in the write process, there are parts that are not erased outside the check area. There is no functional impact. For this reason, if the check area is blank at the time of erasure abnormality after retry, it is configured to terminate normally.

  FIG. 11 is a flowchart of the migration process in the electronic control apparatus according to Embodiment 1 of the present invention, and shows the division block migration process. In FIG. 11, step 1101 is a start step of block migration processing. The step block 1000a is a step of erasing the data memory block described above with reference to FIG.

  In the subsequent step 1102a, when the erasing process by the step block 1000a is normally completed, a determination of Yes is made and the process proceeds to the step block 1000b. This is a determination step. The step block 1000b is a block erase step of the data memory described above with reference to FIG. 10, and here, the previous divided block is collectively erased.

  In the subsequent step 1102b, when the erasing process by the step block 1000b is normally completed, a determination of Yes is made and the process proceeds to step 1103a, and when it is not normal, a determination of No is performed and the process proceeds to the abnormal end process 1111. It is a step.

  Step 1103a is a step of updating the write section number of the designated area to the first section using the designated data storage area where the divided blocks have been migrated as a designated area. The subsequent step block 900a is the data writing step described above with reference to FIG. 9, and is configured such that newly generated data is written in the data storage area that is full and the divided block is transferred. Yes.

  In the subsequent step 1102c, when the writing process by the step block 900a is normally completed, the determination of Yes is performed and the process proceeds to step 1103b. When the writing process is not normal, the determination of No is performed and the process proceeds to the abnormal termination step 1111. This is a determination step. In step 1103b, for one of the data storage areas other than the data storage area where the divided block has been migrated, the latest section stored in the divided block before migration is transferred to the first section of the divided block after migration. The write section number is updated to be transferred.

  A subsequent step block 1200 is a data search / read processing step described later with reference to FIG. 12. Here, a normal divided block and a read section are searched for the divided blocks before the transition to search for the existence of an effective section. Subsequent step 1104 is a determination step in which if a valid section exists for the divided block before the transition, a Yes determination is made and the process proceeds to step block 900b, and if there is no valid section, a transition to step block 900c is performed. is there.

  Step block 900b is the write processing step described above with reference to FIG. 9. Here, the latest data in the pre-migration divided block read in step block 1200 is transferred and written to the first section of the post-migration divided block. Step block 900c is the write processing step described above with reference to FIG. 9. Here, the initial setting value written in image memory 108 of RAM memory 112A at step 603b in FIG. Transfer written.

  Step 1102d following step block 900b or 900c makes a Yes determination when the writing process by step blocks 900b and 900c ends normally and proceeds to step 1105, and makes a No determination when the writing process is not normal. This is a determination step for shifting to the abnormal end step 1111.

  Step 1105 determines whether or not the latest data or initial value data has been written in all areas of the first area S10, the second area S20, and the third area S300. Then, the process returns to step 1103b, and if it is completed, a determination of Yes is made and the process moves to step 1106. Step 1106 is a step of writing a predetermined fixed value and the number of batch erasures into the section S1 provided in the check area S0 of the divided block after the transfer. The number of batch erases is the section of the divided block before the transfer. This is a value obtained by adding 1 to the number of batch erases written in S1.

  In the subsequent step 1102e, when the check area writing process in step 1106 is normally completed, the determination of Yes is performed and the process proceeds to step 1107. When the check area is not normal, the determination of No is performed and the abnormal termination step 1111 is performed. This is a determination step for transition. In step 1107, the block number of the latest block in the status memory 112a provided in the RAM memory 112A is updated, and then the process proceeds to step 1108. Step 1108 is a step of proceeding to normal end step 1110 after updating the read section number in the status memory 112a provided in the RAM memory 112A.

  FIG. 12 is an overall flowchart of data reading processing in the electronic control apparatus according to Embodiment 1 of the present invention, and shows data reading processing from the nonvolatile data memory. In FIG. 12, step 1200 is a step of starting reading data from the data memory. A subsequent step block 1300 is a latest data search processing step which will be described later with reference to FIG.

  In the subsequent step 1201, the latest block search result in the step block 1300 is in a state where data is written in all the divided blocks 113a to 113c and the latest block cannot be specified, or all the divided blocks 113a to 113c are not specified. If 113c is a blank block and valid data cannot be searched, the determination is Yes and the process proceeds to reading abnormal end step 1211. When a valid block is searched, the determination is made that there is no abnormality and the determination is No. This is a determination step for shifting to 1202.

  In the following step 1202, if the valid read block and the read section cannot be identified as the latest section search result in the step block 1300, the determination is Yes and the process proceeds to the read abnormal end step 1211. This is a determination step in which a determination of No indicating no abnormality is made and a transition to step 1203 is made when a read block and a read section are searched. Step 1203 is a step of reading the data of the read section in the read block that has been searched, storing it in the image memory area 108 of the RAM memory 112A, and proceeding to a normal reading end step 1210.

  FIG. 13 is a flowchart of the latest data search process in the electronic control apparatus according to Embodiment 1 of the present invention, and shows the latest data search of the nonvolatile data memory. In FIG. 13, step 1301 is a start step of the latest data search. A subsequent step block 1400 is a latest block search step described later with reference to FIG.

  In the subsequent step 1302, as the latest block search result in step block 1400, data is written in all the divided blocks 113a to 113c and the latest block cannot be specified, or all the divided blocks 113a to 113c If it is a blank block and valid data cannot be searched, the determination is Yes and the process proceeds to the reading abnormal end step 1311. When the effective block is searched, the determination of No indicating no abnormality is performed and the process proceeds to step 1303. This is a determination step for transition.

  Step 1303 is a step in which the searched latest block number is stored in the status memory 112a in the RAM memory 112A and then the process proceeds to step 1500a. Step block 1500a is a latest section search step which will be described later with reference to FIG. 15. Here, the latest section in the latest block stored in step 1303 is searched. In the subsequent step 1304, as a result of searching for the latest section by the step block 1500a, if there is no valid section, the determination is Yes and the process proceeds to step 1305. If a valid section is found, No is found. This is a determination step in which the determination is made and the process proceeds to step 1306a.

  Step 1306a is a step in which the searched number information is stored in the status memory 112a in the RAM memory 112A and then the process proceeds to step 1307. As the search number information, the read block number is the latest block stored in step 1303. The read section number is the current number of the latest section number searched by step block 1500a, and the write section is the next section number after the read section number.

  In step 1305, it is determined whether or not the divided block preceding the latest block number stored in step 1303 is a blank block. If it is not a blank block, the determination is Yes and the process proceeds to step block 1500b. If there is, it is a determination step in which a determination of No is made and the process proceeds to step 1306b.

  Step 1306b is a step in which the searched number information is stored in the status memory 112a in the RAM memory 112A and then the process proceeds to step 1307. As the search number information, the read block number is an abnormal number indicating that the search is impossible. The read section number is an abnormal number indicating that search is impossible, and the write section is the top section number.

  Step block 1500b is a latest section search step, which will be described later with reference to FIG. 15. Here, the latest section in the divided block before the latest block stored in step 1303 is searched. Step 1306c is a step in which the searched number information is stored in the status memory 112a in the RAM memory 112A and then the process proceeds to step 1307. As the search number information, the read block number is the latest block stored in step 1303. The read section number is the current number of the latest section number retrieved by step block 1500b, and the write section is the first section of the latest block number stored in step 1303.

  In step 1307, it is determined whether all searches of the first constant area S10, the second constant area S20, and the third constant area S300 have been completed. This is a determination step in which a return shift is made, and if it is completed, a Yes determination is made and the search normal end step 1310 is entered.

  FIG. 14 is a flowchart of the latest block search processing of the nonvolatile data memory in the electronic control apparatus according to Embodiment 1 of the present invention. In FIG. 14, step 1401 is a start step of the latest block search. A subsequent step 1402 is a step in which a blank check is performed on the check area S0 of all the divided blocks 113a to 113d and then the process proceeds to step 1403a.

  In step 1403a, if all of the divided blocks 113a to 113d are blank blocks as a result of the blank check in step 1402, the process proceeds to step 1404, and if any of the divided blocks is not a blank block, No is determined. Is a determination step for performing step 1403b.

  Step 1404 is a step of storing in the status memory 112a that all blocks are blank blocks. In step 1403b, as a result of the blank check in step 1402, when all the divided blocks 113a to 113d are not blank blocks, the determination is Yes, and the process proceeds to step 1406. This is a determination step of performing step 1405.

  In step 1405, the status memory 112a stores the number of the divided block that is not blank immediately before the blank block as the latest block number. In step 1406, it is determined whether or not there is only one divided block having a predetermined fixed constant and the maximum number of batch erasures in the check area S0 of each divided block. Then, the process proceeds to step 1407, and if it does not exist, the determination of No is performed and the process proceeds to step 1408.

  Step 1407 is a step in which the status memory 112a stores the predetermined block constant and the number of the divided block that is the maximum number of batch erasures as the latest block number. Step 1408 is a step of storing in the status memory 112a that there is an abnormal state in which all the divided blocks have data and the latest block number cannot be specified. Steps 1404, 1405, 1407, or 1408 are all configured to move to a normal end step 1410.

  FIG. 15 is a flowchart of the latest section search process of the nonvolatile data memory in the electronic control apparatus according to Embodiment 1 of the present invention. In FIG. 15, step 1501 is a start step of the latest section search. In the subsequent step 1502, the number of sections N10, N20, and N300 regarding any of the data storage areas S10, S20, and S300 in the target divided block is stored in the working memory as the maximum section number, and the process proceeds to step 1503. It is a step. Step 1503 is a step in which a blank check is performed on the section with the largest stored section number to check whether the section is a valid section that is not an empty section or an invalid section, and then the process proceeds to step 1504.

  In step 1504, if the section checked in step 1503 is a valid section, if it is a valid section, Yes is determined and the process proceeds to step 1505. If it is not a valid section, No is determined and step 1505 is performed. This is a determination step for shifting to 1506. In step 1505, the section number stored in step 1503 is stored as a valid section number in the status memory 112a, and the process proceeds to the end step 1510.

  In step 1506, it is determined whether the section number stored in step 1503 exceeds the head section number. If the head section number is exceeded, Yes is determined and the process proceeds to step 1507. If NO, NO is determined and the process proceeds to step 1508. In step 1507, the value of the working memory is updated to a value obtained by subtracting “1” from the currently stored section number, and then the process returns to step 1503. In step 1503, a blank check is performed on the section having the decreased section number. It is configured to be implemented.

  In the process of cyclically executing step 1503, step 1504, step 1506, step 1507, and step 1503, if a valid section is detected, step 1504 makes a Yes determination to stop the cyclic operation, and step 1504 determines Yes. If step 1506 makes a NO determination before performing, the flow proceeds to step 1508 and the circulation operation stops. Step 1508 is a step in which the status memory 112a stores that there is no valid section, and then proceeds to the end step 1510.

  The operation start step in the control flow of FIGS. 7 to 15 described above is a subroutine program start step. When these control flows are normally completed, the original control in which the subroutine call was performed is performed. Move to the next step after the step. However, in the case of an abnormal end, an abnormal process is executed by a control flow (not shown) positioned above these control flows. For example, if all the divided blocks 113a to 113d are not blank blocks, the abnormality history information (cumulative abnormality occurrence number) of a predetermined abnormality code number is stored as specific individual data in the third constant 108a. Thus, the initialization process of the divided blocks is performed.

In addition, a supplemental description of a control flow (not shown) positioned above the individual control flows described above is as follows. First, data transfer from the image memory area 108 of the RAM memory 112A to the nonvolatile data memory 113A is controlled as follows.
(1) When initializing all the divided blocks 113a to 113d and starting writing of the first block 113a, not only the first constant 108a from the first tool 105A but also the second constant 108b stored in the image memory area 108 And the initial value of the third constant 108c can also be transferred. At this time, the second tool 106A is not connected.
(2) When the second constant 108b is transferred from the second tool 106A, only the second constant 108b is transferred, and the first constant 108a and the third constant 108c in the image memory area 108 are transferred to the nonvolatile data memory 113A. Is never transferred.
(3) When the first and second tools 105A and 106A are not connected, the first constant 108a and the second constant 108b in the image memory area 108 are not transferred to the data memory 113A, and the third constant Only 108c can be transferred.

Next, data transfer from the nonvolatile data memory 113A to the image memory area 108 of the RAM memory 112A is controlled as follows.
(1) If an “abnormal voltage drop” or “disconnection of the power supply line” of the external power supply 101A is detected at the time of power-on, or if the control power supply 109A has a form that does not have an auxiliary voltage Vup output, When the relay 102 is closed and the microprocessor 110A starts operating, the first constant area S10, the second constant area S20, and the third constant area S300 of the nonvolatile data memory 113A are transferred to the image memory area 108 of the RAM memory 112A. The latest data of the first constant 108a, the second constant 108b, and the third constant 108c are transferred.
(2) Even when the abnormal voltage drop of the external power supply 101A does not occur, the disconnection of the power supply line is not detected, and the control power supply 109A generates the normal auxiliary voltage Vup, the data in the image memory area 108 is encoded. When an error is detected, the latest data in the target data storage area is transferred from the nonvolatile data memory 113A to the image memory area 108 immediately after the power is turned on or during operation.
(3) Immediately after the power is turned on, the state of the nonvolatile data memory 113A is checked to check whether the status information stored in the status memory 112a before the power is turned off matches the newly checked status information. If they do not match, it is determined that an error has occurred in the data in the image memory area 108, and the latest data is transferred from the nonvolatile data memory 113A to the image memory area 108 immediately after the power is turned on.

  In the above description, the electronic control device 100A has been described as an in-vehicle electronic control device such as an engine control device, for example. However, the electronic control device 100A can also be applied as a dedicated control device in other generally available automation equipment. In that case, the contents of the second constant to be written by the manufacturer of the automation equipment are notified to the manufacturer of the electronic control device, and the first and second constants are collected on the electronic control device manufacturer side in the first constant area. It is also possible to store in S10 and omit the second constant area S20.

  The external power supply 101A is not a battery, but a general commercial AC power supply is used. The power supply circuit 109A can generate the control voltage Vcc from the supplied AC voltage, and the holding voltage Vup can be obtained from the built-in battery. is there. Alternatively, the data stored in the image memory area 108 of the RAM memory 112A does not have an external battery or built-in battery serving as an auxiliary power source, and is stored by the non-volatile data memory 113A during a power failure. The transfer to 108 may be restored.

(3) Main points and features of Embodiment 1 [Claim 1]
As is apparent from the above description, the electronic control device according to the first embodiment of the present invention includes a microprocessor 110A to which the input signal circuit 103 and the output signal circuit 104 are connected, and a nonvolatile program memory that cooperates with the microprocessor. 111A, a volatile RAM memory 112A, and a nonvolatile data memory 113A, an input / output control program 107A written in the nonvolatile program memory 111A, a value of a control constant stored in the nonvolatile data memory 113A, An electronic control device 100A for sending a control output signal to the output signal circuit 104 in response to a signal state of the input signal circuit 103,
The non-volatile data memory 113A is constituted by a non-volatile memory having a plurality of divided blocks 113a to 113d that can be individually erased collectively in units of blocks.
Each of the divided blocks 113a to 113d is further divided into a plurality of data storage areas S10, S20, and S300 having different write frequencies or write times.
Each of the data storage areas S10, S20, and S300 is further composed of a plurality of sections S11, S12, S21 to S24, and S301 to S320 serving as read / write units. The data capacity C10, C20, C300 of one section is the number of bytes corresponding to the number of individual data to be written.
In the plurality of sections S11, S12, S21 to S24, and S301 to S320, new data is sequentially stored in section units after batch erasing of the target divided blocks, and any of the target divided blocks is stored. When the data storage area becomes full and there are no empty sections in which no data has been written, new data is written to the first section of the corresponding data storage area of another divided block that has been erased in advance. The latest data written in the other data storage area in the divided block is transferred and stored in the head section of the corresponding data storage area in the new divided block.
The data in the original divided block is erased at least after the transfer and writing of the latest data to the new divided block is completed, and the number of sections in the data storage areas S10, S20, and S300 is N10 and N20. -N300 is assigned more sections as it is written more frequently.

[Claim 2]
Among the divided blocks 113a to 113d, the total data capacity A of the main data storage area having the largest product of the number of sections N10, N20, and N300 and the data capacity C10, C20, and C300, and the other subordinate data storage areas The ratio B / (A + B) of the total data capacity B, which is the product of the number of sections and the data capacity, is smaller than the reciprocal of the number N of the divided blocks.
As described above, in relation to the invention of claim 2 of the present application, the ratio between the total data capacity of the main data storage area and the total data capacity of other subordinate data storage areas is related to the reciprocal of the number of divided blocks. Is limited.
Therefore, when the main data storage area becomes full and moves to the next divided block, it is necessary to transfer and move the latest data in the other data storage area, but a dedicated divided block for the other data storage area. Is characterized in that the number of batch erasures for one divided block can be reduced.

[Corresponding to claim 3]
The data storage area provided in each of the divided blocks 113a to 113d of the non-volatile data memory 113A is the first / second / third constant area S10 / S20 / S300 or at least the first / third constant area S10 / S300. Sorted into multiple areas.
The first constant area S10 is a first constant that is transferred and written from the first tool 105A prepared as the shipping adjustment facility when the manufacturer of the electronic control device 100A performs the shipping adjustment of the electronic control device. This is the storage area 108a.
The first constant 108a is a control constant corresponding to the model classification of the electronic control device 100A itself, selection number information of a part of the input / output control program 107A, or a variation variation in component characteristics inside the electronic control device. It includes at least one of a calibration constant for correction and a serial number of the electronic control device.
The second constant region S20 was prepared as an inspection adjustment facility when the manufacturer or facility management department of the combined product or combined equipment in which the electronic control device 100A is incorporated performs trial operation adjustment of the combined product / equipment. This is a storage area for the second constant 108b transferred and written from the second tool 106A.
The second constant 108b is a control constant corresponding to the model name / model of the combined product / equipment in which the electronic control device 100A is incorporated, or a part of the selection number information of the input / output control program 107A, or the electronic control device 100A. At least one of calibration constants for correcting variations in the component characteristics of the input / output components connected to the.
In the third constant area S300, during the actual operation of the electronic control unit 100A, the third constant 108c stored in the RAM memory 112A is at least immediately after the operation stop of the electronic control unit 100A or during operation. This is a storage area for the third constant that is transferred and written in a timely manner.
The third constant 108c includes at least one of characteristic variation information of built-in parts or external connection parts of the electronic control unit 100A, learning information for obtaining improved operating characteristics, or abnormality occurrence history information. Yes.
As described above, in relation to the invention of claim 3 of the present application, the data storage area provided in each divided block of the nonvolatile data memory is the first, second, third constant area or at least the first, third, A plurality of constant areas are sorted, and the number of sections in each constant area and the number of bytes that is the data capacity of the section are determined in advance.
Therefore, it becomes easy to write data to each constant area empty section at different times and locations, and the writing frequency of each constant area can be easily estimated, and the number of sections and bytes of each constant area can be estimated. There is a feature that makes the decision easy.

[Corresponding to claim 4]
The data storage area provided in each divided block of the nonvolatile data memory 113A; 113B is in the first / second / third constant area S10 / S20 / S300 or the first / third constant area S10 / S300. In addition, one section S1 serving as a check area S0 is added.
In the first half area of one section S1 in the check area S0, after the block blocks 113a to 113d are collectively erased, at least one of all the data storage areas of the data storage areas S10, S20, and S300 is present. When valid data is written to one section, a predetermined fixed constant is written, and even if any one data storage area, valid data is stored in any section in the data storage area. When it is not written, it becomes a state of a blank block in which the definite constant is not written.
As described above, in relation to the invention of claim 4 of the present application, a check area is provided in each divided block of the nonvolatile data memory, and at least one data storage area in the divided block is included in the check area. Information for determining whether or not there is a written section is stored.
Therefore, in the transition process of the divided block, since the latest data is written in the entire data storage area of the next block and then the check area of the next block is written, if the check area is not blank, the entire data storage area It is confirmed that the latest data has been written in, and when there are a large number of divided blocks, the latest block can be easily searched by monitoring the contents of the check area. .

[Claim 5]
In the latter half of one section S1 in the check area S0, the batch erase count data for the divided block is written at the time when the definite constant is written, and when the divided block is transferred, The number of batch erases of the divided block is a value obtained by adding 1 to the number of batch erases written in the check area of the current divided block immediately before the transfer.
As described above, in relation to the invention of claim 5 of the present application, the batch erase count data is written in the check area in each divided block of the nonvolatile data memory.
Therefore, the lifetime management of the nonvolatile data memory can be easily performed, and among the plurality of divided blocks, it is possible to determine that the divided block having the larger number of batch erases is the latest divided block.

[Corresponding to claim 6]
In the check area S0, at least one spare section S2 is added in addition to one section S1 in which the fixed constant and the batch erase count data are written, and when the divided block is batch erased When one section S1 in the check area S0 cannot be erased, the spare section S2 is applied in place of the section that could not be erased after performing batch erase again.
As described above, in relation to the invention of claim 6 of the present application, a spare section is provided in the case where one section has an erasure defect in the check area in each divided block of the nonvolatile data memory.
Therefore, there is a feature that one whole divided block cannot be made unusable due to one section becoming defective.

[Corresponding to claim 7]
The non-volatile data memory 113A includes at least three or more divided blocks 113a to 113d, and data storage areas S10, S20, and S300 (for example, a third constant area) somewhere in the divided block 113a currently being written. If there is no empty section in S300), first, the next-order divided block 113c is collectively erased, and then the next-order divided block 113b is collectively erased as a confirmation process. New data is written in the first section of the corresponding data storage area (third constant area S300) of the block 113b, and the other data storage areas (first constant area S10 and second constant) in the original divided block 113a are written. The latest data written in the area S20) is the corresponding data storage area of the divided block 113b of the next order. Transferred to and stored in the first section of the area (first constant area S10 and second constant area S20), and when the divided blocks 113a to 113d are transferred, the divided blocks of the blank block preceding the blank block that has been erased collectively It has come to move to.
As described above, in relation to the invention of claim 7 of the present application, the nonvolatile data memory has three or more divided blocks, and at the time of transition between the divided blocks, the next-order divided blocks are preliminarily erased in advance. It is like that.
Therefore, for example, when a power failure occurs while data is being written to the next-order divided block and the power is turned on again, the next-order divided block that has been erased all at once and becomes a blank block is searched. However, it suffices to write data to the previous divided block, and by always ensuring one blank block, it is easy to search for the divided block to be written.
In addition, if the divided block for which batch erasure has not been completed becomes the next-ranked divided block, data writing is started after the batch erasure is performed as a confirmation process. There are features that can be eliminated.
Note that if the batch erased divided block is erased once again, there is no effect on the life, so the batch erase count data written to the check area is written to the check block and the data is written to the check area. When a definite constant is written, it is counted as one batch erasure.

[Corresponding to claim 8]
The nonvolatile program memory 111A includes the input / output control program 107A and a fixed constant that does not change with respect to the input / output control program, and the first constant 108a stored in the nonvolatile data memory 113A or A reference constant 107a related to the second constant 108b or the third constant 108c is stored.
The reference constant 107a includes upper and lower limit value data that is an allowable fluctuation range relating to a part of the fluctuation information in the first, second, and third constants 108a, 108b, and 108c, or a part of the learning information of the driving characteristics. , Initial setting data applied to uncertain constants among the first, second, and third constants, and the initial value setting data is divided at least before the first operation of the electronic control unit 100A is started. The first, second, and third constant areas S10, S20, and S300 in one of the blocks 113a to 113d are transferred and stored.
As described above, in relation to the invention of claim 8 of the present application, the fixed constant and the reference constant are stored in the nonvolatile program memory.
Therefore, since a fixed constant that does not change is not stored in the nonvolatile data memory, it is possible to reduce the capacity of the nonvolatile data memory and to learn characteristic variation information and operational characteristics in which the constant is determined sequentially during operation of the electronic control unit. The information has a feature that an initial set value is stored in advance in a nonvolatile data memory, and operation can be started by a suboptimal constant.
In addition, for characteristic variation information for which constants are sequentially determined during operation of the electronic control unit and learning information for operating characteristics, it is determined whether the determined constant is within a predetermined upper and lower limit value, or stored in a RAM memory. It is possible to determine whether or not an error has occurred in these constants.
Further, there is a feature that the initial value data in the reference constant can be applied as a temporary constant when some of the first and second constants are uncertain.

[Corresponding to claim 9]
The microprocessor 110A generates a batch erase command signal and a blank check command signal for the nonvolatile data memory 113A, and the nonvolatile data memory 113A that has received the blank check command has been erased at least for each section. Returns the decision information of whether or not.
The microprocessor 110A determines that the erased section is an empty section by performing batch erase.
The microprocessor 110A has a section that could not be erased even after batch erase, or a power failure occurred while writing data to the nonvolatile data memory 113A. If it is detected that a data write part and a non-write part are mixed, it is determined that the relevant section is an invalid section, and a section that is not an invalid section because data exists in the section is a valid section. It is determined that
When reading data from the nonvolatile data memory 113A, the microprocessor 110A searches the effective section from the last section to the top section of each data storage area, and reads the data stored in the effective section detected for the first time.
When the microprocessor 110A writes to the nonvolatile data memory 113A, the microprocessor 110A searches for the valid section from the last section to the top section of each data storage area, and searches for the first time from the valid section detected for the first time. Write data to the designated empty section.
As described above, in relation to the invention of claim 9 of the present application, the microprocessor determines an empty section, an invalid section, and a valid section with respect to the nonvolatile data memory, and sequentially searches from the last section of each data storage area to obtain a read section. It is configured to determine the writing section.
Therefore, even if an invalid section exists, divided blocks are not updated or erased immediately, and data is written to the next empty section without leaving an empty section. There are features that can be reduced.
Further, in the reading of the nonvolatile data memory, there is a feature that the invalid section can be excluded and the latest valid section can be read.

[Corresponding to claim 10]
When the microprocessor 110A writes to the nonvolatile data memory 113A, the microprocessor 110A searches for the valid section from the last section to the top section of each data storage area, and searches for the first time from the valid section detected for the first time. The data is written in the empty section, and if data cannot be correctly written in the empty section, the search is further performed in the reverse direction and the data is written in the newly detected empty section.
As described above, in relation to the invention of claim 10 of the present application, when a write failure occurs in each section of the nonvolatile data memory, the next section is written.
Therefore, even if there is a cell abnormality in a part of the write section, there is a feature that correct data can be written in the next section.

[Corresponding to claim 11]
The RAM memory 112A includes a status memory 112a into which data corresponding to the erase / write state of the nonvolatile data memory 113A is written.
In the status memory 112a, at least the identification number information of the latest divided blocks 113a to 113d in which writing is in progress at the present time, and the latest in each data storage area S10, S20, S300 in the latest divided block. Stores section number information in which data is written.
As described above, in relation to the invention of claim 11 of the present application, the RAM memory includes a status memory in which data corresponding to the erase / write state of the nonvolatile data memory is written.
Therefore, searching for the read section number in which the latest data is stored or searching for the write section number for writing the latest data needs to be performed only once immediately after the power is turned on. There is.

[Corresponding to claim 12]
The microprocessor 110A, the RAM memory 112A, the non-volatile program memory 111A, and the non-volatile data memory 113A include an output contact of the power supply relay 102 that is energized when the operation power switch is closed from the external power supply 101A, and a drive power supply terminal 102a. Power is supplied via
The power supply relay 102 is turned off after a predetermined delay power supply time after the power switch is opened, and the RAM memory 112A is assisted even during a period in which the drive power supply terminal 102a is not supplied with power. The power supply to the RAM memory is also cut off during the period when the power is supplied by the power supply or the drive power supply terminal 102a is not supplied.
The auxiliary power supply is an external battery 101A directly connected to the auxiliary power supply terminal 101a or a built-in battery.
Even when the power supply to the RAM memory 112A is stopped or the power supply is continued during the period when the power supply relay 102 is turned off, the voltage of the auxiliary power supply abnormally decreases or the auxiliary power supply When the circuit is shut down and the stored contents of the RAM memory 112A are lost, or when the contents of the status memory 112a are abnormal, the power supply relay 102 is energized and the microprocessor 110A is "started". Or the contents of the latest section written in at least the third data storage area S300 in the non-volatile data memory 113A during the “actual operation” of the microprocessor 110A are stored in the image memory area 108 of the RAM memory 112A. The microprocessor 110A transfers the image memo. It is configured to perform the control of the input and output on the basis of the third constant 108c that is written in the area 108.
As described above, in relation to the invention of claim 12 of the present application, regardless of the presence or absence of an auxiliary power supply for maintaining the storage state of the RAM memory, the content of the RAM memory is abnormal or the content of the RAM memory is When in doubt, the third constant stored in the nonvolatile data memory can be read and used.
Further, the learning data and abnormality occurrence history information updated and written in the RAM memory during operation can be transferred and saved to the nonvolatile data memory during the delay power feeding period of the power relay.

Embodiment 2. FIG.
(1) Detailed Description of Configuration Hereinafter, the configuration of an electronic control apparatus according to Embodiment 2 of the present invention will be described with reference to FIG. 16 which is a block diagram showing the overall configuration and FIG. 17 which is a section configuration diagram of a nonvolatile data memory. This will be described in detail. In the drawings, the same reference numerals indicate the same or corresponding parts.

  First, in FIG. 16, an electronic control unit 100B is composed mainly of a microprocessor 110B, a nonvolatile program memory 111B, a volatile RAM memory 112B, and a nonvolatile data memory 113B which is a flash memory. A special programmable controller used in the system is configured, and power is supplied from an external power supply 101B, which is a general commercial AC power supply, via a power supply relay 102. The power relay 102 is configured to close immediately when a power switch (not shown) is turned on, and to open after a predetermined delay power feeding period when the power switch is turned off.

  The input signal circuit 103 is an open / close sensor or an analog sensor connected via a connector (not shown). The input signal circuit 103 is connected to the microprocessor 110B via an input interface circuit (not shown) and an input signal bus 130. Yes. The output signal circuit 104 is an electric load such as a driving device or a display connected via a connector (not shown). The output signal circuit 104 is connected to the microprocessor 110B via an output interface circuit (not shown) and an output signal bus 140. It is connected.

  The first tool 105B is connected to the microprocessor 110B via the serial signal bus 150 at the time of shipment adjustment / inspection or maintenance / inspection of the electronic control unit 100B. It is a portable device equipped with a vessel. The second tool 106B is serially connected to the electronic control device 100B in place of the first tool 105B, and the second tool 106B is manufactured by a manufacturer of a combined product such as a facility device in which the electronic control device 100B is assembled. A keyboard that is prepared as a shipping adjustment facility at the time of shipping adjustment or that is used by the facility management department of the user who uses the electronic control device 100B at the time of installation adjustment The portable device is equipped with a display. The facility management department is in the same category as the manufacturer of the combined product, and will be described as a manufacturer of the combined product in the following description.

  The second tool 106B stores an input / output control control program 107B used in the electronic control device 100B. The input / output control program 107B uses, for example, a user language suitable for sequence control. The microprocessor 110B is configured to perform input / output control by replacing the input / output control program 107B programmed in the user language by the system program in the mask ROM memory 111b with a machine language suitable for the microprocessor 110B.

  This system program further includes a communication control program for the first tool 105B and the second tool 106B, and the microprocessor 110B uses the system program to store the first constant 108a stored in the first tool 105B in a nonvolatile manner. The data is transferred to the first constant area S10 of the data memory 113B. The microprocessor 110B also transfers the input / output control program 107B stored in the second tool 106B to the non-volatile program memory 111B by the system program by the mask ROM memory 111b and also stores the second constant stored in the second tool 106B. 108b is transferred to the second constant area S20 of the nonvolatile data memory 113B.

  The input / output control control program 107B includes fixed constants that do not change with respect to the input / output control program, and first, second, and third constants 108a and 108b described later that are stored in the nonvolatile data memory 113B. Includes a reference constant 107a associated with 108c. This reference constant 107a includes upper and lower limit value data that is an allowable fluctuation range regarding a part of the fluctuation information in the first, second, and third constants 108a, 108b, and 108c, or a part of the learning information of the driving characteristics, Initial setting data applied to uncertain constants among the first, second, and third constants, and the initial value setting data is a divided block described later at least before the first operation of the electronic control unit 100B is started. The first, second, and third constant areas S10, S20, and S300 in one of 113e and 113f are transferred and stored.

  The first tool 105B further includes a first constant 108a transferred to the non-volatile data memory 113A. The first constant 108a is a control constant or input / output corresponding to the model classification of the electronic control unit 100A itself. It is control device specific information such as a part of the selection number information of the control program 107A, a calibration constant for correcting variation in the component characteristics in the electronic control device, and the manufacturing number of the electronic control device.

  The timing for transferring the first constant 108a from the first tool 105B to the nonvolatile data memory 113B is when the transfer operation key provided in the first tool 105B is pressed or the transfer operation key. Is transferred to the RAM memory 112B, the power switch for the electronic control device 100B is opened, and is transferred from the RAM memory 112B to the non-volatile data memory 113B at the timing when delayed power feeding is performed by the power relay 102. It is configured.

  The second tool 106B includes a second constant 108b transferred to the non-volatile data memory 113B. The second constant 108b is a control constant corresponding to the model name / model of the combined product / equipment in which the electronic control device 100B is incorporated. Alternatively, it is combined product specific information such as a calibration constant for correcting variations in the component characteristics of the input / output components connected to the electronic control unit 100B. The transfer timing of the second constant 108b is when the transfer operation key of the second tool 106B is operated or when the power switch of the electronic control device 100B is shut off.

  The microprocessor 110B that performs the operation by the input / output control program 107B stored in the non-volatile program memory 111B learns to obtain characteristic variation information of internal components or external connection components of the electronic control unit 100B or improved operation characteristics. The third constant 112a such as information or abnormality occurrence history information is generated and stored in the RAM memory 112B. The non-volatile data memory 113B is a flash memory that is collectively erased in units of blocks, and includes first and second divided blocks 113e and 113f.

  Next, FIG. 17 shows a configuration in each divided block. In FIG. 17, each of the divided blocks 113e and 113f includes a check area S0 and first, second, and third constant areas S10, S20, and S300 that serve as data storage areas. The check area S0 is composed of, for example, a section S1 having a data capacity C0 of 16 bytes and a spare section S2 that is used as a substitute when the section S1 becomes abnormal.

  The first constant area S10 has a data capacity C10 of 32 bytes, for example, and is composed of sections S11 to S14 having the number of sections N10 [= 4]. The total data capacity is [C10 × N10 = 32 × 4 = 128 bytes]. The second constant area S20 has a data capacity C20 of 96 bytes, for example, and is composed of sections S21 to S28 having the number of sections N20 [= 8]. The total data capacity is [C20 × N20 = 96 × 8]. = 768] bytes.

  The third constant area S300 has a data capacity C300 of 384 bytes, for example, and is composed of sections S301 to S340 having the number of sections N300 [= 40]. The total data capacity is [C300 × N300 = 384 × 40]. = 15360] bytes.

  Each section is a minimum unit of writing / reading, a plurality of individual data is written in a predetermined order in each section, and the values of the data capacities C10, C20, and C300 of one section are written. The number of bytes corresponds to the number of individual data. Each section is added with sum data for detecting a code error or error correcting code data in addition to a plurality of individual data.

  In the second embodiment, the total data capacity of the main data storage area S300 having the largest product of the number of sections N10, N20, and N300 and the data capacity C10, C20, and C300 in the divided blocks 113e and 113f. A [= N300 × C300 = 40 × 384 = 15360] and the total data capacity B [= N0 × C0 + N10 × C10 + N20, which is the product of the number of sections and the data capacity of the other subordinate data storage areas S0, S10, S20. The ratio B / (A + B) [= 928 / (15360 + 928) = 0.057] with × C20 = 16 × 2 + 32 × 4 + 96 × 8 = 928] is smaller than the reciprocal of the number N [= 2] of the divided blocks. It has become.

  Returning to FIG. 16, the erase / write control circuit 114 receives various command signals COMn from the microprocessor 110B to control the nonvolatile data memory 113B, and sends the answer signal ANSn obtained from the nonvolatile data memory 113B to the microprocessor 110B. It is configured to reply. The contents of the command signals COM1 to COM4 and the contents of the answer signals ANS1 to ANS4 are the same as those in FIG.

  The RAM memory 112B includes an image memory area 108. The image memory 108 is used as a relay memory when transferring the first constant 108a from the first tool 105B to the nonvolatile data memory 113B, or from the second tool 106B. The third constant 108c is configured to be used as a relay memory when transferring the two constants 108b to the nonvolatile data memory 113B, or to store a third constant 108c generated during the operation of the microprocessor 110B.

  The RAM memory 112B includes a status memory 112b into which data corresponding to the erase / write state of the nonvolatile data memory 113B is written. The status memory 112b includes at least the latest write that is currently being written. The identification number information of the divided blocks 113e and 113f and the section number information in which the latest data is written in the data storage areas S10, S20, and S300 in the latest divided block are stored.

  The power supply circuit 109B is supplied with power via an output contact of the power supply relay 102 energized when the operation power switch is closed, for example, from an external power supply 101B, which is a commercial AC power supply, and the drive power supply terminal 102a. Power is supplied from the built-in battery 109b to the RAM memory 112B. When the power supply relay 102 is energized, the power supply circuit 109B generates a stabilized control voltage Vcc of, for example, DC 5V, and supplies it to the microprocessor 110B, the nonvolatile program memory 111B, the RAM memory 112B, and the nonvolatile data memory 113B. To do. When the power relay 102 is not energized, the built-in battery 109b supplies power to the RAM memory 112B as a backup power source.

  When the voltage of the built-in battery 109b serving as the auxiliary power supply is abnormally reduced during the period when the power supply relay 102 is turned off, or the auxiliary power supply circuit is disconnected and the stored contents of the RAM memory 112B are lost, or the status At least the third data storage area in the non-volatile data memory 113B when the contents of the memory 112b are abnormal, when the power relay 102 is energized and the microprocessor 110B starts operation, or during the operation of the microprocessor 110B The contents of the latest section written in S300 are transferred to the image memory area 108 of the RAM memory 112B, and the microprocessor 110B controls input / output based on the third constant 108c written in the image memory area 108.

  Actually, when the microprocessor 110B starts operation, not only the third constant 108c but also the first and second constants 108a and 108b are transferred and read from the nonvolatile data memory 113B to the RAM memory 112B, and the microprocessor 110B Control is performed while referring to the image memory area 108 of the RAM memory 112B.

  Further, as an abnormality of the status memory 112b, the identification number information of the latest divided block 113e and 113f that is currently being written is not stored, or each data storage area S10 in the latest divided block is stored. In S20 and S300, the section number information in which the latest data is written is not stored, and there are cases where bit information is mixed or missing due to a code error in the RAM memory 112B as a whole. included.

(2) Detailed Description of Action / Operation Next, the operation / action of the electronic control apparatus according to the second embodiment of the present invention will be described with a focus on differences from the first embodiment.

  First, in relation to the erasing / writing process shown in FIG. 3 described above, in the second embodiment shown in FIGS. 16 and 17, there are two divided blocks, and the first constant of one of the divided blocks. If any of the area S10, the second constant area S20, or the third constant area S300 is full (there is no empty section), the process proceeds to the other divided block. It is comprised so that.

  Therefore, even if a power failure occurs during the batch erasure of the divided blocks, the latest data is stored in the other divided block, so that valuable data is not lost. Further, the handling of the check area S0 is the same as in the case of FIGS. 1 and 2 in the first embodiment, and the definite constants and the batch are collectively written after the data writing to all the data storage areas S10, S20, S300 is completed. The number of times of erasure is written.

  Next, in relation to the search / read processing shown in FIG. 4, the latest divided block is the latest block when the number of batch erases in the check area S0 is larger, and the latest section in this latest block is shown in FIG. In the same manner as in the case of No. 4, the last section side is sequentially searched and determined. Further, the abnormality process shown in FIG. 5 is the same as that in FIGS. 16 and 17 in the second embodiment.

  On the other hand, the control program in the second embodiment corresponding to the control flow from FIG. 6 to FIG. 15 in the first embodiment is stored in the mask ROM memory 111b, and the number of divided blocks is small. As a result, the search procedure for the latest block has been changed as described above. Particularly, in the case of the first embodiment and the case of the second embodiment, the order of execution is different with respect to the entire flow of FIG.

  The flowchart of FIG. 6 is a general representation of a combination of various processes executed at different times. First, as the first processing, step 600a to step 605a, step block 700, and step 600c are executed, and the first constant 108a is transferred to the non-volatile data memory 113B. For example, data 0 is transferred as a fictitious initial setting value.

  As subsequent second processing, step 600a to step block 602b, step 603b, step 605b, step block 700, and step 600c are executed to transfer the input / output control program 107B and the second constant 108b for the nonvolatile data memory 113B. And initial value transfer processing for the second and third constants.

  Similarly, as the third processing, step 600a, step 605c, step block 700, and step 600c are executed, and the third constant 108c for the non-volatile data memory 113B is transferred. A large number of individual data are sequentially expanded and stored in the RAM memory 112B while circulating through step 605c, step 606, step 609, and step 601, and immediately after the power switch is cut off, the process block 700 collectively transfers to the nonvolatile data memory 113B. Will be transferred.

  In the above description, the RAM memory 112B is backed up by the built-in battery 109b, but does not have an external battery or built-in battery as an auxiliary power source, and the data stored in the image memory area 108 of the RAM memory 112B is nonvolatile. The power failure may be stored by the data memory 113B, and the transfer may be restored from the nonvolatile data memory 113B to the image memory area 108 at the start of operation.

  Further, the first constant 108a and the second constant 108b can always be read directly from the non-volatile data memories 113A and 113B so that the data in the image memory 108 is not used.

  In the above description, it is assumed that at least the third constant 108c in the image memory area 108 is transferred to the non-volatile data memories 113A and 113B immediately after the power switch is turned off, but the electronic control devices 100A and 100B are in actual operation. It is also possible to transfer and save the third constant 108c at the time when any abnormality occurs.

  The electronic control devices 100A and 100B include an external battery or built-in battery serving as an auxiliary power source, and a time counter for low power consumption. The electronic control devices 100A and 100B measure the elapsed time including the time when the power is shut off, and the predetermined time It is also possible to transfer and save the third constant 108c to the nonvolatile data memories 113A and 113B at intervals. In this case, the transfer save is executed in the delay power supply period after the power switch is shut off, and if the elapsed time from the previous power switch shut-off to the current power switch shut-off is short, the third constant 108c is set to be non-volatile. You may make it abbreviate | omit transfer and evacuation to data memory 113A * 113B.

(3) Main points and features of the second embodiment [corresponding to claim 1]
As is apparent from the above description, the electronic control apparatus according to Embodiment 2 of the present invention includes a microprocessor 110B to which the input signal circuit 103 and the output signal circuit 104 are connected, and a nonvolatile program memory 111B that cooperates with the microprocessor. A volatile RAM memory 112B and a nonvolatile data memory 113B, an input / output control program 107B written in the nonvolatile program memory 111B, a value of a control constant stored in the nonvolatile data memory 113B, and the input An electronic control unit 100B for sending a control output signal to the output signal circuit 104 in response to a signal state of the signal circuit 103;
The non-volatile data memory 113B is constituted by a non-volatile memory having a plurality of divided blocks 113e and 113f that can be collectively erased in units of blocks.
Each of the divided blocks 113e and 113f is further divided into a plurality of data storage areas S10, S20, and S300 having different write frequencies or write times.
Each of the data storage areas S10, S20, and S300 is further composed of a plurality of sections S11 to S14, S21 to S28, and S301 to S340 serving as read / write units. The data capacity C10, C20, C300 of one section is the number of bytes corresponding to the number of individual data to be written.
In the plurality of sections S11 to S14, S21 to S28, and S301 to S340, new data is sequentially stored in section units after batch erasure of the target divided blocks, and any of the target divided blocks is stored. When the data storage area is full and there are no empty sections in which no data is written, new data is written to the first section of the corresponding data storage area of another divided block that has been erased in advance,
The latest data written in the other data storage area in the original divided block is transferred and stored in the head section of the corresponding data storage area in the new divided block.
The data in the original divided block is erased at least after the transfer and writing of the latest data to the new divided block is completed, and the number of sections in the data storage areas S10, S20, S300 is N10. N20 and N300 are assigned more sections as the writing frequency is higher.

[Claim 2]
Among the divided blocks 113e and 113f, the total data capacity A of the main data storage area in which the product of the number of sections N10, N20, and N300 and the data capacity C10, C20, and C300 is the largest, and all other subordinate data storage areas The ratio [B / (A + B)] of the total data capacity B, which is the product of the number of sections and the data capacity, is smaller than the reciprocal of the number N of the divided blocks.
As described above, in relation to the invention of claim 2 of the present application, the ratio between the total data capacity of the main data storage area and the total data capacity of other subordinate data storage areas is related to the reciprocal of the number of divided blocks. Is limited.
Therefore, when the main data storage area becomes full and moves to the next divided block, it is necessary to transfer and move the latest data in the other data storage area, but a dedicated divided block for the other data storage area. Is characterized in that the number of batch erasures for one divided block can be reduced.

[Claim 3]
The data storage areas provided in the respective divided blocks 113e and 113f of the nonvolatile data memory 113B are the first, second, and third constant areas S10, S20, and S300, or at least the first and third constant areas S10 and S300. Sorted into multiple areas.
The first constant area S10 is first written and transferred from the first tool 105B prepared as a shipping adjustment facility at the time when the manufacturer of the electronic control device 100B performs the shipping adjustment of the electronic control device. This is a storage area for the constant 108a.
The first constant 108a is a control constant corresponding to the model classification of the electronic control device 100B itself, a calibration constant for correcting variation in component characteristics in the electronic control device, or a serial number of the electronic control device. At least one of the following.
The second constant area S20 is prepared as an inspection adjustment facility when the manufacturer or facility management department of the united product or united equipment in which the electronic control unit 100B is incorporated performs trial operation adjustment of the united product / equipment. This is a storage area for the second constant 108b transferred and written from the second tool 106B.
The second constant 108b is a control constant corresponding to the model name / model of the combined product / equipment in which the electronic control device 100B is incorporated, or a part of the selection number information of the input / output control program 107B, or the electronic control device 100B. At least one of calibration constants for correcting variations in the component characteristics of the input / output components connected to the.
In the third constant area S300, during the actual operation of the electronic control unit 100B, the third constant 108c stored in the RAM memory 112B is at least immediately after the operation stop of the electronic control unit 100B or during operation. This is a storage area for the third constant that is transferred and written in a timely manner.
The third constant 108c includes at least one of characteristic variation information of built-in parts or external connection parts of the electronic control device 100B, learning information for obtaining improved driving characteristics, or abnormality occurrence history information. Yes.
As described above, in relation to claim 3 of the present application, the data storage area provided in each divided block of the nonvolatile data memory is the first / second / third constant area or at least the first / third constant area. The number of sections in each constant area and the number of bytes as the data capacity of the section are determined in advance.
Therefore, it becomes easy to write data to each constant area empty section at different times and locations, and the writing frequency of each constant area can be easily estimated, and the number of sections and bytes of each constant area can be estimated. There is a feature that makes the decision easy.

[Corresponding to claim 9]
The microprocessor 110B generates a batch erase command signal and a blank check command signal for the nonvolatile data memory 113B, and whether or not the nonvolatile data memory 113B that has received the blank check command has been erased at least in the section unit. Is returned.
The microprocessor 110B determines that the erased section is an empty section by performing batch erase.
The microprocessor 110B has a section that could not be erased even after batch erase, or a power failure occurred while writing data to the nonvolatile data memory 113B. If it is detected that a data write part and a non-write part are mixed, it is determined that the relevant section is an invalid section, and a section that is not an invalid section because data exists in the section is a valid section. It is determined that
When reading data from the nonvolatile data memory 113B, the microprocessor 110B searches the valid section from the last section to the top section of each data storage area, and reads the data stored in the valid section detected for the first time.

When writing to the nonvolatile data memory 113B, the microprocessor 110B searches for the valid section from the last section to the top section of each data storage area, and searches for the first time from the valid section detected for the first time. Write data to the designated empty section.
As described above, in relation to the invention of claim 9 of the present application, the microprocessor determines an empty section, an invalid section, and a valid section with respect to the nonvolatile data memory, and sequentially searches from the last section of each data storage area to obtain a read section. It is configured to determine the writing section.
Therefore, even if an invalid section exists, divided blocks are not updated or erased immediately, and data is written to the next empty section without leaving an empty section. There are features that can be reduced.
Further, in the reading of the nonvolatile data memory, there is a feature that the invalid section can be excluded and the latest valid section can be read.

100A, 100B Electronic control unit COMn Command signal 101a Auxiliary power supply terminal ANSn Response signal 102 Power relay ADR Block number or section number designation 102a Drive power supply terminal WRD Write data 103 Input signal circuit RDD Read data 104 Output signal circuit 105A, 105B First Tool S0 Check area 106A, 106B Second tool S10 First constant area 107A, 107B Input / output control program S20 Second constant area 107a, 107b Reference constant S300 Third constant area 108 Image memory area 108a First constant S1 section ( Check area)
108b Second constant S2 Reserved section (check area)
108c Third constant S11 to S14 section (first constant region)
109b Built-in battery S21 to S28 section (second constant area)
110A, 110B Microprocessors S301 to S340 Section (third constant area)
111A, 111B Nonvolatile program memory 112A, 112B RAM memory 112a, 112b Status memory 113A, 113B Nonvolatile data memory 113a, 113e First block 113b, 113f Second block 113c Third block 113d Fourth block

Claims (12)

A microprocessor to which an input signal circuit and an output signal circuit are connected, a nonvolatile program memory that cooperates with the microprocessor, a volatile RAM memory, and a nonvolatile data memory, and an input / output written in the nonvolatile program memory An electronic control device for sending a control output signal to the output signal circuit in response to a control program, a value of a control constant stored in the nonvolatile data memory, and a signal state of the input signal circuit,
The non-volatile data memory is constituted by a non-volatile memory having a plurality of divided blocks that can be collectively erased in units of blocks,
Each of the divided blocks is sorted into a plurality of data storage areas having different writing frequencies or writing times,
Each of the data storage areas is composed of a plurality of sections serving as read / write units. A plurality of individual data is written in a predetermined order in the section, and the data capacity of one section is individually written. It is composed of the number of bytes corresponding to the number of data,
In the plurality of sections, new data is sequentially stored in section units after batch erasure of the target divided blocks, and any data storage area in the target divided blocks becomes full. When there is no empty section to which no data has been written, new data is written to the top section of the corresponding data storage area of another divided block that has been erased in advance,
The latest data written in the other data storage area in the original divided block is transferred and stored in the first section of the corresponding data storage area in the new divided block.
The data in the original divided block is erased at least after the transfer writing of the latest data to the new divided block is completed, and
The number of sections in the data storage area is assigned to a larger number of sections as the frequency of writing increases. The total data capacity A of the main data storage area where the product of the number of sections and the data capacity is the largest among the divided blocks, and the total data capacity B which is the product of the number of sections and the data capacity of the other subordinate data storage areas 2. The electronic control according to claim 1, wherein a ratio [B / (A + B)] of the total data capacity A and the total data capacity B is smaller than a reciprocal of the number N of the divided blocks. apparatus. The data storage area provided in each divided block of the nonvolatile data memory includes a plurality of first constant areas, second constant areas, and third constant areas, or at least a first constant area and a third constant area. The first constant area is transferred and written from a first tool prepared as a shipping adjustment facility at the time when the electronic control device manufacturer adjusts the shipping of the electronic control apparatus. Storage area for the first constant,
The first constant is used to correct variations in variation of the control constant corresponding to the model classification of the electronic control device itself, part of the input / output control program, or part characteristics inside the electronic control device. Including at least one of a calibration constant and a serial number of the electronic control unit;
The second constant area is prepared as an inspection and adjustment facility at the time when the manufacturer or facility management department of the united product or united facility in which the electronic control device is incorporated performs trial operation adjustment of the united product or united facility. This is a storage area for the second constant transferred and written from the second tool. The second constant is the type name of the combined product or equipment in which the electronic control unit is incorporated, the control constant corresponding to the model, or the input Including at least one of selection number information of a part of the output control program or a calibration constant for correcting variation in the component characteristics of the input / output components connected to the electronic control unit;
In the third constant area, during actual operation of the electronic control unit, the third constant stored in the RAM memory is transferred and written at least immediately after the electronic control unit is shut down or at an appropriate time during operation. The third constant is a storage area of the third constant, and the third constant is characteristic variation information of the internal component or external connection component of the electronic control device, learning information for obtaining improved operating characteristics, or abnormality occurrence history information. The electronic control device according to claim 1, wherein at least one of the electronic control devices is included. In addition to the first constant area, the second constant area, and the third constant area, the data storage area provided in each divided block of the non-volatile data memory has a section added as a check area. And
In the first half area of one section in the check area, after the divided blocks are collectively erased, valid data for at least one section is written in all the data storage areas of the data storage area. When a predetermined fixed constant is written at the time of loading, and no valid data is written in any section in the data storage area even in any one data storage area, 4. The electronic control device according to claim 3, wherein the electronic control device is in a blank block state in which a definite constant is not written. In the second half area of one section in the check area, the batch erase count data for the divided block is written when the definite constant is written,
When the divided block is transferred, the number of batch erases of the divided blocks after the transfer is a value obtained by adding “1” to the number of batch erases written in the check area of the current divided block immediately before the transfer. The electronic control device according to claim 4. In the check area, at least one spare section is added in addition to one section in which the definite constant and batch erase count data are written,
If one section in the check area cannot be erased when the divided block is erased at once, the spare section replaces the section that could not be erased even after performing batch erase again. The electronic control device according to claim 4, wherein: is applied. The nonvolatile data memory includes at least three divided blocks,
If there is no empty section in any data storage area in the divided block currently being written, the divided blocks of the next order are first erased at a time, and then the next order is used as a confirmation process. Erase all the divided blocks at once,
New data is written in the first section of the corresponding data storage area of the divided block of the next order, and the latest data written in the other data storage areas in the original divided block is the data of the next order. It is transferred and stored in the first section of the corresponding data storage area of the divided block,
The electronic control device according to any one of claims 4 to 6, wherein when the divided block is transferred, the divided block is transferred to a divided block of a blank block preceding a blank block that has been erased in a batch. The nonvolatile program memory includes the input / output control program and a fixed constant that does not change with respect to the input / output control program.
Reference constants related to the first constant, the second constant, or the third constant stored in the nonvolatile data memory are stored,
The reference constant includes upper and lower limit value data that is an allowable fluctuation range relating to a part of fluctuation information in the first constant, the second constant, and the third constant or a part of learning information of operation characteristics; Including at least one of initial setting data applied to an indeterminate constant among the first constant, the second constant, and the third constant;
The initial value setting data is transferred and stored in the first section of the first constant area, the second constant area, and the third constant area in one of the divided blocks at least before the first operation of the electronic control device is started. The electronic control device according to claim 3. The microprocessor generates a batch erase command signal and a blank check command signal for the nonvolatile data memory, and determines whether or not the nonvolatile data memory that has received the blank check command has been erased at least in the section unit. Reply
The microprocessor determines that the erased section is an empty section by performing batch erase,
The microprocessor has a section that could not be erased even after batch erasure, or because a power failure occurred while writing data to the nonvolatile data memory. When it is detected that a written part and an unwritten part are mixed, it is determined that the relevant section is an invalid section, and a section which is not an invalid section because data exists in the section is a valid section. And
When reading the nonvolatile data memory, the microprocessor searches the valid section from the last section to the first section of each data storage area, reads the data stored in the valid section detected for the first time,
The microprocessor searches the valid section from the last section to the top section of each data storage area when writing to the nonvolatile data memory, and searches for the first time from the valid section detected for the first time. 3. The electronic control device according to claim 1, wherein data is written in the empty section. The microprocessor searches the valid section from the last section to the top section of each data storage area when writing to the nonvolatile data memory, and searches for the first time from the valid section detected for the first time. The data is written in the empty section, and when data cannot be correctly written in the empty section, the search is further performed in the reverse direction and the data is written in the newly detected empty section. 9. The electronic control device according to 9. The RAM memory includes a status memory in which data corresponding to the erase / write state of the nonvolatile data memory is written,
In the status memory, at least the identification number information of the latest divided block that is currently being written, and the section number information in which the latest data is written in each data storage area in the latest divided block And the electronic control device according to claim 9. The microprocessor, the RAM memory, the non-volatile program memory, and the non-volatile data memory are connected via an output contact of a power supply relay and a drive power supply terminal that are energized when an operation power switch is closed from an external power source. Powered,
The power relay is de-energized after a predetermined delay power feeding time after the power switch is opened,
The RAM memory is powered by an auxiliary power source even during a period when power is not supplied to the driving power supply terminal, or power supply to the RAM memory is also interrupted during a period when power is not supplied to the driving power supply terminal,
The auxiliary power supply is an external battery directly connected to an auxiliary power supply terminal or an internal battery,
Even when the power supply to the RAM memory is stopped or the power supply is continued during the period when the power supply relay is turned off, the voltage of the auxiliary power supply is abnormally reduced, or the auxiliary power supply When the circuit is shut down and the stored contents of the RAM memory are lost, or when the contents of the status memory are abnormal, the power relay is energized and the microprocessor starts operating, or the micro The content of the latest section written in at least the third data storage area in the nonvolatile data memory during the actual operation of the processor is transferred to the image memory area of the RAM memory,
The electronic control device according to claim 11, wherein the microprocessor performs input / output control based on a third constant written in the image memory area.

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