JP4642348B2 - Data processing LSI - Google Patents

Description

  The present invention relates to a data processing LSI having a plurality of DSPs accessing the same external memory in the same package.

  In recent years, the amount of signal processing using a DSP that can digitally process voice, musical instrument sound, and audio signals has been increasing. For this purpose, measures are taken by using a DSP having a high signal processing capability or by using a plurality of DSPs.

  As shown in FIG. 10, the DSP 2c is generally used by connecting an external memory 102 for storing digital delay data. The figure shows a state where there are 64 times when the external memory 102 can be accessed in one sampling period (44.1 KHz).

  However, when the amount of delay in the external memory is small compared to the memory size, it is wasteful in capacity to connect the external memories independently, and the cost is increased. Further, when a plurality of DSPs are used, a plurality of external memories are usually required, and the number of discrete parts increases, which causes a problem in circuit design.

  The present invention was devised in view of the above problems, and by providing a data processing LSI in which a plurality of DSPs are packaged and these DSPs can share one external memory, the above problems can be solved. We are going to try to solve it.

  The second object is to provide a configuration in which such a data processing LSI can be used particularly for effect processing on musical sound waveform data stored in one external memory.

Therefore, the configuration of the present invention is as follows.
A data processing LSI having a predetermined number of memory access timings per sampling period and having a plurality of DSPs in the same package for accessing the same external memory,
The LSI
Read / write control that controls to enable the access command when there is a command from only one DSP without issuing an access command to the external memory when there are a plurality of commands from each DSP at the same timing Means,
An access determination means for controlling the DSP to perform memory access when there is a plurality of instructions from each DSP at the same timing, without accessing any DSP, and when there is an instruction from only one DSP ; ,
A first selector that outputs an address from the DSP in response to a determination signal from the access determination means;
And a second selector for outputting data from the DSP based on the determination signal,
A basic feature of the DSP is that it includes data acquisition control means for acquiring data from an external memory in response to a determination signal from the access determination means.

  According to the above configuration, when there is a read command or a write command from each DSP at the same timing, the read / write control means controls which of these commands is valid, and each of them is also at the same timing. When there is a DSP read instruction or write instruction, the access determination means determines which DSP has memory access. The first selector outputs the address from the DSP to the external memory in response to the determination signal from the access determination means, and the second selector also outputs the data from the DSP based on the determination signal. Output to external memory. On the other hand, the DSP that has performed memory access by the access determination means and has read the data receives the determination signal from the access determination means, and receives data input from the external memory by the data acquisition control means provided in the DSP. Will get. By such an action of each means, it is possible to provide a data processing LSI in which a plurality of DSPs are packaged and these DSPs can share one external memory.

The configuration of claim 2 is as follows:
A data processing LSI having a predetermined number of memory access timings per sampling period and having a plurality of DSPs in a single package for accessing one external memory for storing musical sound waveform data,
The LSI
Read / write control that controls to enable the access command when there is a command from only one DSP without issuing an access command to the external memory when there are a plurality of commands from each DSP at the same timing Means,
An access determination means for controlling the DSP to perform memory access when there is a plurality of instructions from each DSP at the same timing, without accessing any DSP, and when there is an instruction from only one DSP ; ,
A first selector that outputs an address from the DSP in response to a determination signal from the access determination means;
And a second selector for outputting data from the DSP based on the determination signal,
The DSP includes data acquisition control means for acquiring data from an external memory in response to a determination signal from the access determination means.

When musical sound waveform data is output from a plurality of channels, two or more DSPs that apply effects to the musical sound waveform data may be used depending on the number of effects to be applied (including cases of different types of effects). . Such mounting of a plurality of DSPs accompanying an increase in signal processing using DSPs is considered more rational in terms of reducing power consumption and improving processing speed when one package is used as a system LSI. Conceivable. Therefore, the configuration of claim 2 uses a configuration of a data processing LSI in which a plurality of DSPs are packaged in one package and these DSPs can share one external memory as a configuration for applying an effect to musical tone waveform data. Is provided.

According to the data processing LSI of claim 1 to claim 2, wherein the present invention, one package a plurality of DSP, moreover that the LSI is provided which these DSP can share a single external memory, the external memory It is possible to eliminate the wasted capacity, and it is possible to achieve an excellent effect that the design of a circuit that performs signal processing using a plurality of DSPs can be simplified.

In particular, as according to claim 2, for applying two or more effects to the musical tone waveform data by the DSP, if the DSP is required more than one, it is possible to avoid wasting capacity of the external memory, and the configuration is used The circuit around an electronic musical instrument or the like to be used is not complicated, and the manufacturing process can be shortened.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit schematic diagram of an electronic keyboard instrument in which the configuration of a waveform reproducing device according to the present invention is used.

  In this electronic keyboard instrument, a plurality of timbre settings can be made, but two effects that can be applied to those timbres can also be set simultaneously. There are a case where two effects are automatically determined by the tone color setting, and a case where two effects are determined by selection by the player of the effect to be added.

  As shown in FIG. 1, the electronic keyboard instrument is configured by connecting a CPU 111, a ROM 112, a RAM 113, a panel scan circuit 114a, a keyboard scan circuit 115a, a sound source 100, and an effect LSI 10 via a system bus 110. Yes. The system bus 110 is used for sending and receiving address signals, data signals, control signals, and the like.

  The CPU 111 controls the entire electronic keyboard instrument by operating according to a control program stored in the ROM 112.

  The ROM 112 stores various data referred to by the CPU 111 in addition to the control program described above.

  The RAM 113 is used for temporarily storing various data when the CPU 111 executes various processes. In the RAM 113, registers, counters, flags, and the like are defined. The main ones will be described.

  (A) Tone setting flag: Stores data for indicating from which channel the tone color generated from the sound source 100 is generated according to the setting of the operation panel 114 described later.

  (B) Effect setting flag: From a plurality of types of selectable effects, one or two main flags to be automatically set for the timbre are selected by the timbre setting, or 1 by direct selection by the performer. Or, this flag of 2 is set, and the setting data is stored.

  (C) Two-chip mode flag: This electronic keyboard instrument relates to the effect addition to the musical tone data generated from the sound source 100. When the effect is determined by the tone setting as described above or selected by the player, the CPU 111 The number of effect setting flags is confirmed by the above. If the number is two, two DSPs (DSP 2a and DSP 2b) used in the effect LSI 10 to be described later are used. You will stand (= 1). At this time, the CPU 111 refers to the 2-chip mode flag and outputs a mode switching signal (0: 1 chip mode, 1: 2 chip mode).

  An operation panel 114 is connected to the panel scan circuit 114a. The operation panel 114 includes, for example, a panel switch that can set a tone color used in a performance and can set an arbitrary effect to be output to the musical tone. In that case, a timbre setting flag is set by selecting a timbre on the operation panel 114, an effect to be added when the timbre is output is automatically selected, and the effect setting flag is set. Further, as described above, the effect setting flag is changed, the two-chip mode flag is set, and the effect LSI 10 is set to the two-chip mode by a direct operation of the player's operation panel 114 or the like. There is also. Although not shown, an LED display that displays the setting state of each switch, an LCD that displays various messages, and the like are provided.

  When the two-chip mode flag is canceled by the tone setting or the player's operation panel 114, the DSP in the effect LSI 10 is in a state where either DSP 2a or DSP 2b is used, and the effect is applied. It is possible to output a musical sound with no effect, or to output with one effect applied. When the two-chip mode flag is set by changing the tone color setting or operating the operation panel 114, two effects can be applied and output.

  The panel scan circuit 114a scans each switch on the operation panel 114 in response to a command from the CPU 111, and sets each switch to 1 bit based on a signal indicating the open / closed state of each switch obtained by the scan. Create the corresponding panel data. Each bit represents, for example, “1” indicating a switch-on state, and “0” indicating a switch-off state. This panel data is sent to the CPU 111 via the system bus 110. This panel data is used to determine whether an on event or an off event of a switch on the operation panel 114 has occurred.

  Further, the panel scan circuit 114a sends the display data sent from the CPU 111 to the LED display and the LCD on the operation panel 114. Thereby, the LED display is turned on / off according to the data sent from the CPU 111, and a message is displayed on the LCD.

  The keyboard scan circuit 115a detects key press data generated by the keyboard 115. That is, each of these keyboards 115 is provided with a two-point switch. When it is detected that an arbitrary keyboard 115 is pressed down to a predetermined depth or more, a key pressing signal of pitch data (key number) of the keyboard is detected. Are generated from the speed passing between the two-point switches, and are sent as key press data to the keyboard scan circuit 115a. As the two-point switch, an optical sensor, a pressure sensor, or other sensors that can detect that the key has been pressed down to a predetermined depth or more can be used. When the keyboard scan circuit 115 a receives key depression data from the two-point switch, it sends it to the CPU 111.

  The key depression data from the keyboard scan circuit 115a is sent by the CPU 111 to the sound source 100 corresponding to each channel with reference to the tone color setting flag on the RAM 113. At that time, the CPU 111 also refers to the effect setting flag and the two-chip mode flag, and the command for the required effect effect and the command for the required number of DSP chips (command for whether to set the two-chip mode) It is sent to the LSI 10.

  The sound source 100 uses the waveform memory 101 and performs memory access thereto. That is, a read address is generated for the waveform memory 101 to read the original data. After interpolating the read original data, multiply the envelope for each timbre generated by the same circuit, accumulate the waveform data of each timbre for the set channel, and output the waveform data to the outside. As a normal sound source configuration.

  As shown in FIGS. 1 and 2, the effect LSI 10 includes two DSPs 2 a and 2 b inside. The effect LSI 10 receives a command from the CPU 111 and applies necessary effects to the musical sound data received from the sound source 100. And output to the D / A conversion circuit 116 side.

  The command received from the CPU 111 is based on the effect setting flag and the two-chip mode flag referred to by the CPU 111. That is, at the time of panel scanning of the operation panel 114, the CPU 111 checks what effect can be applied to the output musical sound by using the effect setting flag, and prepares a command for the effect LSI 10. At this time, whether or not the effect addition processing is performed by one DSP in the effect LSI 10 or processing by two DSPs is required, and a two-chip mode flag is set. Further, when sound generation processing is actually performed, according to the setting of the two-chip mode flag, the CPU 111 instructs the effect LSI 10 whether to use two DSPs 2a and 2b or only one of them (for example, DSP 2a). After that, an effect command necessary for actual effect processing is issued.

  In the effect LSI 10, as described above, the external memory 102 is used for storing the digital delay data. However, in the two-chip mode, the two DSPs 2a and 2b share the external memory 102. . Details thereof will be described later.

  Further, the waveform data to which a desired effect is applied by the effect LSI 10 is input to the D / A conversion circuit 116, converted from digital to analog, amplified by the amplifier 117, and emitted from the speaker 118 to the outside as a musical sound.

  FIG. 2 is a schematic explanatory diagram of the internal circuit of the effect LSI 10 as described above. The effect LSI 10 includes DSPs 2 a and 2 b in the same package, and the memory access control unit 1 is used and controlled for memory access to the external memory 102.

  In the configuration of this embodiment, DSP 2a and DSP 2b having a memory access timing of 64 times per sampling period are used, and a read instruction (R1 / R2) or a write instruction (R1 / R2) output from DSP 2a and DSP 2b in the two-chip mode ( W1 / W2) is received once by the memory access control unit 1, and it is determined there which DSP chip instruction is valid, and a chip enable signal (EAcID) is output to the DSP 2a and DSP 2b. Based on this, addressing (A1 or A2) is performed on the external memory 102, and data is input / output to / from the DSP 2a or DSP 2b.

  FIG. 3 is an explanatory diagram showing a circuit configuration (indicated by a broken line in the drawing) of the memory access control unit 1 among the internal configurations of the effect LSI 10. Here, a read / write control unit 11, an access determination unit 12, an address output selector 13, and a data output selector 14 are provided.

  When there is a read instruction (R1 / R2) or a write instruction (W1 / W2) of each DSP 2a or DSP 2b at the same timing, the read / write control unit 11 controls which of these instructions is enabled. .

  That is, as shown in FIG. 4A, when either instruction (W / R) is output from both the DSP 2a and DSP 2b, or when neither instruction is output from both, it is sent to the external memory 102. Are not accessed (N after control: no access). On the other hand, when any instruction (W / R) is output from either the DSP 2a or the DSP 2b, access to the external memory 102 is validated.

  When there is a read instruction (R1 / R2) or a write instruction (W1 / W2) of each DSP 2a or DSP 2b at the same timing, the access determination unit 12 determines which DSP is to make memory access.

  In this embodiment, as shown in FIG. 3, the read instruction R1 and the write instruction W1 of the DSP 2a are input, and a NOR circuit that outputs a chip enable signal (EAcID) from the output side is constituted. As shown in FIG. 4B, when no instruction is issued from the DSP 2a side, the chip enable signal (EAcID) is output as 1, and the memory access of the DSP 2b is validated.

  On the other hand, if any instruction is issued from the DSP 2a side, the chip enable signal (EAcID) is output as 0, and the memory access of the DSP 2a is validated.

  The address output selector 13 outputs the address A1 or A2 from the DSP 2a or DSP 2b according to the chip enable signal (EAcID) from the access determination unit 12. This address is, of course, for data write address designation to the external memory 102 or data read address designation from the external memory 102.

  Similarly, the data output selector 14 outputs the data D1 or D2 from the DSP 2a or DSP 2b based on the chip enable signal (EAcID). This output data is, of course, data written to the external memory 102, and is data being processed by the DSP 2a or DSP 2b.

  FIG. 5 is a schematic explanatory diagram of the circuit configuration of the DSP 2a or DSP 2b housed in the same package among the internal configurations of the effect LSI 10. The DSP 2a or DSP 2b includes a data register 21 for temporarily storing data in the digital signal processing, an instruction RAM 22 for storing instructions sent from the CPU 111, a decoder 23 for decoding the instructions, A normal DSP configuration such as a DSP arithmetic unit 24 that performs arithmetic processing (addition / multiplication instruction, etc.) on data stored in the data register 21 in accordance with the decoded instruction is provided.

  In the configuration of the present embodiment, data acquisition that causes the data register 21 to acquire data read from the external memory 102 in response to the chip enable signal (EAcID) from the access determination unit 12 in the DSP 2a or DSP 2b. A control unit 15 is provided. Since this data acquisition is accompanied by the data read command R from the DSP itself, the read command of the decoder 23 is also input to the data acquisition control unit 15.

  FIG. 6 shows the DSP 2a and DSP 2b at 64 access timings within one sampling period (44.1 KHz) when the effect LSI 10 having the above configuration is operated in the 2-chip mode. It is explanatory drawing which shows the state of a command and the control function of the memory access control part. As shown in the figure, when any instruction (W / R) is output from either the DSP 2a or the DSP 2b at each access timing, the access to the external memory 102 is enabled, and the external memory Data is written to or read from 102.

  On the other hand, when either instruction (W / R) is output from both the DSP 2a and DSP 2b or neither instruction is output from both, the external memory 102 is not accessed (N: after control). No access).

  FIG. 7 is a flowchart showing main processing of the electronic keyboard instrument of the present embodiment. This main processing routine is started by turning on the power. That is, when the power is turned on, first, the CPU 111, the RAM 113, the scan circuits 114a and 115a, the external memory 102, and other initial processes are performed (step S101). In these initial processes, the internal hardware of the CPU 111 and the effect LSI 10 is set to an initial state, and initial values are set to registers, counters, flags, and the like defined in the RAM 113.

  When this initial process is completed, a panel scan process of the operation panel 114 described later is performed (step S102).

  Then, keyboard processing (keyboard scanning processing) of the keyboard 115 is performed (step S103). In this keyboard process, key press data corresponding to the key press of the electronic keyboard instrument is created and output to the sound source 100 described above.

  Thereafter, based on the key depression data, the sound source 100 and the effect LSI 10 are used to perform sound generation processing (and mute processing according to key release) (step S104).

  Next, other processing is performed (step S105). In this processing, processing other than those described above, pedal ON / OFF processing, MIDI processing, and the like are performed.

  Thereafter, the process returns to step S102, and the processes of steps S102 to S105 are repeated.

  FIG. 8 is a flowchart showing the procedure of the panel scan process in step S102 of FIG.

  First, the panel operation of the operation panel 114 is detected by the panel scan of the panel scan circuit 114a, and flag processing and register writing corresponding to those operations are performed (step S201).

  Here, as described above, the operation panel 114 may be used to set, for example, a tone color used in a performance or to add an arbitrary effect to an output musical tone. In that case, a timbre setting flag is set by selecting a timbre on the operation panel 114, an effect to be added when the timbre is output is automatically selected, and the effect setting flag is set.

  Further, as described above, the effect setting flag is changed, the two-chip mode flag is set, and the effect LSI 10 is set to the two-chip mode by a direct operation of the player's operation panel 114 or the like. There is also.

  Next, the CPU 111 refers to the timbre setting flag and checks whether a new timbre setting flag is set (step S202). If there is no new timbre setting or no timbre setting (step S202; N), the timbre (for example, piano timbre) designated by default is set (step S207).

  Then, the CPU 111 refers to the effect setting flag and checks whether there is an effect to be added (step S203). If there is no such effect (step S203; N), the panel scan process is terminated and the process returns to the main routine.

  On the contrary, if there is an effect that needs to be added (step S203; Y), it is further checked whether or not there are two effects (step S204). If two such effects are not necessary (step S204; N), the DSP 2a is enabled (step S208), and the process returns to the main routine.

  Conversely, if two such effects are required (step S204; Y), the partition processing of the external memory 102 is performed for the DSP 2a and the DSP 2b (step S205), and the enabling processing of the DSP 2a and the DSP 2b is further performed (step S205). Step S206). Thereafter, the process returns to the main routine.

  According to the configuration of the present embodiment described in detail above, the system LSI 10 is configured so that a DSP that applies an effect to the musical sound waveform data to be output is packaged in a single package and can share one external memory 102. In addition to reducing power consumption and improving processing speed, the capacity of the external memory 102 can be eliminated, and a circuit that performs signal processing using a plurality of DSPs can be designed. It becomes possible to simplify more.

  FIG. 9 is an explanatory diagram showing another configuration of the access determination unit 12 in FIG. As shown in the figure, all read / write instructions (RD1, RD2, W1, and W2) of the DSP 2a and DSP 2b are connected to the input side, and the read instructions (R1 / R2) of the respective DSP 2a or DSP 2b at the same timing. Alternatively, when there is a write command (W1 / W2), it is determined which DSP is to be accessed by the memory.

  As shown in the figure, there is a logic circuit configuration in which the read instruction R1 and write instruction W1 of the DSP 2a and the read instruction R2 and write instruction W2 of the DSP 2b are input, and a chip enable signal (EAcID) is output from the output side. It is used. Even in this configuration, when no instruction is issued from the DSP 2a side, the chip enable signal (EAcID) is output as 1, and the memory access of the DSP 2b is validated.

  On the other hand, if any instruction is issued from the DSP 2a side, the chip enable signal (EAcID) is output as 0, and the memory access of the DSP 2a is validated.

  Note that the data processing LSI of the present invention is not limited to the above-described illustrated examples, and it goes without saying that various modifications can be made without departing from the scope of the present invention.

1 is a circuit schematic diagram of an electronic keyboard instrument in which a configuration of a waveform reproducing device according to the present invention is used. 3 is a schematic explanatory diagram of an internal circuit of an effect LSI 10. FIG. FIG. 3 is an explanatory diagram showing a circuit configuration of the memory access control unit 1 among the internal configurations of the effect LSI 10. The control output state of the read / write control unit 11 when a read command or a write command is output from the DSP 2a and DSP 2b, and the control output state of the access determination unit 12 when a read command or a write command is output from the DSP 2a It is explanatory drawing which shows. 2 is a schematic explanatory diagram of a circuit configuration of a DSP 2a or a DSP 2b housed in the same package among the internal configurations of the effect LSI 10. FIG. When the effect LSI 10 is set to operate in the two-chip mode, it is an explanatory diagram showing the state of the instruction of each DSP 2a and DSP 2b and the control function of the memory access control unit 1 at 64 access timings within one sampling period. It is a flowchart which shows the main process of the electronic keyboard instrument of a present Example. It is a flowchart which shows the procedure of the panel scan process of step S102. It is explanatory drawing which shows the other structure of the access determination part 12 in FIG. It is explanatory drawing which shows the connection state of conventional DSP2c which connects and uses the external memory 102 for digital delay data preservation | save.

Explanation of symbols

1 Memory access controller 2a, 2b, 2c DSP
10 Effect LSI
11 Read / Write Control Unit 12 Access Determination Unit 13 Address Output Selector 14 Data Output Selector 15 Data Acquisition Control Unit 21 Data Register 22 Instruction RAM
23 Decoder 24 DSP Operation Unit 100 Sound Source 101 Waveform Memory 102 External Memory 110 System Bus 111 CPU
112 ROM
113 RAM
114 Operation Panel 114a Panel Scan Circuit 115 Keyboard 115a Keyboard Scan Circuit 116 D / A Conversion Circuit 117 Amplifier 118 Speaker

Claims (2)

A data processing LSI having a predetermined number of memory access timings per sampling period and having a plurality of DSPs in the same package for accessing the same external memory,
The LSI
Read / write control that controls to enable the access command when there is a command from only one DSP without issuing an access command to the external memory when there are a plurality of commands from each DSP at the same timing Means,
An access determination means for controlling the DSP to perform memory access when there is a plurality of instructions from each DSP at the same timing, without accessing any DSP, and when there is an instruction from only one DSP ; ,
A first selector that outputs an address from the DSP in response to a determination signal from the access determination means;
And a second selector for outputting data from the DSP based on the determination signal,
A data processing LSI, wherein the DSP includes data acquisition control means for acquiring data from an external memory in response to a determination signal from the access determination means. A data processing LSI having a predetermined number of memory access timings per sampling period and having a plurality of DSPs in a single package for accessing one external memory for storing musical sound waveform data,
The LSI
Read / write control that controls to enable the access command when there is a command from only one DSP without issuing an access command to the external memory when there are a plurality of commands from each DSP at the same timing Means,
An access determination means for controlling the DSP to perform memory access when there is a plurality of instructions from each DSP at the same timing, without accessing any DSP, and when there is an instruction from only one DSP ; ,
A first selector that outputs an address from the DSP in response to a determination signal from the access determination means;
And a second selector for outputting data from the DSP based on the determination signal,
A data processing LSI, wherein the DSP includes data acquisition control means for acquiring data from an external memory in response to a determination signal from the access determination means.

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