JP4637526B2 - Memory card and nonvolatile storage device - Google Patents

Description

  The present invention relates to a technique for improving data reliability in a memory card, and more particularly to a technique effective when applied to data error detection and correction due to interruption of data writing processing.

  As storage devices such as personal computers and multi-function terminals, for example, memory cards such as multimedia cards and CF (Compact Flash (R)) cards are widely known.

  In such a memory card, for example, if the writing process is interrupted due to power interruption, unstable system operation, or interrupt processing during data writing, etc., the write data or writing process is interrupted at the next access. There is a technique for improving the reliability of read / write data by detecting / correcting errors in the data in the range affected by redundant data such as ECC (Error Collecting Code).

As a technique for improving the reliability of read / write data in this type of memory card, for example, only small-scale data correction is executed in a memory card that is an information storage device, and large-scale error correction is performed by a host. There is a technology that, when executed on a certain information processing device, reduces the processing performance of the information processing system, minimizes the increase in cost, and improves the reliability of data without increasing the circuit scale (patent) Reference 1).
Japanese Patent Application No. 2003-030292

  However, the present inventors have found that the data correction technology in the memory card as described above has the following problems.

  That is, if a power interruption occurs during the data writing process, many errors will occur in the data. In this case, there is a problem that data correction capability by ECC or the like is exceeded and erroneous detection / correction of data occurs, which may impair the reliability of the memory card.

  An object of the present invention is to provide a technique capable of greatly improving the reliability of data by detecting occurrence of write interruption in a memory card.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention has a plurality of non-volatile memory cells, and the non-volatile memory cells are set to a plurality of threshold voltages at a certain voltage level, store non-volatile data capable of storing two or more bits of data and storing predetermined information. Memory card, and a controller for instructing operation of the non-volatile semiconductor memory based on a command issued from the outside, wherein the controller generates a bit pattern for each of a plurality of set threshold voltages. Each is provided with a pattern adding unit that writes a bit pattern corresponding to at least the threshold voltage for writing the last data as an additional pattern together with write data when writing data.

  In the present invention, when the pattern adding unit performs writing in order from a voltage having a low threshold voltage of the nonvolatile memory cell, a bit pattern corresponding to at least the highest threshold voltage is added as an additional pattern, When writing is performed in order from the voltage having the highest threshold voltage of the nonvolatile memory cell, a bit pattern corresponding to at least the lowest threshold voltage is added as an additional pattern.

  In the memory card of the present invention, the pattern adding unit writes bit patterns corresponding to all threshold voltages to which multi-value writing has been performed as write patterns together with write data.

  Further, the memory card of the present invention stores the additional pattern added by the pattern adding unit for each sector which is a data storage unit.

  Further, the memory card of the present invention detects whether the added pattern added by the pattern adding unit matches the added pattern read at the time of reading data to the controller, and confirms the validity of the read data. A pattern detection unit is provided.

  Furthermore, the memory card of the present invention includes an ECC generation unit that generates and adds an ECC code to the controller based on write data and an additional pattern added by the pattern addition unit at the time of writing.

  In the memory card of the present invention, the controller includes an ECC detection unit that checks the ECC code added by the ECC generation unit when reading data from the nonvolatile semiconductor memory.

  Furthermore, the memory card of the present invention is provided with an ECC correction unit that performs a data correction process when the ECC detection unit detects an error in the controller.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  The present invention relates to a nonvolatile memory device having a plurality of memory cells and electrically storing or erasing information and a controller, and the controller writes data to the nonvolatile memory. It is possible to issue a plurality of operation instructions including an operation instruction, and the nonvolatile memory further reduces the amount of current flowing between the source terminal and the drain terminal in a state where a predetermined voltage is applied to the gate terminal of the memory cell. A sense circuit that determines which one of the plurality of states of the corresponding memory cell is in, and a control circuit that performs control to perform a predetermined operation in accordance with an operation instruction issued by the controller. In response to the write operation instruction, the control circuit selects the first memory cell and the second memory cell from the plurality of memory cells, and the first memory cell A transition is made to one state corresponding to the write data supplied from the controller in the plurality of states, and the second memory cell is transitioned to the first state in which the state transition is completed at the end of the plurality of states. Control is performed.

  Further, in the nonvolatile memory device of the present invention, in the control for one write operation instruction, the first state in which the state transition is completed at the end of the plurality of states is set in each of the plurality of first memory cells. When the state should transition to one different state among a plurality of states, the state finally consists of a state in which the state transition is completed.

  Furthermore, in the nonvolatile memory device according to the present invention, the controller causes the data for causing the second memory cell to transition to the first state in which the state transition is completed at the end of the plurality of states together with the write data. To supply.

  In the nonvolatile memory device of the present invention, the sense circuit may change the state of the first memory cell and the second memory cell at the end of one state or a plurality of states corresponding to the write data. Is used to determine whether or not the state has transitioned to 1 state.

  Furthermore, in the nonvolatile memory device of the present invention, the control circuit selects the first memory cell and the second memory cell in accordance with the read operation instruction from the controller, and according to the state determined by the sense circuit. Whether or not the data corresponding to the state of the second memory cell is data corresponding to one state in which the state transition is completed at the end of the plurality of states. If the data does not correspond to the first state in which the state transition is completed at the end of the plurality of states, the control according to the write operation instruction is completed for the data according to the state of the first memory cell. It is determined that it is not.

  In the nonvolatile memory device of the present invention, the plurality of states of the memory cell are determined depending on which of the voltage ranges corresponding to the plurality of states the threshold voltage of each memory cell is included in. It is what is done.

  Furthermore, in the nonvolatile memory device of the present invention, in response to the read instruction, the control circuit has a plurality of voltages corresponding to each of a plurality of voltage ranges at the gate terminals of the first memory cell and the second memory cell. The sense circuit senses whether each memory cell is turned on or off, and determines the state of each memory cell.

  In the nonvolatile memory device of the present invention, the plurality of states of the memory cell have a plurality of current amounts flowing between the source terminal and the drain terminal when a predetermined voltage is applied to the gate terminal of each memory cell. It is determined depending on which of the current ranges corresponding to each of the states is included.

  Furthermore, in the nonvolatile memory device of the present invention, the control circuit applies a first voltage to the gate terminals of the first memory cell and the second memory cell in response to the read operation instruction, It senses which of the current ranges corresponding to each of the plurality of states the amount of current flowing between the source terminal and the drain terminal of the memory cell is to determine the state of each memory cell.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Since it can be determined by the additional pattern whether or not the write data has been written without any problem, erroneous detection or correction of data due to the interruption of the writing process or the like can be greatly reduced.

  (2) According to the above (1), the reliability of the memory card can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1 is a block diagram of a memory card according to an embodiment of the present invention, FIG. 2 is a block diagram of a controller provided in the memory card of FIG. 1, and FIG. 3 is a flash provided in the memory card of FIG. FIG. 4 is an explanatory diagram showing a configuration example of a memory map in the memory array of FIG. 3, and FIG. 5 is a data section provided in a data section in the memory array of FIG. FIG. 6 is an explanatory diagram showing an example of the distribution of threshold voltages of nonvolatile memory cells provided in the memory array of FIG. 3 and an additional pattern, and FIG. 7 is an explanatory diagram showing the configuration example of FIG. FIG. 8 is an explanatory diagram showing another configuration example of the memory array in the flash memory provided in the memory card, and FIG. 8 shows the distribution of the threshold voltage in the nonvolatile memory cell shown in FIG. Explanatory view showing an example of over emissions, 9 is a flowchart of read processing in the memory card of FIG. 1, FIG. 10 is a flowchart of write processing in the memory card of FIG.

  In the present embodiment, as shown in FIG. 1, the memory card 1 is configured such that a host device 2 can be connected to the outside of the memory card 1, for example, a digital video camera, a mobile phone, a portable music player. It is used as an external storage medium for the host device 2 such as a personal computer.

  The memory card 1 includes a nonvolatile memory exemplified by a flash memory (nonvolatile semiconductor memory) 3 and a controller 4. The flash memory 3 is composed of, for example, a multi-level flash memory using a multi-level storage technique for storing data of 2 bits or more.

  The flash memory 3 is composed of a nonvolatile semiconductor memory capable of electrically rewriting and erasing data. Here, the flash memory 3 is composed of one semiconductor memory, but it is sufficient if the number of the semiconductor memories is one or more.

  As shown in FIG. 2, the controller 4 includes a host side interface 5, an MPU (MicroProcessing Unit) 6, a buffer interface 7, a data buffer 8, a storage unit side interface 9, a pattern addition unit 10, a pattern detection unit 11, and an ECC detection unit. 12, an ECC generation unit 13, and an ECC correction unit 14.

  The controller 4 is connected to the host device 2 and controls the flash memory 3. The controller 4 reads out the program or data stored in the flash memory 3 and outputs it to the host device 2 or input from the host device 2. Instructions for program and data write operations.

  The host side interface 5 is an interface between the host device 2 and the MPU 6. The MPU 6 manages all the controls in the controller 4. The buffer interface 7 is an interface between the MPU 6 and the data buffer 8.

  The data buffer 8 is composed of a volatile memory such as SRAM (Static Random Access Memory), and is also used as a work area of the CPU provided in the MPU 6. The storage unit side interface 9 is an interface between the MPU 6 and the flash memory 3.

  The pattern adding unit 10 generates a pattern (bit pattern) corresponding to a plurality of threshold voltages in the nonvolatile memory cell S (FIG. 3), and writes an additional pattern (expected value) for confirming the correctness of the data as write data. Append to The pattern detection unit 11 checks the additional pattern added to the pattern addition unit 10 and the additional pattern read at the time of data reading.

  When the data is read from the flash memory 3, the ECC detection unit 12 detects an error from the ECC code generated by the ECC generation unit 13 and the data in the range to which the ECC code is added. When an error is detected, the ECC detection unit 12 Start the correction process. Further, the success / failure of the correction is detected during the correction process, and when the correction is impossible, the correction process is stopped, the fact that the correction is impossible is output to the MPU 6, and an error notification is sent to the host device 2.

  The ECC generation unit 13 generates an ECC code from the data to which the ECC is added and adds it to the data. Here, the data to which the ECC is added indicates write data and an additional pattern. When the ECC detection unit 12 detects an error, the ECC correction unit 14 performs data correction processing from the error detection result, the data, and the ECC code. Further, the error detection result need not be used during the data correction process.

  The pattern adding unit 10, the pattern detecting unit 11, the ECC detecting unit 12, the ECC generating unit 13, and the ECC correcting unit 14 are not provided as circuits, and may be replaced by firmware processing by the MPU 6, for example.

  FIG. 3 is an explanatory diagram showing a configuration example of the memory array MA in the flash memory 3.

  As shown in the figure, the memory array MA has an AND-type or NOR-type array structure in which a plurality of sub-bit lines SBL are connected to a global bit line GBL, and AG-AND (Assist Gate AND) is connected to the sub-bit lines SBL. The nonvolatile memory cells S each having a type are connected to each other.

  A voltage sense SV is connected to the global bit line GBL. The voltage sense SV detects a voltage difference of the global bit line GBL, and detects a difference in threshold voltage of the nonvolatile memory cell S by the voltage sense SV.

  A plurality of nonvolatile memory cells S connected to the word line WL can be erased collectively, and this is called a block (erase unit). When reading data, a write voltage is applied to the selected word line WL, and the data is read from the nonvolatile memory cell S connected to the word line WL via the sub bit line SBL. When data is written, the word line WL and the sub bit line SBL are selected and a voltage is applied, and the data is written to the nonvolatile memory cell S.

  FIG. 4 is an explanatory diagram showing a map configuration of the memory array MA in the flash memory 3.

  As shown in the figure, a block that is an erase unit in the memory array MA is divided into sectors that are data storage units, and a data unit D that stores user data and a management unit that stores management information for managing the block. And K, respectively.

  Further, as shown in FIG. 5, the data portion D of the block is composed of data to be written, an additional pattern added by the pattern adding portion 10, and an ECC for protecting the data. In the ECC, the data to be written and the added pattern added may be separately generated and added.

  FIG. 6 is an explanatory diagram showing an example of threshold voltage distribution and additional patterns of the nonvolatile memory cell S of FIG.

  As described above, the flash memory 3 is composed of a multi-level flash memory. A plurality of threshold voltages of a certain voltage level are set in one nonvolatile memory cell S, and data of 2 bits or more is stored.

  When the nonvolatile memory cell S has a quaternary value, the pattern adding unit 10 assigns patterns corresponding to the four threshold voltages. For example, in FIG. 6, “01”, “00”, “10”, and “11” are respectively added to the four threshold voltages in order from the top. '11' is in the erased state.

  Thereafter, the pattern adding unit 10 adds a pattern corresponding to the threshold voltage distribution to be written last to the data unit D as an additional pattern at the time of data writing. For example, when the data writing order is “01”, “00”, and “10”, “10” is added as an additional pattern.

  Further, here, a pattern corresponding to the threshold voltage distribution for the last writing is added as an additional pattern. However, as long as the additional pattern has a pattern corresponding to at least the threshold voltage distribution for the last writing. For example, a pattern corresponding to all threshold voltage distributions written in multiple values may be added as an additional pattern.

  FIG. 7 is an explanatory diagram showing another configuration example of the memory array MA in the flash memory 3.

  In this case, the nonvolatile memory cell S is formed of a NOR type, a NAND type, or the like, and as illustrated, the memory array MA includes a plurality of word lines WL and a plurality of bit lines BL, and each of the nonvolatile memory cells S is nonvolatile. The memory cell S is formed in an array by connecting a gate electrode to a corresponding word line and connecting to a corresponding data line.

  Further, a current sense SI is connected to the bit line BL, and a current difference of the bit line BL is detected by the current sense SI, and a difference in threshold voltage of the nonvolatile memory cell S is detected. Further, a plurality of nonvolatile memory cells S connected to the word line WL can be erased at once, which is called a block (erase unit).

  When reading data, a read voltage is applied to the selected word line WL, and a non-select voltage is applied to the non-selected word line WL. Data is read from the nonvolatile memory cell S connected to the selected word line WL via the bit line BL. When writing data, the word line WL and the bit line BL are selected and a voltage is applied to write data to the nonvolatile memory cell S.

  FIG. 8 is an explanatory diagram showing an example of threshold voltage distribution and additional patterns in the nonvolatile memory cell S shown in FIG.

  In this case, the threshold voltage of one nonvolatile memory cell S is a main factor that determines the amount of current sensed by the current sense SI, and the resistance of other nonvolatile memory cells S connected in series is an additional factor. More than a bit of data is stored.

  When the nonvolatile memory cell S has a quaternary value, the pattern adding unit 10 changes patterns corresponding to the four threshold voltages to “01”, “00”, “10”, “ 11 (erase state) '' is added to each.

  Then, the pattern adding unit 10 has a pattern corresponding to the threshold voltage distribution to be written last, for example, the data write order is “01”, “00”, “ In the case of “10”, “10” is added to the data part D as an additional pattern.

  Also, here, a pattern corresponding to the threshold voltage distribution for the last writing is added as an additional pattern. However, if the additional pattern has at least a pattern corresponding to the threshold voltage distribution for the last writing, added. For example, patterns corresponding to all threshold voltage distributions for multilevel writing may be added as additional patterns.

  Next, read processing in the memory card 1 according to the present embodiment will be described with reference to the flowchart of FIG.

  First, when there is a read request from the host device 2, the MPU 6 reads data from the flash memory 3, and performs an ECC check of the data read by the ECC detection unit 12 (step S101).

  If the ECC check is OK, the pattern detection unit 11 performs a pattern check that compares the additional pattern added by the pattern adding unit with the additional pattern read from the flash memory 3 (step S102).

  In the process of step S101, when the ECC check is NG, the ECC correction unit 14 tries to correct the ECC (step S103).

  In the process of step S103, if ECC correction is possible, the correction process is performed, and then the process of step S102 is performed. If ECC correction is not possible, an error notification is sent to the MPU 6 and the host device 2 and the error ends (step S104).

  In the process of step S102, if the pattern check matches, the data is valid. If the read data is user data, the data is output to the host device 2. If the read data is system data, the data is To execute the process.

  If the pattern check does not match in the process of step S102, an error notification is sent to the MPU 6 or the host device 2 and the error ends (step S104). In FIG. 9, the processing for checking the additional pattern is performed after performing the ECC check. However, the ECC checking may be performed after checking the additional pattern.

  Next, the writing process in the memory card 1 will be described using the flowchart of FIG.

  First, an additional pattern is generated by the pattern adding unit 10, and the additional pattern is added to the write data (step S201). Subsequently, the ECC detection unit 12 generates and adds an ECC code based on the write data and the additional pattern (step S202).

  Thereafter, the write data to which the ECC code is added is written to the flash memory 3, and if the write is OK (step S203), the write ends. If the writing is NG (step S203), a rewriting process or an alternative process is performed (step S204), and the process of step S203 is performed.

  In the process of step S204, the rewrite process is performed again on the same block. In the alternative process, the write process is performed on a new block. If the write is NG, the block is regarded as a defective block. Perform processing.

  As a result, according to the present embodiment, it is possible to determine whether or not the writing process has been performed to the end by the additional pattern, thereby reducing the detection of the writing interruption and the erroneous detection / correction of data. The reliability of the memory card 1 can be improved.

  In the present embodiment, the controller 4 (FIG. 2) is provided with the pattern addition unit 10, the pattern detection unit 11, the ECC detection unit 12, the ECC generation unit 13, the ECC correction unit 14, and the like. For example, as shown in FIG. 11, these functions may be provided in the flash memory 3.

  In this case, as shown in FIG. 11, the flash memory 3 includes a pattern addition unit 10, a pattern detection unit 11, an ECC detection unit 12, an ECC generation unit 13, an ECC correction unit 14, an input / output unit 15, a control circuit 16, and data. The buffer 17 and the memory array MA are included.

  The input / output unit 15 is an input / output unit for data input / output to / from the flash memory 3 and control signals. The control circuit 16 includes peripheral circuits including a sequencer, a buffer, a power supply circuit, a decoder, and the like, and controls all of the flash memory 3. The data buffer 17 is a buffer for saving write / read data.

  In this case, the ECC detection unit 12, the ECC generation unit 13, and the ECC correction unit 14 may be included in the controller 4 without being included in the flash memory 3 as a circuit. The flash memory 3 detects an additional pattern at the time of data reading by the pattern detection unit 11 and notifies the controller as a read error when the writing process has not been performed to the end. Data misdetection / correction can be reduced, and the reliability of the memory card 1 can be improved.

  On the other hand, this configuration in FIG. 11 eliminates the need to connect a controller or the like to the outside, so that the mounting area can be reduced when mounted on an embedded device such as an electronic system. Also in this case, the pattern addition unit 10, the pattern detection unit 11, the ECC detection unit 12, the ECC generation unit 13, and the ECC correction unit 14 are not provided as circuits, and may be replaced by firmware processing by the MPU 6, for example.

  In FIGS. 6 and 8 of the present embodiment, the data is written in the nonvolatile memory cell S in order from the highest threshold voltage (“01”, “00”). ',' '10' '). However, for example, as shown in FIGS. 12 and 13, when writing is performed in order from the lowest threshold voltage of the nonvolatile memory cell S, An additional pattern “P_data4” corresponding to the upper threshold voltage is added.

  Here, the pattern corresponding to the threshold voltage distribution for the last writing is added as an additional pattern, but the additional pattern only needs to add a pattern corresponding to at least the threshold voltage distribution for the last writing. For example, patterns corresponding to all threshold voltage distributions for multilevel writing may be added as additional patterns.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the additional pattern is protected by adding ECC, but the additional pattern may not be protected by ECC.

  FIG. 14 is an explanatory diagram showing a configuration example of the data portion D in the block when the additional pattern is not protected by ECC.

  As shown in the figure, the data portion D is composed of write data, ECC added to the data, and an additional pattern, and the additional pattern is outside the range of detection / correction by the ECC code.

  As a result, the data length to which the ECC is added is shortened, so that the time required for error detection and error correction can be shortened.

  Further, the pattern may be able to cope with some garbled bits. For example, if up to 1 bit is supported and the additional pattern is “Fh”, “Eh”, “Dh”, “Bh”, “7h” It shall be handled in the same way as Fh ″.

  FIG. 15 is a flowchart showing another example of the reading process in the memory card 1 when the additional pattern shown in FIG. 14 is not protected by ECC. In this case, the additional pattern is checked after the ECC check.

  First, when there is a read request from the host device 2, data is read from the flash memory 3, and a pattern check is performed by the pattern detection unit 11 (step S301).

  If the pattern checks match, the ECC check of the data read by the ECC detection unit 12 is performed (step S302). If the pattern check does not match in the process of step S301, an error notification is sent to the MPU 6 or the host device 2 and the error ends (step S303).

  If the ECC check is OK in the processing of step S302, the data is valid. If the read data is user data, the data is output to the host device 2. If the data is system data, the data is used. Execute the process.

  If the ECC check is NG in the process of step S302, the ECC correction unit 14 attempts the ECC correction (step S304), and performs the correction process if the ECC correction is possible. When ECC correction is impossible, an error notification is sent to the MPU 6 and the host device 2 and the error is terminated (step S303).

  FIG. 16 is a flowchart of data write processing in the memory card 1 when the additional pattern shown in FIG. 14 is not protected by ECC. Here, an ECC is generated and added to the write data, and an additional pattern is added to the data to which the ECC is added.

  In this case, the ECC detection unit 12 generates and adds an ECC code based on the write data and the additional pattern (step S401). Subsequently, the pattern adding unit 10 generates an additional pattern and adds the additional pattern to the write data (step S402).

  Thereafter, the write data to which the ECC code is added is written to the flash memory 3, and if the write is OK (step S403), the write is completed. If the write is NG (step S403), the rewrite process, the substitute process is performed (step S404), and the process of step S403 is performed.

  Furthermore, in the said embodiment, it was set as the structure which adds an additional pattern to the data part D (FIG. 5) in a block, For example, as shown in FIG. 17, the data part D is comprised by data and ECC, As shown in FIG. 18, an additional pattern may be added to the management unit K.

  Further, as shown in FIG. 21, the controller 4 issues a plurality of write operation instructions to the flash memory 3 so as to store a plurality of data (each 512 bytes) per block (for example, 2 Kbytes). You may comprise as follows.

  In this case, control is performed so that data 1 is written after the block is erased when data 1 is written, and additional writing is performed when data 2 to 4 are written thereafter. In this case, the additional data may be written to a location corresponding to the data n of the management unit K in addition to the data n. By reading the corresponding additional data together with the data n when reading the data, it is possible to detect in units of data whether the writing process has been interrupted.

  The configuration of the nonvolatile memory cell S in this case is shown in FIG. 19 and FIG.

  FIG. 19 is an explanatory diagram showing the configuration of the nonvolatile memory cell S in the data part D in which data and ECC are written, and FIG. 20 is a nonvolatile memory cell in the management part K in which management information and additional patterns are written. 3 is an explanatory diagram of a nonvolatile memory cell S showing a configuration of S. FIG.

  In the nonvolatile memory cell S, for example, a floating gate FG is formed on a diffusion layer composed of a source SC and a drain DN and a semiconductor substrate W between the source SC / drain DN via a tunnel film. A stacked structure in which a control CG is formed via an interlayer insulating film is formed above.

  The nonvolatile memory cell S of FIG. 19 has a structure in which the floating gate FG is formed thicker than the nonvolatile memory cell S of FIG. 20, and the data writing speed is lower than that of the nonvolatile memory cell S of FIG. It has become.

  Thus, by making the data writing speed slower than the writing speed of the management information and the additional pattern, the management information and the additional pattern are surely completed when the data writing is completed.

  This is particularly effective when the writing speed of the nonvolatile memory cell varies within the writing unit.

  The memory card of the present invention is suitable for a technique for greatly improving the reliability of data at the time of reading.

1 is a block diagram of a memory card according to an embodiment of the present invention. FIG. 2 is a block diagram of a controller provided in the memory card of FIG. 1. FIG. 2 is an explanatory diagram showing a configuration example of a memory array in a flash memory provided in the memory card of FIG. 1. FIG. 4 is an explanatory diagram showing a configuration example of a memory map in the memory array of FIG. 3. FIG. 5 is an explanatory diagram illustrating a configuration example of a data portion provided in a data portion in the memory array of FIG. 4. FIG. 4 is an explanatory diagram showing an example of threshold voltage distributions and additional patterns of nonvolatile memory cells provided in the flash memory of FIG. 3. FIG. 7 is an explanatory diagram showing another configuration example of the memory array in the flash memory provided in the memory card of FIG. 1. FIG. 8 is an explanatory diagram showing an example of threshold voltage distribution and additional patterns in the nonvolatile memory cell shown in FIG. 7. 3 is a flowchart of a reading process in the memory card of FIG. 2 is a flowchart of a writing process in the memory card of FIG. FIG. 6 is a block diagram of a flash memory according to another embodiment of the present invention. FIG. 6 is an explanatory diagram showing another example of threshold voltage distribution and additional patterns of nonvolatile memory cells provided in the flash memory of FIG. 1. FIG. 8 is an explanatory diagram showing another example of threshold voltage distribution and additional patterns in the nonvolatile memory cell shown in FIG. 7. It is explanatory drawing which shows the structure of the data part when the additional pattern by other embodiment of this invention is not protected by ECC. It is a flowchart of the read-out process in the memory card in FIG. It is a flowchart of the write-in process in the memory card in FIG. It is explanatory drawing which shows the structural example in the block by other embodiment of this invention. It is explanatory drawing which shows the structural example in the block following FIG. FIG. 18 is an explanatory diagram illustrating a configuration example of a nonvolatile memory cell in the data portion of FIG. 17. It is explanatory drawing which shows the structural example of the non-volatile memory cell in the management part of FIG. It is explanatory drawing which shows the other structural example in the block of the flash memory by other embodiment of this invention.

Explanation of symbols

1 Memory card 2 Host device 3 Flash memory (nonvolatile semiconductor memory)
4 Controller 5 Host side interface 6 MPU
7 buffer interface 8 data buffer 9 storage unit side interface 10 pattern addition unit 11 pattern detection unit 12 ECC detection unit 13 ECC generation unit 14 ECC correction unit 15 input / output unit 16 control circuit 17 data buffer MA memory array GBL global bit line SBL subbit Line S Non-volatile memory cell SV Voltage sense D Data part K Management part WL Word line BL Bit line SI Current sense SC Source DN Drain W Semiconductor substrate FG Floating gate CG Control

Claims (17)

A plurality of threshold voltages of a certain voltage level, a plurality of nonvolatile memory cells storing two or more bits of data, a nonvolatile semiconductor memory capable of storing predetermined information, and an externally issued command A memory card having a controller for instructing operation of the nonvolatile semiconductor memory based on
The controller is
Arbitrary bit patterns are assigned to each of the set threshold voltages, and at the time of data writing, a pattern that writes at least the bit pattern corresponding to the threshold voltage that becomes the last data writing as an additional pattern is added along with the write data Memory card characterized by comprising a portion. The memory card according to claim 1,
The pattern adding unit is
When writing in order from the lowest threshold voltage of the nonvolatile memory cell, a bit pattern corresponding to at least the highest threshold voltage excluding the threshold voltage in the erased state is added as an additional pattern. When writing in order from the highest threshold voltage of the nonvolatile memory cell, a bit pattern corresponding to at least the lowest threshold voltage excluding the threshold voltage in the erased state is added as an additional pattern. A memory card characterized by The memory card according to claim 1 or 2,
The pattern adding unit is
A memory card, wherein a bit pattern corresponding to all threshold voltages written in multiple values is written together with write data as an additional pattern. The memory card according to any one of claims 1 to 3,
The memory card, wherein the additional pattern added by the pattern adding unit is stored for each sector as a data storage unit. The memory card according to any one of claims 1 to 4,
The controller is
A memory comprising a pattern detection unit that detects whether or not the additional pattern added by the pattern addition unit matches the additional pattern read at the time of reading data, and confirms the validity of the read data card. The memory card according to any one of claims 1 to 5,
The controller is
A memory card comprising an ECC generation unit that generates and adds an ECC code based on write data and an additional pattern added by the pattern addition unit at the time of writing. The memory card according to claim 6, wherein
The controller is
A memory card comprising: an ECC detection unit that checks an ECC code added by the ECC generation unit when reading data from the nonvolatile semiconductor memory. The memory card according to claim 6 or 7,
The controller is
A memory card comprising an ECC correction unit for performing a data correction process when the ECC detection unit detects an error. A non-volatile memory having a plurality of memory cells and electrically writing or erasing information; and a controller;
The controller can issue a plurality of operation instructions including a write operation instruction to the nonvolatile memory;
The non-volatile memory is further in one of a plurality of states of the memory cell depending on the amount of current flowing between the source terminal and the drain terminal when a predetermined voltage is applied to the gate terminal of the memory cell. And a control circuit that performs control to perform a predetermined operation in accordance with an operation instruction issued by the controller,
In response to a write operation instruction from the controller, the control circuit selects a first memory cell and a second memory cell from the plurality of memory cells, and selects the first memory cell from the plurality of states. Control to change to the one state corresponding to the write data supplied from the controller, and to change the second memory cell to the one state in which the state transition is completed at the end of the plurality of states. Nonvolatile storage device to perform. The nonvolatile memory device according to claim 9,
One state in which the state transition is completed at the end of the plurality of states is one in which each of the plurality of first memory cells is different from each other in the control for one write operation instruction. A non-volatile memory device characterized by being in a state where the state transition is finally completed when the state should be transitioned to The nonvolatile memory device according to claim 9 or 10,
The controller supplies, together with the write data, data for causing the second memory cell to transition to one state in which the state transition is completed at the end of the plurality of states. Storage device. The non-volatile memory device according to claim 9,
The sense circuit transitions to a state in which each of the first memory cell and the second memory cell is in a state corresponding to the write data or a state in which a state transition is completed at the end of a plurality of states. A non-volatile storage device, characterized in that it is used to determine whether or not it has been performed. The non-volatile memory device according to any one of claims 9 to 12,
In response to a read operation instruction from the controller, the control circuit selects the first memory cell and the second memory cell, and supplies data corresponding to the state determined by the sense circuit to the controller. And
The controller determines whether or not the data corresponding to the state of the second memory cell is data corresponding to one state in which the state transition is completed at the end of the plurality of states, If the data does not correspond to the state 1 at which the state transition is completed at the end of the states, the control according to the write operation instruction is not completed for the data according to the state of the first memory cell. A non-volatile storage device, characterized by: The nonvolatile memory device according to any one of claims 9 to 13,
The plurality of states of the memory cell are determined depending on which of the voltage ranges corresponding to each of the plurality of states is included in the threshold voltage of each memory cell. apparatus. The non-volatile memory device according to claim 14.
In response to the read instruction, the control circuit applies 1 of a plurality of voltages corresponding to each of the plurality of voltage ranges to the gate terminals of the first memory cell and the second memory cell, and A non-volatile memory device, wherein the sense circuit senses whether each memory cell is turned on or off, and determines a state of each memory cell. The non-volatile memory device according to any one of claims 9 to 15,
The plurality of states of the memory cells are such that when a predetermined voltage is applied to the gate terminal of each memory cell, the amount of current flowing between the source terminal and the drain terminal is a current range corresponding to each of the plurality of states. A non-volatile memory device, which is determined depending on which of them is included. The non-volatile memory device according to claim 16.
In response to the read operation instruction, the control circuit applies a first voltage to the gate terminals of the first memory cell and the second memory cell, and the sense circuit has a source terminal and a drain of each memory cell. A non-volatile memory device, wherein the state of each memory cell is determined by sensing which of the current ranges corresponding to each of the plurality of states is included in the amount of current flowing between the terminals.

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