JP4619393B2 - Program method for ferroelectric memory device - Google Patents

Description

  The present invention relates to a method for programming a ferroelectric memory device, and more particularly, to adjust the capacitance of a capacitor connected to a driving power source by using a programmable register device that can program an output signal by a signal applied from outside. A ferroelectric memory device including a redundant address decoder, wherein the reference voltage level can be adjusted by controlling on / off of the switch, and the programmable register device is used as an on / off control device of a redundant address program switch. It relates to the programming method.

In general, a ferroelectric memory, that is, a FRAM (Ferroelectric Random Access Memory) has a data processing speed as high as that of a DRAM (Dynamic Random Access Memory), and can store data even when the power is turned off. It is attracting attention as.
The FRAM is a memory element having a structure almost similar to that of a DRAM, and uses a ferroelectric material as a capacitor material and utilizes high remanent polarization which is a characteristic of the ferroelectric material. Even if the electric field is removed by such remanent polarization characteristics, data is not lost.

  FIG. 1 is a diagram showing a hysteresis loop of a general ferroelectric substance. As shown in FIG. 1, it can be seen that the polarization induced by the electric field does not disappear due to the residual polarization or the presence of polarization even when the electric field is removed, and maintains a certain amount (d, a state). . The ferroelectric memory cell is applied to a memory element with the d and a states corresponding to 1 and 0, respectively.

  FIG. 2 is a diagram showing a unit cell of the ferroelectric memory. As shown in FIG. 2, a bit line BL is formed in one direction, a word line WL is formed in a direction crossing the bit line, and the word line is spaced in the same direction as the word line. The plate line PL is formed, the transistor T1 is formed such that the gate is connected to the word line, the source is connected to the bit line, the first terminal of the two terminals is connected to the drain of the transistor T1, and the first The ferroelectric capacitor FC1 is formed so that the terminal 2 is connected to the plate line (see, for example, Patent Document 1).

The data input / output operation of such a ferroelectric memory device is as follows. FIG. 3A is a timing chart showing a write operation of the ferroelectric memory element. FIG. 3B is a timing chart showing the read mode operation.
Explaining the write operation shown in FIG. 3A, the chip enable signal CSBpad applied from the outside is activated from high to low, and at the same time, the write mode starts when the write enable signal WEBpad is applied from high to low. Is done. Next, when address decoding is started in the write mode, a pulse applied to the corresponding word line transitions from “low” to “high” to select a cell.
In order to write a logic value “1” to the selected cell, a “high” signal is applied to the bit line, a “low” signal is applied to the plate line, and a logic value “0” is written to the cell. Applies a “low” signal to the bit line and a “high” signal to the plate line.

Next, the read operation shown in FIG. 3B will be described. When the chip enable signal CSBpad is externally activated from “high” to “low”, all the bit lines are equipotentialized to “low” voltage by the equalize signal before the corresponding word line is selected.
Then, after deactivating each bit line, the address is decoded, and the “low” signal is changed to the “high” signal in the corresponding word line according to the decoded address to select the corresponding cell. A “high” signal is applied to the plate line of the selected cell, and the data Qs corresponding to the logic value “1” stored in the ferroelectric memory is destroyed. If the logic value “0” is stored in the ferroelectric memory, the corresponding data Qns is not destroyed.
The data thus destroyed and the data not destroyed are outputted with different values according to the above-described hysteresis loop principle, and the sense amplifier senses a logic value “1” or “0”. . That is, the case where the data is destroyed corresponds to the case where the data changes from d to f as in the hysteresis loop of FIG. 1, and the case where the data is not destroyed corresponds to the case where the data changes from a to f.
Therefore, when the sense amplifier is enabled after a certain time has elapsed, if the data is destroyed, it is amplified and outputs a logic value “1”, and if the data is not destroyed, it is amplified and the logic value “0” is output. Output. In this way, after the data is amplified by the sense amplifier, it must be restored to the original data, so the plate line is deactivated from “high” to “low” with the “high” signal applied to the corresponding word line. Make it.
Japanese Patent Laid-Open No. 11-121705

  The conventional reference voltage generator has a problem that the level of the output voltage is fixed at the same time as production. Furthermore, in the conventional redundancy processing method using metal / polysilicon wiring, a means such as laser cutting of the fuse is used. Since it is physically removed by using it, there is a problem that it cannot be recovered again if it is handled by mistake.

The present invention has been made to solve the above-described problems of the prior art. The output signal can be programmed by an externally applied signal, and the program result is retained even without a power source. A reference generating device capable of adjusting the level of a reference voltage by controlling on / off of a switch that adjusts the capacitance of a capacitor connected to a driving power source using a programmable register device is disclosed.
Furthermore, a switch and a programmable register device that controls the switch are introduced into the redundancy process, and the redundant address decoder is programmed by a software method so that even if the program is wrong, it can be easily recovered.

  In order to solve the above problems, the level of the output signal can be programmed by an externally applied signal, and a capacitor connected to a driving power source using a programmable register device that retains a program result without a power source. A reference generator for adjusting the level of a reference voltage by controlling on / off of a switch that adjusts the capacity of the memory, and a redundant decoder that uses the programmable register device as an on / off control device for a switch for a redundant address program A method for programming a ferroelectric memory device includes: a first step of decoding a signal input to a signal input unit; a program mode corresponding to the program mode when a predetermined program mode is indicated as a result of the decoding Activate the operation signal However, it is desirable to include a third step of performing a second step of deactivating the signal input unit, and a program mode in response to the program mode operation signal.

  The program modes may include a row redundancy program mode, a column redundancy program mode, and a reference level program mode.

  The low redundancy program mode is preferably activated when the output enable signal toggles N times while the chip enable signal is deactivated and the write enable signal is deactivated.

  The column redundancy program mode is preferably activated when the output enable signal toggles N times while the chip enable signal is deactivated and the write enable signal is activated.

  The reference program mode is preferably activated when the write enable signal toggles N times while the chip enable signal is deactivated and the output enable signal is activated.

  In the present invention, the reference voltage can be variously adjusted by applying a programmable register device to the reference generator, and the programmable register device is used as a means for controlling on / off of a switch for programming a redundant decoder. Even if the address of the redundant cell is erroneously decoded, it can be remedied again, so that the reliability and yield of the chip can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 4 is an overall schematic diagram of a ferroelectric memory device according to the present invention.
The reference voltage generator provides a reference voltage to the sense amplifier. The sense amplifier compares the voltage output from the bit line of the cell array with the reference voltage during the read operation, and outputs data corresponding to the logic level of the cell data via the data I / O buffer. The sense amplifier compares the voltage of the signal input from the data I / O buffer with the reference voltage during the write operation and provides data corresponding to the input signal to the bit line of the cell.

FIG. 5 shows the cell array structure shown in FIG.
Each column in the cell array compares the main bit line pool up control unit, the cell array, the column selection control unit, the column redundancy cell array, the row redundancy cell array, and a predetermined critical voltage with the detected power supply voltage, and determines the driving voltage based on the comparison result. A drive voltage generator (not shown) that can adjust the level is included.
The cell array includes one or more main bitline load control units and a plurality of subcell blocks.

Each component will be described below.
FIG. 6 is a diagram illustrating a main bit line pool up control unit.
The main bit line pool up control unit includes a PMOS transistor having a gate connected to a control signal MBPUC, a source connected to VPP or VCC, and a drain connected to the main bit line.
The main bit line pool up control unit plays a role of pooling up the main bit line to a “high” level during “precharge”.

FIG. 7 is a diagram illustrating a main bit line load control unit.
The main bit line load control unit includes a PMOS transistor having a gate to which a control signal MBLC is input, a source connected to VPP or VCC, and a drain connected to the main bit line.
When the control signal MBLC is activated, the main bit line load controller serves as a load for the main bit line MBL. The sense voltage of the main bit line MBL is determined by the load resistance and current level of the main bit line MBL.
One or more main bit line load control units are connected to each main bit line. When two or more main bitline load control units are connected, each main bitline load control unit is uniformly arranged for each of a plurality of subcell blocks.

FIG. 8 is a diagram showing a column selection control unit according to the present invention.
The column selection control unit is configured by a switch that is turned on / off by column selection control signals CSN and CSP and connects the main bit line MBL and the data bus.

FIG. 9 is a diagram illustrating a main bitline load control unit and a subcell block according to the present invention.
The sub cell block includes a sub bit line SBL in which a plurality of unit memory cells connected to a word line WL <m> and a plate line PL <m> are commonly connected, and a first end of the sub bit line SBL is connected to a gate. A current adjusting NMOS transistor N1 having a drain connected to the main bit line MBL; a control signal MBSW connected to the gate; a drain connected to the source of the current adjusting NMOS transistor N1; and a source grounded. N2, the gate is connected to the control signal SBPD, the drain is connected to the second end of the sub bit line SBL, the source is connected to the grounded NMOS transistor N3, the gate is connected to the control signal SBSW2, and the drain is connected to the sub bit line SBL. Connected to the second end of the The NMOS transistor N4 is connected to the control signal SBPU, and the control signal SBSW1 is connected to the gate, the drain is connected to the main bit line MBL, and the source is connected to the second end of the sub bit line SBL. Has been.

  When approaching a specific cell, only one sub bit line is connected to the main bit line by activating only the NMOS transistor N5 included in the sub cell block including the specific cell. Accordingly, the bit line driving load is reduced to the level of the driving load of one sub bit line SBL.

When the SBPD signal, which is a control signal for the pool down NMOS transistor N3, is activated, the sub bit line SBL pools down the potential of the sub bit line SBL to the ground level.
The SBPU signal is a signal for adjusting the power supply voltage supplied to the sub bit line SBL. When a “high” voltage is required at a low voltage, a voltage higher than the VCC voltage is generated and supplied.
SBSW1 and SBSW2 are control signals for adjusting the signal flow between the SBPU and the sub bit line SBL. A plurality of unit cells are connected to the sub bit line SBL.

  The sub bit line SBL is connected to the gate of the NMOS transistor N1 to adjust the sensing voltage of the main bit line MBL. The source terminal of the NMOS transistor N1 is connected to the drain of the NMOS transistor N2 whose gate is connected to the control signal MBSW.

FIG. 10 is a configuration diagram of a circuit for outputting the reference voltage REF (n) included in the reference voltage generator according to the present invention.
The reference voltage generator has a gate grounded, a source connected to the positive power supply VCC, a PMOS transistor P1, a gate grounded, a source connected to the positive power supply VCC, and a drain connected to the drain of the PMOS transistor P1. The reference level control signal REFSN is input to the PMOS transistor P2, the gate, the NMOS transistor N1 connected to the drain of the PMOS transistor P1, the gate connected to the positive power supply VCC, and the drain connected to the source of the NMOS transistor N1. The source is connected to the grounded NMOS transistor N2, the gate is supplied with the control signal MBLPU_CON, the source is connected to the positive power supply VCC, the PMOS transistor P3, the PMOS transistor P1 drain and the PMOS transistor. An on-state switch S1 connected between the drain of the transistor P3 and a capacitor C1 connected between the drain of the PMOS transistor P3 and the ground, and the reference voltage REF (n) is derived from the drain of the PMOS transistor P3. Is output.

The reference voltage generator includes constituent elements corresponding to the constituent elements of the subcell block in order to implement operating conditions similar to those of the subcell block according to the present invention.
The two PMOS transistors P1 and P2 correspond to a main bit line load control unit, and the PMOS transistor P3 corresponds to a main bit line pool up control unit. The NMOS transistor N2 corresponds to the NMOS transistor of the subcell block, N2 shown in FIG. The sensing voltage of the sub bit line SBL corresponds to the reference level control signal REFSN, and the NMOS transistor N1 corresponds to the NMOS transistor N1 of the sub cell block shown in FIG. The switch S1 corresponds to the column selection control unit of each block. All the elements are configured to have the same size as the corresponding part of the subcell block, and an NMOS capacitor element C1 is added to adjust the RC delay.

FIG. 11 is a diagram illustrating a reference program unit for generating a reference level control signal REFSN provided to the reference voltage output unit illustrated in FIG.
The reference program unit is a drive voltage unit (not shown) that pumps the power supply voltage to provide the drive voltage REF_PL, the gate of the control signal REF_EQ is input, the source is grounded, the NMOS transistor 114, the drain of the NMOS transistor 114, A plurality of ferroelectric capacitors 111 connected to the output line of the driving voltage generator, and a capacitance adjustment that adjusts the capacitance between the drain of the NMOS transistor 114 and the output line of the driving voltage generator. Part 112 is included.

The capacitance adjustment unit 112 includes a plurality of pairs of a ferroelectric capacitor and a switch 113 connected in series between the drain of the NMOS transistor 114 and the output line of the drive voltage generation unit.
The switch is controlled on and off by the programmable register device, but the output of the programmable register device can be programmed by controlling the input signal, and the result of the program can be retained and read again without power it can.
By controlling the input signal of the programmable register device, the capacitance between the output line REF_PL of the driving voltage unit and the NMOS transistor 114 is adjusted, thereby adjusting the reference level control signal REFSN. The reference voltage is adjusted by a reference level control signal REFSN.

FIG. 12 is a circuit diagram illustrating a drive voltage generation unit that supplies the drive voltage REF_PL to the reference program unit illustrated in FIG. 11.
The driving voltage generator has a level output from the power supply voltage pumping unit 121 in response to an external control signal REF_PL_CON and a power supply voltage pumping unit 121 that pumps and outputs the power supply voltage if the power supply voltage is equal to or lower than a predetermined voltage. A level shifter 122 that outputs a voltage or a ground level voltage is included.

  The power supply voltage pumping unit 121 is a NAND gate that outputs a “low” signal when the control signal VCC_Limit activated when the power supply voltage is lower than a predetermined level and the control signal REFVPP_CON instructing the power supply voltage pumping are all activated. An inverter chain composed of an odd number of inverters connected to the output part of the NAND gate, an NMOS capacitor NC whose first electrode is connected to the output part of the inverter chain, and a source connected to the positive power supply voltage The PMOS transistor P1 has a drain connected to the second electrode of the NMOS capacitor, a gate connected to the output of the NAND gate, a source connected to the second electrode of the NMOS capacitor, and a drain connected to the gate of the PMOS transistor P1. Connected PMOS transistor P2, Fine gate connected to the output of the NAND gate, the source is grounded, the drain is composed of NMOS transistors N1 connected to the drain of the PMOS transistor P2.

When the power supply voltage VCC is equal to or higher than the critical voltage, the control signal VCC_Limit becomes “low” level to suppress the pumping operation. When this signal becomes “low” level, the output of the NAND gate becomes “high”, the transistor N1 and the transistor P1 are turned on, and the output voltage becomes VCC.
When the power supply voltage VCC is equal to or lower than the critical voltage, the control signal VCC_Limit becomes “high” and the pumping operation is performed according to the control signal REFVPP_CON.

When the control signal REF_CON changes from “low” to “high”, the output of the NAND gate changes from “high” to “low”.
Due to the inverter chain, a pulse transitioning from “low” to “high” is delayed and transmitted to the NMOS capacitor.
When the “high” pulse reaches the NMOS capacitor, all of the transistors N1 and P1 are already turned off, so that a voltage pumped to the NMOS capacitor is output to both ends of the NMOS capacitor.

  The level shifter unit 122 includes a PMOS transistor P3 whose source is connected to the second electrode of the NMOS capacitor, a gate connected to the drain of the PMOS transistor P3, a source connected to the second electrode of the NMOS capacitor, and a drain connected to the PMOS. The PMOS transistor P4 connected to the gate of the transistor P3, the external signal REF_PL_CON is input to the gate, the drain is connected to the drain of the PMOS transistor P3, the source is the grounded NMOS transistor N2, and the gate is opposite to the external signal REF_PL_CON. The level signal is input, the drain is connected to the drain of the PMOS transistor P4, the source is grounded, the NMOS transistor N3, the gate is connected to the drain of the NMOS transistor, and the source is the above-mentioned A PMOS transistor P5 connected to the output line of the source voltage pumping unit, and an NMOS transistor N4 having a gate connected to the drain of the NMOS transistor N2, a source grounded, and a drain connected to the drain of the PMOS transistor P5. . The drive voltage REF_PL is output from the drain of the NMOS transistor N4.

  When the control signal REF_PL_CON is at the “low” level, the transistors N3, P3, and N4 are turned on, so that the output voltage REF_PL becomes “low”. When the control signal REF_PL_CON is at the “high” level, the transistors N2, P4, and P5 are turned on, and the output voltage REF_PL becomes the power supply voltage or the pumped power supply voltage.

FIG. 13 is a timing diagram for generating a reference voltage. The reference charge is charged in the ferroelectric capacitor in the period t1, and the reference voltage REF (n) is generated in the period t2.
In the interval t2, the level of the reference level control signal REFSN is determined by the capacitance, and the level of the reference voltage REF (n) is determined according to the level of the reference level control signal REFSN.
As the reference level control signal REFSN increases, the current flowing through the NMOS transistor N1 in FIG. 10 increases, so that the voltage drop in the PMOS transistors P1 and P2 increases and the reference voltage REF (n) decreases.

FIG. 14 is a block diagram of a programmable register device according to the present invention.
The programmable register device according to the present invention includes a first amplifier, an input unit, a storage unit, and a second amplifier.
The first amplifier and the second amplifier operate when the control signals ENP and ENN are activated. The first amplifier and the second amplifier fix the voltages of the two electrodes connected to the storage unit to a certain value, or amplify the signal stored in the storage unit and output the amplified signal to the external P_CON and N_CON. Play a role.

When the control signal ENW is activated, the input unit supplies a constant voltage to the two electrodes connected to the storage unit according to the input signals SET and RESET, and the supplied signal is as described above. Are fixed by the first and second amplifiers. However, when the control signal ENW is deactivated, the two electrodes connected to the storage unit are separated from the input signals SET and RESET.
The storage unit stores an input signal and holds the signal without a power source so that the stored signal can be output later. In the present invention, a ferroelectric capacitor is used as a storage means so that written information can be held even when the power is turned off.

Each component of the programmable register device will be described in detail with reference to FIG.
The first amplifier has a PMOS transistor P1 whose gate is connected to a positive power source and a source connected to a positive power source, a gate connected to the first electrode of the first amplifier, and a source connected to the drain of the PMOS transistor P1. PMOS transistor P2 having a drain connected to the second electrode of the first amplifier, a gate connected to the second electrode of the first amplifier, a source connected to the drain of the PMOS transistor P1, and a drain. Is composed of a PMOS transistor P3 connected to the first electrode of the first amplifier.

  The input unit receives an AND operation result of the first input signal SET and the control signal ENW in the gate, the drain is connected to the first electrode of the first amplifier, and the source is grounded in the NMOS transistor N3, the gate The result of NAND operation of the first input signal SET and the control signal ENW is input to the PMOS transistor P4 whose drain is connected to the second electrode of the first amplifier and the source is connected to the positive power supply VCC, and to the gate. The result of NAND operation of the second input signal RESET and the control signal ENW is input, the drain is connected to the first electrode of the first amplifier and the source is connected to the positive power supply VCC, and the gate The result of ANDing the second input signal RESET and the control signal ENW is input to the second electrode, and the drain is connected to the second electrode of the first amplifier. Formation has been the source is an NMOS transistor N4 which is grounded.

  In the storage unit, the control signal CPL is input to the first electrode, the second electrode is connected to the first electrode of the first amplifier, the ferroelectric capacitor FC1, and the control signal CPL is input to the first electrode. The ferroelectric capacitor FC2 in which the second electrode is connected to the second electrode of the first amplifier, the first electrode is connected to the first electrode of the first amplifier, and the second electrode is grounded The ferroelectric capacitor FC3, and the ferroelectric capacitor FC4 having the first electrode connected to the second electrode of the first amplifier and the second electrode grounded.

The second amplifier includes an NMOS transistor N5 having a gate connected to the second electrode of the first amplifier, a drain connected to the first electrode of the first amplifier, and a gate connected to the first amplifier of the first amplifier. The NMOS transistor N6 is connected to the electrode, the drain is connected to the second electrode of the first amplifier, and the control signal ENN is input to the gate, and the drain is connected to the source of the NMOS transistor N5 and the source of the NMOS transistor N6. , And an NMOS transistor N7 whose source is grounded.
Further, a control signal EQN is input to the gate, a drain is connected to the drain of the PMOS transistor P2, an NMOS transistor N1 whose source is grounded, and a control signal EQN is input to the gate, and a drain is connected to the drain of the PMOS transistor P3. And an NMOS transistor N1 whose source is grounded.

The operation of the programmable register device will be described with reference to FIGS.
FIG. 16 is a timing diagram illustrating the operation of the programmable register device during programming according to the present invention.
When a predetermined program mode is started, the program mode operation signal CMD_3 is activated. At this time, the control signals ENN and ENP are activated so that the circuit can operate, and the control signal EQN is deactivated to prepare for input voltage supply.

When the control signals ENW and CPL are activated, the input signals SET and RESET are provided to the ferroelectric capacitor. For example, when the input signal SET is “high” and the input signal RESET is “low”, charges are stored in the ferroelectric capacitors FC1 and FC4.
When the control signal FNW is set to “low”, the input signals SET and RESET are separated from the ferroelectric capacitors FC1, FC2, FC3, and FC4. Further, when the control signal CPL is set to “low”, fluctuations in the charge amount occur in FC1 and FC2.
When the power supply is cut off, electric field redistribution occurs in the ferroelectric capacitors FC1, FC2, FC3, FC4. In this case, the voltage of the output node P_CON becomes lower than the voltage of the output node N_CON due to the stored charge. .

FIG. 17 is a timing diagram showing an operation of reading a program result when the power is turned on in the ferroelectric memory device according to the present invention.
When the power supply reaches a stable level, a power-up detection pulse PUP is generated. When this signal is used to change the control signal EQN signal from “high” to “low” and the equalization is canceled and then the control signal CPL signal is changed to “high”, the ferroelectric capacitors FC1, FC2, FC3, The charges stored in FC4 generate a potential difference on both output nodes N_CON and P_CON. In this example, the voltage of the output node N_CON appears high.

When a sufficient potential difference is generated, the control signals ENN and ENP are activated to “high” and “low”, respectively, and the data at both ends of the storage unit are amplified by the first amplifier and the second amplifier.
When amplification is completed, the control signal CPL signal is changed to “low” again, and the “high” data of the ferroelectric capacitors FC2 and FC4 that have been destroyed are restored again. At this time, the control signal ENW signal is deactivated to “low” to prevent external data from being written again.

  FIG. 18 is a diagram showing an example of a circuit for generating control signals ENW and CPL signals. This figure shows an example of a circuit configured to generate the control signals ENW and CPL as shown in FIGS. 16 and 17, and those skilled in the art will be able to refer to this circuit with reference to the timing diagram described above. Since the operation of the figure can be easily understood, a description of the specific operation is omitted.

In FIG. 19, the output signal can be programmed by a signal applied from the outside, and the capacitance of the capacitor connected to the driving power source is adjusted by using a programmable register device in which the result of the program is held without a power source. A ferroelectric memory including a redundant address decoder, wherein the reference voltage level can be adjusted by controlling on / off of the switch to be used, and the programmable register device is used as an on / off control device for a redundant address program switch It is a block diagram of the apparatus for performing a program mode in an apparatus.
A program processing method using this is a first step of decoding a signal input to a signal input unit, and when the decoding result corresponds to a predetermined program mode, the program mode operation signal CMD_1 is activated to generate a signal input unit. And a third step of performing a program mode by the program mode operation signal CMD_1.

  In the present invention, the program mode includes three parts, a low redundancy program mode, a column redundancy program mode, and a reference level program mode, and other program modes can be added as necessary. In the present embodiment, CMD_1 activates the low redundancy program mode, CMD_2 activates the column redundancy program mode, and CMD_3 activates the reference level program mode. This signal is further fed back to the signal input section, and the stability is ensured by blocking the input of the signal input section when each signal is activated to “high”.

20 to 22 are explanatory diagrams of the operation of the decoder unit of FIG.
CMD_1 is activated to “high” at the nth falling edge of the output enable signal OEB while the chip enable signal CEB and the write enable signal WEB are held at “high”.
CMD_2 is activated to “high” at the nth falling edge of the output enable signal OEB in a state where CEB is held “high” and WEB is held “low”.
CMD_3 is activated to “high” at the nth falling edge of the write enable signal WEB in a state where CEB is held “high” and OEB is held “low”.

23 to 25 are circuit configuration diagrams for generating CMD_1 to CMD_3, respectively. This is composed of n flip-flops and control elements.
FIG. 23 activates the CMD_1 signal that activates the low redundancy program mode by decoding the input signals CEB, OEB, and WEB. If the chip enable signal CEB is “high”, when the output enable signal OEB toggles, the result of “AND” operation of the chip enable signal CEB and the output enable signal OEB will also toggle the signal. Therefore, when the output enable signal OEB toggles n times, the output of the nth D flip-flop becomes the same level as the write enable signal WEB. Therefore, when the write enable signal WEB is applied to “high”, the output of CMD_1 also becomes “high”.

  The operation principle of the circuit shown in FIGS. 24 and 25 is the same as the operation principle of the circuit shown in FIG.

FIG. 26 is a configuration diagram of the D flip-flop shown in FIGS.
In general, the D flip-flop is a circuit that is synchronized with a clock edge and samples and outputs a signal provided to an input terminal. The operation of this circuit will be briefly described as follows.
This circuit is a circuit that samples the input signal d in synchronization with the falling edge of the clock. When the clock is at the “high” level, the master unit 241 opens the switch S1 of the master unit 241 and stores the input signal d in the latch. At this time, since the switch S2 in the slave unit 242 is closed, the input signal d is not transmitted to the latch of the slave unit 242.
When the clock transitions to “low”, the switch S1 of the master unit 241 is closed and the switch S2 in the slave unit 242 is opened, and the data stored in the latch of the master unit 241 becomes the latch of the slave unit 242. The signal stored and stored in the latch of the slave unit 242 is continuously output until the next falling edge of the clock.

  27 (a) and 27 (b) use a programmable register device in which the output signal can be programmed by an externally applied signal and the result of the program is held without a power supply, and the drive power supply The level of the reference voltage can be adjusted by controlling on / off of a switch for adjusting the capacitance of the capacitor connected to the redundant, and the programmable register device is used as a redundant address program switch on / off control device. FIG. 5 is a diagram illustrating a method of finding and repairing a weak cell by adjusting a reference level in a ferroelectric memory device including an address decoder.

  The weak cell relief method according to the present invention includes a first stage in which the reference voltage 250 is provided at a predetermined first level, and includes data at the first level with reference to the reference voltage provided at the first level. The second stage of processing the cells including data below the reference voltage to the weak cells 254 to perform the redundancy program, the reference voltage 250 is set to the second level lower than the first level. Among the cells provided so as to contain the second level data with reference to the reference voltage provided at the second level in the third stage, and the cells including data higher than the reference voltage And the like to the weak cell 253 to perform the redundancy program, and the reference voltage is set to the first level 252 and the second level. A fifth step of providing a median level of 251.

  The reference voltage level REF (n) is achieved by adjusting the capacitance and changing the reference level control signal REFSN as described above. At this time, the reference level control signal REFSN can be adjusted by adjusting the capacitance using a switch connected in series with the capacitor and a programmable register device that controls on / off of the switch.

In general, the redundancy program is an operation for programming the fuse attached to the redundant address decoder. In the present invention, a switch is used instead of a fuse, and the output of the programmable register device is used as a signal for controlling switch on / off. Therefore, the on / off of the switch can be readjusted at any time.
When all the redundancy program operations are completed, the maximum sensing margin is ensured by reprogramming so that the reference level is located at the center between the first level and the second level.

  The scope of the present invention is not limited by the above-described embodiments, but is determined by what is described in the claims.

It is a hysteresis curve. It is a block diagram of a FRAM cell element. (a) is an operation timing diagram of the ferroelectric memory device according to the prior art, and (b) is an operation timing diagram of the ferroelectric memory device according to the prior art. 1 is a schematic configuration diagram of a ferroelectric memory device according to the present invention. 1 is a configuration diagram of a cell array included in a ferroelectric memory device according to the present invention. FIG. FIG. 3 is a configuration diagram of a main bit line pool up control unit included in a ferroelectric memory device according to the present invention. FIG. 3 is a configuration diagram of a main bit line load control unit included in a ferroelectric memory device according to the present invention. FIG. 3 is a configuration diagram of a column selection control unit included in a ferroelectric memory device according to the present invention. 3 is a configuration diagram of a sub cell block and a main bit line load control unit included in a ferroelectric memory device according to the present invention; FIG. 1 is a circuit diagram of a reference level generator included in a ferroelectric memory device according to the present invention. FIG. FIG. 3 is a configuration diagram of a reference capacitance adjusting unit included in a ferroelectric memory device according to the present invention. FIG. 4 is a configuration diagram of a drive unit of a reference program unit included in a ferroelectric memory device according to the present invention. FIG. 5 is an operation timing chart of the reference generator included in the ferroelectric memory device according to the present invention. 1 is a block diagram of a programmable register device included in a ferroelectric memory device according to the present invention. FIG. 1 is a circuit diagram of a programmable register device included in a ferroelectric memory device according to the present invention. FIG. 3 is an operation timing chart of the programmable register device during programming of the ferroelectric memory device according to the present invention. FIG. 3 is an operation timing chart of the programmable register device in the power-up mode of the ferroelectric memory device according to the present invention. FIG. FIG. 5 is a configuration diagram of a control signal CPL and an ENW generation circuit input to a programmable register device when programming a ferroelectric memory device according to the present invention. 1 is a block diagram of a circuit for setting a program mode of a ferroelectric memory device according to the present invention. FIG. FIG. 10 is an operation timing chart of the decoding unit in the program mode of the ferroelectric memory device according to the present invention. FIG. 10 is an operation timing chart of the decoding unit in the program mode of the ferroelectric memory device according to the present invention. FIG. 10 is an operation timing chart of the decoding unit in the program mode of the ferroelectric memory device according to the present invention. It is a block diagram of a Command_1 processing unit of the ferroelectric memory device according to the present invention. It is a block diagram of a Command_2 processing unit of the ferroelectric memory device according to the present invention. It is a block diagram of a Command_3 processing unit of the ferroelectric memory device according to the present invention. FIG. 3 is a detailed configuration diagram of a flip-flop circuit included in a decoding unit of a ferroelectric memory device according to the present invention. FIG. 4A is a method diagram illustrating a repair order of weak cells in a ferroelectric memory device according to the present invention, and FIG. 5B is a repair diagram of weak cells in the ferroelectric memory device according to the present invention. FIG. 4C is a method diagram showing a repair order of weak cells in the ferroelectric memory device according to the present invention.

Explanation of symbols

111 Ferroelectric capacitor 112 Capacitance adjustment unit 113 Switch 114 NMOS transistor 121 Power supply voltage pumping unit 122 Level shifter unit 241 Master unit 242 Slave unit 250 Reference voltage 251 Second level 252 First level 253, 254 Weak cell

Claims (2)

The level of the output signal can be programmed by an externally applied signal, and a programmable register device that retains the program result without a power source is used to adjust the capacitance of a capacitor connected to the driving power source. A reference generator for adjusting a reference voltage level by controlling on / off, and a ferroelectric memory device including a redundant decoder using the programmable register device as an on / off control device for a redundant address program switch In the programming method,
A first stage for decoding a signal input to the signal input unit;
A second step of activating a program mode operation signal corresponding to the program mode and deactivating the signal input unit when the predetermined program mode is indicated as a result of the decoding, and responding to the program mode operation signal A program method for a ferroelectric memory device comprising a third step of performing a program mode.   The method of claim 1, wherein the program mode includes a row redundancy program mode, a column redundancy program mode, and a reference level program mode.

Images