JP4607638B2 - Variable length decoding apparatus and method - Google Patents

Description

  The present invention relates to a variable-length decoding device that decodes variable-length encoded code data.

  As a method for compressing and expanding moving image data, international standards (Non-Patent Document 1) such as MPEG2 and MPEG4 are known. In recent years, LSIs and software cores conforming to these international standards are always mounted in digital home appliances that handle moving images.

  According to these international standards, moving image data is divided into 8 × 8 pixel blocks or 16 × 16 pixel macroblocks, and data processing is executed in units of blocks or macroblocks.

  An encoder for compressing moving image data such as MPEG2 and MPEG4 mainly comprises a discrete cosine transformer (DCT), a quantizer (Q), and a variable length encoder (VLC). The The input pixel data is first converted from spatial domain data to frequency domain data by a discrete cosine transformer. When the pixel data is a natural image, if the pixel data is converted into frequency domain data, the data concentrates in the low frequency domain. Next, in the quantizer, the frequency domain data obtained by the discrete cosine transformer is coarsely quantized in order to set the coefficient of the high frequency component to the value “0”. Then, the non-zero values of the frequency data are concentrated on the low frequency component data, and all the high frequency component data is converted to the value “0”. In variable length encoder, non-zero and zero data are scanned while zigzag so that data is composed from low frequency component to high frequency component, that is, high frequency component value “0” is easily connected. Generate a set. This data set is variable-length encoded using a Huffman code table to obtain variable-length encoded data.

  The variable length encoded data described above is provided through a recording medium or a network. A decoder for decoding variable length encoded data and restoring moving image data generally comprises a variable length decoder (VLD), an inverse quantizer (IQ), and an inverse discrete cosine transformer (IDCT). Is done.

  FIG. 15 is a block diagram of a conventional image decoding apparatus. The conventional image decoding apparatus shown in FIG. 15 includes an encoded data memory 1, a variable length decoder (VLD) 2 having an address generator 2a, a coefficient data memory 3, an inverse quantizer (IQ) 4, and an inverse DCT. A device (IDCT) 5 is provided. The encoded data memory 1 stores variable-length encoded data obtained by variable-length encoding moving image data. The coefficient data memory 3 stores a run length value that is coefficient data (that is, quantized data) converted by the variable length decoder 2.

  The outline of the operation of the conventional image decoding apparatus shown in FIG. 15 will be described below.

  When variable length encoded data is supplied from the encoded data memory 1 to the variable length decoder 2, the variable length decoder 2 first initializes the coefficient data memory 3. That is, as this initialization process, the variable length decoder 2 performs the clear process by writing the value “0” to all addresses in the coefficient data memory 3.

  In general, image data processing in the image decoding apparatus is performed in units of macroblocks. For example, assuming that the composition ratio of pixel data is Y: Cb: Cr = 4: 2: 0, one macroblock has Y: 16 × 16 pixels, Cb: 8 × 8 pixels, and Cr: 8 × 8 pixels. Since it is composed of a total of 384 pixels, it is necessary to initialize 384 symbols to initialize one macroblock. (One pixel usually has a pixel value of one symbol consisting of 8 bits.) If one cycle of initialization processing is required per pixel, 384 cycles are required for initialization processing of one macroblock.

  When the initialization process is completed, the variable length decoder 2 compares the variable length encoded data (bit string) from the encoded data memory 1 with a separately prepared variable length decoding table, and decodes the quantized data. Only the non-zero quantized data is written in the coefficient data memory 3. The address of the coefficient data memory 3 where non-zero quantized data is written is generated by the address generator 2a.

  In this way, when the decoding process for one macroblock is completed, the decoding process for the next macroblock is performed. At this time, in the conventional image decoding apparatus shown in FIG. 15, the coefficient data memory 3 needs to be initialized in order to decode a new macroblock. Since this initialization is necessary for each macroblock decoding process, the ratio of the time required for the initialization process in the time required for the decoding process is large.

In the conventional image decoding apparatus shown in FIG. 15, the number of decoding processing cycles required until the final coefficient data (quantized data) is stored is
(Decoding processing cycle) = (Minimum 384 cycles of initialization processing) +
(Number of non-zero symbols) * (Number of decoding processing cycles per symbol in VLD)
It becomes. Here, the number of one symbol corresponds to one data of quantized data.

  In an image decoding apparatus mounted on a portable device that operates on a battery, it is desirable that the operating frequency is low, and therefore it is desirable that the number of decoding processing cycles be as small as possible. However, in recent years, the number of decoding processing cycles has been increasing due to an increase in the screen size and the number of moving image processing frames, and the number of cycles required for initialization processing needs to be as small as possible. Furthermore, since there are 384 cycles of access for the initialization process of the coefficient data memory 3 in the decoding process of each macroblock, the power consumption increases. It is necessary to reduce the number of accesses to the coefficient data memory 3 as much as possible.

  FIG. 16 shows an improvement in the conventional image decoding apparatus of FIG. 1 so as to reduce the influence of the time required for the initialization process. That is, FIG. 16 is a block diagram of a conventional improved image decoding apparatus. In FIG. 16, the same components as those in FIG. 15 are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 16, the conventional improved image decoding apparatus includes a coefficient data memory 3a and a coefficient data memory 3b installed in parallel, and a switcher 6 that switches between them alternately.

  In the conventional improved image decoding apparatus shown in FIG. 16, when variable length encoded data is supplied from the encoded data memory 1 to the variable length decoder 2, the variable length decoder 2 first stores the coefficient data memory 3a. Perform initialization. When the initialization is completed, the variable length decoder 2 switches the selection of the switch 6 and initializes the coefficient data memory 3b. At the same time, the variable length decoder 2 compares the variable length encoded data (bit stream) from the encoded data memory 1 with a separately prepared variable length decoding table, decodes the quantized data, Only non-zero quantized data is written into the coefficient data memory 3a.

  As described above, the two coefficient data memories 3a and 3b installed in parallel are alternately switched, and the initialization process and the decoding and data writing processes are executed in parallel, thereby reducing the time required for the initialization process. The impact is reduced.

In the conventional improved image decoding apparatus shown in FIG. 16, the number of decoding processing cycles required until the final coefficient data (quantized data) is stored is
(Minimum 384 cycles of initialization)
Of (the number of non-zero symbols) * (the number of decoding processing cycles per symbol in the VLD), the larger number of cycles. However, in the conventional improved image decoding apparatus shown in FIG. 16, since the two coefficient data memories 3a and 3b must be installed, an increase in circuit area is inevitable.
ISO / IEC 14496-10: 2003, "Information technology, Coding of audio-visual objects-Parts 10: Advanced video coding"

  Therefore, an object of the present invention is to provide a variable length decoding device that can realize decoding of variable length encoded data with low hardware resources with high efficiency and low power consumption.

  A variable length decoding device according to a first aspect of the present invention is a variable length decoding device that decodes encoded data that has been subjected to variable length encoding, a variable length decoding unit that converts encoded data into quantized data, and quantization The variable length decoding unit stores only non-zero quantized data of the converted quantized data in the storage unit.

  According to this configuration, the variable length decoding unit only needs to store non-zero quantized data in the converted quantized data in the storage unit, so that the time for decoding processing can be shortened. In addition, the variable length decoding device of the present configuration has expandability because a storage unit with an initialization function or a non-zero data display flag memory can be added to further expand the functions.

  In the variable length decoding device according to the second invention, the storage unit has an initialization mechanism for initializing the entire area of the storage unit, and the variable length decoding unit is configured such that the initialization mechanism reduces the entire area of the storage unit to zero ( After initialization to “0”), only non-zero quantized data of the converted quantized data is stored in the storage unit.

  According to this configuration, since the initialization of the storage unit required for each decoding of the macroblock can be processed in one cycle using the initialization mechanism, the time required for the initialization of the storage unit can be greatly shortened. .

  In the variable length decoding device according to the third invention, the variable length decoding unit includes a control unit, a decoding unit, and an address generation unit, the control unit issues a control signal to the initialization mechanism, and the initialization mechanism includes: When the control signal is received, the entire area of the storage unit is initialized to zero (“0”), and the decoding unit converts the encoded data to generate intermediate data, and generates quantized data from the generated intermediate data. The address generation unit generates the address of the storage unit that stores the non-zero quantized data based on the intermediate data, and the decoding unit initially sets the entire area of the storage unit to zero (“0”). Then, the non-zero quantized data is stored in the address of the storage unit generated by the address generation unit.

  According to this configuration, the storage unit is initialized using a control signal generated by the control unit as a trigger, and then the decoding unit stores non-zero quantized data among the quantized data obtained by converting the encoded data. Therefore, the decoding process can be performed in the correct order. In addition, the number of processing cycles required for initializing the storage unit is reduced, and the decoding speed can be increased.

  The variable length decoding device according to a fourth aspect of the present invention further includes an inverse quantization unit and an inverse DCT unit, the inverse quantization unit generates DCT data based on the quantized data read from the storage unit, and performs inverse processing. The DCT unit generates decoded data based on the DCT data.

  According to this configuration, since the time required for initialization of the storage unit for each macroblock decoding is short, a variable-length decoding device capable of high-speed processing can be realized.

  In the variable length decoding device according to the fifth aspect of the present invention, the variable length decoding unit further includes a flag register that stores a flag indicating that the quantized data is zero or non-zero, corresponding to each address of the storage unit. After setting the flag indicating zero (“0”) to all addresses of the flag register and initializing the flag register, only non-zero quantized data of the converted quantized data is stored in the storage unit. Then, a flag indicating non-zero is set at the corresponding address of the flag register.

  According to this configuration, since the address of the zero quantized data on the storage unit can be known by examining the flag in the flag register, the storage unit has a non-zero quantized quantized data. Only the data is stored and there is no need to store zero quantized data. Further, since initialization of the storage unit is not necessary, there is an advantage that a normal memory or register can be used for the storage unit.

  In the variable length decoding device according to the sixth aspect of the present invention, the variable length decoding unit has a control unit, a decoding unit, and an address generation unit, and the control unit issues a control signal to the flag register, and all addresses of the flag register In addition, a flag indicating zero (“0”) is set to initialize the flag register, and the decoding unit converts the encoded data to generate intermediate data, generates quantized data from the generated intermediate data, The address generation unit generates an address of a storage unit that stores non-zero quantized data based on the intermediate data, and the decoding unit stores the memory generated by the address generation unit after the control unit initializes the flag register. Non-zero quantized data is stored at the unit address, and a flag indicating non-zero is set at the corresponding address of the flag register.

  According to this configuration, the flag register is initialized using a control signal generated by the control unit as a trigger, and then the decoding unit stores non-zero quantized data among the quantized data obtained by converting the encoded data. At the same time, a non-zero flag is set in the corresponding address of the flag register. By doing so, the address of the zero quantized data on the storage unit can be known by examining the flag in the flag register. Further, there is no need to initialize the storage unit, and a normal memory can be used for the storage unit.

  The variable length decoding device according to a seventh aspect of the present invention further includes an inverse quantization unit, and the inverse quantization unit quantizes from a corresponding address of the storage unit when the flag register indicates that the flag is non-zero. When data is read and the flag in the flag register indicates zero (“0”), the value “0” is taken in and a DCT coefficient is generated.

  According to this configuration, the quantization unit does not access the address where the zero quantized data is to be stored, and therefore the storage unit need not be initialized. Therefore, it is possible to save the processing cycle necessary for initializing the storage unit.

  The variable length decoding device according to an eighth aspect of the present invention further includes an inverse DCT unit, and the inverse DCT unit generates decoded data based on the DCT coefficient generated by the inverse quantization unit.

  According to this configuration, a highly efficient variable-length decoding device that decodes variable-length encoded data can be realized by setting a flag register in a normal variable-length decoding device.

  According to the present invention, it is possible to provide a variable-length decoding device that can realize decoding of variable-length encoded data with low hardware resources with high efficiency and low power consumption.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram of a variable-length decoding device 100 according to Embodiment 1 of the present invention. The variable length decoding device 100 of the present embodiment includes a first storage unit 10 that stores encoded data, a variable length decoding unit (VLD) 20, a second storage unit 30 that stores coefficient data, and an inverse quantization unit (IQ) 40. And an inverse DCT unit (IDCT) 50.

  The variable length decoding unit 20 includes a control unit 21, a decoding unit 22, and an address generation unit 23.

  The second storage unit 30 has an initialization mechanism, and can initialize all the addresses of the second storage unit 30 simultaneously by a control signal input to the reset terminal 31. In the following description, for the sake of simplicity, it is assumed that the second storage unit 30 has a (4 × 4) two-dimensional array.

  FIG. 3 is a flowchart of variable length decoding apparatus 100 according to Embodiment 1 of the present invention. The operation of the variable length decoding device 100 of the present embodiment shown in FIG. 1 will be described according to the flowchart shown in FIG.

  Assume that the first storage unit 10 stores the encoded data shown in FIG. 6 together with the header. That is, FIG. 6 is a data storage state diagram of the first storage unit 10 according to Embodiment 1 of the present invention. The header value is stored in the address (0x0000) and the address (0x0001) of the first storage unit 10, respectively, and the encoded data is stored after the address (0x0002).

  When the decoding process is started in step S10, the variable length decoding unit 20 is activated.

  In step S11, the decoding unit 22 reads the header value (0xC000) (hexadecimal notation, the same applies hereinafter) and the value (0xC1B3) from the address (0x0000) and address (0x0001) of the first storage unit 10, and performs header processing. I do. Then, the control unit 21 outputs a reset signal that is a control signal for initializing the second storage unit 30 to the reset terminal 31 of the second storage unit 30.

  In step S <b> 12, when the second storage unit 30 receives the reset signal at the reset terminal 31, the data of all addresses in the second storage unit 30 are reset to the value “0” and initialization is performed. When the initialization is completed, all the addresses in the (4 × 4) array element of the second storage unit 30 are replaced with the value “0” as shown in FIG. That is, FIG. 7 is a state diagram after initialization of the second storage unit 30 in Embodiment 1 of the present invention. When the initialization is completed, the variable length decoding unit 20 moves to a decoding process state.

In step S <b> 13, the decoding unit 22 reads the encoded data from the first storage unit 10. First, the decoding unit 22 reads data (0xBCA5) from the address (0x0002) of the first storage unit 10 and data (0xDFFF) from the address (0x0003). These hexadecimal display data are represented by binary display bit strings as follows.
(0xBCA5) = (1011110010100101)
(0xDFFF) = (11011111111111111)
The read bit string is divided into a plurality of code data strings based on information representing the bit string delimiter included in the header. FIG. 8 is an exemplary diagram of a bit string read from the first storage unit 10 according to Embodiment 1 of the present invention. As shown in FIG. 8, the read bit string is divided into a code data string (101), a code data string (1110), a code data string (0101001), and a code data string (01110) following the header.

  Returning to FIG. 3, in step S <b> 14, the decoding unit 22 performs decoding by comparing the read code string with a separately prepared variable length decoding table (VLC table). The variable length decoding table is incorporated in the decoding unit 22 as a logic circuit. This logic circuit functions as a so-called lookup table.

  FIG. 9 is an exemplary diagram of a variable length decoding table according to Embodiment 1 of the present invention. The variable length decoding table shown in FIG. 9 shows the correspondence for converting a code data string into combination data (LAST, RUN, LEVEL). The combination data (LAST, RUN, LEVEL) corresponds to intermediate data.

  In the combination data (LAST, RUN, LEVEL), the data (LAST) represents whether the decoded data is the last data. When LAST = 1, the decoded data is the last data. When LAST = 0, the decoded data is not the last data.

  Data (RUN) represents the number of values “0” consecutive before the decoded data.

  Data (LEVEL) represents a non-zero value of the decoded data.

  In FIG. 9, the least significant bit “s” of the code data string is a bit representing the code. When s = 0, the data (LEVEL) is positive, and when s = 1, the data (LEVEL) is negative. Represents that.

  9, for convenience, the code data strings are arranged in the order of the input code data strings shown in FIG. This table is for explanation and does not necessarily conform to the MPEG4 standard.

  Returning to FIG. 3 again, in step S15, the decoding unit 22 sequentially converts the input code data string of FIG. 8 into combination data (LAST, RUN, LEVEL) according to FIG. First, the code data string (101) is converted into combination data (0, 0, 1) (the sign of data (LEVEL) is negative).

  In step S16, it is determined whether LAST = 1. In this case, since LAST = 0, the determination result is “No”, and the process returns to step S14.

  By performing the processing of step S14 and step S15, the decoding unit 22 converts the code data string (1110) into combination data (0, 0, 3) (the sign of the data (LEVEL) is positive).

  In step S16, since LAST = 0, the determination result is “No”, and the process returns to step S14.

  By performing the processing of step S14 and step S15, the decoding unit 22 converts the code data string (0101001) into combination data (0, 1, 2) (the sign of the data (LEVEL) is negative).

  In step S16, since LAST = 0, the determination result is “No”, and the process returns to step S14.

  By performing the processing of step S14 and step S15, the decoding unit 22 converts the code data string (01110) into combination data (1, 0, 1) (the sign of the data (LEVEL) is positive).

  In step S16, since LAST = 1, the determination result is “Yes”, and the process proceeds to step S17.

  Thus, the conversion process for collating the input code data string with the variable length decoding table of FIG. 9 is completed, and the combination data (0, 0, 1), (0, 0, 3), (0, 1, 2) and (1, 0, 1) are obtained.

In step S <b> 17, non-zero data is stored in the second storage unit 30. First, the address generation unit 23 refers to the value of the obtained combination data (RUN) and sequentially obtains the address of the second storage unit 30 that stores non-zero data. as a result,
The address for storing LEVEL = 1 is address (0);
The address storing LEVEL = 3 is address (1);
The address for storing LEVEL = 2 is address (3) (because RUN = 1 and there is one data of value “0” before this);
The address for storing LEVEL = 1 is address (4).
It becomes.

  The decoding unit 22 stores the value of each LEVEL in the address of the second storage unit 30 obtained by the control unit 21 in consideration of the sign.

  FIG. 10 is a state diagram after data storage in the second storage unit 30 according to the first embodiment of the present invention. In the second storage unit 30, the addresses are set in a zigzag shape as indicated by the dotted arrows in FIG.

  Thus, the conversion of the encoded data into the quantized data is completed, and the conversion result is stored in the second storage unit 30.

  In step S18, the inverse quantization unit 40 reads the data of the variable length decoding unit 20, performs an inverse quantization process, and generates DCT data.

  In step S <b> 19, the inverse DCT unit 50 performs inverse DCT processing using the DCT data generated by the inverse quantization unit 40 and outputs decoded data to the output terminal 90.

  Moving to step S20, the decoding process for one macroblock is completed.

  According to the variable length decoding device 100 of the present embodiment, the initialization of the storage unit required for each decoding of the macroblock can be processed in one cycle using the initialization mechanism, so that it is necessary for the initialization of the storage unit. Time can be greatly reduced.

  As is clear from FIG. 10, in the variable length decoding device 100 of the present embodiment, only the non-zero value is obtained after the second storage unit 30 is initialized to the value “0” at the beginning of the decoding process of one macroblock. The address to be stored is obtained and stored in the second storage unit 30. By this method, in the example of the encoded data described above, the decoding unit 22 does not have to access the addresses after the address (2) and the address (5) at all. As described above, according to the variable length decoding device 100 of the present embodiment, the variable length decoding unit 20 needs to store only non-zero quantized data among the converted quantized data in the storage unit. The processing time can be shortened, and the power required for accessing the storage unit can be reduced.

  In the description of the first embodiment of the present invention described above, the second storage unit 30 assumes a (4 × 4) two-dimensional array as shown in FIGS. 7 and 10 for the sake of simplicity. However, the second storage unit 30 may be a one-dimensional array storage unit. In that case, the addresses of the one-dimensional array storage unit need only be ordered in the zigzag scan order of the two-dimensional array storage unit shown in FIG.

  FIG. 11 is a block diagram of the second storage unit 30 having a one-dimensional array according to Embodiment 1 of the present invention. The upper diagram of FIG. 11 shows a memory cell configuration for storing one bit of the second storage unit 30. This memory cell has a reset input (R), a clock input (CLK), a data input (Data), and a write enable signal input (WE). The lower diagram of FIG. 11 is a block diagram of the second storage unit 30. The memory cells of the upper diagram are arranged in 12 per address to form a configuration of 1 address-12 bits, and further, 384 of them are combined, and 384 A storage unit with an address * 12-bit configuration is created.

FIG. 12 is a state diagram after data storage in the second storage unit of the one-dimensional array according to Embodiment 1 of the present invention. FIG. 12 shows a state in which the same decoded quantized data as stored in FIG. 10 is stored in the second storage unit 30 of FIG. That is, after all addresses in FIG. 12 are initialized to data (0x000), only non-zero quantized data is stored. as a result,
At the address (0x0000), the data (0xFFF) which is the hexadecimal notation of the data (-1) is
At address (0x0001), data (0x003), which is the hexadecimal notation of data (3),
At the address (0x0003), the data (0xFFE) which is the hexadecimal notation of the data (-2) is
Data (0x001), which is the hexadecimal notation of data (1), is stored at the address (0x0004).

  Needless to say, according to the second storage unit 30 shown in FIG. 11, the initialization of the second storage unit 30 can be executed in one cycle.

(Embodiment 2)
FIG. 2 is a block diagram of variable length decoding apparatus 200 according to Embodiment 2 of the present invention. A variable length decoding device 200 of the present embodiment shown in FIG. 2 includes a first storage unit 10 that stores encoded data, a variable length decoding unit (VLD) 20, a second storage unit 30 that stores coefficient data, a flag register 60, An inverse quantization unit (IQ) 40 and an inverse DCT unit (IDCT) 50 are provided.

  The variable length decoding unit 20 includes a control unit 21, a decoding unit 22, and an address generation unit 23. The control unit 21 sends a control signal to the flag register 60.

  The inverse quantization unit 40 includes an inverse quantization processing unit 41, a selector 42, and a data setting unit 43. The data setting unit 43 always outputs the set value “0”. The selector 42 selects whether the data read by the inverse quantization processing unit 41 is obtained from the second storage unit 30 or the data setting unit 43. This control is performed by the flag of the flag register 60.

  The flag register 60 stores a flag indicating that the quantized data stored in the second storage unit 30 is zero or non-zero corresponding to each address of the second storage unit 30. The flag register 60 of this embodiment stores a flag value “0” when the quantized data is zero, and stores a flag value “1” when the quantized data is non-zero.

  FIG. 4 is a flowchart of the first half of variable-length decoding apparatus 200 according to Embodiment 2 of the present invention. FIG. 5 is a flowchart of the latter half of variable-length decoding apparatus 200 according to Embodiment 2 of the present invention. The operation of the variable length decoding device 200 of the present embodiment shown in FIG. 2 will be described according to the flowcharts shown in FIGS.

  In the description of the operation of the variable length decoding device 200 of the present embodiment, the encoded data shown in FIG. 6 and the header are stored in the first storage unit 10 as in the second embodiment of the present invention. To do. Also, for the sake of simplicity, it is assumed that the second storage unit 30 has a (4 × 4) two-dimensional array. Furthermore, it is assumed that the flag register 60 can set a flag from address (0) to address (15) corresponding to the address of the second storage unit 30.

  When the decoding process is started in step S30 of FIG. 4, the variable length decoding unit 20 is activated.

  In step S31, the decoding unit 22 reads the header value (0xC000) and the value (0xC1B3) from the address (0x0000) and the address (0x0001) of the first storage unit 10, and performs header processing. Then, the control unit 21 outputs a reset signal that is a control signal for initializing the flag register 60 to the flag register 60.

  In step S32, when receiving the reset signal, the flag register 60 resets the flags of all the addresses in the flag register 60 to the value “0” and performs initialization. When the initialization is completed, the variable length decoding unit 20 moves to a decoding process state.

  In step S <b> 33, the decoding unit 22 reads the encoded data from the first storage unit 10. Also in the variable length decoding device 200 of the present embodiment, the variable length decoding unit 20 reads the encoded data from the first storage unit 10 as a bit string, as in Embodiment 1 of the present invention, and as shown in FIG. The header and the code data string (101), code data string (1110), code data string (0101001), and code data string (01110) following the header are acquired.

  In step S34, the decoding unit 22 collates the read code string with the variable length decoding table (VLC table) shown in FIG.

  In step S35, the decoding unit 22 sequentially converts the input code data string into combination data (LAST, RUN, LEVEL).

  From step S34 to step S36, combination data (0, 0, 1), (0, 0, 3), (0, 1, 2), (1, 0) are processed in the same manner as in the first embodiment of the present invention. 1) is obtained.

In step S <b> 37, the address generator 23 refers to the obtained combination data (RUN) and sequentially obtains the addresses of the second storage units 30 that store the non-zero data. as a result,
The address for storing LEVEL = 1 is address (0);
The address storing LEVEL = 3 is address (1);
The address for storing LEVEL = 2 is address (3);
The address for storing LEVEL = 1 is address (4).
It becomes.

  In step S38, the decoding unit 22 stores the value of each LEVEL in the address of the second storage unit 30 obtained by the control unit 21 in consideration of the sign.

  FIG. 13 is a state diagram after data storage in the second storage unit 30 according to the second embodiment of the present invention. In the second storage unit 30, the addresses are set in a zigzag shape as indicated by the dotted arrows in FIG. In FIG. 13, the symbol “x” is an unspecified meaningless value at the address where the quantized data of zero is obtained in the decoding process described above.

  In step S <b> 39, the control unit 21 sets a flag value “1” to the address of the flag register 60 corresponding to the address of the second storage unit 30 obtained by the control unit 21. As a result, the flag register 60 becomes as shown in FIG. That is, FIG. 14 is a state diagram after setting the flag of the flag register 60 in the second embodiment of the present invention.

  This completes the conversion to quantized data, and the control shifts to step S40.

  Next, referring to FIG. 5, when the control is shifted to step S40, the inverse quantization unit 40 is activated.

  In step S41, the inverse quantization unit 40 sets the addresses of the second storage unit 30 from which the quantized data is read in order from the address (0).

  In step S42, the selector 42 checks the flag of the address of the flag register 60 corresponding to the address of the second storage unit 30 set in step S41, and determines whether or not it is a value “0”. If the determination result is “No”, the process proceeds to step S43, and if the determination result is “Yes”, the process proceeds to step S44.

  In step S43, since the flag indicates the value “1”, the selector 42 selects the quantized data (non-zero) stored at the address of the second storage unit 30 set in step S41, This is sent to the inverse quantization processing unit 41.

  In step S44, since the flag indicates the value “0”, the selector 42 selects the value “0” set by the data setting unit 43 and sends it to the inverse quantization processing unit 41.

  In step S45, it is determined whether or not acquisition of all coefficient data has been completed. If acquisition of all coefficient data is not completed, the process returns to step S41, the next address of the second storage unit is set, and steps S42 to S45 are repeated. If acquisition of all the coefficient data is completed in step S45, the process proceeds to step S46.

  In step S46, the inverse quantization processing unit 41 performs inverse quantization processing using coefficient data (that is, quantized data) sent from the selector 42 to generate DCT data.

  In step S <b> 47, the inverse DCT unit 50 performs inverse DCT processing using the DCT data generated by the inverse quantization processing unit 41 and outputs decoded data to the output terminal 90.

  Moving to step S48, the decoding process for one macroblock is completed.

  As described above, the variable length decoding device 200 of this embodiment includes the flag register 60 corresponding to each address of the second storage unit 30, stores only non-zero quantized data in the second storage unit 30, and The corresponding flag of the flag register 60 is set to a value “1” indicating non-zero. By this method, when the inverse quantization unit 40 reads out the quantized data from the second storage unit 30, it refers to the flag in the flag register 60 and reads out only the non-zero quantized data in the second storage unit 30. Can be masked to the value “0” set in the data setting unit 43.

  As described above, in the variable length decoding device 200 of this embodiment, it is necessary to provide the number of flag registers 60 corresponding to the number of addresses of the second storage unit 30, but the initialization of the second storage unit 30 is performed every macroblock. It is not necessary to perform this every decoding process. Therefore, a normally used memory can be used for the second storage unit 30. Further, the initialization of the flag register 60 needs to be performed for each decoding process of each macroblock, but this processing amount is very small. As a result, according to the variable length decoding device 200 of the present embodiment, it is possible to shorten the decoding processing time of the variable length encoded data.

  In the description of the variable length decoding device 200 of the present embodiment described above, the second storage unit 30 assumes a (4 × 4) two-dimensional array as shown in FIG. 13 for the sake of simplicity. The second storage unit 30 may be a one-dimensional array storage unit as shown in FIG. In that case, the addresses of the one-dimensional array storage unit shown in FIG. 12 need only be ordered in the zigzag scan order of the two-dimensional array storage unit shown in FIG.

  Further, the flag register 60 shown in FIG. 14 is assumed to have addresses (0) to (15). The size of the flag register 60 needs to correspond to the size of the address of the second storage unit 30. When the one-dimensional array storage unit shown in FIG. 12 is used as the second storage unit 30, the flag register 60 only needs to have addresses (0x0000) to (0x017F) and can store 1 bit in each address.

  The variable-length decoding apparatus according to the present invention can be suitably used in, for example, a technical field for decoding encoded data that has been subjected to variable-length coding, an application field thereof, and the like.

Block diagram of variable-length decoding apparatus in Embodiment 1 of the present invention Block diagram of variable-length decoding apparatus in Embodiment 2 of the present invention Flowchart of variable-length decoding device in Embodiment 1 of the present invention Flowchart of the first half of the variable length decoding device in Embodiment 2 of the present invention Flowchart of the second half of the variable length decoding device in Embodiment 2 of the present invention Data storage state diagram of first storage unit in Embodiment 1 of the present invention State diagram after initialization of the second storage unit in Embodiment 1 of the present invention FIG. 3 is an exemplary diagram of a bit string read from the first storage unit in Embodiment 1 of the present invention. FIG. 3 is an exemplary diagram of a variable-length decoding table in Embodiment 1 of the present invention. State diagram after storing data in second storage unit in Embodiment 1 of the present invention The block diagram of the 2nd storage unit of the one-dimensional arrangement | sequence in Embodiment 1 of this invention State diagram after storing data in second storage unit of one-dimensional array in Embodiment 1 of the present invention State diagram after storing data in second storage unit in Embodiment 2 of the present invention State diagram after flag setting of flag register in embodiment 2 of the present invention Block diagram of a conventional image decoding device Block diagram of a conventional improved image decoding apparatus

Explanation of symbols

10 first storage unit 20 variable length decoding unit 21 control unit 22 decoding unit 23 address generation unit 30 second storage unit 31 reset terminal 40 inverse quantization unit 41 inverse quantization processing unit 42 selector 43 data setting unit 50 inverse DCT unit 60 Flag register

Claims (3)

A variable length decoding device for decoding encoded data that has been subjected to variable length encoding,
A storage unit;
A variable length decoding unit that converts encoded data that has been subjected to variable length encoding into intermediate data that includes a value indicating the end of non-zero quantized data;
The variable length decoding unit generates partially quantized data from the intermediate data to the end of the non-zero quantized data indicated by the value ,
The variable length decoding unit stores only the partially quantized data in the storage unit,
A flag register for storing a flag indicating that the quantized data is zero or non-zero corresponding to each address of the storage unit;
The variable length decoding unit sets a flag indicating zero (“0”) in all addresses of the flag register, initializes the flag register, and then converts non-zero quantum data in the converted quantized data. Storing only the digitized data in the storage unit, and setting a flag indicating non-zero in the corresponding address of the flag register,
An inverse quantization unit;
A data setting unit that outputs a value “0”;
If the flag in the flag register indicates non-zero, the inverse quantization unit reads the quantized data from the corresponding address in the storage unit, and the flag register flag is zero (“0”). In the case of indicating that there is a variable length decoding device , the quantized data is not read from the storage unit, the value “0” output from the data setting unit is taken in, and a DCT coefficient is generated . Electronic equipment including a variable length decoding apparatus according to claim 1 Symbol placement. A variable length decoding method for decoding encoded data that has been subjected to variable length encoding,
A variable-length decoding step of converting the encoded data that has been variable-length encoded into intermediate data including a value indicating the end of the non-zero quantized data;
In the variable length decoding step, partial quantized data from the intermediate data to the end of the non-zero quantized data indicated by the value is generated,
In the variable length decoding step, only the partially quantized data is stored in a storage unit ;
Corresponding to each address of the storage unit, a flag register for storing a flag indicating that the quantized data is zero or non-zero is further provided,
In the variable length decoding step, a flag indicating zero (“0”) is set in all addresses of the flag register, the flag register is initialized, and then the non-zero quantum of the converted quantized data is set. Storing only the digitized data in the storage unit, and setting a flag indicating non-zero in the corresponding address of the flag register,
And further includes an inverse quantization step and a data setting step of outputting a value “0”,
In the dequantization step, when the flag register indicates that the flag is non-zero, the quantized data is read from the corresponding address of the storage unit, and the flag register flag is zero (“0”). A variable-length decoding method that, when indicating that there is a data, does not read the quantized data, takes in the value “0” output in the data setting step, and generates a DCT coefficient .

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