JP4603490B2 - Amplitude adjusting apparatus, amplitude adjusting method, and storage system - Google Patents

Description

  The present invention relates to a technology for accessing a storage medium, and more particularly to an amplitude adjustment device, an amplitude adjustment method, and a storage system that adjust the amplitude of a signal read from the storage medium.

  In recent years, storage devices using hard disks are becoming essential devices in various fields such as personal computers, hard disk recorders, video cameras, and mobile phones. Storage devices using a hard disk have various specifications required depending on the field to which they are applied. For example, a hard disk mounted on a personal computer is required to have high speed and large capacity. However, since the amount of data handled per unit time increases as the speed increases, errors per unit time also increase proportionally. Then, it becomes difficult to correct all errors, and as a result, the time required to access the hard disk may increase, which becomes a bottleneck for speeding up.

  Generally, a magnetoresistive element (MagnetoResitive) has been used as an element for reading a signal stored in a storage device. However, the reproduced signal waveform read from the storage device via the magnetoresistive element has a problem that the output amplitude of the positive pulse and the output amplitude of the negative pulse are asymmetric (hereinafter referred to as “amplitude asymmetry”). (For example, see Non-Patent Document 1). The problem of amplitude asymmetry (Amplitude Asymmetry) occurs when the output amplitude of either the positive pulse or the negative pulse is reduced by the magnetoresistive element, and the dynamic range of both pulses is different. . When the asymmetry of the amplitude appears remarkably, the detection accuracy of the data detection process executed in the subsequent stage of the magnetoresistive element deteriorates. If it does so, the correction capability of the error correction decoding performed after data detection will reduce. In such a case, it is necessary to access the storage device again in order to correctly reproduce the data stored in the storage device, so that it is difficult to increase the speed of the storage device. As a technique for eliminating this asymmetry, conventionally, a bias magnetic field applied to the magnetoresistive element has been controlled (see, for example, Patent Document 1). Further, the asymmetry is corrected by adjusting the zero level of the analog / digital converter (see, for example, Patent Document 2). Further, the asymmetry is corrected by feeding back the result after error correction processing (see, for example, Patent Document 3).

Akihiko Takeo, et. al. , “Characterization of GMR Nonlinear Response and the Impact on BER in Permendicular Magnetic Recording”, IEEE Transactions on Magnetics, July, 2004. 40, no. 4 JP-A-4-205903 JP-A-5-205205 Japanese Patent Laid-Open No. 11-238205

  Under such circumstances, the present inventor has come to recognize the following problems. That is, depending on the analog circuit, the operation becomes unstable, so that it is difficult to correct nonlinearity accurately, and the circuit scale increases. On the other hand, when nonlinearity is corrected by digital processing, there are problems such as generation of a delay associated with a feedback loop or increase in circuit scale accompanying an increase in the number of bits in an analog / digital converter.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a storage device that can reduce amplitude asymmetry with a smaller circuit scale.

  In order to solve the above problems, an amplitude adjustment device according to an aspect of the present invention includes an input unit and an analog-digital conversion unit. The input unit is an analog signal output via a magnetoresistive element, and the dynamic range in the positive section and the dynamic range in the negative section are asymmetric, and an analog signal including a non-linear section in one of the sections is input. . When the amplitude of the analog signal input from the input unit is present in the nonlinear section, the analog-to-digital conversion unit converts the analog signal into a digital signal while adjusting the amplitude, and outputs the digital signal. The analog-to-digital conversion unit includes a pre-adjustment unit that adjusts the amplitude of the analog signal so as to cancel the non-linearity in the non-linear period before converting the analog signal into the digital signal.

  Here, the “nonlinear section” includes a section in which the amplitude of an analog signal input to the magnetoresistive element is distorted and output in the input / output characteristics of the magnetoresistive element. In addition, “the pre-adjustment unit that adjusts the amplitude of the analog signal so as to cancel the non-linearity in the non-linear section” means that the input / output characteristics are the reverse of the input / output characteristics in the non-linear section or approximate to the reverse characteristics Including a precorrector having the above characteristics.

  According to this aspect, the amplitude non-linearity generated in the magnetoresistive element can be canceled by adjusting the amplitude of the analog signal in the analog-to-digital converter. Further, by canceling the non-linearity of the amplitude generated in the magnetoresistive element, it is possible to improve the detection accuracy of data detection executed in the subsequent stage. Further, it is possible to improve error characteristics after error correction decoding executed in the subsequent stage.

  The pre-adjusting unit may adjust the amplitude of the analog signal in the nonlinear interval by setting the input / output characteristics in the nonlinear interval to a value corresponding to the inverse of the hyperbolic tangent function. In the plurality of partial sections included in the non-linear section, the pre-adjustment unit is set with a linear function having a first slope greater than at least 1 as input / output characteristics of the first partial section of the plurality of partial sections. Also, a linear function having a slope different from the first slope may be set as the input / output characteristics of the second partial section that is continuous with the first partial section among the plurality of partial sections. Here, the “value corresponding to the reciprocal of the hyperbolic tangent function” includes at least a value approximating the input / output characteristics of the hyperbolic tangent function, for example, the input / output characteristics of the hyperbolic tangent function and the n-order function (n is 1). A plurality of values obtained by adding, subtracting, multiplying, or dividing the above input / output characteristics. Further, “continuous” includes that the end point of the first partial section and the start point of the second partial section match, and the start point of the first partial section and the end point of the second partial section match. Including.

  The pre-adjustment unit may include a plurality of resistance elements and a comparison unit. The plurality of resistance elements are a plurality of resistance elements installed in series, and each receives a reference signal having a constant voltage and sequentially outputs a reference signal whose amplitude is adjusted to the subsequent resistance element. The comparison unit adjusts the amplitude of the analog signal by comparing the reference signal output from each of the plurality of resistance elements with the amplitude of the analog signal input from the input unit. Further, the width of the amplitude adjustment of the plurality of resistance elements may be changed by making the resistance values of the respective resistance elements non-uniform. Moreover, the resistance element corresponding to the non-linear section among the plurality of resistance elements is set to a resistance value different from the resistance value of the resistance element corresponding to the section other than the non-linear section, thereby adjusting the non-linearity in the non-linear section. Also good. Here, “to make the resistance value of each resistance element non-uniform” means that the resistance value of at least one or more of the resistance elements is different from the resistance value of other resistance elements. In addition, in a plurality of resistance elements, a plurality of resistance elements having the same resistance value may exist. According to this aspect, the analog signal amplitude asymmetry can be reduced with a small circuit by simply setting the resistance values of the plurality of resistance elements included in the analog-digital conversion unit.

  The pre-adjusting unit is connected to an input terminal of at least one of the plurality of resistance elements, and applies a corresponding reference voltage to each of the input terminals, so that each of the plurality of resistance elements And a reference voltage control unit that adjusts the amplitude of the output reference signal. In this case, the plurality of resistance elements may have the same resistance value. Further, the reference voltage control unit applies a reference voltage different from the input end of the resistance element corresponding to the section other than the non-linear section to the input end of the resistance element corresponding to the non-linear section among the plurality of resistance elements. The nonlinearity in the nonlinear section may be adjusted. Here, the “corresponding reference voltage” includes a reference voltage determined in association with each resistive element, may be set in advance, and dynamically changes according to the quality of the magnetoresistive element. May be. According to this aspect, the reference voltage controller can flexibly control the amplitude of the reference signal. Further, since the resistance values of the plurality of resistance elements included in the analog-digital conversion unit can be made the same, the circuit cost can be reduced. In addition, the amplitude asymmetry of the analog signal can be reduced with a small circuit.

  Another aspect of the present invention is an amplitude adjustment method. The method includes an input step and an output step. The input step is an analog signal output via the magnetoresistive element, and the dynamic range in the positive interval and the dynamic range in the negative interval become asymmetric, and an analog signal including a non-linear interval is input in one of the intervals To do. In the outputting step, the analog signal existing in the non-linear section is converted into a digital signal and output while adjusting the amplitude so as to cancel the non-linearity in the non-linear section. According to this aspect, the amplitude nonlinearity generated in the magnetoresistive element can be canceled by adjusting the amplitude of the analog signal in the outputting step. Further, by canceling the non-linearity of the amplitude generated in the magnetoresistive element, it is possible to improve the detection accuracy of data detection executed in the subsequent stage. Further, it is possible to improve error characteristics after error correction decoding executed in the subsequent stage.

  Yet another embodiment of the present invention is a storage system. This storage system is a signal storage system including a write channel for writing data to the storage device and a read channel for reading data stored in the storage device. The write channel includes a first encoding unit that performs run-length encoding of data, and a second encoding that encodes the data encoded by the first encoding unit using a low-density parity check code And a writing unit that writes the data encoded by the second encoding unit to the storage device. The read channel includes an input unit, an analog / digital conversion unit, a soft output detection unit, a first decoding unit, and a second decoding unit. The input unit is an analog signal output from the storage device via the magnetoresistive element, and the dynamic range in the positive section and the dynamic range in the negative section are asymmetric, and one of the sections includes a nonlinear section Enter. The analog-digital conversion unit converts the analog signal input from the input unit into a digital signal and outputs the digital signal. The soft output detection unit calculates the likelihood of the digital signal output from the analog-digital conversion unit and outputs a soft decision value. The first decoding unit decodes the data output from the soft output detection unit and corresponds to the second encoding unit. The second decoding unit decodes the data decoded by the first decoding unit and corresponds to the first encoding unit. The analog-to-digital conversion unit cancels the non-linearity in the non-linear section with respect to the analog signal before converting the analog signal to the digital signal when the amplitude of the analog signal input from the input unit exists in the non-linear section. A pre-adjustment unit for adjusting the amplitude; According to this aspect, it is possible to reduce the influence of the asymmetry of the amplitude generated in the magnetoresistive element, and it is possible to access the storage system at a higher speed.

  Yet another embodiment of the present invention is also a storage system. The storage system further includes a storage device that stores data, and a control unit that controls writing to the storage device and reading from the storage device. The read channel reads data stored in the storage device via the magnetoresistive element in accordance with an instruction from the control unit, and the write channel writes encoded data to the storage device in accordance with the instruction from the control unit. According to this aspect, it is possible to reduce the influence of the asymmetry of the amplitude generated in the magnetoresistive element, and it is possible to access the storage system at a higher speed.

  Yet another embodiment of the present invention is an amplitude adjusting device. This apparatus is integrated on a single semiconductor substrate. According to this aspect, a low-scale semiconductor integrated circuit can be realized by being integrated.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the present invention, it is possible to provide a storage device that can further reduce amplitude asymmetry with a smaller circuit scale.

  Before specifically describing the embodiment of the present invention, an outline of the storage device according to the present embodiment will be described first. The storage device according to the present embodiment includes a hard disk controller, a magnetic disk device, and a read / write channel including a read channel and a write channel. In a magnetic disk device, data stored in a hard disk is usually read through a head including a magnetoresistive element (hereinafter referred to as “MR element”). Here, in the waveform of the signal read from the hard disk, the output amplitude of the positive pulse and the output amplitude of the negative pulse may be asymmetric, which has become a bottleneck for speeding up. Therefore, in the embodiment of the present invention, amplitude asymmetry is improved when an analog signal read in the read channel is converted into a digital signal. Although details will be described later, the asymmetry of the amplitude is reduced by setting the input / output characteristics of the analog-digital converter so as to cancel the asymmetry of the amplitude.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a magnetic disk device 100 according to an embodiment of the present invention. 1 is broadly divided into a hard disk controller 1 (hereinafter abbreviated as “HDC1”), a central processing unit 2 (hereinafter abbreviated as “CPU2”), and a read / write channel 3 ( Hereinafter, abbreviated as “R / W channel 3”), voice coil motor / spindle motor control unit 4 (hereinafter abbreviated as “VCM / SPM control unit 4”), and disk enclosure 5 (hereinafter “DE5”). Is abbreviated as “.”). In general, the HDC 1, CPU 2, R / W channel 3, and VCM / SPM control unit 4 are configured on the same substrate.

  The HDC 1 includes a main control unit 11 that controls the entire HDC 1, a data format control unit 12, an error correction coding control unit 13 (hereinafter abbreviated as “ECC control unit 13”), and a buffer RAM 14. The HDC 1 is connected to the host system via an interface unit (not shown). Further, it is connected to the DE 5 via the R / W channel 3, and performs data transfer between the host and the DE 5 under the control of the main control unit 11. A read reference clock (RRCK) generated by the R / W channel 3 is input to the HDC 1. The data format control unit 12 converts the data transferred from the host into a format suitable for recording on the disk medium 50, and conversely, suitable for transferring the data reproduced from the disk medium 50 to the host. Convert to format. The disk medium 50 includes, for example, a magnetic disk. The ECC control unit 13 adds redundant symbols using data to be recorded as information symbols in order to enable correction and detection of errors contained in data reproduced from the disk medium 50. The ECC control unit 13 determines whether or not an error has occurred in the reproduced data, and corrects or detects if there is an error. However, the number of symbols that can correct errors is limited, and is related to the length of redundant data. That is, if a large amount of redundant data is added, the format efficiency deteriorates, so that there is a trade-off with the number of error correctable symbols. When error correction is performed using Reed-Solomon (RS) code as ECC, up to (redundant symbols / 2) errors can be corrected. The buffer RAM 14 temporarily stores data transferred from the host and transfers it to the R / W channel 3 at an appropriate timing. On the contrary, the read data transferred from the R / W channel 3 is temporarily stored and transferred to the host at an appropriate timing after the ECC decoding process or the like is completed.

  The CPU 2 includes a flash ROM 21 (hereinafter abbreviated as “FROM 21”) and a RAM 22, and is connected to the HDC 1, the R / W channel 3, the VCM / SPM control unit 4, and the DE 5. The FROM 21 stores an operation program for the CPU 2.

  The R / W channel 3 is roughly divided into a write channel 31 and a read channel 32, and transfers data to be recorded and reproduced data to and from the HDC 1. The R / W channel 3 is connected to the DE 5 and transmits a recording signal and receives a reproduction signal. Details will be described later.

  The VCM / SPM control unit 4 controls a voice coil motor 52 (hereinafter abbreviated as “VCM52”) and a spindle motor 53 (hereinafter abbreviated as “SPM53”) in the DE 5.

  The DE 5 is connected to the R / W channel 3 and receives a recording signal and transmits a reproduction signal. The DE 5 is connected to the VCM / SPM control unit 4. The DE 5 includes a disk medium 50, a head 51, a VCM 52, an SPM 53, a preamplifier 54, and the like. In the magnetic disk device 100 of FIG. 1, it is assumed that there is one disk medium 50 and the head 51 is disposed only on one surface side of the disk medium 50. May be arranged in a stacked manner. The head 51 is generally provided corresponding to each surface of the disk medium 50. The recording signal transmitted by the R / W channel 3 is supplied to the head 51 via the preamplifier 54 in the DE 5 and is recorded on the disk medium 50 by the head 51. Conversely, a signal reproduced from the disk medium 50 by the head 51 is transmitted to the R / W channel 3 via the preamplifier 54. The VCM 52 in the DE 5 moves the head 51 in the radial direction of the disk medium 50 in order to position the head 51 at a target position on the disk medium 50. The SPM 53 rotates the disk medium 50. As described above, the output amplitude of the head 51 is asymmetric due to the MR element. Details will be described later.

  Here, the R / W channel 3 will be described with reference to FIG. FIG. 2 is a diagram showing a configuration of the R / W channel 3 of FIG. The R / W channel 3 is roughly composed of a write channel 31 and a read channel 32.

  The write channel 31 includes a byte interface unit 301, a scrambler 302, a run length limited encoding unit 303 (hereinafter abbreviated as “RLL encoding unit 303”), and a low density parity check encoding unit 304 (hereinafter referred to as “LDPC”). An encoding unit 304 ”, a write compensation unit 305 (hereinafter abbreviated as“ write precon unit 305 ”), and a driver 306.

  In the byte interface unit 301, data transferred from the HDC 1 is processed as input data. Data to be written on the medium is input from the HDC 1 in units of one sector. At this time, not only user data (512 bytes) for one sector but also ECC bytes added by the HDC 1 are input simultaneously. The data bus is normally 1 byte (8 bits) and is processed as input data by the byte interface unit 301. The scrambler 302 converts the write data into a random series. This is because the repetition of data with the same rule adversely affects the detection performance at the time of reading and prevents the error rate from deteriorating. The RLL encoding unit 303 is for limiting the maximum continuous length of zero. By limiting the maximum continuous length of 0, a data series suitable for the automatic gain control unit 317 (hereinafter abbreviated as “AGC317”) or the like is obtained.

  The LDPC encoding unit 304 has a role of generating a sequence including parity bits, which are redundant bits, by LDPC encoding the data sequence. LDPC encoding is performed by multiplying a k × n matrix called a generator matrix by a data sequence of length k from the left. Each element included in the parity check matrix H corresponding to this generator matrix is 0 or 1, and since the number of 1 is smaller than the number of 0, it is called a low density parity check code (Low Density Parity Check Codes). It is. By using this arrangement of 1 and 0, the LDPC iterative decoding unit can efficiently correct errors.

  The write pre-con unit 305 is a circuit that compensates for non-linear distortion due to continuous magnetization transitions on the medium. A rule necessary for compensation is detected from the write data, and the write current waveform is adjusted in advance so that the magnetization transition occurs at the correct position. The driver 306 is a driver that outputs a signal corresponding to the pseudo ECL level. The output from the driver 306 is sent to the DE 5 (not shown), sent to the head 51 through the preamplifier 54, and the write data is recorded on the disk medium 50.

  The read channel 32 includes a variable gain amplifier 311 (hereinafter abbreviated as “VGA 311”), a low-pass filter 312 (hereinafter abbreviated as “LPF 312”), an AGC 317, a digital / analog converter 313 (hereinafter “ADC 313”). And a frequency synthesizer 314, a filter 315, a soft output detection unit 320, an LDPC repetition decoding unit 322, a synchronization signal detection unit 321, and a run length limited decoding unit 323 (hereinafter abbreviated as "RLL decoding unit 323"). ), A descrambler 324.

  The VGA 311 and AGC 317 adjust the amplitude of the read waveform of data sent from the preamplifier 54 (not shown). The AGC 317 compares the ideal amplitude with the actual amplitude, and determines the gain to be set in the VGA 311. The LPF 312 can adjust the cutoff frequency and the boost amount, and is responsible for part of the reduction to high-frequency noise and equalization to a partial response (hereinafter referred to as “PR”) waveform. The LPF 312 equalizes the PR waveform, but it is difficult to completely equalize with the analog LPF due to many factors such as fluctuations in the flying height of the head, non-uniformity of the medium, and fluctuations in the rotation of the motor. Then, equalization to the PR waveform is performed again using the filter 315 having more flexibility. The filter 315 may have a function of adaptively adjusting the tap coefficient. The frequency synthesizer 314 generates a sampling clock for the ADC 313.

  The ADC 313 is configured to directly obtain synchronous samples by AD conversion. In addition to this configuration, an asynchronous sample may be obtained by AD conversion. In this case, a zero-phase restart unit, a timing control unit, and an interpolation filter may be further provided after the ADC 313. Synchronous samples need to be obtained from asynchronous samples, and these blocks play that role. The zero phase restart unit is a block for determining an initial phase, and is used to obtain a synchronization sample as soon as possible. After determining the initial phase, the timing controller compares the ideal sample value with the actual sample value to detect a phase shift. A synchronous sample can be obtained by determining parameters of the interpolation filter using this. The ADC 313 is configured to have an input / output characteristic opposite to the asymmetry, and improves the amplitude asymmetry generated in the head 51. Details will be described later.

  The soft output detection unit 320 is a soft output Viterbi algorithm (Soft-Output Viterbi Algorithm; hereinafter abbreviated as “SOVA”), which is a kind of Viterbi algorithm in order to avoid degradation of decoding characteristics due to intersymbol interference. Used. That is, in order to solve the problem that the interference between recorded codes increases and the decoding characteristics deteriorate as the recording density of magnetic disk devices increases in recent years, a partial response due to intersymbol interference is a method for overcoming this problem. The most likely decoding (Partial Response Maximum Like Like) (hereinafter abbreviated as “PRML”) method is used. PRML is a method for obtaining a signal sequence that maximizes the likelihood of a partial response of a reproduction signal.

  When the SOVA method is used as the soft output detection unit 320, a soft decision value is output. For example, assume that a soft decision value (−0.71, +0.18, +0.45, −0.45, −0.9) is output as the SOVA output. These values represent numerical values as to whether the possibility of being 0 or 1 is high. For example, the first “−0.71” indicates that the possibility of 1 is large, and the second “+0.18” is likely to be 0, but the possibility of 1 is small. Means no. The output of the conventional Viterbi detector is a hard value, and the output of SOVA is hard-decided. In the case of the above example, it is (1, 0, 0, 1, 1). The hard value represents only whether it is 0 or 1, and information on which is more likely is lost. For this reason, decoding performance is improved by inputting a soft decision value to the LDPC iterative decoding unit 322.

  The LDPC iterative decoding unit 322 has a role of restoring an LDPC encoded data sequence to a sequence before LDPC encoding. As a decoding method, there are mainly a sum-product decoding method and a min-sum decoding method. The sum-product decoding method is advantageous in terms of decoding performance, but the min-sum decoding method is realized by hardware. With the feature that is easy. In an actual decoding operation using an LDPC code, very good decoding performance can be obtained by performing iterative decoding between the soft output detection unit 320 and the LDPC iterative decoding unit 322. For this reason, a configuration is actually required in which a plurality of stages of software output detection units 320 and LDPC iterative decoding units 322 are arranged.

  The synchronization signal detection unit 321 has a role of detecting a synchronization signal (Sync Mark) added to the head of data and recognizing the head position of the data. The RLL decoding unit 323 performs the reverse operation of the RLL encoding unit 303 of the write channel 31 on the data output from the LDPC iterative decoding unit 322 to restore the original data series. The descrambler 324 performs the reverse operation of the scrambler 302 of the write channel 31 to restore the original data series. The data generated here is transferred to the HDC 1.

  These configurations can be realized in terms of hardware by a CPU, memory, or other LSI of an arbitrary computer, and in terms of software, they are realized by a program having a communication function loaded in the memory. The functional block realized by those cooperation is drawn. Accordingly, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

Here, the input / output characteristics of the head 51 of FIG. 1 and the input / output characteristics desired for the ADC 313 of FIG. 2 will be described. FIG. 3A is a diagram illustrating an example of input / output characteristics of the head 51 of FIG. The horizontal axis represents the input magnetic field Hin, and the vertical axis represents the output voltage Vout. The input magnetic field takes a value in the range of Hin0_min to Hin0_max. When there is no non-linearity due to the MR element of the head 51, the output voltage has a value in the range of Vout0_min to Vout0_max as illustrated by a broken line. However, if the non-linearity due to the MR elements of the head 51 is present, as shown by the solid line, the output voltage is a value in the range of Vout0_min~V ^'out0_max. That is, the input / output characteristics are asymmetric with respect to the origin. FIG. 3A shows that the input / output characteristics are nonlinear in the non-linear section 200 in the positive section. Therefore, the output voltage when the input voltage is Vin0_max becomes V ^'out0_max to not become Vout0_max. FIG. 3B is a diagram illustrating an example of output characteristics of the LPF 312 in FIG. FIG. 3B is a diagram showing that the dynamic range of the output voltage of the head 51 shown in FIG. The horizontal axis represents the input magnetic field Hin, and the vertical axis represents the output voltage Vout. The input magnetic field takes a value in the range of Hin0_min to Hin0_max.

FIG. 3C is a diagram illustrating an example of an output waveform of the head 51 in FIG. The horizontal axis represents time, and the vertical axis represents output voltage. FIG. 3C illustrates that the positive section and the negative section are asymmetric with respect to 0V. That is, the head 51, indicating that the amplitude energy is reduced by (Vout0_max-V ^'out0_max). As a result, the detection accuracy of data detection (not shown) existing in the subsequent stage deteriorates. Further, the error correction capability of an error correction circuit (not shown) existing in the subsequent stage is deteriorated. Note that the non-linearity caused by the MR element means that the dynamic range in the positive section and the dynamic range in the negative section become asymmetric as shown in FIG.

4A and 4B are diagrams illustrating examples of input / output characteristics of the ADC 313 in FIG. The horizontal axis represents the input voltage Vin, and the vertical axis represents the output voltage Vout. The output voltage shown in FIGS. 4A to 4B is not the digital signal output in the ADC 313 but the output voltage of the analog signal whose amplitude is adjusted in the ADC 313. The input voltage takes a value in the range of Vin1_min to Vin1_max. Further, when there is non-linearity due to the MR element of the head 51, the output voltage has a value in the range of Vout1_min to Vout1_max as illustrated by the solid line. FIG. 4A shows a case where the ADC 313 is provided with a characteristic corresponding to the reverse characteristic in order to eliminate the non-linearity caused by the MR element of the head 51 shown in FIG. 4B, the ADC 313 is provided with a characteristic corresponding to the reverse characteristic in order to eliminate the non-linearity caused by the MR element of the head 51 shown in FIG. 3B and the distortion caused by the LPF 312. Indicates the case. Here, assuming that there is no voltage fluctuation between the head 51 and the ADC 313, the voltages illustrated in FIGS. 3A to 3B and 4A to 4B are as follows. It becomes a relationship.
Vin1_max = V ^'out0_max ··· formula (1)
Vout1_max = Vout0_max Expression (2)

・・・式（３）
したがって、ＡＤＣ３１３の入出力特性としては、たとえば次式で示すような、双曲線正接関数の逆特性に相当する特性とすればよい。ここで、ａは実数であり、ヘッド５１の特性により決定されてもよい。

・・・式（４） These mean that the nonlinearity caused by the MR element included in the head 51 has been eliminated. In other words, the ADC 313 is provided with a characteristic that is an inverse characteristic of the input / output characteristics in each nonlinear section 200 of FIGS. 3A to 3B, that is, a characteristic in the nonlinear section 300 in FIGS. 4A to 4B. By doing so, the nonlinearity caused by the MR element can be eliminated. It is known that the input / output characteristics in the non-linear section 200 in FIG. 3A are generally hyperbolic tangent functions as shown in the following equation.

... Formula (3)
Therefore, the input / output characteristic of the ADC 313 may be a characteristic corresponding to the inverse characteristic of the hyperbolic tangent function, as shown by the following equation, for example. Here, a is a real number, and may be determined by the characteristics of the head 51.

... Formula (4)

  FIG. 4C is a diagram illustrating an example of the input / output characteristics of the ADC 313 when the input / output characteristics in the nonlinear section 300 of FIG. 4B are approximated by two linear functions. 4C, as in FIG. 4B, the horizontal axis indicates the input voltage, and the vertical axis indicates the output voltage. The input voltage takes a value in the range of Vin1_min to Vin1_max. Further, the output voltage has a value in the range of Vout1_min to Vout1_max. As described above, in order to eliminate the non-linearity caused by the MR element, the input / output characteristic of the ADC 313 may be set to a characteristic opposite to the hyperbolic tangent function. However, it is generally difficult to achieve this characteristic. Therefore, in the embodiment of the present invention, approximation is made with two linear functions as shown in FIG. Specifically, when the input voltage is in the range of Vin1a to Vin1b, the input / output characteristics represented by the first linear function 330 are used. When the input voltage is in the range of Vin1b to Vin1_max, the input / output characteristics represented by the second linear function 340 may be used.

  Here, a specific configuration of the ADC 313 that realizes the input / output characteristics shown in FIG. FIG. 5 is a diagram illustrating a configuration example of the ADC 313 in FIG. 2. The ADC 313 includes a front adjustment unit 60 and a discretization unit 62 indicated by broken lines. Although the case where an analog signal is converted into a digital signal consisting of 3 bits is shown here, the present invention is not limited to this.

  When the amplitude of the analog signal input from the input unit is present in the nonlinear section, the ADC 313 converts the analog signal into a digital signal while adjusting the amplitude, and outputs the digital signal. That is, the pre-adjustment unit 60 adjusts the amplitude of the analog signal so as to cancel the nonlinearity in the nonlinear section before converting the analog signal into a digital signal. Specifically, the pre-adjustment unit 60 adjusts the amplitude of the analog signal in the nonlinear section by setting the input / output characteristics in the nonlinear section as an approximate value of the inverse of the hyperbolic tangent function. Next, the discretization unit 62 converts the analog signal whose amplitude has been adjusted by the pre-adjustment unit 60 into a 3-bit digital signal and outputs it.

  The pre-adjustment unit 60 has a first primary having a first slope greater than at least 1 as input / output characteristics of the first partial section of the plurality of partial sections in the plurality of partial sections included in the nonlinear section. A function 330 is set. In addition, a second linear function 340 having a slope different from the first slope is set as the input / output characteristic of the second partial section that is continuous with the first partial section among the plurality of partial sections. Here, the first partial section refers to, for example, the section from Vin1a to Vin1b illustrated in FIG. Further, the second partial section that is continuous with the first partial section is, for example, a section from Vin1b to Vin1_max illustrated in FIG. When the input / output characteristics of the second partial section are the input / output characteristics shown in FIG. 4C, the slope of the second linear function 340 is set to be smaller than the first slope.

  This will be specifically described. The pre-adjustment unit 60 includes a first resistance element 64, a second resistance element 66, a third resistance element 68, a fourth resistance element 70, a fifth resistance element 72, and a sixth resistance element 74, represented by a resistance element 400. A seventh resistance element 76, an eighth resistance element 78, a ninth resistance element 80, and a comparison unit 82 are included. Each of the resistance elements 400 is installed in series and receives a reference signal Vref having a constant voltage as input, and sequentially outputs reference signals whose amplitudes are adjusted to the subsequent resistance elements. Next, the comparison unit 82 adjusts the amplitude of the analog signal by comparing the reference signal output from each of the plurality of resistance elements 400 with the amplitude of the analog signal input from the LPF 312. That is, an analog signal having a temporally continuous value is compared with a reference signal output from each resistance element 400, and eight discrete signals are output according to the magnitude relationship. The eight signals here are analog signals, but each has a constant amplitude indicating either plus or minus.

  The plurality of resistance elements 400 change the decrease width of the voltage output from each resistance element by making each resistance value non-uniform value. Specifically, the voltage Vref of the reference signal applied to each resistance element is reduced and output according to the resistance value at the output of each resistance element. That is, the voltage is reduced as the resistance value is increased, and the degree of reduction is decreased as the resistance value is decreased. In other words, in each of the plurality of resistance elements 400, by making each resistance value non-uniform value for each section, the voltage adjustment width in each resistance element 400 is different, and thereby, the slope of the input / output characteristics is changed for each section. Can be changed. In the embodiment of the present invention, in each of the first partial section and the second partial section, which are nonlinear sections, the resistance value of the corresponding resistive element 400 is different from the resistance value of the other resistive elements, so The slope of the output characteristics is adjusted.

  For example, it is assumed that resistance elements corresponding to sections other than the first partial section or the second partial section are a fifth resistance element 72, a sixth resistance element 74, a seventh resistance element 76, and an eighth resistance element 78. These resistance values are assumed to be R. Further, it is assumed that the resistance elements corresponding to the first partial section are the third resistance element 68 and the fourth resistance element 70. Further, it is assumed that the resistance element corresponding to the second partial section is the second resistance element 66. In this case, the resistance values of the third resistance element 68 and the fourth resistance element 70 corresponding to the first partial section are smaller than the resistance value R of the resistance element corresponding to a section other than the first partial section or the second partial section. A value, for example, R / 3 may be set. The resistance value of the second resistance element 66 corresponding to the second partial section may be set to a value larger than the resistance value R, for example, 2R. In general, the first resistance element 64 and the ninth resistance element 80 which are resistance elements at both ends are set to a value R / 2 which is half of the resistance value R of the normal resistance element.

6A to 6C are diagrams illustrating examples of output signal characteristics of the soft output detection unit 320 of FIG. In each figure, the vertical axis represents the bit error rate, and the horizontal axis represents the signal-to-noise ratio (Signal to Noise Ratio). FIG. 6A applies the first bit error rate characteristic 350 of the soft output detector 320 when the input / output characteristic of the head 51 of FIG. 1 has an asymmetry of 5%, and the embodiment of the present invention. It is a figure which shows the 2nd bit error rate characteristic 360 in the case. FIG. 6A further shows the third bit error rate characteristic when the above-described asymmetry can be ideally eliminated, or when the input / output characteristic does not exist in the head 51 of FIG. FIG. The asymmetry of 5% means that the dynamic range V1 in the positive interval is about 90% of the dynamic range V2 in the negative interval (V1 = V2 × (1−0.05) / (1 + 0.05) ≈0.9 × V2). It means that. As illustrated in the second bit error rate characteristic 360 of FIG. 6A, the bit error rate characteristic can be improved by applying the embodiment of the present invention. For example, as shown in the second bit error rate characteristic 360, the desired SNR when the bit error rate is 10 ⁻⁵ is improved by about 0.1 dB compared to the first bit error rate characteristic 350 to which the embodiment of the present invention is not applied. Has been.

  In general, in the field of storage devices such as hard disks, it is generally known that about one generation of technological innovation is necessary to improve the bit error rate by about 0.1 dB. Therefore, it goes without saying that the bit error rate improvement of 0.1 dB according to the embodiment of the present invention is a remarkable effect for those skilled in the art.

  FIG. 6B is a diagram showing the bit error rate characteristics when 10% asymmetry exists in the input / output characteristics in the head 51 of FIG. FIG. 6C is a diagram showing the bit error rate characteristics when the input / output characteristics have a 15% asymmetry in the head 51 of FIG. As illustrated in the second bit error rate characteristic 360 of FIGS. 6B and 6C, as in FIG. 6A, the embodiment of the present invention reduces amplitude asymmetry, In addition, the bit error rate can be remarkably improved.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications can be made to combinations of the embodiments or combinations of their constituent elements and processing processes, and such modifications are also within the scope of the present invention. It will be understood by those skilled in the art.

  According to the present embodiment, by adjusting the amplitude of the analog signal in the analog-to-digital converter, the nonlinearity of the amplitude generated in the magnetoresistive element can be reduced. Further, by reducing the nonlinearity of the amplitude generated in the magnetoresistive element, the error characteristics after error correction decoding can be remarkably improved. In addition, by simply setting the resistance values of a plurality of resistance elements included in the analog-digital conversion unit, it is possible to reduce the amplitude asymmetry of the analog signal with a small-scale and highly stable circuit. Further, the storage system can be accessed at a higher speed by reducing the influence of the asymmetry of the amplitude generated in the magnetoresistive element. Moreover, since it is not necessary to install extra hardware, a low-scale semiconductor integrated circuit can be realized.

  Next, a modification of the embodiment of the present invention will be shown. First, an overview. The present modification relates to a storage system that reduces amplitude asymmetry caused by an MR element included in a head. In the present modification, the magnetic disk device 100 has the same configuration as that shown in FIG. The R / W channel 3 has the same configuration as that shown in FIG. The difference in the embodiment of the present invention is that the ADC 313 in FIG. 2 has the configuration in FIG. 7. That is, this modification is characterized in that the resistance value in the analog-digital converter included in the storage system is variable. In addition, the same code | symbol is attached | subjected about the part which is common in embodiment mentioned above, and description is simplified.

  FIG. 7 is a diagram illustrating a modified example of the configuration of the ADC 313 in FIG. 2. The ADC 313 includes a pre-adjustment unit 60, a discretization unit 62, and a resistance value control unit 86. The resistance value control unit 86 controls the resistance value of the resistance element 400 included in the pre-adjustment unit 60 in accordance with an instruction from the outside. The “external instruction” includes an instruction from a circuit other than the ADC 313, and may be an instruction from the LDPC iterative decoding unit 322, for example. In this case, the error correction result in the LDPC iterative decoding unit 322 is notified, and if the result is good, the resistance value of the pre-adjustment unit 60 is not changed. Good. In addition, the resistance value control unit 86 instructs the pre-adjustment unit 60 regarding the resistance element whose resistance value is to be changed and the resistance value after the change in response to a user instruction via an interface (not shown). Also good. In this case, the resistance value control unit 86 controls the pre-adjustment unit 60 so that the designated resistance element 400 has the designated resistance value.

  FIG. 8 is a diagram showing a modification of the configuration of the resistance element 400 of FIG. The resistance element 400 includes a first adjustment resistance element 84a represented by the adjustment resistance element 84, a second adjustment resistance element 84b, an nth adjustment resistance element 84n, and a first switching section 88a represented by the switching section 88. , M-th switching unit 88m. n is an integer of 2 or more, and m is an integer of 1 or more. Each switching unit 88 turns the switch on or off based on an instruction from the resistance value control unit 86. A specific example will be described. For example, it is assumed that the resistance values of all the adjustment resistance elements 84 are 2R. In this case, when any switching unit 88 is OFF, the resistance value in the resistance element 400 is 2R. When only one of the switching units 88 is ON, the resistance value in the resistance element 400 is R. Further, when the k switching units 88 are ON, the resistance value in the resistance element 400 is 2R / k. In other words, for the resistance element 400 corresponding to a section other than the non-linear section, the resistance value control unit 86 turns on any one switching unit 88 and sets its resistance value to R. Further, for the resistance element 400 corresponding to the non-linear section, the resistance value control unit 86 may set 0 or two or more switching units 88 to ON and set the resistance value to a value other than R. Note that only one or more of the plurality of resistance elements included in the pre-adjustment unit 60 may be configured as shown in FIG. Further, the resistance values of the adjustment resistance elements 84 need not all be the same. Even in these cases, it goes without saying that the same effect can be obtained by appropriately changing the control of the switching unit 88 by the resistance value control unit 86.

  FIG. 9 is a diagram illustrating a modification of the configuration of the front adjustment unit 60 of FIG. A pre-adjustment unit 60 shown in FIG. 9 has a configuration in which a reference voltage control unit 90 is added to the pre-adjustment unit 60 shown in FIG. In addition, the same code | symbol is attached | subjected about the part which is common in the front adjustment part 60 shown in FIG. 5 mentioned above, and description is simplified. The reference voltage control unit 90 is connected to the input terminals of at least one of the plurality of resistance elements, and applies a corresponding reference voltage to each of the input terminals, thereby each of the plurality of resistance elements. The amplitude of the reference signal output from is adjusted. In the present modification, the plurality of resistance elements may have the same resistance value. Further, the reference voltage control unit 90 applies a reference voltage different from the input end of the resistance element corresponding to the section other than the non-linear section to the input end of the resistance element corresponding to the non-linear section among the plurality of resistance elements. May adjust the non-linearity in the non-linear section. Here, the “corresponding reference voltage” includes a reference voltage determined in association with each resistive element, may be set in advance, and dynamically changes according to the quality of the magnetoresistive element. May be. According to this aspect, the reference voltage controller can flexibly control the amplitude of the reference signal. Further, since the resistance values of the plurality of resistance elements included in the analog-digital conversion unit can be made the same, the circuit cost can be reduced. In addition, the amplitude asymmetry of the analog signal can be reduced with a small circuit.

  In the above, the modification of this invention was demonstrated based on embodiment. This modification is an exemplification, and various other modifications are possible in the combination of the embodiments, or in the combination of each component and each process, and such a modification is also within the scope of the present invention. This will be understood by those skilled in the art.

  According to the modification of this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, by making the resistance value of the resistance element variable, it is possible to flexibly improve the nonlinearity of the amplitude.

  In the present embodiment, the input / output characteristics of the head 51 have been described as having a non-linear section in the positive section. However, the present invention is not limited to this, and nonlinearity may exist in the negative interval. Even in this case, the same effect can be obtained by making the resistance value of the resistance element 400 corresponding to the non-linear section different from the resistance value of other sections. The R / W channel 3 may be integrated on a single semiconductor substrate.

1 is a diagram showing a configuration of a magnetic disk device according to an embodiment of the present invention. It is a figure which shows the structure of the R / W channel of FIG. FIG. 3A is a diagram showing an example of input / output characteristics of the head of FIG. FIG. 3B is a diagram illustrating an example of output characteristics of the LPF in FIG. FIG. 3C is a diagram illustrating an example of an output waveform of the head of FIG. 4A to 4C are diagrams illustrating examples of input / output characteristics of the ADC of FIG. It is a figure which shows the structural example of ADC of FIG. 6A to 6C are diagrams illustrating examples of output signal characteristics of the soft output detection unit in FIG. FIG. 3 is a diagram illustrating a modification of the configuration of the ADC of FIG. 2. It is a figure which shows the modification of a structure of the resistive element of FIG. It is a figure which shows the modification of a structure of the front adjustment part of FIG.

Explanation of symbols

  1 HDC, 2 CPU, 3 R / W channel, 4 VCM / SPM controller, 5 DE, 11 Main controller, 12 Data format controller, 13 ECC controller, 14 Buffer RAM, 21 FROM, 22 RAM, 31 Write Channel, 32 read channel, 50 disk medium, 51 head, 52 VCM, 53 SPM, 54 preamplifier, 60 pre-adjustment unit, 62 discretization unit, 64 first resistance element, 66 second resistance element, 68 third resistance element , 70 4th resistance element, 72 5th resistance element, 74 6th resistance element, 76 7th resistance element, 78 8th resistance element, 80 9th resistance element, 82 Comparison part, 84 Adjustment resistance element, 84a 1st adjustment Resistance element, 84b second adjustment resistance element, 84n nth adjustment resistance 86, resistance value control unit, 88 switching unit, 88a first switching unit, 88m mth switching unit, 90 reference voltage control unit, 200 nonlinear section, 300 nonlinear section, 301 byte interface section, 302 scrambler, 303 RLL code Unit, 304 LDPC encoding unit, 305 write precon unit, 306 driver, 311 VGA, 312 LPF, 313 ADC, 314 frequency synthesizer, 315 filter, 316 interpolation filter, 317 AGC, 318 zero phase restart unit, 319 timing control 320, soft output detector, 321 synchronization signal detector, 322 LDPC iterative decoder, 323 RLL decoder, 324 descrambler, 330 first linear function, 340 second linear function 350 first bit error rate performance, 360 second bit error rate performance, 370 the third bit error rate characteristic, 400 resistance element.

Claims (10)

An analog signal output from a magnetoresistive element to which an input magnetic field is input, the dynamic range in the positive section and the dynamic range in the negative section become asymmetric, and an analog signal including a non-linear section is input in one of the sections. An input section;
An analog-to-digital conversion unit that compares the amplitude of the analog signal input from the input unit with each of a plurality of reference signals and converts the analog signal into a digital signal; and
The plurality of reference signals are input to the analog-to-digital conversion unit so that the digital signal is data indicating a value obtained by linearly quantizing the input magnetic field. amplitude adjusting device according to claim Rukoto is configured to equip the input-output characteristics becomes. The analog signal has nonlinearity according to a hyperbolic tangent function with respect to the input magnetic field in the nonlinear section,
Wherein the plurality of reference signals, the amplitude controller according to claim 1, characterized in Rukoto is configured to equip the input-output characteristic to be the inverse characteristic of the hyperbolic tangent function in the analog-to-digital conversion unit. The plurality of reference signals have the analog-to-digital converter have input / output characteristics that are linear functions having a first slope in a first partial section among a plurality of partial sections included in the nonlinear section, Further, among the plurality of subintervals, Rukoto is set to equip the input-output characteristics as a linear function having different slopes from the first inclination in a second part section continuous with the first subinterval The amplitude adjusting device according to claim 1, wherein: The analog-digital converter is
A plurality of resistive elements installed in series, each having a constant voltage input to one end, and each resistive element outputting a corresponding reference signal;
A comparison unit that compares a reference signal output from each of the plurality of resistance elements and an amplitude of an analog signal input from the input unit;
Resistance values of the plurality of resistive elements, wherein, wherein Rukoto is configured to equip the input-output characteristic to be the inverse characteristic of the input-output characteristic of the magnetoresistive element in the non-linear section in the analog-digital conversion section Item 4. The amplitude adjusting device according to any one of Items 1 to 3.   The amplitude adjustment apparatus according to claim 4, wherein resistance values of the plurality of resistance elements are non-uniform values. By resistive element corresponding to the non-linear section of the plurality of resistor elements are set to a resistance value different from the resistance value of the resistance element corresponding to the section other than the non-linear sections, the analog-digital converter unit in the non-linear section 6. The amplitude adjusting apparatus according to claim 5, further comprising an input / output characteristic that is opposite to the input / output characteristic of the magnetoresistive element . An analog signal output from a magnetoresistive element to which an input magnetic field is input, the dynamic range in the positive section and the dynamic range in the negative section become asymmetric, and an analog signal including a non-linear section is input in one of the sections. Steps,
An analog-to-digital converter that compares the amplitude of the input analog signal with each of a plurality of reference signals, and converts the analog signal into a digital signal;
The plurality of reference signals are sent to the analog-to-digital conversion unit so that the digital signal becomes data indicating a value obtained by linearly quantizing the input magnetic field. And a step of setting so as to have an input / output characteristic . A signal storage system comprising a write channel for writing data to a storage device and a read channel for reading data stored in the storage device,
The light channel is
A first encoding unit for run-length encoding data;
A second encoding unit that encodes the data encoded by the first encoding unit using a low-density parity check code;
A writing unit for writing the data encoded by the second encoding unit to a storage device;
Have
The lead channel is
An analog signal output from a magnetoresistive element to which an input magnetic field corresponding to data stored in the storage device is input, and the dynamic range in the positive section and the dynamic range in the negative section are asymmetric, either An input unit for inputting an analog signal including a non-linear section in the section of
An analog-to-digital converter that compares the amplitude of the analog signal input from the input unit with each of a plurality of reference signals and converts the analog signal into a digital signal;
A soft output detector that calculates the likelihood of the digital signal output from the analog-digital converter and outputs a soft decision value;
A first decoding unit corresponding to a second encoding unit for decoding the data output from the soft output detection unit;
A second decoding unit corresponding to the first encoding unit, which decodes the data decoded by the first decoding unit;
Have
The plurality of reference signals are input to the analog-to-digital conversion unit so that the digital signal is data indicating a value obtained by linearly quantizing the input magnetic field. storage system according to claim Rukoto is configured to equip the input-output characteristics becomes. 9. The storage system according to claim 8 , further comprising:
A storage device for storing data;
A control unit for controlling writing to the storage device and reading from the storage device;
Have
The read channel reads data stored in the storage device via the magnetoresistive element according to an instruction from the control unit,
The storage system, wherein the write channel writes encoded data into the storage device in accordance with an instruction from the control unit.   2. The amplitude adjusting device according to claim 1, wherein the device is integrated on a single semiconductor substrate.

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