JP4569947B2 - Hard random number monitoring device for gaming machines - Google Patents

Description

  The present invention relates to a hard random number monitoring device capable of identifying a malfunction of a random number generation unit in a gaming machine including a random number generation unit that generates a hard random number at a predetermined timing.

  Conventionally, in gaming machines such as slot machines and pachinko machines, a count value acquired from software by an increment counter (hereinafter referred to as a soft random number) at a predetermined timing or a count value acquired from an increment counter by hardware. The value (hereinafter referred to as a hard random number) and a winning value stored in advance in a ROM (read only memory) are compared to determine the winning of the symbol and the internal winning mode.

  In recent years, software random numbers are subject to fraud because the increment counter operates in synchronization with the external control clock, and the addition speed of the counter is limited by the operation clock of the CPU. Hard random numbers are being widely adopted (see, for example, Patent Document 1).

JP 7-124296 A

  However, in the conventional hard random number method described above, random number generation is performed completely asynchronously with the software, so that it is difficult to discriminate even if an abnormality occurs in the circuit unit that generates the hard random number. There was a problem. In particular, since the random number is formed by a plurality of bits (usually 16 bits), if a failure occurs in a specific bit, for example, the upper component bit portion or the lower component bit portion, the frequency of winning is determined. There is a risk that it will be higher than the original design value and disadvantageous to the game shop, or conversely, the frequency of winning will be reduced and disadvantageous to the player.

  The present invention has been made in order to solve the above-described problems. A hardware in a gaming machine capable of quickly finding a defect in a circuit unit that generates a hard random number and quickly inspecting and replacing the circuit unit. A random number monitoring device is provided.

  The present invention is a hard random number monitoring device 30 in a gaming machine 1 having a random number generator 25 that generates a hard random number at a predetermined timing, and a random number storage means 31 for storing a hard random number acquired from the random number generator 25; The random number comparison unit 32 that reads and compares the hard random number acquired at the current time and the hard random number acquired before the current time from the random number storage unit 31, and the comparison result storage unit 33 that stores the comparison result by the random number comparison unit 32; And a display means 22 for displaying the contents of the comparison results stored in the comparison result storage means 33.

  Preferably, the random number comparison unit 32 includes an upper bit comparison unit 34 and a lower bit comparison unit 35, and the upper and lower bits of the hard random number acquired at the current time are the upper bits of the hard random number acquired before the current time. The bit and the lower bit may be separately compared.

  Further, in the present invention, the random number comparison means 32 is configured to determine whether or not the currently acquired hard random number matches the previously acquired hard random number, and when the number of times of matching reaches a predetermined number of times. You may further provide the alerting | reporting means 45 which can alert | report that.

  According to the present invention, since the comparison result by the random number comparison means is displayed on the display means, a random number that generates a hard random number by confirming the display on the display means after closing, for example, at a game store Abnormality of the generation part can be detected at an early stage, and a board on which a defect has occurred can be repaired or replaced at an early stage. Therefore, it is possible to eliminate the possibility of causing a great disadvantage to the game store or the player.

  In addition, when it is possible to compare the upper bits and the lower bits separately, it is possible to predict a more partial malfunction of the random number generator at an early stage.

  Further, when means for notifying the malfunction of the random number generator is provided, the malfunction can be found almost simultaneously with the occurrence of the malfunction of the random number generator, and the countermeasure can be taken more quickly. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, a case where the present invention is applied to a pachinko gaming machine will be described. First, a schematic configuration of a pachinko gaming machine will be described with reference to FIGS. 1 and 2. Here, FIG. 1 is a front view of a gaming board of a pachinko gaming machine, and FIG. 2 is a rear view showing a back set board of the pachinko gaming machine.

  A game board 3 is accommodated in the front frame 2 of the pachinko gaming machine 1, and a game area 6 is formed on the front surface of the game board 3 on the inner side of the outer rail 4 and the inner rail 5 attached in an annular shape. Yes. In the game area 6, a symbol display device 7 for variably displaying three symbols is arranged at substantially the center, and the symbol display device 7 is provided with four holding lamps 44 on the upper left side when viewed from the front. Yes. In the game area 6, the first start winning opening 8, the second starting winning opening 9, the big winning opening 10, and the general winning opening 11 are arranged around the symbol display device 7. A first start prize sensor 12, a second start prize sensor 13, a big prize sensor 46 (see FIG. 5), and a general prize sensor 47 (see FIG. 5) are provided at the mouths.

  A glass door 14 is provided on the front side of the front frame 2 so as to be openable and detachable with respect to the front frame 2, and the game area 6 formed on the front side of the game board 3 is closed by the glass door 14. It is supposed to be retained. Below the glass door 14 of the front frame 2, an upper ball tray 15 is provided so as to protrude forward. Further, below the upper ball tray 15, a lower ball tray 16 is provided so as to protrude forward. The lower ball tray 16 is provided with a launch handle 17 projecting forward on the right side of the front. When the launch handle 17 is rotated in the clockwise direction, the game ball launched from the upper ball tray 15 enters the game area 6. It is to be sent out.

  A back set board 18 is provided on the back side of the front frame 2, and the back set board 18 is provided so as to be opened and closed by hinges 19 a and 19 b installed on the upper and lower sides when viewed from the back side. 20a, 20b, and 20c are held in a closed state so as to cover the back surface of the game board 3. In addition, the back set board 18 is provided with a game control device 21 at a lower left portion when viewed from the back side, and the game control device 21 is provided with a display means 22 and a display operation switch 23 thereof.

  Next, the game board control device 21 in the present embodiment will be described with reference to FIGS. Here, FIG. 3 is a block diagram showing a part related to generation of a hard random number in the present embodiment, FIG. 4 is a circuit diagram of a main part related to generation of the hard random number, and FIG. 5 is a hard random number according to the present embodiment. It is a block diagram which shows the structure of a monitoring apparatus.

  The game control device 21 includes a main control unit 24 that executes control of the pachinko gaming machine 1 according to a control program, and hardware control regardless of the control of the main roll unit 24 based on detection signals of the winning sensors 12, 13, 46, and 47. The random number generator 25 for generating random numbers, the winning determination means 26 for determining whether or not the hit ball has won, the hit determination means 27 for determining whether or not the acquired hard random number is hit, and the big prize opening solenoid 48 are operated. The special game executing means 28 for executing the special game, the symbol display control means 29 for variably displaying the symbols of the symbol display device 7, and the random number monitoring means 30 for monitoring the hard random numbers.

  As shown in FIG. 5, the random number monitoring unit 30 stores a random number storage unit 31 that stores the hard random number acquired from the random number generation unit 25, and reads the currently acquired hard random number and the previously acquired hard random number from the random number storage unit 31. A random number comparison means 32 for comparison, a comparison result storage means 33 for storing a comparison result by the random number comparison means 32, and a display means 22 for displaying the contents of the comparison result stored in the comparison result storage means 33. Preferably, the random number comparison unit 32 includes an upper bit comparison unit 34 that compares the upper bit and the lower bit of the hard random number acquired this time separately with the upper bit and the lower bit of the previously acquired hard random number, respectively. The low-order bit comparison means 35 is comprised.

  The main control unit 24 includes a control unit including a reference clock generation circuit 36 that generates a reference clock, a frequency division unit 37 that divides a pulse generated by the reference clock generation circuit 36, and a CPU 38, a ROM 39, and a RAM 40. 41, an input circuit unit 42 and an output circuit unit 43, and a notification LED 45 connected to the output circuit unit 43 are provided.

  The reference clock generation circuit 36 is a circuit that generates a reference clock that is an operation reference of the CPU 38 that plays a central role in the control, and generates pulses at predetermined intervals using a crystal oscillator, a crystal resonator, or the like. In the present embodiment, the reference clock generation circuit 36 generates a 4.096 MHz pulse, and this pulse itself is used as a reference clock. A reference clock can be obtained by appropriately dividing this pulse. The ROM 39 stores a control program to be executed by the CPU 38 and data necessary for the control process, and the RAM 40 temporarily stores parameter values generated and changed during the control process.

  The input circuit unit 42 is used to input input information from the outside of the game control device 21 and a random number generated by the random number generation unit 25 provided in the game control device 21, and is configured by a buffer IC or the like. Has been. Specifically, the input circuit unit 42 receives a first sensor input unit to which an input signal from the first start prize sensor 12 is input, and a second sensor input to which an input signal from the second start prize sensor 13 is input. And an upper random number reading unit to which upper 8 bits of the random number generated by the random number generation unit 25 are input and a lower random number reading unit to which lower 8 bits are input are provided.

  Each of the first sensor input unit and the second sensor input unit is provided with a capacitor for removing chattering of the winning signal and an inverting circuit for logical inversion. Specifically, as shown in FIG. 4, SW1 as the first start winning sensor 12 is electrically connected to CN1. The signal input through CN1 is divided to an appropriate voltage value by R1, R2, and C1, chattering is removed, and then input to the 1A terminal of IC14. Then, the signal is input from the 1Y terminal of the IC 14 to the A1 terminal of the IC 15 and finally input from the Y1 terminal to the first sensor input unit. Similarly, the signal from the second start winning sensor 13 (SW2) passes from CN2 through R3, R4 and C2, and further through the 2A terminal and 2Y terminal of IC14 and the A2 terminal and Y2 terminal of IC15 to the second sensor input section. Is input. Therefore, the signals passing through these input units are input as a high signal when winning a prize and as a low signal when not winning a prize, respectively. The input buffer IC 15 is configured to output the data input to the An terminal from the Yn terminal in response to the input of the inverted R5 signal from the control unit 41 having the CPU 38, the ROM 39, and the RAM 40.

  The output circuit unit 43 is for outputting signals such as control signals to external electrical components of the game control device 21 and signals for reading random numbers generated by the random number generation unit 25 provided in the game control device 21. Further, it is configured by an IC such as a buffer. Specifically, the output circuit unit 43 sends a signal to a sub-control device (not shown) that controls each part based on a control signal from the game control device 21 such as a symbol display device 7 or a prize ball control device (not shown). It is determined that the sub control signal output unit for outputting, the solenoid drive signal output unit for outputting the drive signal for driving the large winning port solenoid 48 for opening / closing the large winning port, and the game control device 21 has won the first start winning port 8. The first latch trigger signal output unit for outputting a first latch trigger signal that triggers the latching of the random number value corresponding to the winning, and when the game control device 21 determines that the second starting winning opening 9 has been won A second latch trigger signal output unit that outputs a second latch trigger signal that triggers the latching of the random number value corresponding to, when the game control device 21 determines that the first start winning opening 8 has been won When it is determined that the first read signal output unit that outputs the first read signal that triggers the reading of the random value corresponding to the winning and the game control device 21 has won the second start winning opening 9, Is provided with a second read signal output unit that outputs a second read signal that triggers the reading of the random value corresponding to.

  The random number generation unit 25 generates a count value used as a random number. Specifically, as shown in FIG. 3, a random number clock generation circuit 49, a random number clock inversion circuit 50, a first latch signal output circuit 51, a second latch signal output circuit 52, a clock count circuit 53, a first count value storage circuit 54, and a second count value storage circuit 55. In the present invention, the random number is not only a value randomly generated in a mathematical sense, but even if the generation is regular, the acquisition timing is random, so that the random number substantially functions as a random number. It also includes possible values.

  The random number clock generation circuit 49 is for generating a random number clock, and includes a random number clock output unit for outputting the generated random number clock. Specifically, a crystal oscillator (OSCI) that generates a 14.9105 MHz clock (hereinafter referred to as “original oscillation”) that is asynchronous with the reference clock, and an output terminal of the crystal oscillator are connected to the original oscillation. Is divided by ½ and is output from the IC 18 that functions as a flip-flop circuit that outputs the random number clock to the clock count circuit 53 (IC1 to IC4). That is, in the IC 18 of FIG. 4, a functional part that is output from the IQ terminal of the random number clock output unit as a random number clock obtained by dividing the original oscillation by ½ constitutes a part of the random number clock generation circuit 49. ing.

  The random number clock inversion circuit 50 is constituted by the IC 18 and inverts the random number clock output from the random number clock generation circuit 49 via the random number clock output unit (1Q), and uses this as the inverted clock to generate an inverted clock output unit (inversion 1Q). ) To the first latch signal output circuit 51 (IC16) and the second latch signal output circuit 52 (IC17). That is, in the IC 18 of FIG. 4, a functional part that outputs a signal obtained by inverting the signal output from the 1Q terminal as an inverted signal and outputs from the inverted 1Q terminal of the inverted clock output unit constitutes the random number clock inverting circuit 50. It has become.

  The clock count circuit 53 includes a random number clock input unit that inputs a random number clock and a count output unit that outputs the counted value. Specifically, as shown in FIG. 4, it is configured by a circuit in which four 4-bit increment counters (IC1 to IC4) are cascade-connected, and is added at the rising edge of the random number clock generated by the random number clock generation circuit 49, It is a circuit for outputting the addition result.

  A random number clock from the random number clock generation circuit 49 is input to the clock count circuit 53 via a random number clock input unit (each CK terminal). When a random number clock is input, first, a count is added from “0000” to “1111” in IC1, and when “1111” becomes “0000” again, a carry signal is sent from the CO terminal of IC1 to the ENT of IC2. Output to the terminal. In IC2, the count is added only when the carry signal and the random number clock are input simultaneously.

  Similarly, a carry signal from IC2 is required for the count addition of IC3, and a carry signal from IC3 is required for the count addition of IC4. In this way, a 16-bit binary number is generated by the clock count circuit 53. That is, of the 16-digit binary numbers, IC1 is in charge of the lowest 4 digits, IC2 is in the upper 4 digits, IC3 is in the upper 4 digits, and IC4 is in the uppermost 4 digits. Yes.

  The count added by the clock count circuit 53 is output to the first count value storage circuit 54 and the second count value storage circuit 55 via the count output units (respective QA, QB, QC and QD terminals). In this embodiment, 16-bit random numbers are generated by four 4-bit counters. However, the present invention is not limited to this, and can be changed as appropriate, such as using two 8-bit counters. Furthermore, in this embodiment, a 16-bit random number is generated. However, in other embodiments, the number of bits is not limited to 16, and may be appropriately changed.

  The latch signal output circuit relates to the first latch signal output circuit 51 (IC16) related to acquisition of random numbers associated with winning in the first start winning opening 8, and the acquisition of random numbers associated with winning in the second starting winning opening 9. The second latch signal output circuit 52 (IC17) is composed of a flip-flop circuit. The first latch signal output circuit 51 is supplied with the inverted clock from the random number clock inverting circuit 50 via the first inverted clock input unit (1CK). Further, the first latch trigger signal from the first latch trigger signal output unit is input to the IC 13 from the ID terminal, and further output from the 1Q terminal, and then input through the first latch trigger signal input unit (1D). It has become.

  When the start latch winning signal (high signal) is input as the first latch trigger signal, the first latch signal output circuit 51 receives the rising edge of this signal from the first inverted clock input unit. The first latch signal is output to the first count value storage circuit 54 through the first latch signal output unit 51 (1Q) after being delayed so as to be synchronized with the rising edge of the inverted clock.

  The second latch signal output circuit 52 is supplied with the inverted clock from the random number clock inverting circuit 50 via the second inverted clock input unit (2CK). Further, the second latch trigger signal from the second latch trigger signal output unit is input to the IC 13 from the 2D terminal, and further output from the 2Q terminal, and then input through the second latch trigger signal input unit (2D). It has become.

  When the start latch winning signal (high signal) is input as the second latch trigger signal, the second latch signal output circuit 52 receives the rising edge of this signal from the second inverted clock input unit. The output is delayed so as to be synchronized with the rising edge of the inverted clock, and is output as a second latch signal to the second count value storage circuit 55 via the second latch signal output section (1Q).

  The count value storage circuit temporarily stores a random number derived from winning at the first start winning opening 8 and temporarily stores a random number derived from winning at the second starting winning opening 9. The second count value storage circuit 55 stores the first count value. The first count value storage circuit 54 stores the random number value counted by the clock count circuit 53 based on the first latch signal from the first latch signal output circuit 51, and uses the first count value storage circuit 54 as the first read signal from the main control unit 24. Based on this, the stored random number is output. The second count value storage circuit 55 stores the random number value counted by the clock count circuit 53 based on the second latch signal from the second latch signal output circuit 52, and the second read value from the main control unit 24. The stored random number is output based on the signal.

  As shown in FIG. 4, the first count value storage circuit 54 includes a register unit (IC5 and IC6) composed of two 8-bit ICs and a buffer unit (IC9 and IC10) composed of two 8-bit ICs. It consists of and. Similarly, the second count value storage circuit 55 includes a register unit (IC7 and IC8) composed of two 8-bit ICs and a buffer unit (IC11 and IC12) composed of two 8-bit ICs. ing. Of the register portion of the first count value storage circuit 54, the IC5 is supplied with the 4-digit count from IC1 through D1 to D4 and the 4-digit count from IC2 through D5 to D8. It has become. In other words, D1 to D8 of IC5 function as a first count input unit, and the last 8 digits of the 16-bit binary random number derived from the first start winning opening 6 are input to IC5 through these. It has become. Further, in the register section of the first count value storage circuit 54, the IC 6 receives the 4-digit count from the IC 3 through D1 to D4 and the 4-digit count from the IC 4 through D5 to D8. It has become so. That is, D1 to D8 of IC6 function as a first count input unit, and the upper 8 digits of a 16-bit binary random number derived from the first start winning opening 6 are input to IC6 through these. It is like that.

  Of the register unit of the second count value storage circuit 55, the IC 7 receives the 4-digit count from the IC1 through D1 to D4 and the 4-digit count from the IC2 through D5 to D8. It has become. That is, D1 to D8 of IC7 function as a second count input unit, and the last 8 digits of the 16-bit binary random numbers derived from the second start winning opening 9 are input to IC7 through these. It has become. Further, in the register section of the second count value storage circuit 55, the 4-digit count from IC3 is input to IC8 through D1 to D4, and the 4-digit count from IC4 is input from D5 to D8. It has become so. That is, D1 to D8 of IC8 function as a second count input unit, and IC8 receives the upper 8 digits of 16-bit binary random numbers derived from the second start winning opening 9 through them. It is like that.

  The first latch signal from the first latch signal output circuit 51 is input from the CLOCK terminal in the register section (IC5 and IC6) of the first count value storage circuit 54. That is, these CLOCK terminals function as a first latch signal input unit. The count input from the clock count circuit 53 at the time of the rising edge when the first latch signal input from the first latch signal input unit becomes a high signal is stored as a random number in the register unit. Yes.

  The second latch signal from the second latch signal output circuit 52 is input from the CLOCK terminal in the register unit (IC7 and IC8) of the second count value storage circuit 55. That is, these CLOCK terminals function as a second latch signal input unit. The count input from the clock count circuit 53 at the time of the rising edge when the second latch signal input from the second latch signal input unit becomes a high signal is stored as a random number in the register unit.

  A first read signal (inverted RD1 and inverted RD2) from the first read signal output unit is input from the G1 terminal in the buffer unit (IC9 and IC10) of the first count value storage circuit 54. . That is, these G1 terminals function as a first read signal input unit. The random number stored in the register unit at the time of the falling edge when the first read signal input from the first read signal input unit becomes a low signal is output to the CPU data bus from the Y1 terminal to the Y8 terminal. It has become so. That is, these terminals function as a first random number output unit.

  Of the random numbers output from the first random number output unit, those that pass through the buffer unit of the IC 9 are input to the CPU 38 through the lower random number reading unit of the input circuit unit 34, and the lower order of the 16-digit random numbers. It will be handled as 8 digits. Among the random numbers output from the first random number output unit, those that pass through the buffer unit of the IC 10 are input to the CPU 38 via the higher random number reading unit of the input circuit unit 42, and the higher number of the 16-digit random numbers. It will be handled as 8 digits.

  A second read signal (inverted RD3 and inverted RD4) from the second read signal output unit is input from the G1 terminal in the buffer unit (IC11 and IC12) of the second count value storage circuit 55. . That is, these G1 terminals function as a second read signal input unit. The random number stored in the register unit at the falling edge when the second read signal input from the second read signal input unit becomes a low signal is output to the CPU data bus from the Y1 terminal to the Y8 terminal. It has become so. That is, these terminals function as a second random number output unit.

  Of the random numbers output from the second random number output unit, those that pass through the buffer unit of the IC 11 are input to the CPU 38 through the lower random number reading unit of the input circuit unit 42, and the lower order of the 16-digit random numbers. It will be handled as 8 digits. Of the random numbers output from the second random number output unit, those that pass through the buffer unit of the IC 12 are input to the CPU 38 through the upper random number reading unit of the input circuit unit 42, and the higher number of the 16-digit random numbers. It will be handled as 8 digits.

  Next, with reference to FIG. 6 to FIG. 10, procedures such as acquisition and monitoring of random numbers in an actual game will be described. Here, FIG. 6 is a flowchart showing a main routine of procedures such as random number acquisition and monitoring processing in this embodiment, FIG. 7 is a flowchart showing a subroutine of the winning check processing, and FIGS. 8 and 9 are random number monitoring processing. FIG. 10 is a flowchart showing a subroutine of the symbol variation process.

  First, when the power of the pachinko gaming machine 1 is turned on, as shown in FIG. 6, initial setting of necessary parameters is performed (S100), and then input check processing (S200) is sequentially performed according to the main routine. ), Random number monitoring process (S300), symbol variation process (S300), and special game determination execution process (S400).

  In the input check processing subroutine, as shown in FIG. 7, first, the winning determination means 26 determines whether or not the hit ball has won the general winning opening 11 (S201). As a result, when it is determined that there is a winning, 10 winning balls are paid out (S202), and then the process proceeds to the next stage (S203). On the other hand, if it is determined in step S201 that there has been no winning, the process proceeds directly to step S203.

  In step S203, the winning determination means 26 determines whether or not there is a winning at the first start winning opening 8. As a result, if it is determined that there is a win, four prize balls are paid out (S204). On the other hand, when it is determined that there is no winning at the first starting winning opening 8, the winning determining means 26 determines whether or not there is a winning at the second starting winning opening 9 (S205). If it is determined that there is a winning at the start winning opening 9, four prize balls are paid out at the stage of S204.

  Next, in step S206, it is determined whether or not the number of reserved balls has reached the upper limit of four. As a result, when it is determined that the number of held balls has not reached the upper limit, the first and second latch trigger signals are output from the output circuit unit 43 to the first latch signal output circuit 51 and the second latch signal output circuit 52, respectively. Is output (S207). The random number for the upper 8 bits is read (S208), the random number for the lower 8 bits is read (S209), the random number read flag is turned on (S210), and the process proceeds to the next step (S211). On the other hand, if it is determined in step S205 that there is no winning at the second start winning opening 9, and if it is determined in step S206 that the number of reserved balls is the upper limit, the step of S211 is immediately performed. Proceed to

  In the stage of S211, the winning determination means 26 determines whether or not there has been a winning at the big winning opening 10. As a result, if it is determined that there is a winning, 15 prize balls are paid out (S212), and then the process returns to the main routine. On the other hand, if it is determined that there has been no winning in the special winning opening 10, the process returns to the main routine without paying out the winning ball.

  Next, as shown in FIGS. 8 and 9, a random number monitoring process subroutine is executed.

  In this random number monitoring processing subroutine, first, as shown in FIG. 8, it is determined whether or not the random number read flag is on. As a result, if it is determined that it is turned on, the process proceeds to the next step (S302). If it is determined that it is not turned on, the random number monitoring process is not executed and the process returns to the main routine. . At the stage of S302, the higher-order bits of the random number are stored in the random-number storage means 31 (S302), and the lower-order bits of the random numbers are stored in the random-number storage means 31 (S303), and then the random number read flag is turned off ( S304).

  Then, the upper bit of the random number stored last time is read from the random number storage means 31 (S305) and the upper bit of the random number stored this time is read (S306), and the upper bit comparison means 34 of the random number comparison means 32 is read. The upper bits of the previous random number and the upper bits of the current random number are compared (S307). As a result, if it is determined that the upper bits of the previous and current random numbers match, 1 is added to the upper match counter (S308) and the upper match flag is turned on (S309). After the comparison result by the upper bit comparison means 34 is stored in the comparison result storage means 33, the process proceeds to the next step (S310). On the other hand, if it is determined in step S307 that the most significant bits of the previous and current random numbers do not match, the process immediately proceeds to step S310.

  Then, the low-order bit of the previously stored random number is read from the random number storage unit 31 (S310) and the low-order bit of the random number stored this time is read (S311). The lower bit of the previous random number and the lower bit of the current random number are compared by the bit comparison unit 35 (S312). As a result, if it is determined that the low-order bits of the previous and current random numbers do not match, the process immediately proceeds to step S317 (see FIG. 9). On the other hand, when it is determined that the low-order bits of the previous and current random numbers match, 1 is added to the low-order match counter (S313), and it is determined whether the high-order match flag is on (S314). ). If it is determined that the upper match flag is turned on, 1 is added to the complete match counter (S315), and the comparison result by the lower bit comparison means 34 is stored in the comparison result storage means 33, and the next The process proceeds to step (S316). On the other hand, if it is determined in step S314 that the upper match flag is not turned on, the process immediately proceeds to step S316. In step S316, the upper match flag is turned off.

  Next, as shown in FIG. 9, it is determined in step S317 whether or not the complete match counter is n. As a result, when it is determined that the number is n, the fact is displayed on the display means 22, the notification LED 45 is turned on (S318), and the complete coincidence cumulative counter is added (S319). The coincidence counter is cleared (S320), and the process proceeds to the next step (S321). On the other hand, if it is determined in step S317 that the complete match counter is not n, the process immediately proceeds to step S321.

  In step S321, it is determined whether or not the upper match counter is y. As a result, if it is determined that it is y, the fact is displayed on the display means 22 and the notification LED 45 is turned on (S322), and the upper match cumulative counter is added (S323). The coincidence counter is cleared (S324), and the process proceeds to the next step (S325). On the other hand, if it is determined in step S321 that the upper match counter is not y, the process immediately proceeds to step S325.

  In step S325, it is determined whether or not the lower match counter is y. As a result, if it is determined that it is y, the fact is displayed on the display means 22, the notification LED is turned on (S326), and the lower match cumulative counter is added (S327). The coincidence counter is cleared (S328), and the process proceeds to the next stage (S329). On the other hand, if it is determined in step S325 that the lower match counter is not y, the process immediately proceeds to step S329.

  In step S329, it is determined whether or not the display operation switch 23 is turned on. As a result, if it is determined that the display operation switch 23 is turned on, the display unit 22 displays the exact match cumulative counter value. (S330), the upper match cumulative counter value (S331), and the lower match cumulative counter value (S332) are sequentially displayed, and the process returns to the main routine. On the other hand, if it is determined in step S329 that the display operation switch 23 is not turned on, the process immediately returns to the main routine.

  In this way, by monitoring the number of times that the hard random number acquired this time matches the previously acquired hard random number, it is possible to find a control board in which a failure has occurred at an early stage. You can do it quickly.

  Next, as shown in FIG. 10, a symbol variation processing subroutine is executed.

  In this symbol variation processing subroutine, it is first determined whether or not symbol variation permission has been issued. As a result, if the permission is given, the process proceeds to the next step (S402). If the permission is not given, the symbol variation process is not executed and the process returns to the main routine.

  In step S402, it is determined whether or not there is a reserve ball number. If there is a reserve ball number, the process proceeds to the next step (S403). If there is no reserve ball number, the symbol variation process is not executed. Return to the main routine.

  Next, of the 16-bit random numbers stored in the RAM 40, the upper bits are read (S403) and the lower bits are read (S404), and the stored random numbers are shifted (cleared) from the RAM 40 (S405). ). In the next step (S406), the range of the random number is read, and whether the random number read from the RAM 40 is included in the range of the random number, that is, whether or not the winning is determined. The determination unit 27 determines (S407). As a result, when it is determined that the winning is made, the winning flag is turned on (S408), and the winning symbol is variably displayed by the symbol display control means 29 (S409), and then the process proceeds to the next stage (S411). On the other hand, if it is determined in step S407 that the winning combination has not been won, the symbol display control unit 29 displays the variably displayed symbols (S410), and proceeds to step S411.

  In the step of S411, it is determined whether or not the symbol variation has ended. If it is determined that the symbol variation has ended, it is determined whether or not the winning flag is on (S412). On the other hand, if it is determined in step S411 that the symbol variation has not been completed, the determination is repeated until it is determined that the symbol variation has been completed.

  In step S412, the special game execution flag is turned on when the hit flag is on, the special game is executed by the special game execution means 28, and after the special game is finished, the special game execution flag is cleared and the main game is executed. Return to the routine. On the other hand, if it is determined in step S412 that the hit flag is not ON, the process immediately returns to the main routine. In the main routine, the game is continued by repeating the subroutine from S200 to S500.

  In the above-described embodiment, the hard random number acquired this time is compared with the hard random number acquired last time, and the occurrence number of hard random numbers is detected by monitoring the number of times of matching, This is merely an example, for example, the frequency and continuity of random numbers are monitored over a plurality of times, and when random numbers occur in a state where they cannot occur stochastically, various configurations such as notification are possible. It can be changed.

  Further, the notification LED 45 is not necessarily installed, and a lamp used for normal production may be blinked, or the comparison result by the random number comparison unit 32 is simply displayed on the display unit 22. May be. In this case, an attendant can regularly monitor the display means 22 to detect an occurrence error of random numbers at an early stage.

  Furthermore, it goes without saying that the present invention is applicable not only to pachinko gaming machines but also to other gaming machines such as slot machines.

It is a front view which shows the game board of the pachinko gaming machine in the embodiment of the present invention. It is a rear view which shows the back set board of the pachinko gaming machine in the embodiment of the present invention. It is a block diagram which shows the part in connection with generation | occurrence | production of the hard random number in embodiment of this invention. It is a circuit diagram which shows the part in connection with generation | occurrence | production of the hard random number in embodiment of this invention. It is a block diagram which shows the structure of the hard random number monitoring apparatus which concerns on embodiment of this invention. It is a flowchart which shows the main routine of procedures, such as acquisition of a random number and monitoring processing, in embodiment of this invention. It is a flowchart which shows the subroutine of the prize check process in embodiment of this invention. It is a flowchart which shows the subroutine of the random number monitoring process in embodiment of this invention. It is a flowchart which shows the subroutine of the random number monitoring process in embodiment of this invention. It is a flowchart which shows the subroutine of the symbol fluctuation | variation process in embodiment of this invention.

Explanation of symbols

1 Pachinko machine 25 Random number generator 31 Random number storage means 32 Random number comparison means 33 Comparison result storage means 34 Upper bit comparison means 35 Lower bit comparison means 45 Notification LED

Claims (1)

A hard random number monitoring device in a gaming machine provided with a random number generator that generates a hard random number at a predetermined timing,
Random number storage means for storing a hard random number obtained from the random number generator;
A random number comparison unit that reads out and compares the hard random number acquired at the time and the hard random number acquired before the time from the random number storage unit;
Comparison result storage means for storing a comparison result by the random number comparison means;
Display means for displaying the contents of the comparison result stored in the comparison result storage means;
The random number generation unit includes a register unit that latches a random value generated at a timing to be acquired, and the random number generation unit cascades counters in multiple stages to generate a 16-bit count value as a random number , The register unit is configured to divide and latch the upper 8-bit count value as the upper 8-bit random number and the lower 8-bit count value as the lower 8-bit random number among the 16-bit random numbers, The random number comparing means compares the upper 8 bits and the lower 8 bits of the hard random number acquired at that time separately with the upper 8 bits and the lower 8 bits of the hard random number acquired before that time, respectively. And the lower bit comparison means. The upper bit comparison means and the lower bit comparison means are the upper 8 bits of the hard random number acquired this time. And Doo and lower 8 bits, are configured such that the upper 8 bits and lower 8 bits of the hard random number previously obtained from the times to determine matching whether each separately, the upper eight of the currently acquired hard random number Informing means for separately informing when the number of times that the upper 8 bits and the lower 8 bits of the hard random number obtained before that time and the lower 8 bits coincide with each other reaches a predetermined number A hard random number monitoring device for a gaming machine.

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