JP4547821B2 - Exclusive control circuit for different period sequencer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit including two sequencers that operate independently at different periods used in a transmission apparatus or the like, and allows exclusive access to any one of these sequencers and a bus line. About.
[0002]
[Prior art]
FIG. 4 is a block diagram showing a configuration of an access control circuit including a plurality of conventional sequencers. As shown here, when the sequencer 404 and the sequencer 406 have different functions and perform independent operations at different periods, independent hardware is required.
[0003]
That is, when the firmware 402 controls the sequencer 404, first, after the control data sent from the firmware 402 is written to the storage element 408, the firmware 402 gives a control trigger to the sequencer 404 and operates the sequencer 404. Let The sequencer 404 reads control data from the storage element 408 under the control of the firmware 402, writes the result to the storage element 408, and transmits a control response to the firmware 402. Upon receiving the control response, the firmware 402 reads the result of the sequencer 404 written in the storage element 408. On the other hand, when the firmware 402 controls the sequencer 406, it is necessary to use the storage element 410 this time as in the case of the sequencer 404.
[0004]
As described above, conventionally, the sequencers 404 and 406 that operate independently are controlled by separate control signals using the separate storage elements 408 and 410.
[0005]
[Problems to be solved by the invention]
When independent sequencer control is performed by such a conventional method, as shown in FIG. 4, as many memory elements and bus lines as the number of sequencers are required, which increases the scale of hardware. The larger the hardware scale, the higher the cost.
[0006]
Therefore, the present invention has been made in view of the above-described problems of the prior art, and the object thereof is to control a plurality of sequencers through the same bus line and to be compact. An object of the present invention is to provide an exclusive control circuit of a sequencer that can achieve a circuit configuration.
[0007]
[Means for Solving the Problems]
To achieve the above object, the exclusive control circuit in different period sequencer of the present invention, through firmware or hardware, and memory means, and two sequencers that operate in a different sequence periods respectively identical bus line, access In a possible connected circuit,
The bus lines are arranged such that the time zone in which one sequencer can access the bus line and the time zone in which the other sequencer can access the bus line are not overlapped by matching the start points of the sequence periods of the two sequencers. And set the timing to access
Immediately after the end of the time slot for accessing the bus line at the end of the two sequencers, the next sequence period of the two sequencers is started in coincidence .
[0008]
Further, the exclusive control circuit of the different cycle sequencer according to the present invention is a circuit in which firmware or hardware, storage means, and a plurality of sequencers operating at different sequence cycles are connected to be accessible via the same bus line. In
The start points of the sequence periods of the plurality of sequencers are all matched, and the timing at which each sequencer can access the bus line is set in advance so that the time zones in which the sequencers can access the bus line do not overlap each other
Immediately after the end of the time slot for accessing the bus line at the end of the plurality of sequencers, the next sequence period of the plurality of sequencers is started in coincidence.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on the illustrated embodiment. FIG. 1 is a block diagram showing a configuration of an access control circuit of a sequencer provided with an exclusive control circuit of a different period sequencer of the present invention. As shown in the figure, the exclusive control circuit 100 of the different period sequencer of the present invention includes firmware 102, a storage element 104, and sequencers 106 and 108 connected by the same bus line, and the firmware 102 and the sequencer are connected via the storage element 104. The access control circuit of the sequencer that transmits / receives control data and the like to / from 106 and 108 is provided. In this case, the data of the sequencer 106 and the data of the sequencer 108 are controlled by the firmware 102 so as to be stored in different address areas of the storage element 104.
[0011]
Here, for example, it is assumed that a sequencer having a sequence period of about 23.6 ms and operating at 8192 counts × 14 periods using a frequency of 4.86 MHz as a base clock is adopted as the sequencer 106. On the other hand, it is assumed that a sequencer having a sequence period of about 23.75 ms and operating at 1215 counts × 95 periods using a frequency of 4.86 MHz as a base clock is adopted as the sequencer 108. At this time, since the sequence period of the sequence period and the sequencer 108 of the sequencer 106 is a time difference of about 0.15 ms, if repeated operation in the configuration shown in FIG. 1, the deviation of the sequence period of the sequencer 106 and the sequencer 108 The same bus line cannot be shared. In addition, when control data and the like are irregularly transmitted and received between the firmware 102 and the sequencers 106 and 108 via the storage element 104, the control to each sequencer competes, and the collision of the data used by each sequencer, Destruction can occur.
[0012]
Therefore, the exclusive control circuit 100 of the different-period sequencer according to the present invention solves such a problem by performing the following operation. Hereinafter, a description will be given with reference to FIG.
[0013]
First, the access to the bus line is permitted for the sequencer 106 only in 1 to 4 cycles out of 8192 counts × 14 cycles. The sequencer 108 is allowed to access the bus line only during 25 to 93 cycles out of 1215 counts × 95 cycles. By doing so, it is possible to avoid that each sequencer accesses the bus line in the same time zone. Therefore, the problem that the control to each sequencer competes does not occur.
[0014]
Next, the 95th period out of 1215 counts × 95 periods in the sequencer 108 is irrelevant to transmission / reception of control data and the like. Moreover, the time of one cycle of the sequencer 108 corresponds to about 0.15 ms generated between the sequencer 106 and the cycle. Therefore, the exclusive control circuit for the different-cycle sequencer of the present invention resets a counter (details will be described later) that counts the cycle of the sequencer 108 provided inside immediately after the 94th cycle of the sequencer 108 ends. The count of the next cycle starts immediately after the end of the 94th cycle. By doing so, it is possible to synchronize with the sequencer 106 in a pseudo manner. Therefore, the same bus line as the sequencer 106 can be shared.
[0015]
Next, the operation will be described while showing a specific configuration of the exclusive control circuit of the different period sequencer of the present invention. FIG. 3 is a block diagram showing an example of a specific configuration of the exclusive control circuit of the different period sequencer of the present invention. Similarly to the sequencers 106 and 108, the exclusive control circuit 100 of the different period sequencer of the present invention uses the frequency 4.86 MHz as a base clock.
[0016]
When the 4.86 MHz clock is input to the exclusive control circuit 100, the operation of the sequencer 106 is counted by the 8192 counter 302. Based on the output from the 8192 counter 302, the period of the sequencer 106 is counted by the 14 counter 304. Based on the output from the 14 counter 304, the permission signal generation unit 306 transmits a signal for permitting access to the bus line to the sequencer 106 only when the operation of the sequencer 106 is 1 to 4 cycles.
[0017]
On the other hand, the 1215 counter 308 counts the operation of the sequencer 108. Based on the output from the 1215 counter 308, the cycle of the sequencer 108 is counted in the 95 counter 310. Based on the output from the 95 counter 310, the permission signal generation unit 312 transmits a signal permitting access to the bus line to the sequencer 108 only when the operation of the sequencer 108 has a period of 25 to 93.
[0018]
Here, when 14 counts are counted by the 14 counter 304 (it is confirmed that the operation of the 14th cycle of the sequencer 106 has been completed), a reset signal is transmitted to the 95 counter 310. Therefore, the 95 counter 310 starts counting the 95th period of the sequencer 108 as the first period of the sequencer 108. By doing so, the operation of the sequencer 106 and the operation of the sequencer 108 can be artificially synchronized.
[0019]
As described above, according to the exclusive control circuit of the different cycle sequencer of the present invention, the operations of two sequencers that operate independently at different cycles can be artificially synchronized, so the same bus line is shared. It becomes possible to do.
Therefore, when configuring an access control circuit for two sequencers, the hardware scale can be reduced, and the cost can be reduced. In addition, by causing each sequencer to access the bus line at different time zones, there is no problem of conflicting controls.
[0020]
The embodiment of the present invention has been described with reference to the drawings. However, the present invention is not limited to the matters shown in the above-described embodiments, and it is obvious that changes, improvements, and the like can be made based on the description of the scope of claims. For example, it is also possible to employ a sequencer that operates at a sequence period different from that of each sequencer. However, also in this case, it is necessary to artificially synchronize the operations of the sequencers as described above. Moreover, it is also possible to provide hardware instead of the firmware.
[0021]
【The invention's effect】
As described above, according to the present invention, it is possible to provide an exclusive control circuit for a sequencer that can control a plurality of sequencers through the same bus line and can achieve a compact circuit configuration.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an access control circuit of a sequencer provided with an exclusive control circuit of a different period sequencer of the present invention.
FIG. 2 is a diagram for explaining operations of the sequencer 106 and the sequencer 108;
FIG. 3 is a block diagram showing an example of a specific configuration of an exclusive control circuit of an odd-period sequencer according to the present invention.
FIG. 4 is a block diagram showing a configuration of an access control circuit including a plurality of conventional sequencers.
[Explanation of symbols]
100 Exclusive control circuit 102, 402 Firmware 104, 408, 410 Storage element 106, 108, 404, 406 Sequencer 302 8192 counter 304 14 counter 306, 312 Permission signal generation unit 308 1215 counter 310 95 counter

Claims (2)

In a circuit in which firmware or hardware, storage means, and two sequencers operating at different sequence periods are connected to be accessible via the same bus line,
The time period in which one sequencer can access the bus line and the time period in which the other sequencer can access the bus line do not overlap when the start points of the sequence periods of the two sequencers are matched. Set the timing to access the bus line in advance,
The exclusive of the different sequencer, wherein the next sequence cycle of the two sequencers starts immediately after the end of the time period for accessing the bus line at the end of the two sequencers. Control circuit. In a circuit in which firmware or hardware, storage means, and a plurality of sequencers operating at different sequence periods are connected to be accessible via the same bus line,
When all match the starting point of the sequence period of the plurality of sequencers, and sets the timing for access to the bus line so that the time zone in which the sequencer each has access to the bus line do not overlap each other in advance,
The exclusion of the different period sequencer, wherein the next sequence period of the plurality of sequencers starts immediately after the end of the time period for accessing the bus line at the end of the plurality of sequencers. Control circuit.

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